The AMBA VIP Release Notes are installed at:

• Synopsys AMBA VIP Release Notes (PDF)

The Synopsys VIP for AHB is a suite of advanced verification components and data objects based on SystemVerilog VMM-compliant technology. This on-line help contains information about the classes, functions, and member variables. It shows class hierarchy and contents and it provides links you can use to navigate to more details. Below is the summary of the components and the user interface of the Synopsys AHB VIP.

AHB VIP Components

• svt_ahb_master_group Defines a group for the AHB Master component. The master group encapsulates atomic generator, scenario generator, master transactor, and port monitor. The master group can be configured to operate in active mode and passive mode.
• svt_ahb_slave_group Defines a group for the AHB Slave component. The slave group encapsulates slave transactor, port monitor, and response generator. The slave group can be configured to operate in active mode and passive mode. slave memory is represented by class svt_mem . Slave memory is instantiated in the slave response generator within the slave group. If the configuration parameter svt_ahb_configuration :: generator_type is set to MEMORY_RESPONSE_GEN, the slave response generator reads/writes data from/to the built-in memory.
• svt_ahb_system_monitor Observes transactions across the ports of a single Bus and performs checks between the transactions of these ports. For the list of system checks supported by the system monitor, click on the "Protocol Checks" tab in this class reference documentation.
• svt_ahb_system_group Defines a system level group for the AHB SVT suite. The AHB System group encapsulates the master groups, slave groups, multi-stream scenario generator (MSSG), AHB System Monitor and AHB system configuration. The number of master and slave groups is configured based on the system configuration provided by the user.

AHB VIP User Interface
Configuration Objects:
Configuration data objects convey the system level and port level testbench configuration. The configuration data objects contain built-in constraints, which come into effect when the configuration objects are randomized. If the configuration needs to be changed later, it can be done through reconfigure() method of the master, slave or system components. The AHB VIP defines following configuration classes:

• svt_ahb_configuration (AHB Base configuration)
• svt_ahb_system_configuration (AHB System configuration)
• svt_ahb_master_configuration (AHB Master configuration)
• svt_ahb_slave_configuration (AHB Slave configuration)

Transaction Objects:
Transaction objects, which are extended from the vmm_data base class, define a unit of AHB protocol information that is passed across the bus. The attributes of transaction objects are public and are accessed directly for setting and getting values. Most transaction attributes can be randomized. The transaction object can represent the desired activity to be simulated on the bus, or the actual bus activity that was monitored. AHB VIP defines following transaction classes:

• svt_ahb_transaction (AHB Base transaction)
• svt_ahb_master_transaction (AHB Master transaction)
• svt_ahb_slave_transaction (AHB Slave transaction)

Analysis port:
The port monitor in the master & slave components provides an analysis port. At the end of the transaction, the master & slave components respectively provide the completed svt_ahb_master_transaction & svt_ahb_slave_transaction object to their analysis port. The analysis port used by master & slave components are:

• svt_ahb_master_monitor :: item_observed_port
• svt_ahb_slave_monitor :: item_observed_port

Callbacks:
Callbacks are an access mechanism that enable the insertion of user-defined code and allow access to objects for scoreboarding and functional coverage. Each master and slave components is associated with a callback class that contains a set of callback methods. AHB VIP provides following callbacks classes:

• svt_ahb_master_callback (Master callback class)
• svt_ahb_slave_callback (Slave callback class)
• svt_ahb_master_monitor_callback (Master monitor callback class)
• svt_ahb_slave_monitor_callback (Slave monitor callback class)
• svt_ahb_system_monitor_callback (System monitor callback class)
• svt_ahb_slave_response_gen_callback (Slave response generator callback class)

Interfaces and modports:
SystemVerilog models signal connections using interfaces and modports. Interfaces define the set of signals which make up a port connection. Modports define collection of signals for a given port, the direction of the signals, and the clock with respect to which these signals are driven and sampled. AHB VIP provides below interfaces:

• svt_ahb_if (Top level interface, which contains an array of master & slave port sub-interfaces)
• svt_ahb_master_if (sub-interface for master ports)
• svt_ahb_slave_if (sub-interface for slave ports)

• svt_ahb_slave_modport (Modport used to connect master VIP component to slave DUT port)
• svt_ahb_master_modport (Modport used to connect slave VIP component to master DUT port)
• svt_ahb_debug_modport (Modport used to access the debug port signals)