VIP Smartsearch

VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.
How to download VIP smartsearch?
1. Get VIP Smartsearch (Available as a seperate run file).
2. Set environment variable
```
DESIGNWARE_HOME
```
  to required designware home location where VIP Smartsearch should be downloaded.
3. Run
```
vip_smartsearch_<version>.run
```
  file.
  VIP Smartsearch will be downloaded to the location
```
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
```

How to install VIP Smartsearch?

Please refer to the file

VIP_Smartsearch_installation_and_usage_guide.pdf

$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

for installation steps.

Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.
Mention your queries along with below details and send email to above email id.
Product: Verification IP
Sub Product: <vip_title>
Tool: VIP Smartsearch

ATB SVT UVM Documentation - Interfaces Reference

Product	Interface Group	Interfaces
amba_svt	Default Group	svt_atb_master_if
svt_atb_slave_if
svt_atb_if	svt_atb_slave_if, svt_atb_master_if

interface svt_atb_slave_if

(

input logic common_atclk

)

General description:

The slave interface svt_atb_slave_if defines the ATB signals appropriate for a single port, along with the modports needed for the ATB slave and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Clock signal description:

Signal Name	Signal Description
atclk	If all ATB interfaces in the system are expected to run on a different clock, user can use the atclk signal in the port interfaces. Set the configuration parameter svt_atb_system_configuration :: common_clock_mode to 0. In this case, connect the atclk signal in each port interface to the appropriate port specific clock in the testbench.

Debug port description:
In active and passive mode, the VIP assigns a unique number to each transaction. This number is also displayed in the messages issued by the VIP. The debug port reflects this unique transaction number. This makes it easy to fnd a particular transaction on the waveforms, by looking at the debug port signals. For example, if messages mentions that there is a error on transaction #100, used can jump to value #100 on debug port signals, to find the transaction.

Signal Name	Signal Description
read_addr_xact_num	Transaction number on read address channel. Used in active mode.

ATB signal description:
The names of the signals match the names specified in the ATB specification. Please refer to the ATB specification for specific description of any of the signals.

Ports

bit

is_active

bit

common_clock_mode

bit

atclken_enable

logic

atclk

logic

atresetn

logic

atclken

logic [SVT_ATB_MAX_ID_WIDTH-1:0]

atid

logic [SVT_ATB_MAX_DATA_VALID_BYTES_WIDTH-1:0]

atbytes

logic [SVT_ATB_MAX_DATA_WIDTH-1:0]

atdata

logic

atvalid

logic

atready

logic

afvalid

logic

afready

logic

syncreq

logic [31:0]

atb_xact_num

logic [31:0]

atb_xfer_id

logic [31:0]

mon_atb_xact_num

logic [31:0]

mon_atb_xfer_id

string

full_name

Modports

modport svt_atb_slave_modport

(

clocking atb_slave_cb

)

Modport used to connect the VIP Slave to ATB interface signals.

modport svt_atb_monitor_modport

(

clocking atb_monitor_cb

)

Modport used to connect the VIP Monitor to ATB interface signals.

modport svt_atb_master_modport

(

input atid,
input atbytes,
input atdata,
input atvalid,
input afready,
input atclken,
output atresetn,
output atready,
output afvalid,
output syncreq

)

Asynchronous modport suitable for connecting to a Master DUT

modport svt_atb_master_async_modport

(

output atid,
output atbytes,
output atdata,
output atvalid,
output afready,
output atclken,
input atresetn,
input atready,
input afvalid,
input syncreq

)

Asynchronous modport suitable for SV Master Bind interface

modport svt_atb_debug_modport

(

output atb_xact_num,
output atb_xfer_id,
output mon_atb_xact_num,
output mon_atb_xfer_id

)

Modport used to connect the VIP Debug Port.

Clocking blocks

clocking atb_monitor_cb @ ( posedge internal_atclk )
default input #0.1 output #0.1

input atresetn,
input atclken,
input atid,
input atbytes,
input atdata,
input atvalid,
input atready,
input afvalid,
input afready,
input syncreq

Clocking block that defines the ATB Monitor Interface signal synchronization and directionality.

clocking atb_debug_cb @ ( posedge atclk )
default input #0.1 output #0.1

output atb_xact_num,
output atb_xfer_id

Clocking block that defines the ATB Debug Interface

clocking atb_slave_cb @ ( posedge internal_atclk )
default input #0.1 output #0.1

input atresetn,
input atclken,
input atid,
input atbytes,
input atdata,
input atvalid,
output atready,
output afvalid,
input afready,
output syncreq

Clocking block that defines the VIP ATB slave Interface signal synchronization and directionality.

Functions

void function

set_enable_signal_log ()

string function

get_full_name ()

interface svt_atb_if ()

General description:

ATB VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_atb_if is defined. The top level interface contains an array of master & slave interfaces. By default, 16 master and 16 slave interfaces are defined in the top level interface. Currently, the maximum master and slave interfaces supported is 128. The number of master and slave interfaces in top level interface can be controlled using macros SVT_ATB_MAX_NUM_MASTERS_{0..128} and SVT_ATB_MAX_NUM_SLAVES_{0..128} respectively. For example, if you want to use 8 master interfaces and 10 slave interfaces, you can define following macros when compiling the VIP:

SVT_ATB_MAX_NUM_MASTERS_8

SVT_ATB_MAX_NUM_SLAVES_10
Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces:

Interface Name	Interface Description
svt_atb_master_if	Master Interface used by master VIP component
svt_atb_slave_if	Slave Interface used by slave VIP component

Clock signal description:

Signal Name

Signal Description

common_atclk

If all ATB interfaces in the system are expected to run on a common clock, user can use the common clock mode. Common clock mode can be selected by setting configuration parameter svt_atb_system_configuration :: common_clock_mode to 1. This is the default mode of operation. When common clock mode is used, connect common_atclk signal to the top level clock signal in the testbench. Pleae note that if you are using the Interconnect VIP component, you are required to always connect common_atclk signalto a clock in the testbench, as Interconnect VIP component internally uses this clock for its operation.

atclk

This signal belongs to the master and slave sub-interfaces. If all ATB interfaces in the system are expected to run on a different clock, user can use the atclk signal in the port interfaces. Set the configuration parameter svt_atb_system_configuration :: common_clock_mode to 0. In this case, connect the atclk signal in each port interface to the appropriate port specific clock in the testbench.

Clock connection examples:

Usage with common clock:
assign atb_if.common_atclk = SystemClock;

Usage with port specific clock:
assign atb_if.master_if[0].atclk = master_clk;
assign atb_if.slave_if[0].atclk = slave_clk;

Interface signal connections:

If master VIP is active, then connect DUT slave port signals to master interface:
assign atb_if.master_if[0].atvalid = DUT_slave_intf.atvalid;

If master VIP is passive, then connect DUT master port signals to master interface:
assign atb_if.master_if[0].atvalid = DUT_master_intf.atvalid;

If slave VIP is active, then connect DUT master port signals to slave interface:
assign atb_if.slave_if[0].atready = DUT_master_intf.atready;

If slave VIP is passive, then connect DUT slave port signals to slave interface:
assign atb_if.slave_if[0].atready = DUT_slave_intf.atready;

Sub-interfaces

svt_atb_master_if

master_if

svt_atb_slave_if

slave_if

Ports

logic

common_atclk

string

full_name

Functions

void function

set_enable_signal_log ()

string function

get_full_name ()

function void
svt_atb_master_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_atb_master_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_atb_master_if signal
input logic common_atclk

bit attribute
svt_atb_master_if::is_active = 1

bit attribute
svt_atb_master_if::common_clock_mode = 1

bit attribute
svt_atb_master_if::atclken_enable = 1

logic attribute
svt_atb_master_if::atclk

logic attribute
svt_atb_master_if::atresetn

logic attribute
svt_atb_master_if::atclken

logic [SVT_ATB_MAX_ID_WIDTH-1:0] attribute
svt_atb_master_if::atid

logic [SVT_ATB_MAX_DATA_VALID_BYTES_WIDTH-1:0] attribute
svt_atb_master_if::atbytes

logic [SVT_ATB_MAX_DATA_WIDTH-1:0] attribute
svt_atb_master_if::atdata

logic attribute
svt_atb_master_if::atvalid

logic attribute
svt_atb_master_if::atready

logic attribute
svt_atb_master_if::afvalid

logic attribute
svt_atb_master_if::afready

logic attribute
svt_atb_master_if::syncreq

logic [31:0] attribute
svt_atb_master_if::atb_xact_num

Debug port signals driven in active mode

logic [31:0] attribute
svt_atb_master_if::atb_xfer_id

logic [31:0] attribute
svt_atb_master_if::mon_atb_xact_num

Debug port signals driven in passive mode

logic [31:0] attribute
svt_atb_master_if::mon_atb_xfer_id

string attribute
svt_atb_master_if::full_name

Full path to this interface or module instance

function void
svt_atb_slave_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_atb_slave_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_atb_slave_if signal
input logic common_atclk

bit attribute
svt_atb_slave_if::is_active = 1

bit attribute
svt_atb_slave_if::common_clock_mode = 1

bit attribute
svt_atb_slave_if::atclken_enable = 1

logic attribute
svt_atb_slave_if::atclk

logic attribute
svt_atb_slave_if::atresetn

logic attribute
svt_atb_slave_if::atclken

logic [SVT_ATB_MAX_ID_WIDTH-1:0] attribute
svt_atb_slave_if::atid

logic [SVT_ATB_MAX_DATA_VALID_BYTES_WIDTH-1:0] attribute
svt_atb_slave_if::atbytes

logic [SVT_ATB_MAX_DATA_WIDTH-1:0] attribute
svt_atb_slave_if::atdata

logic attribute
svt_atb_slave_if::atvalid

logic attribute
svt_atb_slave_if::atready

logic attribute
svt_atb_slave_if::afvalid

logic attribute
svt_atb_slave_if::afready

logic attribute
svt_atb_slave_if::syncreq

logic [31:0] attribute
svt_atb_slave_if::atb_xact_num

Debug port signals driven in active mode

logic [31:0] attribute
svt_atb_slave_if::atb_xfer_id

logic [31:0] attribute
svt_atb_slave_if::mon_atb_xact_num

Debug port signals driven in passive mode

logic [31:0] attribute
svt_atb_slave_if::mon_atb_xfer_id

string attribute
svt_atb_slave_if::full_name

Full path to this interface or module instance

function void
svt_atb_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_atb_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

logic attribute
svt_atb_if::common_atclk

svt_atb_master_if attribute
svt_atb_if::master_if

svt_atb_slave_if attribute
svt_atb_if::slave_if

string attribute
svt_atb_if::full_name

Full path to this interface or module instance

VIP Smartsearch

ATB SVT UVM Documentation - Interfaces Reference

Interface Definition Documentation