VIP Smartsearch

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  • VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.

  • How to download VIP smartsearch?

    1. Get VIP Smartsearch (Available as a seperate run file).
    2. Set environment variable 
      DESIGNWARE_HOME
      to required designware home location where VIP Smartsearch should be downloaded.
    3. Run 
      vip_smartsearch_<version>.run
      file.
      VIP Smartsearch will be downloaded to the location 
      $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

  • How to install VIP Smartsearch?

    Please refer to the file 
    VIP_Smartsearch_installation_and_usage_guide.pdf
    in 
    $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
    for installation steps.

  • Customer Support

    For more details about VIP smartsearch tool, contact support_center@synopsys.com.
    Mention your queries along with below details and send email to above email id.
    Product: Verification IP
    Sub Product: <vip_title>
    Tool: VIP Smartsearch
13 August 2024, Copyright © 2024 Synopsys, Inc.

svt_axi_cache Class Reference

Inheritance diagram for class svt_axi_cache:

List of all members.

Detailed Description

This class is used to model a single cache.

Internally, the cache is modeled with a sparse array of svt_axi_cache_line objects, each of which represents a full cache line.


Member Typedefs

 typedef enum  cache_structure_enum 

Member Typedef Documentation

 Typedefe'd string ==>   bit [SVT_AXI_MAX_ADDR_WIDTH-1:0]

 typedef enum  svt_axi_cache::cache_structure_enum
Enum to represent the different cache structures DIRECT_MAPPED: An entry corresponding to a main memory address is stored in a cache line with a unique index. For example, consider an 8 KB cache where the cache line size is 16 bytes and there are 512 such lines. Then addresses 0, 8K, 16K, 24K etc are always mapped to index 0 of the cache and so on. FULLY_ASSOCIATIVE: In such a cache structure, a given main memory address can be stored in a cache line with any index. TWO_WAY_ASSOCIATIVE: An entry corresponding to a main memory address can be stored in any one of two cache line indices. For example, consider an 8 KB cache where the cache line size is 16 bytes and there are 512 such lines. These 512 lines are divided into 256 sets with "2 ways" for each set. So any given main memory address can be stored in only a unique set, but within this set, it can be stored in one of the two ways. NOTE: Currently only FULLY_ASSOCIATIVE is supported
FULLY_ASSOCIATIVE(SVT_CACHE_FULLY_ASSOCIATIVE)
DIRECT_MAPPED(SVT_CACHE_DIRECT_MAPPED)
TWO_WAY_ASSOCIATIVE(SVT_CACHE_TWO_WAY_ASSOCIATIVE)

 Typedefe'd string ==>   bit [7:0]

13 August 2024, Copyright © 2024 Synopsys, Inc.