VIP Smartsearch

VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.
How to download VIP smartsearch?
1. Get VIP Smartsearch (Available as a seperate run file).
2. Set environment variable
```
DESIGNWARE_HOME
```
  to required designware home location where VIP Smartsearch should be downloaded.
3. Run
```
vip_smartsearch_<version>.run
```
  file.
  VIP Smartsearch will be downloaded to the location
```
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
```

How to install VIP Smartsearch?

Please refer to the file

VIP_Smartsearch_installation_and_usage_guide.pdf

$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

for installation steps.

Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.
Mention your queries along with below details and send email to above email id.
Product: Verification IP
Sub Product: <vip_title>
Tool: VIP Smartsearch

AMBA CHI-A SVT VMM Documentation - Protocol Checks Defined in VIP

Summary of Protocol Checks defined in AMBA CHI-A SVT VMM Documentation:

Product Base	Group	Protocol Check Class
amba_svt	CHI Protocol Layer	svt_chi_protocol_err_check
CHI Link Layer	svt_chi_link_err_check
CHI System	svt_chi_system_err_check

Product Base

Group

Protocol Check Class

amba_svt

CHI Protocol Layer

svt_chi_protocol_err_check

CHI Link Layer

svt_chi_link_err_check

CHI System

svt_chi_system_err_check

Group	Sub Group	Protocol Check Instance name	Reference	Description	Check Intent	Pass Condition	Fail Condition	Applicable Device Type	Additional Information	Error Category	Protocol Check Class
CHI Protocol Layer	Node performance metrics	perf_min_write_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of write transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of write transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_write_throughput	The throughput of write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_min_write_throughput.	The throughput of write transactions in the specified interval is less than svt_chi_node_configuration :: perf_min_write_throughput.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_write_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of write transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of write transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_write_throughput	The throughput of write transactions in the specified interval is less than svt_chi_node_configuration :: perf_max_write_throughput.	The throughput of write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_max_write_throughput.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_min_read_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of read transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of read transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_read_throughput	The throughput of read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_min_read_throughput.	The throughput of read transactions in the specified interval is less than svt_chi_node_configuration :: perf_min_read_throughput.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_read_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of read transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of read transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_read_throughput	The throughput of read transactions in the specified interval is less than svt_chi_node_configuration :: perf_max_read_throughput.	The throughput of read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_max_read_throughput.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_min_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of read transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of read transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_read_xact_latency	The average latency of Read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_min_read_xact_latency.	The average latency of Read transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_min_read_xact_latency.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_max_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of read transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of read transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_read_xact_latency	The average latency of Read transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_max_read_xact_latency.	The average latency of Read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_max_read_xact_latency.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_min_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a read transaction is more than or equal to the configured min value	Checks that the latency of a read transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_read_xact_latency	The latency of a Read transaction is greater than svt_chi_node_configuration :: perf_min_read_xact_latency.	The latency of a Read transaction is less than than svt_chi_node_configuration :: perf_min_read_xact_latency.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a read transaction is less than or equal to the configured max value	Checks that the latency of a read transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_read_xact_latency	The latency of a Read transaction is less than than svt_chi_node_configuration :: perf_max_read_xact_latency.	The latency of a Read transaction is greater than than svt_chi_node_configuration :: perf_max_read_xact_latency.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_min_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of write transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of write transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_write_xact_latency	The average latency of Write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_min_write_xact_latency.	The average latency of Write transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_min_write_xact_latency.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_max_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of write transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of write transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_write_xact_latency	The average latency of Write transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_max_write_xact_latency.	The average latency of Write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_max_write_xact_latency.	RN and SN	Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval. Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_min_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a write transaction is more than or equal to the configured min value	Checks that the latency of a write transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_write_xact_latency	The latency of a Write transaction is greater than svt_chi_node_configuration :: perf_min_write_xact_latency.	The latency of a Write transaction is less than svt_chi_node_configuration :: perf_min_write_xact_latency.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a write transaction is less than or equal to the configured max value	Checks that the latency of a write transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_write_xact_latency	The latency of a Write transaction is less than svt_chi_node_configuration :: perf_max_write_xact_latency.	The latency of a Write transaction is greater than svt_chi_node_configuration :: perf_max_write_xact_latency.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Snoop Transaction timeout check	snp_transaction_inactivity_timeout_check	SYNOPSYS DEFINED	Check that a Snoop transaction ends within the programmed number of clock cycles.	Checks that a given Snoop transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: snp_xact_inactivity_timeout. Vip will continue to process the snoop transaction even the snoop transaction has timedout. The timeout of the snoop transaction doesn't have any impact on the procesing or completion of the snoop transaction. The timer started for snoop transaction will continue to increment even there is a link deactivation when snoop transaction is outstanidng. This check is currently not designed to handle the cases when there is a dynamic reset.	The snoop transaction ends within the programmed number of clock cycles.	The snoop transaction does not end within the programmed number of clock cycles.	RN-F, RN-D(when svt_chi_node_configuration :: dvm_enable is set to 1)	This check is constructed only when configuration parameters snp_xact_inactivity_timeout (svt_chi_node_configuration :: snp_xact_inactivity_timeout) set to non zero values.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Transaction timeout check	transaction_inactivity_timeout_check	SYNOPSYS DEFINED	Check that a transaction ends within the programmed number of clock cycles.	Checks that a given transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: xact_inactivity_timeout. Vip will continue to process the transaction even the transaction has timedout. The timeout of the transaction doesn't have any impact on the procesing or completion of the transaction. The timer started for a transaction will continue to increment even there is a link deactivation when transaction is outstanidng. This check is currently not designed to handle the cases when there is a dynamic reset.	The transaction ends within the programmed number of clock cycles.	The transaction does not end within the programmed number of clock cycles.	RN,SN	This check is constructed only when configuration parameters xact_inactivity_timeout (svt_chi_node_configuration :: xact_inactivity_timeout) set to non zero values.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	exclusive access legal data_size transfer check	non_coherent_excl_access_legal_data_size_transfer_check	ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations	Check that the number of bytes to be transferred in an exclusive access must be a legal data transfer size, that is, 1, 2,4, 8, 16, 32, or 64 bytes.	Check that the number of bytes to be transferred in an exclusive access must be a legal data transfer size, that is, 1, 2,4, 8, 16, 32, or 64 bytes.	The Data size of an Exclusive transaction is one of the values specified in the description.	The Data size of an Exclusive transaction is set to a value apart from the ones mentioned in the description.	RN-F	This check is constructed only when configuration parameters exclusive_access_enable (svt_chi_node_configuration :: exclusive_access_enable) and exclusive_monitor_enable (svt_chi_node_configuration :: exclusive_monitor_enable) are set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	exclusive access address aligned to total bytes check	non_coherent_excl_access_aligned_total_bytes_transaction_check	ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations	Check that the address of an exclusive access must be aligned to the total number of bytes in the transaction.	Check that the address of an exclusive access must be aligned to the total number of bytes in the transaction.	The address of an exclusive transaction is aligned to the Data size.	The address of an exclusive transaction is not aligned to the Data size.	RN-F	This check is constructed only when configuration parameters exclusive_access_enable (svt_chi_node_configuration :: exclusive_access_enable) and exclusive_monitor_enable (svt_chi_node_configuration :: exclusive_monitor_enable) are set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	non-coherent exclusive access same lpid check	non_coherent_excl_read_multiple_entry_for_same_lpid_check	ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations	Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time.	Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time. Multiple exclusive transactions to Non-snoopable memory locations, either read or write, to the same or different addresses, from the same LP must not be outstanding at the same time.	An Exclusive Read transaction is received while there are no outstanding Exclusive Reads with the same LPID.	An Exclusive Read transaction is received but there already is an outstanding Exclusive Read with the same LPID.	RN-F	This check is constructed only when configuration parameters exclusive_access_enable (svt_chi_node_configuration :: exclusive_access_enable) and exclusive_monitor_enable (svt_chi_node_configuration :: exclusive_monitor_enable) are set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	SACTIVE signal validity	valid_rxsactive_signal_check	ARM-IHI0050E.b: 14.7 Protocol layer activity indication	RXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received at the link partner node.	RXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received at the link partner node. A transaction that is given a RetryAck response is considered to be in progress, so RXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned. The check is performed under following conditions: while the link is active and there is no active reset -- Whenever there is a flit activity observed(TXFLITV/RXFLITV asserted), RXSACTIVE must be sampled as HIGH. Otherwise the check fails. Following are the specific conditions under which this check is performed: In case of SN: if REQ flit is received, then rxsactive must be HIGH at the same clock In case of RN: The same clock where the CompAck RSP is observed, this must be high In case of RN: The same clock where SNPRSP is sampled by all receiving/observing components, this must be high In case of RN: The same clock where SNP flit is observed, this must be HIGH In the same cycle the RSP flit is received/observed, this must be high In the same cycle the Read Data flit is received/observed, this must be high In the same cycle the Snp Data flit is received/observed, this must be high In the same cycle the Write Data flit is received/observed, this must be high Whenever the signal RXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity at the link partner node. Otherwise the check fails. Following is the definition of 'pending protocol layer activity': Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits) Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions) Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)	One of the FLITV signals is asserted and the conditions mentioned in the description are satisfied.	One of the FLITV signals is asserted and any of the conditions mentioned in the description are violated.	RN and SN	svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK This check will not be constructed when svt_chi_node_configuration :: use_external_node_prot_monitor is set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	SACTIVE signal validity	valid_txsactive_signal_check	ARM-IHI0050E.b: 14.7 Protocol layer activity indication	TXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received.	TXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received. A transaction that is given a RetryAck response is considered to be in progress, so TXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned. Applicable when : the agent is in PASSIVE mode (svt_chi_node_configuration :: is_active = 0), and svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK The check is performed under following conditions: while the link is active and there is no active reset -- Whenever there is a flit activity observed(TXFLITV/RXFLITV asserted), TXSACTIVE must be sampled as HIGH. Otherwise the check fails. Following are the specific conditions under which this check is performed: REQ flit is received by PASSIVE agent, then txsactive must be HIGH at: at the same clock, in case of RN In case of RN: the same clock where CompAack RSP flit is observed, this must be high In case of RN: The same clock where SNPRSP is observed, this must be high In the same cycle the RSP flit is received/observed, this must be high In the same cycle the Read Data flit is received/observed, this must be high In the same cycle the Snp Data flit is received/observed, this must be high In the same cycle the Write Data flit is received/observed, this must be high Whenever the signal TXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity. Otherwise the check fails. Following is the definition of 'pending protocol layer activity': Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits) Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions) Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)	One of the FLITV signals is asserted and the conditions mentioned in the description are satisfied.	One of the FLITV signals is asserted and any of the conditions mentioned in the description are violated.	Passive RN and Passive SN	svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK. This check will not be constructed when svt_chi_node_configuration :: use_external_node_prot_monitor is set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_readreceipt_to_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	If the request Order field indicates that ordering is required then a ReadReceipt response must be returned on the CRSP channel when order has been established	Check that the Ordering field of the transaction corresponding to the readreceipt is set.	A ReadReceipt response is received for an Ordered Read transaction.	SCENARIO 1: A ReadReceipt is received for a Read transaction whose request order field was set to "NO ORDERING REQUIRED". SCENARIO 2: A ReadReceipt is received, at a CHI Issue C RN, for an Ordered Read transaction which has already received RESPSEPDATA.	RN and Passive SN	If the request Order field indicates that ordering is required then a ReadReceipt response must be returned on the CRSP channel when order has been established.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	barrier xact	valid_resp_err_status_for_barrier_xact_check	ARM-IHI0050A: 9.4.4 Other transactions	A Barrier transaction response must not include an error response.	Check that there are no error responses in case of Barrier transactions . A Barrier transaction response must not include an error response.	RespErr field in the Comp response of a Barrier transaction is set to OK.	RespErr field in the Comp response of a Barrier transaction is set to a value other than OK.	Passive RN and Passive SN-I	Barrier support is enabled (svt_chi_node_configuration :: barrier_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	valid_rn_d_snoop_flit_check	ARM-IHI0050E.b: Table B-2 Snoop communicating nodes	Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.	Check that only DVMOp related snoop transactions are seen on the Snoop Channel in case of RN-D. Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.	A SnpDVMOp is received for an RN-D node.	A Snoop transaction, other than a SnpDVMOp, is received for an RN-D node.	RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readunique_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadUnique transaction. The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the CompData of a ReadUnique transaction is set to UD or UC.	Final cache state in the CompData of a ReadUnique transaction is set to SD, SC or I.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readshared_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadShared transaction. The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the CompData of a ReadShared transaction is set to UC, UD, SC or SD.	Final cache state in the CompData of a ReadShared transaction is set to I.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readclean_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadClean transaction. The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the CompData of a ReadClean transaction is set to UC or SC.	Final cache state in the CompData of a ReadClean transaction is set to I, UD or SD.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleanunique_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a CleanUnique transaction. The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Comp response of a CleanUnique transaction is set to UC.	Final cache state in the Comp response of a CleanUnique transaction is set to a value other than UC.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makeunique_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a MakeUnique transaction. The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Comp response of a MakeUnique transaction is set to UC.	Final cache state in the Comp response of a MakeUnique transaction is set to a value other than UC.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	evict_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a Evict transaction. The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Comp response of an Evict transaction is set to I.	Final cache state in the Comp response of an Evict transaction is set to a value other than I.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readunique_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.	Check that the associated Compdata packet has valid resp_err value for ReadUnique transaction. The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.	The RespErr field in the associated Compdata flits of a ReadUnique transaction are as per Table 9-2 in the CHI Specification.	The RespErr field in the associated Compdata flits of a ReadUnique transaction are set to EXOK.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readshared_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Compdata packet has valid resp_err value for ReadShared transaction.	The RespErr field in the associated Compdata flits of a ReadShared transaction are as per Table 9-2 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the ReadShared request was set to 1.	The RespErr field in the associated Compdata flits are set to EXOK but the Exclusive attribute in the ReadShared request was set to 0.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readclean_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Compdata packet has valid resp_err value for ReadClean transaction.	The RespErr field in the associated Compdata flits of a ReadClean transaction are as per Table 9-2 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the ReadClean request was set to 1.	The RespErr field in the associated Compdata flits are set to EXOK but the Exclusive attribute in the ReadClean request was set to 0.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleanunique_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Comp response packet has valid resp_err value for CleanUnique transaction.	The RespErr field in the associated Comp response flits of a CleanUnique transaction are as per Table 9-3 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the CleanUnique request was set to 1.	The RespErr field in the associated Comp response flits are set to EXOK but the Exclusive attribute in the CleanUnique request was set to 0.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makeunique_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.	Check that the associated Comp response packet has valid resp_err value for MakeUnique transaction. The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.	The RespErr field in the associated Comp response flits of a MakeUnique transaction are as per Table 9-3 in the CHI Specification.	The RespErr field in the associated Comp response flits of a MakeUnique transaction are set to EXOK.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	evict_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.	Check that the associated Comp response packet has valid resp_err value for Evict transaction. The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.	The RespErr field in the associated Comp response flits of an Evict transaction are as per Table 9-3 in the CHI Specification.	The RespErr field in the associated Comp response flits of an Evict transaction are set to EXOK.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeevict_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction.	Check that the associated response and data packets has valid resp_err value for WriteEvict transaction. The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction. The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteEvict transaction. Note that this is applicable only for CHI Issue F or later specification.	The RespErr field in the associated Write data flits of a WriteEvict transaction are as per Table 9-7 in the CHI Issue F Specification. The RespErr field in the associated response flits of a WriteEvict transaction are as per Table 9-6 in the CHI Issue F Specification.	The RespErr field in the associated Write data flits of a WriteEvict transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteEvict transaction violate the legal values specified in Table 9-6 in the CHI Issue F Specification.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeclean_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction.	Check that the associated response and data packets has valid resp_err value for WriteClean transaction. The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction. The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteClean transaction. Note that this is applicable only for CHI Issue F or later specification.	The RespErr field in the associated Write data flits of a WriteClean transaction are as per Table 9-7 in the CHI Issue F Specification. The RespErr field in the associated response flits of a WriteClean transaction are as per Table 9-6 in the CHI Issue F Specification.	The RespErr field in the associated Write data flits of a WriteClean transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteClean transaction violate the legal values specified in Table 9-6 in the CHI Issue F Specification.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeback_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction.	Check that the associated response and data packets has valid resp_err value for WriteBack transaction. The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction. The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteBack transaction. Note that this is applicable only for CHI Issue F or later specification.	The RespErr field in the associated Write data flits of a WriteBack transaction are as per Table 9-7 in the CHI Issue F Specification. The RespErr field in the associated response flits of a WriteBack transaction are as per Table 9-6 in the CHI Issue F Specification.	The RespErr field in the associated Write data flits of a WriteBack transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteBack transaction violate the legal values specified in Table 9-6 in the CHI Issue F Specification.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	cache_transitioned_to_dirty_from_uce_for_read	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache transitioned to dirty stateUD/UDP from UCE.	Check if the RN has transitioned from UCE to UD/UDP state while there is an ongoing READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions. This check will flag an error in case the cache is updated via frontdoor or backdoor accesses to move from UCE to dirty state while there is an outstanding Read. .	If the RN has not transitioned to UD/UDP state from UCE state for READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions.	If the RN has transitioned to UD/UDP state from UCE state for READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions.	Active RN	This check is constructed only when partial_cache states are enabled at RN (svt_chi_node_configuration partial_cache_line_states_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	ordering check	new_req_before_compdbid_resp_for_copyback_to_same_cacheline_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.	Check that a request to a cache line is issued when there are no outstanding Copyback transactions that are expecting CompDBIDResp. An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.	A request flit is received and there are no pending Copybacks to the same address that are yet to receive CompDBIDResp.	A request flit is received and there is an outstanding Copyback to the same address which is yet to receive CompDBIDResp.	Passive RN-F	This check is applicable for all the Copyback transactions except WriteEvictorEvict transaction which are introduced in CHI ISSUE E. Similar kind of check for WriteEvictorEvict transaction is new_req_before_comp_or_compdbid_resp_for_copyback_writes_with_optional_data_to_same_cacheline_check. When the marco SVT_CHI_ISSUE_F_ENABLE is defined and svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_F or later, this check will look at the outstanding copyback write transaction with CAH set to 0, however the check new_req_before_comp_or_compdbid_resp_for_copyback_with_cah_set_and_to_same_cacheline_check will look at the outstanding copyback write transaction with CAH set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpmakeinvalid_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp has valid cache state for SnpMakeInvalid transaction. The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	Final cache state in the SnpResp of a SnpMakeInvalid transaction is set to I.	Final cache state in the SnpResp of a SnpMakeInvalid transaction is set to UC, UD, SC or SD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleaninvalid_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanInvalid transaction. The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	SCENARIO 1 : Final cache state in the SnpResp of a SnpCleanInvalid transaction is set to I. SCENARIO 2 : Final cache state in the SnpRespData of a SnpCleanInvalid transaction is set I.	SCENARIO 1 : Final cache state in the SnpResp of a SnpCleanInvalid transaction is set to UC, UD, SC or SD. SCENARIO 2 : Final cache state in the SnpRespData of a SnpCleanInvalid transaction is set to UC, UD, SC or SD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleanshared_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanShared transaction. The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.	SCENARIO 1 : Final cache state in the SnpResp of a SnpCleanShared transaction is set to UC, SC or I. SCENARIO 2 : Final cache state in the SnpRespData of a SnpCleanShared transaction is set UC, SC or I.	SCENARIO 1 : Final cache state in the SnpResp of a SnpCleanShared transaction is set to UD or SD. SCENARIO 2 : Final cache state in the SnpRespData of a SnpCleanShared transaction is set UD or SD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpunique_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpUnique transaction. The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	SCENARIO 1 : Final cache state in the SnpResp of a SnpUnique transaction is set to I. SCENARIO 2 : Final cache state in the SnpRespData of a SnpUnique transaction is set I.	SCENARIO 1 : Final cache state in the SnpResp of a SnpUnique transaction is set to UC, UD, SC or SD. SCENARIO 2 : Final cache state in the SnpRespData of a SnpUnique transaction is set UC, UD, SC or SD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpshared_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpShared transaction. The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.	SCENARIO 1 : Final cache state in the SnpResp of a SnpShared transaction is set to SC or I. SCENARIO 2 : Final cache state in the SnpRespData of a SnpShared transaction is set to SD, SC or I.	SCENARIO 1 : Final cache state in the SnpResp of a SnpShared transaction is set to UC, UD or SD. SCENARIO 2 : Final cache state in the SnpRespData of a SnpShared transaction is set to UC or UD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpclean_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpClean transaction. The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.	SCENARIO 1 : Final cache state in the SnpResp of a SnpClean transaction is set to SC or I. SCENARIO 2 : Final cache state in the SnpRespData of a SnpClean transaction is set to SD, SC or I.	SCENARIO 1 : Final cache state in the SnpResp of a SnpClean transaction is set to UC, UD or SD. SCENARIO 2 : Final cache state in the SnpRespData of a SnpClean transaction is set to UC or UD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snponce_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpOnce transaction. The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.	SCENARIO 1 : Final cache state in the SnpResp of a SnpOnce transaction is set to UC, SC or I. SCENARIO 2 : Final cache state in the SnpRespData of a SnpOnce transaction is set to UC, SC, UD, SD or I.	Final cache state in the SnpResp of a SnpOnce transaction is set to UD or SD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpmakeinvalid_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.	Check that the associated SnpResp packet has valid resp_err value for SnpMakeInvalid transaction. The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.	SCENARIO 1: RespErr field in SnpResp of a SnpMakeInvalid transaction is set to OK or NDERR. SCENARIO 2: RespErr field in SnpRespData of a SnpMakeInvalid transaction is set to OK or DERR.	SCENARIO 1: RespErr field in SnpResp of a SnpMakeInvalid transaction is set to EXOK or DERR. SCENARIO 2: RespErr field in SnpRespData of a SnpMakeInvalid transaction is set to EXOK or NDERR.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleaninvalid_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanInvalid transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.	SCENARIO 1: RespErr field in SnpResp of a SnpCleanInvalid transaction is set to OK or NDERR. SCENARIO 2: RespErr field in SnpRespData of a SnpCleanInvalid transaction is set to OK or DERR.	SCENARIO 1: RespErr field in SnpResp of a SnpCleanInvalid transaction is set to EXOK or DERR. SCENARIO 2: RespErr field in SnpRespData of a SnpCleanInvalid transaction is set to EXOK or NDERR.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleanshared_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanShared transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.	SCENARIO 1: RespErr field in SnpResp of a SnpCleanShared transaction is set to OK or NDERR. SCENARIO 2: RespErr field in SnpRespData of a SnpCleanShared transaction is set to OK or DERR.	SCENARIO 1: RespErr field in SnpResp of a SnpCleanShared transaction is set to EXOK or DERR. SCENARIO 2: RespErr field in SnpRespData of a SnpCleanShared transaction is set to EXOK or NDERR.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpunique_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpUnique transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.	SCENARIO 1: RespErr field in SnpResp of a SnpUnique transaction is set to OK or NDERR. SCENARIO 2: RespErr field in SnpRespData of a SnpUnique transaction is set to OK or DERR.	SCENARIO 1: RespErr field in SnpResp of a SnpUnique transaction is set to EXOK or DERR. SCENARIO 2: RespErr field in SnpRespData of a SnpUnique transaction is set to EXOK or NDERR.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpshared_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpShared transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.	SCENARIO 1: RespErr field in SnpResp of a SnpShared transaction is set to OK or NDERR. SCENARIO 2: RespErr field in SnpRespData of a SnpShared transaction is set to OK or DERR.	SCENARIO 1: RespErr field in SnpResp of a SnpShared transaction is set to EXOK or DERR. SCENARIO 2: RespErr field in SnpRespData of a SnpShared transaction is set to EXOK or NDERR.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpclean_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.5 Other transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpClean transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.	SCENARIO 1: RespErr field in SnpResp of a SnpClean transaction is set to OK or NDERR. SCENARIO 2: RespErr field in SnpRespData of a SnpClean transaction is set to OK or DERR.	SCENARIO 1: RespErr field in SnpResp of a SnpClean transaction is set to EXOK or DERR. SCENARIO 2: RespErr field in SnpRespData of a SnpClean transaction is set to EXOK or NDERR.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snponce_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpOnce transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.	SCENARIO 1: RespErr field in SnpResp of a SnpOnce transaction is set to OK or NDERR. SCENARIO 2: RespErr field in SnpRespData of a SnpOnce transaction is set to OK or DERR.	SCENARIO 1: RespErr field in SnpResp of a SnpOnce transaction is set to EXOK or DERR. SCENARIO 2: RespErr field in SnpRespData of a SnpOnce transaction is set to EXOK or NDERR.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_snprspdata_flit_with_snp_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.	Check that the Transaction ID, SourceID and TargetID fields are set correctly in SnpResp Data flits. The TgtID must be set to the the SrcID of the Snoop request. The TxnID must be set to the same value as the TxnID of the Snoop request.	Scenario 1: A SnpRespData is received whose TgtID and TxnID match with the SrcID and TxnID of one of the outstanding Snoop requests. Scenario 2: In a CHI-B or later system, a SnpRespDataFwded response is received whose TgtID and TxnID match with the SrcID and TxnID of one of the outstanding Forward type Snoop requests.	Scenario 1: A SnpRespData is received but there are no Snoop requests whose SrcID and TxnID match with the TgtID and TxnID of the SnpRespData flit. Scenario 2: In a CHI-B or later system, a SnpRespDataFwded response is received but there are no Forward type Snoops SrcID and TxnID match with the TgtID and TxnID of the SnpRespDataFwded flit.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_snprsp_flit_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.	Check that the Transaction ID, SourceID and TargetID fields are set correctly in Snoop response flits. The TgtID must be set to the the SrcID of the Snoop request. The TxnID is set to the same value as the TxnID of the Snoop request.	A SnpResp is observed corresponding to one of the outstanding Snoop requests at the RN	A SnpResp is observed but there are no outstanding Snoop requests with matching SourceID and TxnID values	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeevict_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteEvict transaction. The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state of the Write data flits in a WriteEvict transaction is UC, SC or I.	Final cache state of the Write data flits in a WriteEvict transaction is UD or SD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeclean_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteClean transaction. The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state of the Write data flits in a WriteCleanPtl transaction is either UD or I.	Final cache state of the Write data flits in a WriteCleanPtl transaction is either UC, SC or SD.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeback_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteBack transaction. The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state of the Write data flits in a WriteBackPtl transaction is either UD or I. Final cache state of the Write data flits in a WriteBackPtl transaction is either UC or SC or SD and byte_enable is set to all 1's.	Final cache state of the Write data flits in a WriteBackPtl transaction is UC, SC or SD and byte_enable is not set to all 1's.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_dat_flit_type_for_snp_xact_check	ARM-IHI0050E.b: 4.5 Response types	Data flit type must be set to one of the permitted values for the Request	Check that the data type of the flit matches the expected value. Data flit type must be set to one of the permitted values for the Snoop Request	SCENARIO 1: A SnpRespData or SnpRespDataPtl response is observed for a non-forward type Snoop request. SCENARIO 2: A SnpRespDataFwded, CompData or SnpRespDataPtl response is observed for a forward type Snoop request.	SCENARIO 1: A data response other than SnpRespData and SnpRespDataPtl is observed for a non-forward type Snoop request. SCENARIO 2: A data response other than SnpRespDataFwded, CompData and SnpRespDataPtl is observed for a forward type Snoop request.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_cbwrdata_flit_for_xact_check	ARM-IHI0050E.b: 4.5.2 WriteData response	Data flit type must be set to one of the permitted values for the Request	Check that the data type of the flit matches the expected value. COPYBACKWRDATA is valid only in case of WriteBack, WriteClean and WriteEvict type transactions	A CopyBackWrData flit is received for a WriteBack, WriteClean or WriteEvict transaction.	A CopyBackWrData flit is received for a transaction type other than WriteBack, WriteClean and WriteEvict.	Passive RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	new_snp_req_before_compack_of_coherent_xact_which_received_comp_to_same_cacheline_check	ARM-IHI0050E.b: 4.11 Hazard conditions	The completer can send out the Snoop requests to an RN-F only when there are no outstanding coherent transactions from that particular RN-F targetting the same cache line that received completion response and has not yet received the CompAck/WrData	Check that for an RN-F node, Snoop request is observed when there are no outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck or Write Data. Once a completion is received for a transaction, the completer must not send a snoop request to the same cache line until it receives: A CompAck for any Read and Dataless requests except for ReadOnce* and ReadNoSnp. A WriteData response for CopyBack and Atomic requests. For WriteUnique, a WriteData response and, if applicable, CompAck.	A Snoop request flit is received and there are no outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck/WrData.	A Snoop request flit is received and there are outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck/WrData.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	new_snp_req_before_completion_of_previous_snp_xact_to_same_cacheline_check	ARM-IHI0050E.b: 4.11 Hazard conditions	The completer can send out the Snoop requests to an RN-F only when there are no outstanding Snoop transactions targetting the same cache line to that particular RN-F	Check that for an RN-F node, Snoop request is observed when there are no outstanding Snoop transactions targetting the same cache line.	A Snoop request flit is received and there are no outstanding Snoop transactions targetting the same cache line.	A Snoop request flit is received and there are one or more outstanding Snoop transactions targetting the same cache line.	RN-F		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_order_of_dvmop_rspflits_check	ARM-IHI0050E.b: 2.3.7 DVM transactions	Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete	Check that the order of the responses sent by the Completer is correct in case of DVMOp transactions. Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete. When the spec_revision is ISSUE_D or later and the DVMOp is a Non-sync DVMOp, then the interconnect is permitted but not required to wait for WriteData before sending the Comp. Currently VIP does not support early COMP support for DVM transaction.	A Comp response is received after the DBIDResp/WriteData flit.	A Comp response is received before DBIDResp/WriteData flit.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_snpdvmop_part_check	ARM-IHI0050E.b: 8.1.3 Flow control	SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID	Check that both parts of a SnpDVMOp request are received at the RN. SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID	At the end of the simulation, there are no SnpDVMOp transactions for which only one part of the SnpDVMOp request was received.	At the end of the simulation, there are one or more SnpDVMOp transactions for which only one part of the SnpDVMOp request was received.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	single_outstanding_snpdvmop_per_txn_id_check	ARM-IHI0050E.b: 2.4 Transaction identifier fields	The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID	Check that the TxnID of a SnpDVMOp must be unique for a given Requester. The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID	A SnpDVMOp request is received and there are no outstanding SnpDVMOp requests with the same TxnID value.	A SnpDVMOp request is received but there is already an outstanding SnpDVMOp request with the same TxnID value.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	single_outstanding_snpdvmop_sync_check	ARM-IHI0050E.b: 8.1.3 Flow control	Only one SnpDVMOpSync transaction can be outstanding from an MN to an RN.	Check that there is only one outstanding DVMOp sync transaction at a given point in time. Only one SnpDVMOp(Sync) transaction can be outstanding from an MN to an RN.	A SnpDVMOp(Sync) request is received and there are no outstanding SnpDVMOp(Sync) requests at the RN.	A SnpDVMOp(Sync) request is received but there are already outstanding SnpDVMOp(Sync) requests at the RN.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	valid_resp_err_status_for_dvmop_xact_check	ARM-IHI0050E.b: 9.4.5 Other transactions	For DVMOP transaction, resp_err_status field of the associated Comp RSP flit must have one of the following values: 1NORMAL_OKAY 2NON_DATA_ERROR 3in case of chi_spec_revision >= ISSUE_B,DATA_ERROR.	Check that the comp response has valid resp_err value for DVMop transaction. The associated Comp response should take one of the following resp_err values: 1)NORMAL_OKAY 2)NON_DATA_ERROR 3)in case of svt_chi_node_configuration :: chi_spec_revision >= ISSUE_B,DATA_ERROR for DVMop transaction.	If svt_chi_node_configuration :: chi_spec_revision>=ISSUE_B RespErr field in the Comp response of a DVMOp transaction is set to NORMAL_OKAY or NON_DATA_ERROR or DATA_ERROR. If svt_chi_node_configuration :: chi_spec_revision==ISSUE_A RespErr field in the Comp response of a DVMOp transaction is set to NORMAL_OKAY or NON_DATA_ERROR.	If svt_chi_node_configuration :: chi_spec_revision>=ISSUE_B RespErr field in the Comp response of a DVMOp transaction is set to EXCLUSIVE_OKAY. If svt_chi_node_configuration :: chi_spec_revision==ISSUE_A RespErr field in the Comp response of a DVMOp transaction is set to EXCLUSIVE_OKAY or DATA_ERROR.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_rspflit_for_dvmop_check	ARM-IHI0050E.b: 4.5.1 Completion response	A Comp response, with the Resp field set to zero, is always used for DVM transaction completion	Check that only Comp Response is used for DVMOp transactions, and not CompDBIDResp When the spec_revision is ISSUE_D or later the Completer is permitted to opportunistically combine Comp and DBIDResp into CompDBIDResp response. This is applicable only in case of early comp support. Currently VIP does not support early COMP support for DVM transaction. A Comp response, with the Resp field set to zero, is always used for Barrier and DVM transaction completion.	A Comp response is received for a DVMOp transaction.	A CompDBIDResp flit is received for a DVMOp transaction.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpdvmop_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.5 Other transactions	The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.	Check that the associated SnpResp packet has valid resp_err value for SnpDVMop transaction. The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.	RespErr field in SnpResp of a SnpDVMOp transaction is set to OK or NDERR.	RespErr field in SnpResp of a SnpDVMOp transaction is set to EXOK or DERR.	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpresp_for_snpdvmop_sync_only_after_completion_of_prior_snpdvmop_check	ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow	Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no prior SnpDVMOp transactions that are yet to receive a SnpResp from the RN. Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	A SnpResp flit is observed for a SnpDVMOp(sync) and there aren't any prior SnpDVMOp transactions that are yet to receive SnpResp.	A SnpResp flit is observed for a SnpDVMOp(sync) while there are prior SnpDVMOp transactions that are yet to receive SnpResp.	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1)	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpresp_for_snpdvmop_sync_only_after_completion_of_all_non_dvm_sync_check	ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow	Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no outstanding DVMOp transactions at the RN. Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	A SnpResp flit is observed for a SnpDVMOp(sync) and there are no outstanding DVMOp transactions at the RN	A SnpResp flit is observed for a SnpDVMOp(sync) while there are outstanding DVMOp transactions at the RN	Passive RN-F and Passive RN-D	This is an optional check and is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1) and svt_chi_node_configuration :: snp_dvmop_sync_response_policy is set to WAIT_FOR_ALL_OUTSTANDING_DVM_NON_SYNC_TO_COMPLETE.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_snprsp_for_snpdvmop_check	ARM-IHI0050E.b: 8.1.3 Flow control	An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction.	Check that the SnpDVMOpResp is observed only after both SnpDVMOp request packets. An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction. The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively.	A SnpResp flit is observed for a SnpDVMOp transaction, after both parts of the SnpDVMOp request are received	A SnpResp flit is observed for a SnpDVMOp transaction, while only one part of the SnpDVMOp request is received	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_snpdvmop_req_part_num_check	ARM-IHI0050E.b: 8.2 DVM Operation types	Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.	Check that the part numbers of the SnpDVMOp request packets are set correctly. Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.	SnpDVMOp_Part1 and SnpDVMOp_Part2 request flits corresponding to a DVM Snoop transaction are received and the part numbers are set correctly.	Two SnpDVMOp_Part request flits corresponding to a DVM Snoop transaction are received but the part numbers of the two parts are the same.	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	single_outstanding_dvmop_sync_request_check	SYNOPSYS DEFINED	There can only be one outstanding DVMOpSync transaction from an RN at any point in time.	Check that there are no outstanding DVMOp(Sync) transactions when a DVMOp(Sync) request is received. SYNOPSYS DEFINED Not more than one DVMOp(Sync) transaction is expected to be outstanding from an RN at any given point in time, when svt_chi_node_configuration :: allow_multiple_dvm_sync_oustanding_xacts is set to 0.	A DVMOp(sync) request is received and there are no outstanding DVM(Sync) requests at the RN.	A DVMOp(sync) request is received but there already is an outstanding DVM(Sync) requests at the RN.	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1) and svt_chi_node_configuration :: allow_multiple_dvm_sync_oustanding_xacts is set to 0.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	unused_bits_in_dvm_write_data_check	ARM-IHI0050E.b: 8.1.4 DVMOp field value restrictions	All the unused bits in the write data of a DVMOp transaction must be set to zero.	Check that the unused bits in the Write data of a DVMOp transaction are set to zero.	All the bits in the DVMOp write data that are not valid or unused are set to zero.	SCENARIO 1: Bits corresponding to data[55:51] are set to a non-zero values. SCENARIO 2: VA Valid is 0, but the bits corresponding to data[50:4] are set to non-zero values. SCENARIO 3: VA Valid is set to 1 in the DVMOp transaction request that is Invalidate by PA, but bits corresponding to data[50:(44-2)] are set to non-zero values. SCENARIO 4: VA Valid is set to 1 in the DVMOp transaction request that is not Invalidate by PA, but bits corresponding to data[50:(((44 == 44)?49:((44 == 45)?51:53))-2)] are set to non-zero values. SCENARIO 5: In case of CHI-A, bits corresponding to data[63:56] are set to non-zero values. SCENARIO 6: In case of CHI-B or greater revisions, VMID Valid in the DVMOp transaction request is set to 0 but the bits corresponding to data[63:56] are set to non-zero values. SCENARIO 7: In case of CHI-D or earlier revisions, the bits corresponding to data[3:0] are set to non-zero values. SCENARIO 8: In case of CHI-E or greater revisions, for a DVM operation that is not Invalidate by VA type TLBI, the bits corresponding to data[3:0] are set to non-zero values.	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	expected_dvmop_sync_request_check	ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow	All previous DVMOp requests whose completion needs to be guaranteed by the DVMOpSync must have received a Comp response before the RN can send a DVMOpSync.	Check that there are no outstanding DVMOp(Non-sync) transactions when a DVMOp(Sync) request is received. All previous DVMOp requests whose completion needs to be guaranteed by the DVMOp(Sync) must have received a Comp response before the RN can send a DVMOp(Sync).	When svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_ALL_NON_SYNC_TO_COMPLETE and a DVMOp(sync) request is received and there are no outstanding DVM(Non-sync) requests at the RN. When svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_NON_SYNC_FROM_SAME_LPID_TO_COMPLETE and a DVMOp(sync) request is received and there are no outstanding DVM(Non-sync) requests with the same LPID at the RN.	When svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_ALL_NON_SYNC_TO_COMPLETE and a DVMOp(sync) request is received but there are one or more outstanding DVM(Non-sync) requests at the RN. svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_NON_SYNC_FROM_SAME_LPID_TO_COMPLETE and a DVMOp(sync) request is received but there are one or more outstanding DVM(Non-sync) requests with the same LPID at the RN.	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1) and svt_chi_node_configuration :: dvm_sync_transmission_policy is set to a value other than DO_NOT_WAIT_FOR_NON_SYNC_TO_COMPLETE.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	barrier xact	normal_non_cacheable_or_device_writes_between_barriers_check	ARM-IHI0050A: 7.5.1	It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.	Check that Normal Non-cacheable or Device type writes were received, prior to the current Barrier and after the previous Barrier transaction It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.	A Barrier transaction is received and there were normal,non-cacheable or Device type Writes seen before the Barrier, and after the previous Barrier if any.	A Barrier transaction is received and there were no normal,non-cacheable or Device type Writes seen before the Barrier, and after the previous Barrier if any.	Passive RN	This check is constructed only when Barrier support is enabled in the passive RN node (svt_chi_node_configuration :: barrier_enable == 1)	WARNING	svt_chi_protocol_err_check
CHI Protocol Layer	barrier xact	comp_received_for_normal_non_cacheable_or_device_writes_before_barrier_check	ARM-IHI0050A: 7.5 Barriers	An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request	Check that there are no outstanding Normal Non-cacheable or Device type writes, that are targeting an HN-I, which haven't received a Comp Repsonse, before a Barrier is issued by an RN. An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request.	A Barrier is received and there are no pending normal,non-cacheable or Device type Writes to the same address that are yet to receive Comp Response	A Barrier is received and there are one or more pending normal,non-cacheable or Device type Writes to the same address that are yet to receive Comp Response	Passive RN	This check is constructed only when Barrier support is enabled in the passive RN node (svt_chi_node_configuration :: barrier_enable == 1)	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	expected_tgt_id_in_rn_xact_check	ARM-IHI0050E.b: 3.3.1 Target ID determination for Request messages	The Target ID in the request sent by the RN must be set as per the SAM, when target ID remapping is not expected at the Interconnect	Check that the Target ID field in the transaction request is set to the node ID of the HN as per the RN SAM. When Target ID is not expected to be remapped at the Interconnect, RN must program the tgt_id of the request flit to the correct value as per the SAM.	A request is received with the tgt_id set to the expected HN node ID.	A request is received with the tgt_id set to a value other than the expected HN node ID.	Passive RN	This check is applicable only when svt_chi_system_configuration :: expect_target_id_remapping_by_interconnect is set to 0.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Compack timing	owo_writeunique_compack_timing_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	CompAck for an OWO WriteUnique must be sent once the Comp for all previous OWO WriteUnique transactions are received and comp When chi_spec_revision is less than or equal to ISSUE_C/Comp or DBIDResp or CompDBIDReespWhen chi_spec_revision is ISSUE_D or later for current WriteUnique transaction is received.	Check that the CompAck response for an ordered WriteUnique transaction is sent only afer following conditions are met: Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transaction are received. When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Comp response for the current OWO WriteUnique is received.	CompAck response for an ordered WriteUnique transaction is sent only after following conditions are met: Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transactions are received. When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Comp response for the current OWO WriteUnique is received	Check will fail for any one or both of the below cases: CompAck response for an ordered WriteUnique transaction is sent before Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transactions are received. When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, CompAck response for an ordered WriteUnique transaction is sent before DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, CompAck response for an ordered WriteUnique transaction is sent before Comp response for the current OWO WriteUnique is received.	Passive RN	This check is applicable only when svt_chi_node_configuration :: streaming_ordered_writeunique_enable set to 1 and svt_chi_node_configuration :: num_req_order_streams set to 1. This check is performed only on OWO WriteUnique transactions for which order field set to REQ_ORDERING_REQUIRED and exp_comp_Ack is set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	new_req_before_completion_of_previous_cmo_xacts_to_same_cacheline_check	ARM-IHI0050E.b: 4.2.2 Dataless transactions	Transaction intended for a particular address that can allocate data in Requester caches must not be sent to the interconnect before a previous CMO sent to the same address has completed.	Check that an allocating read request is issued when there are no outstanding CMO transactions to the same cache line.	An allocating read request flit is received and there are no pending CMOs to the same cache line.	An allocating read request flit is received and there is an outstanding CMO to the same cache line.	Passive RN	Propogation of CMOs to Slave nodes is currently not supported by the VIP. Therefore, this check is not applicable for SN.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	cmo_xact_before_completion_of_previous_xacts_to_same_cacheline_check	ARM-IHI0050E.b: 4.2.2 Dataless transactions	A CMO intended for a particular address must not be sent before all previous requests, targeting the same cacheline, that can allocate data in the requester cache ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique are complete.	Check that a CMO request is issued when there are no outstanding transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches: ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique	A CMO request flit is received and there are no pending transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches: ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique	A CMO request flit is received and there are one or more pending transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches: ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique	Passive RN	Propagation of CMOs to Slave nodes is currently not supported by the VIP. Therefore, this check is not applicable for SN.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeunique_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteUnique transaction. The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Write data flits of a WriteUnique transaction is set to I.	Final cache state in the Write data flits of a WriteUnique transaction is set to a value other than I.	Passive RN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	expected_compack_check	ARM-IHI0050E.b: 2.3 Transaction structure	CompAck must be observed only after Comp or all CompData responses are received.	Check that the CompAck response is sent only afer Comp* or CompData response. CompAck, if part of the transaction, must be observed only after Comp* or CompData responses are received.	A CompAck response is received for a transaction with ExpCompAck set and whose data phase is complete. For OWO Write transactions(svt_chi_base_transaction :: exp_comp_ack set to 1 and svt_chi_base_transaction :: order_type set to REQ_ORDERING_REQUIRED),: When svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Compack must be send out after reception of Comp response. When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, Compack must be send out after reception of one of the response Comp or DBIDResp or CompDBIDResp. In case of WriteEvictorEvict transaction, the check will pass when CompAck response is received after the reception of Comp response. In case of Copyback transactions with cah set to 1, the check will pass when CompAck response is received after the reception of Comp response.	A CompAck response is received for a transaction with ExpCompAck set but whose data phase is not yet complete. For OWO Write transactions(svt_chi_base_transaction :: exp_comp_ack set to 1 and svt_chi_base_transaction :: order_type set to REQ_ORDERING_REQUIRED),: When svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Compack send out before reception of Comp response. When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, Compack received before reception of one of the responses Comp or DBIDResp or CompDBIDResp. In case of WriteEvictorEvict transaction, the check will fail when CompAck response is received before the reception of any response from the Completer. In case of Copyback transactions with cah set to 1, the check will fail when CompAck response is received before the reception of any response from the Completer.	Passive RN	The data phase status can be known by looking at the data_status field in the transaction handle: data_status == INITIAL implies the data transfer hasn't yet begun for the transaction data_status == PARTIAL_ACCEPT implies the data transfer for the transaction is in progress data_status == ACCEPT implies the data transfer is complete.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_compack_rsp_flit_check	ARM-IHI0050E.b: 2.6.1 Read transactions	The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively. The TxnID is set to the same value as the DBID value provided in the read data response.	Check that the TransactionID, TargetID and SourceID fields are set correctly in the CompAck response. The TgtID and SrcID must be set to the the SrcID and TgtID of the read data/comp/dbidresp/compdbidresp respectively. The TxnID is set to the same value as the DBID value provided in the read data/comp/dbidresp/compdbidresp response.	A CompAck response is received and there's an outstanding transaction with ExpCompAck asserted, whose Source ID, Target ID and DBID match with the TargetID, Source ID and TxnID of the CompAck respectively.	A CompAck response is received when there are no outstanding transactions with expcompack asserted, whose Source ID, Target ID and DBID match with the TargetID, Source ID and TxnID of the CompAck respectively.	Passive RN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	single req order stream	single_req_order_stream_check	ARM-IHI0050E.b: 2.8 Ordering	The ordering requirements must be met for preceding active transactions with ReqOrder asserted before initiating next ordered transaction	Check that single ordered stream of requests from RN are ordered as per Request Ordering rules. Request Ordering Rules update from CHI Issue D onwards: In CHI Issue C or earlier, the Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range and includes the guarantee of Request Order. In CHI Issue D or later, there will be no ordering guarantees between two ordered transactions from the same source that have different ordering requirements. In other words, Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range, but doesn’t include the guarantee of Request Order.	In CHI Issue C or earlier: When a new Ordered transaction is observed and there are either no preceding Ordered transactions or there are preceding Ordered transactions whose ordering conditions are already met. In CHI Issue D or later: When a new Request_Ordered transaction is observed and there are either no preceding Request_Ordered transactions or there are preceding Request_Ordered transactions whose ordering conditions are already met. When a new Endpoint_Ordered transaction is observed and there are either no preceding Endpoint_Ordered transactions or there are preceding Endpoint_Ordered transactions whose ordering conditions are already met.	In CHI Issue C or earlier: When a new Ordered transaction is observed and there are preceding Ordered transactions whose ordering requirements are not yet met. In CHI Issue D or later: When a new Request_Ordered transaction is observed and there are preceding Request_Ordered transactions whose ordering requirements are not yet met. When a new Endpoint_Ordered transaction is observed and there are preceding Endpoint_Ordered transactions whose ordering requirements are not yet met.	Passive RN	svt_chi_node_configuration :: num_req_order_streams should reflect the number of request order streams that the RN has. The passive RN agent performs this check only when the number of request order streams is one, ie, svt_chi_node_configuration :: num_req_order_streams is set to 1. This is because the stream ID to which a given transaction belongs is not transmitted on the interface. So it is important to make sure that the passive RN agent is configured appropriately for this. The passive RN agent can track the transactions those have the ReqOrder information transmitted on the interface, that is available through svt_chi_base_transaction :: order_type. Note that the CopyBack type transactions do not transmit the ReqOrder information on the interface through REQ VC Flit.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	expected_remapped_tgt_id_in_response_check	ARM-IHI0050E.b: 3.3.1 Target ID determination for Request messages	The Target ID in the request must be remapped correctly as per the SAM and the Source ID of the subsequent response flits must be set to the remapped Target ID value	Check that the Target ID is remapped correctly at the Interconnect. When Target ID remapping is expected at the Interconnect, the Target ID field in the received request must be remapped correctly as per the SAM. This check is performed when target ID is remapped by the Interconnect and the SAM is specified correctly in the system configuration.	Remapped Target ID received in the response from the Interconnect matches the HN node ID as per the SAM.	Remapped Target ID received in the response from the Interconnect does not match the HN node ID as per the SAM.	RN	This check is applicable only when svt_chi_system_configuration :: expect_target_id_remapping_by_interconnect and svt_chi_system_configuration :: rn_sam_specified_with_exp_tgt_id_remap_at_icn_enabled are set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_pcrdgrant_check	ARM-IHI0050E.b: 2.11 Request Retry	PcrdGrant is not seen without any outstanding transaction	Checks PcrdGrant is not seen without any outstanding transaction.	PcrdGrant is seen and there are outstanding transaction.	PcrdGrant is seen without any outstanding transaction.	RN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeunique_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUnique transaction.	Check that the associated response and data packets has valid resp_err value for WriteUnique transaction. The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUnique transaction.	The RespErr field in the associated Write data flits of a WriteUnique transaction are as per Table 9-5 in the CHI Specification. The RespErr field in the associated response flits of a WriteUnique transaction are as per Table 9-4 in the CHI Specification.	The RespErr field in the associated Write data flits of a WriteUnique transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteUnique transaction violate the legal values specified in Table 9-4 in the CHI Specification.	RN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readonce_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadOnce transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadOnce transaction. The cache state in the associated CompData flits of a ReadOnce transaction should indicate a valid value when the RespErr field does not indicate any errors.	In case of a CHI-A node: final cache state in the CompData of a ReadOnce transaction is set to I. In case of a CHI-B or later node: final cache state in the CompData of a ReadOnce transaction is set to I or UC when DMT is not used. final cache state in the CompData of a ReadOnce transaction is set to UC when DMT is used.	In case of a CHI-A node: final cache state in the CompData of a ReadOnce transaction is set to a value other than I. In case of a CHI-B or later node: final cache state in the CompData of a ReadOnce transaction is set to a value other than I or UC when DMT is not used. final cache state in the CompData of a ReadOnce transaction is set to a value other than UC when DMT is used.	RN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readonce_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The associated compdata packet's resp_err field should not take EXOK value for ReadOnce transaction.	Check that the associated Compdata packet has valid resp_err value for ReadOnce transaction. The associated compdata packet's resp_err field should not take EXOK value for ReadOnce transaction.	The RespErr field in the associated Compdata flits of a ReadOnce transaction are as per Table 9-2 in the CHI Specification.	The RespErr field in the associated Compdata flits of a ReadOnce transaction are set to EXOK.	RN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makeinvalid_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response packet of a MakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a MakeInvalid transaction. The cache state in the associated comp response of a MakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Comp response of a MakeInvalid transaction is set to I.	Final cache state in the Comp response of a MakeInvalid transaction is set to a value other than I.	RN, Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleaninvalid_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response packet of a CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a CleanInvalid transaction. The cache state in the associated comp response of a CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Comp response of a CleanInvalid transaction is set to I.	Final cache state in the Comp response of a CleanInvalid transaction is set to a value other than I.	RN, Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleanshared_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response packet of a CleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a CleanShared transaction. The cache state in the associated comp response of a CleanShared transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Comp response of a CleanShared transaction is set to UC, SC or I.	Final cache state in the Comp response of a CleanShared transaction is set to UD or SD.	RN, Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makeinvalid_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp response packet's resp_err field should not take EXOK value for MakeInvalid transaction.	Check that the associated Comp response packet has valid resp_err value for MakeInvalid transaction. The associated comp response packet's resp_err field should not take EXOK value for MakeInvalid transaction.	The RespErr field in the associated Comp response flits of a MakeInvalid transaction are as per Table 9-3 in the CHI Specification.	The RespErr field in the associated Comp response flits of a MakeInvalid transaction are set to EXOK.	RN, Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleaninvalid_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp response packet's resp_err field should not take EXOK value for CleanInvalid transaction.	Check that the associated Comp response packet has valid resp_err value for CleanInvalid transaction. The associated comp response packet's resp_err field should not take EXOK value for CleanInvalid transaction.	The RespErr field in the associated Comp response flits of a CleanInvalid transaction are as per Table 9-3 in the CHI Specification.	The RespErr field in the associated Comp response flits of a CleanInvalid transaction are set to EXOK.	RN, Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleanshared_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp response packet's resp_err field should not take EXOK value for CleanShared transaction.	Check that the associated Comp response packet has valid resp_err value for CleanShared transaction. The associated comp response packet's resp_err field should not take EXOK value for CleanShared transaction.	The RespErr field in the associated Comp response flits of a CleanShared transaction are as per Table 9-3 in the CHI Specification.	The RespErr field in the associated Comp response flits of a CleanShared transaction are set to EXOK.	RN, Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_resp_for_data_packet_check	ARM-IHI0050E.b: 4.5 Response types	The Resp field in a response must have the same value for every packet of a data message regardless of whether or not there is an error condition.	Check that the resp field has the same value for all data flits of a multi-flit data transfer . The resp field in a response must have the same value for every packet of a data message regardless of whether or not there is an error condition.	The Resp field in the data flits corresponding to a transaction are all set to the same value.	The Resp field in the data flits corresponding to a transaction are not set to the same value.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	single_xact_mix_ok_exok_response_check	ARM-IHI0050E.b: 9.2 Error response fields	A single transaction is not permitted to mix OK and EXOK responses.	Check that a single transaction does not mix OK and EXOK responses within its data packets . A single transaction is not permitted to mix OK and EXOK responses.	The RespErr field in the data flits corresponding to a transaction are all set to the same value.	The RespErr field in the data flits corresponding to a transaction are not set to the same value.	RN and passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit field	valid_ccid_in_dat_flit_check	ARM-IHI0050E.b: 2.10.6 Critical Chunk Identifier	CCID of all the data packets belonging to a transaction must be the same and equal to addr[5:4] of the corresponding Request	Check that the CCID field value in the data flit is set correctly. CCID of all the data packets belonging to a transaction must be the same and equal to addr[5:4] of the corresponding Request.	The CCID field in the Data flit does not match with addr[5:4] of the corresponding transaction.	The CCID field in the Data flit are equal to addr[5:4] of the corresponding transaction.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	dbid_value_must_be_same_across_read_data_flits_check	ARM-IHI0050E.b: 2.5.9 Data Buffer ID	DBID must take the same value in all read data flits corresponding to a Read transaction with ExpCompAck set to 1	For a Read transaction, if the DBID is valid then the DBID field must take same value in all the corresponding read data flits. DBID is valid if ExpCompAck is set to 1 for the corresponding Read transaction.	A same DBID field value is observed in all the read data flits (CompData or DataSepResp) corresponding to a Read request with ExpCompAck set to 1.	A difference in DBID field value is observed across the read data flits (CompData or DataSepResp) corresponding to a Read request with ExpCompAck set to 1.	RN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	separate_dbidresp_and_comp_must_include_same_dbid_value_check	ARM-IHI0050E.b: 2.5 Details of transaction identifier fields	A Comp response message sent separate from a DBIDResp or DBIDRespOrd message for a Write transaction must include the same DBID field value in the Comp and DBIDResp or DBIDRespOrd message	A Comp response sent separate from a DBIDResp or DBIDRespOrd response for a write transaction (except Atomic transactions) must include the same DBID field value in the Comp and DBIDResp or DBIDRespOrd message. Applicable only in case of non-copyback Write transactions and non-copyback Combined Write plus CMO transactions as the copyback transactions always include a combined CompDBIDResp response. Applicable only if the Direct Write Data transfer is not exercised for the Write transaction.	A same DBID field value is observed in Comp and DBIDResp or DBIDRespOrd reponses for a non-copyback Write transaction or non-copyback Combined Write plus CMO transaction with separate comp and DBIDResp or DBIDRespOrd reponses.	A different DBID field value is observed in Comp and DBIDResp or DBIDRespOrd reponses for a non-copyback Write transaction or non-copyback Combined Write plus CMO transaction with separate comp and DBIDResp or DBIDRespOrd reponses.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	rsp_flit_dbid_check	ARM-IHI0050E.b: Table A-8 Response message field mappings	DBID field of the observed RSP flit must be valid	Check that the DBID field value of the following RSP flits is as follows. RSP flits: Comp/DBID/CompDBIDResp: DBID field must be unique for a given transaction and can be reused only after the transaction completes In case of WriteNoSnpZero and WriteUniqueZero transactions dbid field in Comp/DBID/COMPSBISREesp is inapplicable and can take any value.	For Dataless transactions with ExpCompAck asserted, the DBID field in the Comp response is unique and there are no other outstanding non-DMT and non-DCT transactions that have received the same DBID value. For Read transactions with ExpCompAck asserted, the DBID field in the RespSepData response is unique and there are no other outstanding non-DMT and non-DCT transactions that have received the same DBID value. For Write transactions(except WriteNoSnpZero and WriteUniqueZero), the DBID field in Comp (for Issue B or lower revisions) or DBIDResp or CompDBIDResp is unique and there are no other outstanding non-DMT and non-DCT transactions that have received the same DBID value.	For Dataless transactions with ExpCompAck asserted, the DBID field in the Comp response is not unique; there is already an outstanding non-DMT and non-DCT transaction with the same DBID value. For Read transactions with ExpCompAck asserted, the DBID field in the RespSepData response is not unique; there is already an outstanding non-DMT and non-DCT transaction with the same DBID value. For Write transactions(except WriteNoSnpZero and WriteUniqueZero), the DBID field in Comp (for Issue B or lower revisions) DBIDResp or CompDBIDResp is not unique; there is already an outstanding non-DMT and non-DCT transaction with the same DBID value.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readnosnp_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadNoSnp transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadNoSnp transaction. The cache state in the associated CompData flits of a ReadNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.	In case of a CHI-A node: final cache state in the CompData of a ReadNoSnp transaction is set to I. In case of a CHI-B or later node: final cache state in the CompData of a ReadNoSnp transaction is set to I or UC when DMT is not used. final cache state in the CompData of a ReadNoSnp transaction is set to UC when DMT is used.	In case of a CHI-A node: final cache state in the CompData of a ReadNoSnp transaction is set to a value other than I. In case of a CHI-B or later node: final cache state in the CompData of a ReadNoSnp transaction is set to a value other than I or UC when DMT is not used. final cache state in the CompData of a ReadNoSnp transaction is set to a value other than UC when DMT is used.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readnosnp_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Compdata packet has valid resp_err value for ReadNoSnp transaction. The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	The RespErr field in the associated Compdata flits of a ReadNoSnp transaction are as per Table 9-2 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the ReadNoSnp request was set to 1.	The RespErr field in the associated Compdata flits are set to EXOK but the Exclusive attribute in the ReadNoSnp request was set to 0.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_compdbid_flit_type_for_xact_check	ARM-IHI0050E.b: 4.5 Response types	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	Check that CompDBID Response flit is seen only in case of Write/CopyBack or AtomicStore transactions. The Response flit type must correspond to one of the permitted values depending on the type of the transaction	CompDBIDResp is received for a WriteNoSnp, WriteUnique, CopyBack or AtomicStore request.	CompDBIDResp is received for a Read, dataless, DVMop or AtomicLoad/Swap/Compare request.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_dbid_flit_type_for_xact_check	ARM-IHI0050E.b: 4.5 Response types	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	Check that DBID Response flit is seen only in case of non-Copyback Write transactions. The Response flit type must correspond to one of the permitted values depending on the type of the transaction	DBIDResp is received for a WriteNoSnp or WriteUnique request.	DBIDResp is received for a Copyback request.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_comp_flit_type_for_xact_check	ARM-IHI0050E.b: 4.5.1 Completion response	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	Check that Comp Response flit is seen only in case of non-Snoop transactions. The Response flit type must correspond to one of the permitted values depending on the type of the transaction	Comp response is received for a dataless, DVMOp, WriteEvictorEvict or a non-Copyback Write transaction.	Comp response is received for a Read or a Copyback transaction(except WriteEvictorEvict).	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	expected_rsp_flit_for_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The number of Response flits received for a transaction must match the number of responses, specified in the spec, for that transaction type.	Check that the transaction for which the coherent response is received has not already received a coherent response The number of Response flits received for a transaction must match the number of responses, specified in the spec, for that transaction type.	A response flit is received for one of the outstanding transactions which is yet to receive a coherent response.	A response flit is received for one of the outstanding transactions which has already received all applicable coherent responses (resp_status == ACCEPT).	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_rsp_flit_to_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The SrcID of the response flit must be match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request	Check that the Transaction ID, SourceID and TargetID fields are set correctly in the Response flits. The SrcID and TgtID of the response flit must match the TgtID and SrcID of the request while the Txn ID of the response flit must be the same as that of the Request	A response flit is received for one of the outstanding transactions which is yet to receive a coherent response.	A response flit is received but there are no outstanding transactions whose SrcID,TgtID and TxnID match the TgtID,SrcID and TxnID of the response.	RN and Passive SN	In case svt_chi_system_configuration :: expect_target_id_remapping_by_interconnect is set to 1, the SrcID of the response flit will not be compared with the TgtID of the outstanding requests at the RN.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	expected_num_read_data_flits_check	ARM-IHI0050E.b: 2.10.4 Data packetization	The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width	Check that the number of Read Data flits is equal to the expected value The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width	A Read Data flit is received for a Read transaction whose data phase is not yet complete (data_status is either INITIAL or PARTIAL_ACCEPT)	A Read Data flit is received for a Read transaction whose data phase is complete (data_status == ACCEPT)	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_read_dat_flit_with_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The SrcID of the Read data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request	Check that the Transaction ID, SourceID and TargetID fields are set correctly in Read Data flits. When SVT_CHI_ISSUE_B_ENABLE or SVT_CHI_ISSUE_C_ENABLE macro is not defined: The TgtID of the Read data flit must match the SrcID of the Request The SrcID of the Read data flit must match the TgtID of the Request The TxnID of the Read data flit must be the same as that of the Request When SVT_CHI_ISSUE_B_ENABLE or SVT_CHI_ISSUE_C_ENABLE macro is defined: For RN: The TgtID of the Read data flit must match the SrcID of the Request irrespective of spec revision For SN/HN: The TgtID of the Read data flit must match the SrcID of the Request for spec revision ISSUE_A For SN/HN: The TgtID of the Read data flit must match the ReturnNID of the Request for spec revision ISSUE_B or later For RN: The SrcID of the Read data flit must match the TgtID of the Request for ISSUE_A For RN: The HomeNID of the Read data flit must match the TgtID of the Request for ISSUE_B or later For SN/HN: The SrcID of the Read data flit must match the TgtID of the Request irrespective of spec revision For RN: The TxnID of the Read data flit must be the same as that of the Request irrespective of spec revision For SN/HN: The TxnID of the Read data flit must be the same as that of the Request for spec revision ISSUE_A For SN/HN: The TxnID of the Read data flit must be the same as that of the ReturnTxnID Request for spec revision ISSUE_B or later	A CompData flit is received for one of the outstanding Read transactions whose data phase isn't complete yet.	In case of a CHI-A node, a CompData flit is received but there are no outstanding transactions whose TgtID,SrcID and TxnID match with the SrcID,TgtID and TxnID of the CompData. In case of CHI-B or later RN, a CompData flit is received but there are no outstanding transactions whose TgtID,SrcID and TxnID match with the HomeNID,TgtID and TxnID of the CompData. In case of CHI-B or later SN, a CompData flit is received but there are no outstanding transactions whose TgtID,ReturnNID and ReturnTxnID match with the HomeNID,TgtID and TxnID of the CompData.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_compdata_flit_for_xact_check	ARM-IHI0050E.b: 4.5.1 Completion response	Data flit type must be set to one of the permitted values for the Request	Check that the data type of the flit matches the expected value. COMPDATA is valid only in case of Read type transactions	A CompData flit is received for a Read transaction.	A CompData flit is received for a non-Read type transaction.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	new_req_before_completion_of_previous_read_write_xact_to_same_cacheline_check	ARM-IHI0050E.b: 2.9.4 Transaction attribute combinations	Read and Write transactions from the same source to addresses that overlap must remain ordered.	Check that a Read, Write, Dataless or Atomic request is issued when there are no outstanding Read or Write transactions to the same cache line. "Outstanding Read" refers to all Read as well as dataless transactions other than CMOs. "Outstanding Write" refers to all Write and Atomic transactions.	A Read, Write, Dataless or Atomic request flit is received and there are no outstanding Read, Write, Dataless or Atomic transactions to the same cache line.	A Read, Write, Dataless or Atomic request flit is received and there are one or more outstanding Read, Write, Dataless or Atomic transactions to the same cache line.	Passive RN, SN	In case there are multiple sources within an RN, it cannot be determined if the requests are issued by the same source based on the request fields. Therefore, this check will not be performed at passive RN when svt_chi_node_configuration :: multiple_req_sources_within_rn_node is set to 1. In case DMT Reads are issued at the SN, it is possible that the Interconnect de-allocates the Reads before SN sends CompData to the RN. In such a case, it is possible that the Interconnect issues a second request to the same address while the CompData of the previous DMT Read is in progress or is yet to be sent to the RN. Therefore, this check will not consider DMT Reads at the SN while looking for outstanding transactions to a given cacheline.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	expected_xact_type_check	SYNOPSYS DEFINED	Only supported transaction types must be issued to a given node.	Check that only supported transaction types are received for a given node. SYNOPSYS DEFINED: DVMOp transactions are epected to be seen only for RNs with svt_chi_node_configuration :: dvm_enable set to 1 CHI-B or later specific transactions (RNSD, ROMI, ROCI, CSP, PrefetchTgt, AtomicOps) are expected to be seen only for a CHI-B or later compliant RN. CHI-E or later specific transactions (Write*Zero, WriteEvictorEivct,...) are expected to be seen only for a CHI-E or later compliant RN. CHI-F or later specific transactions (CleanInvalidPopa, WriteNoSnpDef, WriteBackFull_CleanInvalidPopa, WriteNoSnpFull_CleanInvalidPopa, WriteNoSnpPtl_CleanInvalidPopa) are expected to be seen only for a CHI-F or later compliant RN. CHI-F transaction WriteNoSnpDef is currently unsupported by all CHI VIP components. VIP currently does not support PrefetchTgt transactions.	Scenario 1: A request other than PrefetchTgt, ReadNotSharedDirty, ROMI, ROCI, PrefetchTgt and AtomicOps is seen for a CHI-A RN-F. Scenario 2: A request other than PrefetchTgt is seen for a CHI-B or later RN-F. Scenario 3: A ReadNoSnp or WriteNoSnp transaction is received by an SN. Scenario 4: A DVMOp transaction is seen for an RN-F or RN-D whose svt_chi_node_configuration :: dvm_enable is set to 1. Scenario 5: ReadNoSnpSep is seen by an SN for a CHI-C or later. Scenario 6: ReadNoSnpSep is send from an HN with sep read and sep resp enabled. Scenario 7: CHI ISSUE E specific transaction request is seen for a CHI-E or later compliant RN. Scenario 8: CHI ISSUE F specific transaction request is seen for a CHI-F or later compliant RN. Scenario 9: CHI ISSUE F WriteNoSnpDef request is NOT observed on any CHI VIP component.	Scenario 1: A PrefetchTgt, ReadNotSharedDirty, ROMI, ROCI, PrefetchTgt or AtomicOps transaction request is seen for a CHI-A RN-F. Scenario 2: A PrefetchTgt transaction request is seen for a CHI-B or later RN-F. Scenario 3: A transaction of type other than WriteNoSnp and ReadNoSnp is received by an SN. Scenario 4: A DVMOp transaction is seen for an RN whose svt_chi_node_configuration :: dvm_enable is 0. Scenario 5: A DVMOp transaction is seen for an RN-I. Scenario 6: ReadNoSnpSep is seen by an SN for a CHI-B or before. Scenario 7: ReadNoSnpSep is send from an HN with sep read and sep resp disabled. Scenario 8: CHI ISSUE E specific transaction request is seen for a CHI-D or earlier compliant RN. Scenario 9: CHI ISSUE F specific transaction request is seen for a CHI-E or earlier compliant RN. Scenario 10: CHI ISSUE F WriteNoSnpDef request is observed at a CHI VIP component.	Passive RN and SN	VIP CHI-F or later transactions are currently not supported by CHI VIP components. VIP CHI-E or later SN currently does not support combined write and (P)CMO transactions. VIP CHI-E or later SN currently supports Atomics only with TAG_OP as TAG_INVALID. The check will be updated once support for these transactions is added.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	retry xact	valid_pcrdreturn_check	ARM-IHI0050E.b: 2.3.8 Retry	PcrdReturn transaction can only be sent after the reception of a PcrdGrant flit	Check that PCrdReturn is sent only after RetryAck and PCrdGrant flits are received from the Target node. PcrdReturn transaction can only be sent after the reception of a PcrdGrant flit	A PCrdReturn transaction is seen after the prior reception of PCrdGrant and RetryAck, with the SrcID and PCrdType set to the same value as the TgtID and PCrdType of the PCrdReturn.	A PCrdReturn transaction is seen but there were no corresponding PCrdGrant and RetryAck, whose SrcID and PCrdType match the TgtID and PCrdType of the PCrdReturn.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	retry xact	valid_retry_xact_check	ARM-IHI0050E.b: 2.3.8 Retry	The transaction with credit must only be sent by the Requester after both the RetryAck response and an appropriate PCrdGrant response are received	Check that the transaction is retried only after RetryAck and PCrdGrant responses are received from the Target node. The transaction with credit must only be sent by the Requester after both the RetryAck response and an appropriate PCrdGrant response are received, and the transaction attributes other than PCrdType, AllowRetry and QoS must be the same as the original request.	A retry transaction is seen after the prior reception of PCrdGrant and RetryAck, with the SrcID and PCrdType set to the same value as the TgtID and PCrdType of the retry transaction, and, The valid appliacble attributes of the retry transaction match with those of the original request.	A retry transaction is seen but there were no corresponding PCrdGrant and RetryAck, whose SrcID and PCrdType match the TgtID and PCrdType of the retry transaction, or, One or more applicable attributes of the retry transaction do not match with those of the Original request.	RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	retry xact	valid_retry_xact_after_pcrdcgrant_check	ARM-IHI0050E.b: 2.11 Request Retry	The transaction must only be retried by the Requester when a PCrdGrant is received with the correct PCrdType.	The transaction must only be retried by the Requester when a PCrdGrant is received with the correct PCrdType	A retry transaction is received while there are available granted credits for the PCrdType.	A retry transaction is received while there are no available granted credits for the PCrdType,ie, the retry tranaction is received without the recpetion of a PCrdGrant with the same PCrdType	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	retry xact	valid_p_crd_type_in_pcrdreturn_flit_check	ARM-IHI0050E.b: 2.11.2 Transaction Retry mechanism	A PCrdReturn transaction must have the credit type set to the value of the credit type that is being returned	Check that the credit type field in a PCrdReturn transaction is set correctly. Before the PCrdReturn flit, a PCrdGrant must have been received with the same PCrdType	A PCrdReturn flit is seen after the reception of a corresponding PCrdGrant with the same PCrdType value.	A PCrdReturn flit is seen without prior reception of a PCrdGrant with the same PCrdType value.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_write_dat_flit_with_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The SrcID of the Write data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request	Check that the Transaction ID, SourceID and TargetID fields are set correctly in Write Data flits. The SrcID of the Write data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request	A Write Data flit is received for one of the outstanding transactions whose data phase isn't yet complete (data_status is either INITIAL or PARTIAL_ACCEPT).	A Write Data flit is received but there are no outstanding transactions whose SrcID,TgtID and TxnID match the SrcID, TgtID and TxnID of the Write Data.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	valid_byte_enable_for_write_data_check	ARM-IHI0050E.b: 2.10.3 Byte Enables	For all Write transactions, byte enables that are not within the data window, specified by Addr and Size, must be deasserted.	Check that the Byte Enables are set correctly for Write Data For all Write transactions, byte enables that are not within the data window, specified by Addr and Size, must be deasserted. For DVMOp transactions, only the least significant 8 bits must be asserted. For all Atomic transactions, byte enables that are not within the data window,specified by Addr and Size ,muts be deasserted.	SCENARIO 1: For a full cacheline Write transaction, all Byte Enable bits are asserted. SCENARIO 2: For a partial cacheline Write, none of the Byte Enable bits outside of the data window are set. SCENARIO 3: When chi_spec_revision is ISSUE_B or greater, the cache state in the CopyBackWriteData is set to I and all BE bits are set to zero. SCENARIO 4: For a DVMOp, Byte Enable is set to 'hff. SCENARIO 5: For Atomic Transactions,all Byte enables are asserted within the data window,and byte enables outside the data window are set to zero.	SCENARIO 1: For a full cacheline Write transaction, one or more Byte Enable bits are deasserted. SCENARIO 2: For a partial cacheline Write, any of the Byte Enable bits outside of the data window are set. SCENARIO 3: When chi_spec_revision is ISSUE_B or greater, the cache state in the CopyBackWriteData is set to I but one or more Byte Enable bits are asserted. SCENARIO 4: For a DVMOp, Byte Enable is not set to 'hff. SCENARIO 5: For Atomic Transactions,one or more Byte enables outside the data window are set to one.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	expected_num_write_data_flits_check	ARM-IHI0050E.b: 2.10.4 Data packetization	The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width	Check that the number of Write Data flits is equal to the expected value The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width	A Write Data flit is received and there is an active xact with matching src_id, tgt_id and txn_id whose data_status is either INITIAL or PARTIAL_ACCEPT.	A Write Data flit is received and there is an active xact with matching src_id, tgt_id and txn_id whose data_status is ACCEPT.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	write_dat_xfer_after_dbid_check	ARM-IHI0050E.b: 2.3 Transaction structure	WriteData must only be sent by the Requester after either DBIDResp or CompDBIDResp is received.	Check that the Write Data flits are transmitted only after CompDBIDResp/DBIDResp.	A Write Data flit is received and there is an active xact with matching src_id, tgt_id and txn_id which has received a DBIDResp/CompDBIDResp	A Write Data flit is received and there is an active transaction with matching src_id, tgt_id and txn_id which hasn't yet received a DBIDResp/CompDBIDResp	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	writenosnp_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteNoSnp transaction. The cache state in the associated Write data flits of a WriteNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.	Final cache state in the Write data flits of a WriteNoSnp transaction is set to I.	Final cache state in the Write data flits of a WriteNoSnp transaction is set to a value other than I.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_noncbwrdata_flit_for_xact_check	ARM-IHI0050E.b: 4.5.2 WriteData response	Data flit type must be set to one of the permitted values for the Request	Check that the data type of the flit matches the expected value. NONCOPYBACKWRDATA is valid only in case of WriteNoSnoop, WriteUnique and DVMOp type transactions	A NonCopyBackWrData flit is received for a WriteNoSnoop, WriteUnique or DVMOp type transaction.	A CopyBackWrData flit is received for a transaction type other than WriteNoSnoop, WriteUnique and DVMOp.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	single_outstanding_req_per_txn_id_check	ARM-IHI0050E.b: 2.5.2 Transaction ID	The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID	Check that there are no multiple outstanding transactions from the same source with the same transaction IDs. The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID	SCENARIO 1: A request is received at an RN, and there are no outstanding transactions with the same TxnID. SCENARIO 2: A request is received at an SN, and there are no outstanding non-DMT transactions with the same TxnID.	SCENARIO 1: A request is received at an RN, but there already is an outstanding request with the same TxnID. SCENARIO 2: A request is received at an SN, but there already is an outstanding non-DMT request with the same TxnID.	Passive RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit field	dat_flit_dbid_check	ARM-IHI0050E.b: Table A-9 Data message field mappings	DBID field of the observed DAT flit must be valid	Check that the DBID field value of the following DAT flits is as follows. DAT flits: SnpRespData, SnpRespDataPtl, NonCopyBackWrData, CopyBackWrData: In case of CHI-A nodes, DBID field must be zeroes or must be set to TxnID of originating request. For SnpRespData*, originating request is the Snoop request. CompData: DBID field must be unique for a given non-DMT and non-DCT Read transaction with ExpCompAck asserted and can be reused only after the transaction completes.	SCENARIO 1: For Write/Snoop transactions, the DBID of the observed Data flit is either zero or equal to the TxnID of the associated transaction. SCENARIO 2: For Read transactions with ExpCompAck asserted, the DBID of the observed Data flits is unique and there are no other Outstanding non-DMT and non-DCT transactions that have received read data with the same DBID value.	In case of Write/Snoop transactions, the DBID of the observed Data flit is neither zero or equal to the TxnID of the associated transaction. In case of non-DMT and non-DCT Read transactions with ExpCompAck asserted, the DBID of the observed Data flits is not unique; there already is an outstanding non-DMT and non-DCT transaction that has received read data with the same DBID value.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit field	tx_dat_flit_data_id_check	ARM-IHI0050E.b: 13.10.50 Data Identifier, DataID	data_id of the observed Tx DAT flit must be valid	Check the DataId field value of transmitted DAT flits from the monitored DUT. This is determined based on data width of DAT VC along with data size of the corresponding transaction. Note that this check, in case CCF Wrap Order is set to True at the sender, checks that the first data flit transmitted corresponds to the critical chunk indicated by CCID (,ie, the data_id of the first data flit matches the CCID value). For the subsequent flits, the check ensures that the data_id values are set correctly. In case CCF Wrap Order is set to False at the sender, this check only verifies that the data_id takes one of the legal values prescribed in Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b) Following are the Tx DAT flit types considered by this check. . If the monitored DUT is RN: CopyBackWrData NonCopyBackWrData SnpRespData SnpRespDataPtl If the monitored DUT is SN: CompData	DataID value in the data flit transmitted by the active RN/SN agent is as per Table 11-29 (ARM-IHI0050A), Table 12-41 (ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).	DataID value in the data flit transmitted by the active RN/SN agent violates the legal values specified in Table 11-29 (ARM-IHI0050A), Table 12-41 (ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).	Passive RN and Passive SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit field	rx_dat_flit_data_id_check	ARM-IHI0050E.b: 13.10.50 Data Identifier, DataID	data_id of the observed Rx DAT flit must be valid	Check the DataId field value of received DAT flits by the monitored DUT. This is determined based on data width of DAT VC along with data size of the corresponding transaction. Note that this check, in case of in-order Interconnect, checks that the first data flit transmitted corresponds to the critical chunk indicated by CCID (,ie, the data_id of the first data flit matches the CCID value). For the subsequent flits, the check ensures that the data_id values are set correctly. Incase of out-of-order interconnect, this check only verifies that the Data_ID takes one of the legal values prescribed in Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b). Following are the Rx DAT flit types considered by this check. . If the monitored DUT is RN: CompData If the monitored DUT is SN: NonCopyBackWrData	DataID value in the data flit received by the RN/SN agent is as per Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).	DataID value in the data flit received by the RN/SN agent violates the legal values specified in Table 11-29 (ARM-IHI0050A), Table 12-41 (ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm outstanding transactions	num_non_dvm_snoop_exceeded_configured_value_check	SYNOPSYS DEFINED	The number of outstanding non-dvm snoop should not exceed the configured value.	Check that the number of outstanding non-dvm snoop transactions have not reached the value configured in svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact.	The number of outstanding non-dvm snoop transactions are less than the value configured in svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact.	The number of outstanding non-dvm snoop transactions have reached the value configured in svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact.	Active RN-F/RN-D	This check is applicable only when svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact is set to value other than -1. This is synopsys defined check.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm outstanding transactions	num_dvm_snoop_exceeded_configured_value_check	SYNOPSYS DEFINED	The number of outstanding dvm snoop should not exceed the configured value.	Check that the number of outstanding dvm snoop transactions have not reached the value configured in svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact.	The number of outstanding dvm snoop transactions are less than the value configured in svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact.	The number of outstanding dvm snoop transactions have reached the value configured in svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact.	Active RN-F/RN-D	This check is applicable only when svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact is set to value other than -1. This is synopsys defined check.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	retry xact	end_of_simulation_outstanding_protocol_credit_check	SYNOPSYS DEFINED	There shouldn't be any outstanding protocol credits at the end of simulation. Protocol credits must be utilized by retrying the original transaction or by PCRDRETURN	Check that there shouldn't be any outstanding protocol credits at the end of simulation. Protocol credits must be utilized by retrying the original transaction or returned via PCRDRETURN.	There are no outstanding protocol credits at the end of simulation.	There are outstanding protocol credits at the end of simulation.	RN and SN	This check is applicable only when svt_chi_node_configuration :: end_of_simulation_checks_enable is set to 1.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writenosnp_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated data packet's resp_err field should not take EXOK or NDERR value for WriteNoSnp transaction. The resp_err field in the associated response should not take EXOKAY for a non-Exclusive WriteNoSnp transaction	Check that the associated response and data packets has valid resp_err value for WriteNoSnp transaction. The associated data packet's resp_err field should not take EXOK or NDERR value for WriteNoSnp transaction.	The RespErr field in the associated Write data flits of a WriteNoSnp transaction are as per Table 9-5 in the CHI Specification. The RespErr field in the associated response flits of a WriteNoSnp transaction are as per Table 9-4 in the CHI Specification.	The RespErr field in the associated Write data flits of a WriteNoSnp transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteNoSnp transaction violate the legal values specified in Table 9-4 in the CHI Specification.	RN and SN		ERROR	svt_chi_protocol_err_check
CHI Link Layer	signal validity	valid_rxdatflit_signal_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit. Description : RXDATFLIT must not be X/Z when RXDATFLITV is asserted	RXDATFLIT must not be X/Z when RXDATFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	RXDATFLIT doest not take X/Z value when RXDATFLITV is asserted	one or more bit in RXDATFLIT is set to X/Z value when RXDATFLITV is asserted	RN and SN	Currently this check is performed on entire RXDATFLIT. if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of RXDATFLIT. if svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_B or later: RXDATFLIT bits corresponding to datacheck and poison fields are also applicable.	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_txdatflit_signal_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit. Description : TXDATFLIT must not be X/Z when TXDATFLITV is asserted	TXDATFLIT must not be X/Z when TXDATFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	TXDATFLIT doest not take X/Z value when TXDATFLITV is asserted	one or more bit in TXDATFLIT is set to X/Z value when TXDATFLITV is asserted	Passive RN and Passive SN	Currently this check is performed on entire TXDATFLIT. if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of TXDATFLIT. if svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_B or later: TXDATFLIT bits corresponding to datacheck and poison fields are also applicable.	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_reqflit_signal_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit. Description : REQFLIT must not be X/Z when REQFLITV is asserted	REQFLIT must not be X/Z when REQFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	REQFLIT doest not take X/Z value when REQFLITV is asserted	one or more bit in REQFLIT is set to X/Z value when REQFLITV is asserted	Passive RN and SN	Currently this check is performed on entire REQFLIT. if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of REQFLIT.	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txdatlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATLCRDV must be 0 during reset	TXDATLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXDATLCRDV is 0 during reset.	TXDATLCRDV is non zero during reset.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxdatflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATFLITV must be 0 during reset	RXDATFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXDATFLITV is 0 during reset.	RXDATFLITV is non zero during reset.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txrsplcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPLCRDV must be 0 during reset	TXRSPLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXRSPLCRDV is 0 during reset.	TXRSPLCRDV is non zero during reset.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxreqlcrdv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request L-Credit Valid Description : RXREQLCRDV must not be X/Z	RXREQLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXREQLCRDV is not X/Z.	RXREQLCRDV is X/Z.	Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxreqlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQLCRDV must be 0 during reset	RXREQLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXREQLCRDV is 0 during reset.	RXREQLCRDV is non zero during reset.	Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsnpflitv_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop Flit Valid Description : RXSNPFLITV must not be X/Z	RXSNPFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXSNPFLITV is not X/Z.	RXSNPFLITV is X/Z.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsnpflitpend_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop Flit Pending Description : RXSNPFLITPEND must not be X/Z	RXSNPFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXSNPFLITPEND is not X/Z.	RXSNPFLITPEND is X/Z.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxrspflitv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Valid Description : RXRSPFLITV must not be X/Z	RXRSPFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXRSPFLITV is not X/Z.	RXRSPFLITV is X/Z.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxrspflitpend_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Pending Description : RXRSPFLITPEND must not be X/Z	RXRSPFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXRSPFLITPEND is not X/Z.	RXRSPFLITPEND is X/Z.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txreqlcrdv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request L-Credit Valid Description : TXREQLCRDV must not be X/Z	TXREQLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXREQLCRDV is not X/Z.	TXREQLCRDV is X/Z.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_rxrspflit_signal_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit. Description : RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted	RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	RXRSPFLIT doest not take X/Z value when RXRSPFLITV is asserted	one or more bit in RXRSPFLIT is set to X/Z value when RXRSPFLITV is asserted	RN	Currently this check is performed on entire RXRSPFLIT. if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of RXRSPFLIT.	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxrspflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPFLITV must be 0 during reset	RXRSPFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXRSPFLITV is 0 during reset.	RXRSPFLITV is non zero during reset.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txreqlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQLCRDV must be 0 during reset	TXREQLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXREQLCRDV is 0 during reset.	TXREQLCRDV is non zero during reset.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxreqflitv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Valid Description : RXREQFLITV must not be X/Z	RXREQFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXREQFLITV is not X/Z.	RXREQFLITV is X/Z.	SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxreqflitpend_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Pending Description : RXREQFLITPEND must not be X/Z	RXREQFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXREQFLITPEND is not X/Z.	RXREQFLITPEND is X/Z.	SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxreqflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQFLITV must be 0 during reset	RXREQFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXREQFLITV is 0 during reset.	RXREQFLITV is non zero during reset.	SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxrsplcrdv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response L-Credit Valid Description : RXRSPLCRDV must not be X/Z	RXRSPLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXRSPLCRDV is not X/Z.	RXRSPLCRDV is X/Z.	Passive RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txreqflitv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Valid Description : TXREQFLITV must not be X/Z	TXREQFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXREQFLITV is not X/Z.	TXREQFLITV is X/Z.	Passive RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsnplcrdv_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop L-Credit Valid Description : RXSNPLCRDV must not be X/Z	RXSNPLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXSNPLCRDV is not X/Z.	RXSNPLCRDV is X/Z.	Passive RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txreqflitpend_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Pending Description : TXREQFLITPEND must not be X/Z	TXREQFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXREQFLITPEND is not X/Z.	TXREQFLITPEND is X/Z.	Passive RN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxrsplcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPLCRDV must be 0 during reset	RXRSPLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXRSPLCRDV is 0 during reset.	RXRSPLCRDV is non zero during reset.	Passive RN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txreqflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQFLITV must be 0 during reset	TXREQFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXREQFLITV is 0 during reset.	TXREQFLITV is non zero during reset.	Passive RN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxlinkactivereq_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEREQ must be 0 during reset	RXLINKACTIVEREQ must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXLINKACTIVEREQ is 0 during reset.	RXLINKACTIVEREQ is non zero during reset.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txlinkactiveack_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEACK must be 0 during reset	TXLINKACTIVEACK must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXLINKACTIVEACK is 0 during reset.	TXLINKACTIVEACK is non zero during reset.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxlinkactivereq_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEREQ must not be X/Z	RXLINKACTIVEREQ must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXLINKACTIVEREQ is not X/Z.	RXLINKACTIVEREQ is X/Z.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxdatflitv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Valid Description : RXDATFLITV must not be X/Z	RXDATFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXDATFLITV is not X/Z.	RXDATFLITV is X/Z.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxdatflitpend_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Pending Description : RXDATFLITPEND must not be X/Z	RXDATFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXDATFLITPEND is not X/Z.	RXDATFLITPEND is X/Z.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txrsplcrdv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response L-Credit Valid Description : TXRSPLCRDV must not be X/Z	TXRSPLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXRSPLCRDV is not X/Z.	TXRSPLCRDV is X/Z.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txdatlcrdv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data L-Credit Valid Description : TXDATLCRDV must not be X/Z	TXDATLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXDATLCRDV is not X/Z.	TXDATLCRDV is X/Z.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsactive_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : RXSACTIVE signal Description : RXSACTIVE must not be X/Z	RXSACTIVE must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXSACTIVE is not X/Z.	RXSACTIVE is X/Z.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txlinkactiveack_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEACK must not be X/Z	TXLINKACTIVEACK must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXLINKACTIVEACK is not X/Z.	TXLINKACTIVEACK is X/Z.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_txrspflit_signal_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit. Description : TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted	TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	TXRSPFLIT doest not take X/Z value when TXRSPFLITV is asserted	one or more bit in TXRSPFLIT is set to X/Z value when TXRSPFLITV is asserted	Passive RN and Passive SN	Currently this check is performed on entire TXRSPFLIT. if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of TXRSPFLIT.	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxdatlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATLCRDV must be 0 during reset	RXDATLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXDATLCRDV is 0 during reset.	RXDATLCRDV is non zero during reset.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txdatflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATFLITV must be 0 during reset	TXDATFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXDATFLITV is 0 during reset.	TXDATFLITV is non zero during reset.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txrspflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPFLITV must be 0 during reset	TXRSPFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXRSPFLITV is 0 during reset.	TXRSPFLITV is non zero during reset.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxlinkactiveack_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEACK must be 0 during reset	RXLINKACTIVEACK must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXLINKACTIVEACK is 0 during reset.	RXLINKACTIVEACK is non zero during reset.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txlinkactivereq_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEREQ must be 0 during reset	TXLINKACTIVEREQ must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	TXLINKACTIVEREQ is 0 during reset.	TXLINKACTIVEREQ is non zero during reset.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxdatlcrdv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data L-Credit Valid Description : RXDATLCRDV must not be X/Z	RXDATLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXDATLCRDV is not X/Z.	RXDATLCRDV is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txrspflitv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Valid Description : TXRSPFLITV must not be X/Z	TXRSPFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXRSPFLITV is not X/Z.	TXRSPFLITV is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txrspflitpend_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Pending Description : TXRSPFLITPEND must not be X/Z	TXRSPFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXRSPFLITPEND is not X/Z.	TXRSPFLITPEND is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txdatflitv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Valid Description : TXDATFLITV must not be X/Z	TXDATFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXDATFLITV is not X/Z.	TXDATFLITV is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txdatflitpend_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Pending Description : TXDATFLITPEND must not be X/Z	TXDATFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXDATFLITPEND is not X/Z.	TXDATFLITPEND is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxlinkactiveack_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEACK must not be X/Z	RXLINKACTIVEACK must not be X/Z. Performed from second clock edge onwards once the reset is asserted	RXLINKACTIVEACK is not X/Z.	RXLINKACTIVEACK is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txsactive_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : TXSACTIVE signal Description : TXSACTIVE must not be X/Z	TXSACTIVE must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXSACTIVE is not X/Z.	TXSACTIVE is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txlinkactivereq_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEREQ must not be X/Z	TXLINKACTIVEREQ must not be X/Z. Performed from second clock edge onwards once the reset is asserted	TXLINKACTIVEREQ is not X/Z.	TXLINKACTIVEREQ is X/Z.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_lcredit_range_check	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : The minimum number of L-Credits that a Receiver can provide is one.The maximum number of L-Credits that a Receiver can provide is 15 Description : The l-credit must be within the valid range	The minimum number of L-Credits that a receiver can provide is one. The maximum number of L-Credits that a receiver can provide is defined as follows based on vc_id RXREQ: svt_chi_node_configuration :: rx_req_vc_flit_buffer_size RXDAT: svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size RXRSP: svt_chi_node_configuration :: rx_rsp_vc_flit_buffer_size RXSNP: svt_chi_node_configuration :: rx_snp_vc_flit_buffer_size	L-credit value falls within the valid range as described above	L-credit value falls outside the valid range as described above	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	link deactivation	tx_link_deactive_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner Description : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner	Link deactivation must complete in a timely manner in response to a received request.	Link goes to deactivate state in response to deactivation well within the value specified in svt_chi_node_configuration :: tx_link_deactivation_timeout.	If the number of cycles exceeds the value specified in svt_chi_node_configuration :: tx_link_deactivation_timeout,the check errors out.	Passive RN and Passive SN	This check uses the value of svt_chi_node_configuration :: tx_link_deactivation_timeout.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	tx_link_active_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner Description : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner	Link activation must complete in a timely manner in response to a received request.	Link goes to activate state in response to activation well within the value specified in svt_chi_node_configuration :: tx_link_activation_timeout.	If the number of cycles exceeds the value specified in svt_chi_node_configuration :: tx_link_activation_timeout,the check errors out.	Passive RN and Passive SN	This check uses the value of svt_chi_node_configuration :: tx_link_activation_timeout.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	tx_link_not_active_during_flit_transfer	ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake	Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be sent on its virtual channel only if the link is active.	Flits must not be transmitted while the link is not active	Flits transmitted while the link is active.	Flits transmitted while the link is not active.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	link deactivation	rx_link_deactive_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If a component moves the TXLINK to the DEACTIVATE state, which it controls, it can expect the RXLINK to also move to the DEACTIVATE state, in a timely manner Description : If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner	Link deactivation must complete in a timely manner in response to a received request. If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner.	Link goes to deactivate state in response to deactivation well within the value specified in svt_chi_node_configuration :: rx_link_deactivation_timeout	If the number of cycles exceeds the value specified in svt_chi_node_configuration :: rx_link_deactivation_timeout,the check errors out.	RN and SN	This check uses the value of svt_chi_node_configuration :: rx_link_deactivation_timeout. By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: rx_link_deactivation_timeout to a value greater than or equal to 0 for this check to be performed.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	rx_link_active_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If a component moves the TXLINK to the ACTIVATE state, which it controls, it can expect the RXLINK to also move to the ACTIVATE state, in a timely manner Description : If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner	Link activation must complete in a timely manner in response to a received request. If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner.	Link goes to activate state in response to activation well within the value specified in svt_chi_node_configuration :: rx_link_activation_timeout.	If the number of cycles exceeds the value specified in svt_chi_node_configuration :: rx_link_activation_timeout,the check errors out.	RN and SN	This check uses the value of svt_chi_node_configuration :: rx_link_activation_timeout. By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: rx_link_activation_timeout to a value greater than or equal to 0 for this check to be performed.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	rx_link_not_active_during_flit_reception	ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake	Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be observed on its RX virtual channel only if the corresponding link is active.	Flits must be observed only when the link is active	Flits observed while the link is active.	Flits observed while the link is not active.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	invalid_data_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : DAT channel opcodes encoding Description : Check for Reserved opcode bits for Data VC commands	Reserved (opcodes) Data VC commands cannot be used.	Data flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-14, ARM-IHI0050B: 12.9.15 Table 12-18, ARM-IHI0050E.b: 13.10.17 Table 13-16.	Data flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-14, ARM-IHI0050B: 12.9.15 Table 12-18, ARM-IHI0050E.b: 13.10.17 Table 13-16.	RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_lcrdreturn_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : DatLCrdReturn Description : Check fields for a DataLCrdReturn flit	Data VC message fields must be set to valid values for a DataLCrdReturn transaction	if ( dat_vc_flit_opcode == DATLCREDIT) and all the fields take legal values	if ( dat_vc_flit_opcode == DATLCREDIT) and one or more of the fields take an unexpected value	RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_lcrdreturn_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : RspLCrdReturn Description : Check fields for a RspLCrdReturn flit	Response VC message fields must be set to valid values for a RspLCrdReturn transaction	if ( rsp_vc_flit_opcode == RSPLCREDIT) and all the fields take legal values	if ( rsp_vc_flit_opcode == RSPLCREDIT) and one or more of the fields take an unexpected value	RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_lcrdreturn_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReqLCrdReturn Description : Check fields for a ReqLCrdReturn flit	Request VC message fields must be set to valid values for a ReqLCrdReturn transaction	if ( req_vc_flit_opcode == REQLCREDIT) and all the fields take legal values	if ( req_vc_flit_opcode == REQLCREDIT) and one or more of the fields take an unexpected value	RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	invalid_rsp_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : RSP channel opcodes encoding Description : Check for Reserved opcode bits for Response VC commands	Reserved (opcodes) Response VC commands cannot be used.	Response flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-12, ARM-IHI0050B: 12.9.15 Table 12-16, ARM-IHI0050E.b 13.10.17 Table 13-14.	Response flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-12, ARM-IHI0050B: 12.9.15 Table 12-16, ARM-IHI0050E.b 13.10.17 Table 13-14.	RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_compdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : CompData Description : Check fields for data VC flit of a CompData transaction	Data VC message fields must be set to valid values for a CompData transaction.	if ( dat_vc_flit_opcode == COMPDATA), the communicating node pairs are allowed as per the spec and all the fields take legal values	if ( dat_vc_flit_opcode == COMPDATA) and one or more of the fields take an unexpected value or the communicating pairs are in violation with the spec	RN and Passive SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_pcrdgrant_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : PCrdGrant Description : Check fields for response VC flit of a PCrdGrant transaction	Response VC message fields must be set to valid values for a PCrdGrant transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	RN and Passive SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_dbidresp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : DBIDResp Description : Check fields for response VC flit of a DBIDResp transaction	Response VC message fields must be set to valid values for a DBIDResp transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	RN and Passive SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_compdbidresp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : CompDBIDResp Description : Check fields for response VC flit of a CompDBIDResp transaction	Response VC message fields must be set to valid values for a CompDBIDResp transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	RN and Passive SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_comp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : Comp Description : Check fields for response VC flit of a Comp transaction	Response VC message fields must be set to valid values for a Comp transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	RN and Passive SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_retryack_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : RetryAck Description : Check fields for response VC flit of a RetryAck transaction	Response VC message fields must be set to valid values for a RetryAck transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	RN and Passive SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	valid_xact_attributes_combination_check	ARM-IHI0050E.b:2.9.4 Transaction attribute combinations	Spec Text : Legal combinations of MemAttr, SnpAttr, and Order field values Description : check combinations of MemAttr, SnpAttr, LikelyShared and Order for a transaction	Transaction attributes in the Request VC message must take valid combinations.	Valid combination of MemAttr, SnpAttr, LikelyShared and order field for a transaction.	Invalid combination of MemAttr, SnpAttr, LikelyShared and order field for a transaction.	Passive RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	invalid_req_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : REQ channel opcodes Description : Check for Reserved opcode bits for Request VC commands	Reserved (opcodes) Request VC commands cannot be used.	Request flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-11, ARM-IHI0050B: 12.9.15 Table 12-14, ARM-IHI0050E.b: 13.10.17 Table 13-12.	Request flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-11, ARM-IHI0050B: 12.9.15 Table 12-14, ARM-IHI0050E.b: 13.10.17 Table 13-12.	Passive RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_noncopybackwrdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : NonCopyBackWrData Description : Check fields for data VC flit of a NonCopyBackWrData transaction	Data VC message fields must be set to valid values for a NonCopyBackWrData transaction.	All the fields in the data flit are as per Data message field mappings of the CHI Specification	One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification	Passive RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readnosnp_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadNoSnp Description : Check fields for request VC flit of a ReadNoSnp transaction	Request VC message fields must be set to valid values for a ReadNoSnp transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpFull Description : Check fields for request VC flit of a WriteNoSnpFull transaction	Request VC message fields must be set to valid values for a WriteNoSnpFull transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpptl_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpPtl Description : Check fields for request VC flit of a WriteNoSnpPtl transaction	Request VC message fields must be set to valid values for a WriteNoSnpPtl transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_pcrdreturn_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : PCrdReturn Description : Check fields for request VC flit of a PCrdReturn transaction	Request VC message fields must be set to valid values for a PCrdReturn transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN and SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_compack_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : CompAck Description : Check fields for response VC flit of a CompAck transaction	Response VC message fields must be set to valid values for a CompAck transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	Passive RN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readonce_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadOnce Description : Check fields for request VC flit of a ReadOnce transaction	Request VC message fields must be set to valid values for a ReadOnce transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniquefull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniqueFull Description : Check fields for request VC flit of a WriteUniqueFull transaction	Request VC message fields must be set to valid values for a WriteUniqueFull transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniqueptl_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniquePtl Description : Check fields for request VC flit of a WriteUniquePtl transaction	Request VC message fields must be set to valid values for a WriteUniquePtl transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_makeinvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : MakeInvalid Description : Check fields for request VC flit of a MakeInvalid transaction	Request VC message fields must be set to valid values for a MakeInvalid value for transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN, SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleaninvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanInvalid Description : Check fields for request VC flit of a CleanInvalid transaction	Request VC message fields must be set to valid values for a CleanInvalid value for transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN, SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanShared Description : Check fields for request VC flit of a CleanShared transaction	Request VC message fields must be set to valid values for a CleanShared transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN, SN	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	invalid_snp_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : SNP channel opcodes encoding Description : Check for Reserved opcode bits for Snoop VC commands	Reserved (opcodes) Snoop VC commands cannot be used.	Snoop flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-13, ARM-IHI0050B: 12.9.15 Table 12-17, ARM-IHI0050B: 13.10.17 Table 13-15, ARM-IHI0050B: 13.10.17 Table 13-15.	Snoop flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-13, ARM-IHI0050B: 12.9.15 Table 12-17, ARM-IHI0050B: 13.10.17 Table 13-15, ARM-IHI0050B: 13.10.17 Table 13-15.	RN-F and RN-D		ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	snoop_flit_lcrdreturn_check	ARM-IHI0050E.b:A.4 Snoop Request message field mappings	Spec Text : SnpLCrdReturn Description : Check fields for a SnpLCrdReturn flit	Data VC message fields must be set to valid values for a SnoopLCrdReturn transaction	if ( snp_vc_flit_opcode == SNPLCREDIT) and all the fields take legal values	if ( snp_vc_flit_opcode == SNPLCREDIT) and one or more of the fields take an unexpected value	RN-F and RN-D		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_snpflit_signal_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop Flit. Description : SNPFLIT must not be X/Z when SNPFLITV is asserted	SNPFLIT must not be X/Z when SNPFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	SNPFLIT doest not take X/Z value when SNPFLITV is asserted	one or more bit in SNPFLIT is set to X/Z value when SNPFLITV is asserted	RN-F and RN-D	Currently this check is performed on entire SNPFLIT. if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of SNPFLIT.	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxsnpflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPFLITV must be 0 during reset	RXSNPFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXSNPFLITV is 0 during reset.	RXSNPFLITV is non zero during reset.	RN-F and RN-D		ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	snoop_flit_snpdvmop_check	ARM-IHI0050E.b:A.4 Snoop Request message field mappings	Spec Text : SnpDVMOp Description : Check fields for snoop VC flit of a SnpDVMOp transaction	Snoop VC message fields must be set to valid values for a SnpDVMOp transaction.	All the fields in the snoop flit are as per Snoop request message field mappings of the CHI Specification	One or more fields in the snoop flit violate the legal values specified in Snoop request message field mappings of the CHI Specification	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1)..	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxsnplcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPLCRDV must be 0 during reset	RXSNPLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	RXSNPLCRDV is 0 during reset.	RXSNPLCRDV is non zero during reset.	Passive RN-F and Passive RN-D		ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_snpresp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : SnpResp Description : Check fields for response VC flit of a SnpRsp transaction	Response VC message fields must be set to valid values for a SnpRsp transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	Passive RN-F and Passive RN-D	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_dvmop_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : DVMOp Description : Check fields for request VC flit of a DVMOp transaction	Request VC message fields must be set to valid values for a DVMOp transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F and Passive RN-D	This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).. At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_readreceipt_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : ReadReceipt Description : Check fields for response VC flit of a ReadReceipt transaction	Response VC message fields must be set to valid values for a ReadReceipt transaction.	All the fields in the response flit are as per Response message field mappings of the CHI Specification	One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification	RN and Passive SN-I	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_ecbarrier_check	ARM-IHI0050A:A.1 Request message field mappings	Check fields for request VC flit of a ECBarrier transaction	Request VC message fields must be set to valid values for a ECBarrier transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN and SN-I	This check is constructed only when svt_chi_node_configuration :: chi_spec_revision is set to svt_chi_node_configuration :: ISSUE_A. At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_eobarrier_check	ARM-IHI0050A:A.1 Request message field mappings	Check fields for request VC flit of a EOBarrier transaction	Request VC message fields must be set to valid values for a EOBarrier transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN and SN-I	This check is constructed only when svt_chi_node_configuration :: chi_spec_revision is set to svt_chi_node_configuration :: ISSUE_A. At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	snoop_flit_snpreq_check	ARM-IHI0050E.b:A.4 Snoop Request message field mappings	Spec Text : Snoop Request message Description : Check fields for snoop VC flit of a Snoop transaction	Snoop VC message fields must be set to valid values for a Snoop transaction (non-DVMOp).	if a non-DVM Snoop request is received and the communicating node pairs are allowed as per the spec and also all the fields take legal values	if a non-DVM Snoop request is received, and, either the communicating node pairs are not permitted by the spec or any of the fields take an invalid value	RN-F		ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_snprespdataptl_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : SnpRespDataPtl Description : Check fields for data VC flit of a SnpRespDataPtl transaction	Data VC message fields must be set to valid values for a SnpRespDataPtl transaction.	All the fields in the data flit are as per Data message field mappings of the CHI Specification	One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_copybackwrdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : CopyBackWrData Description : Check fields for data VC flit of a CopyBackWrData transaction	Data VC message fields must be set to valid values for a CopyBackWrData transaction.	All the fields in the data flit are as per Data message field mappings of the CHI Specification	One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_snprespdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : SnpRespData Description : Check fields for data VC flit of a SnpRespData transaction	Data VC message fields must be set to valid values for a SnpRespData transaction.	All the fields in the data flit are as per Data message field mappings of the CHI Specification	One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_evict_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : Evict Description : Check fields for request VC flit of a Evict transaction	Request VC message fields must be set to valid values for a Evict transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writecleanptl_check	ARM-IHI0050A:A.1 Request message field mappings	Check fields for request VC flit of a WriteCleanPtl transaction	Request VC message fields must be set to valid values for a WriteCleanPtl transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	This check is constructed only when svt_chi_node_configuration :: chi_spec_revision is set to svt_chi_node_configuration :: ISSUE_A. At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writebackptl_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteBackPtl Description : Check fields for request VC flit of a WriteBackPtl transaction	Request VC message fields must be set to valid values for a WriteBackPtl transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeevictfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteEvictFull Description : Check fields for request VC flit of a WriteEvictFull transaction	Request VC message fields must be set to valid values for a WriteEvictFull transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writecleanfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteCleanFull Description : Check fields for request VC flit of a WriteCleanFull transaction	Request VC message fields must be set to valid values for a WriteCleanFull transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writebackfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteBackFull Description : Check fields for request VC flit of a WriteBackFull transaction	Request VC message fields must be set to valid values for a WriteBackFull transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_makeunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : MakeUnique Description : Check fields for request VC flit of a MakeUnique transaction	Request VC message fields must be set to valid values for a MakeUnique transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleanunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanUnique Description : Check fields for request VC flit of a CleanUnique transaction	Request VC message fields must be set to valid values for a CleanUnique transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadUnique Description : Check fields for request VC flit of a ReadUnique transaction	Request VC message fields must be set to valid values for a ReadUnique transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readclean_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadClean Description : Check fields for request VC flit of a ReadClean transaction	Request VC message fields must be set to valid values for a ReadClean transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadShared Description : check fields for request VC flit of a ReadShared transaction	Request VC message fields must be set to valid values for a ReadShared transaction.	All the fields in the request flit are as per Request message field mappings of the CHI Specification	One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification	Passive RN-F	At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value. At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_num_prot_flits_in_txlasm_deactivate_state_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : The Transmitter must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit Description : The Transmitter in Deactivate state is allowed to transmit protocol flits For each additional credit received it must send an L-Credit return flit to return the credit.	The maximum number of protocol flits that a transmitter (per channel) can send in Deactivate state is the number of l-credits available at the time of entry into Deactivate state. In other words, The Transmitter in Deactivate state must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit.	The number of protocol flits observed during transmitter deactivate state is less than or equal to the maximum allowed value, as mentioned in the description.	The number of protocol flits observed during transmitter deactivate state is greater than the maximum allowed value.	Passive RN	Applicable only when svt_chi_node_configuration :: allow_protocol_flits_transmission_in_tx_lasm_deactivate_state configuration is set to 1	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_lcredit_count_in_rx_stop_state_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : Before entering a low power state, the sending of payload flits must be stopped and all credits must be returned to the Receiver Description : The reciever must ensure that it has received all the lcredits before moving to the stop state	The reciever must ensure that it has received all the lcredits before moving to the stop state i.e before deasserting the RXLINKACTIVEACK signal. Applicable channels: RN_I: RXRSP VC and RXDAT VC RN_F/RN_D: RXSNP VC, RXRSP VC and RXDAT VC SN: RXREQ VC and RXDAT VC	All the lcredits are reveiced before moving to the stop state.	All the lcredits are not reveiced before moving to the stop state.	Passive RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	rx_no_lcredit_issued_for_flit_type	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : When the link is active, the Receiver must provide L-Credits in a timely manner without requiring any action on the part of the Transmitter Description : When the link is active, the receiver at each virtual channel must distribute L-credits for all its flit buffers in a timely manner without requiring any action on the part of the transmitter.	Checks if credits are sent, in a timely manner, by the corresponding active node. While the number of available L-Credits is less than the configured number of L-Credits (rx_\*_vc_flit_buffer_size in svt_chi_node_configuration), an L-Credit should be returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.	while the number of available L-Credits is less than the configured number of L-Credits (rx_*_vc_flit_buffer_size in svt_chi_node_configuration), an L-Credit is returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.	while the number of available L-Credits is less than the configured number of L-Credits (rx_*_vc_flit_buffer_size in svt_chi_node_configuration), no L-Credits are returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.	Passive RN and Passive SN		ERROR	svt_chi_link_err_check
CHI Link Layer	port interleaving	port_interleaving_check	SYNOPSYS DEFINED:SYNOPSYS DEFINED	Monitor checks that if interleaved port is expected port for the given flit	Checks if address does fall to correct interleaved port. Valid when node cfg svt_chi_node_configuration :: port_interleaving_enable = 1. Applicable for snoop transactions in case of active and passive RN. Applicable for RN transactions in case of passive RN.	address does fall to correct interleaved port.	address does not fall to correct interleaved port.	RN		ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_flitpend_and_flitv_signal_check	ARM-IHI0050E.b:14.4 Flit level clock gating	Spec Text : It is required that the signal is asserted exactly one cycle before a flit is sent from the Transmitter Description : FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter	FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter	FLITPEND is asserted exactly one clock cycle before FLTIV is asserted.	FLITPEND is not asserted exactly one clock cycle before FLTIV is asserted.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_entry_into_banned_output_race_state_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : The red states can only be reached by observing a race between two output signals. A race between two outputs is not permitted at the edge of a component and therefore the transition into these states is labeled with Banned Output Race Description : The component's Link Active State Machine entry into Banned Output Race state condition is not expected.	lasm is acronym for "Link Active State Machine". A given component's Link Active State Machine entry into Banned Output Race states can happen when there is a race condition at the output signals of the local component. A given component's Link Active State Machine entry into Banned Output Race states results in the connected link partner component being entering Async Input Race States. When a component’s Link Active State Machine entry into Banned Output Race state is observed this check will fail, if not the check will pass. This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected is set to 0.	When the component Link Active State Machine doesn't enter into Banned Output Race State.	When the component Link Active State Machine entry into Banned Output Race State is observed. The check will fail for below Link Active State Machine transitions: TX_STOP RX_ACTIVATE to TX_STOP RX_RUN+ TX_RUN RX_ACTIVATE to TX_DEACTIVATE+ RX_ACTIVATE TX_RUN RX_DEACTIVATE to TX_RUN RX_STOP+ TX_STOP RX_DEACTIVATE to TX_ACTIVATE+ RX_DEACTIVATE	Passive RN and Passive SN	This check will be constructed and executed only when the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected is set to 0. Use case: For a given component, the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected can be set to 0 (which inturn enables this check) for below cases: An error needs to be thrown when the component's Link Active State Machine to enter into Banned Output Race State An error needs to be thrown when the connected link partner component's Link Active State Machine to enter into Async Input Race State	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	illegal_tx_rx_state_transition_combinations_from_async_input_race_state	ARM-IHI0050E.b:14.6.3 Expected transitions	Combination of Tx and Rx link active state machine together from async input race combination must be valid	Check to monitor the illegal Tx and Rx link active state combinations from the async input race states for a given node Legal Tx and Rx link active state combinations from the async input race states are: TXRUN+/RXSTOP to TXRUN/RXACT TXACT/RXDEACT+ to TXRUN/RXDEACT TXSTOP+/RXRUN to TXSTOP/RXDEACT TXDEACT/RXACT+ to TXSTOP/RXDEACT	Link Active State Machine from an async input race state moves to a valid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.	Link Active State Machine from an async input race state moves to a invalid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.	RN and SN	This check will be constructed and executed only when the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 1.	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_entry_into_async_input_race_state_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : The yellow states can only be reached by observing a race between two input signals. The transition into these states is labeled with Async Input Race Description : The component's Link Active State Machine entry into Async Input Race state condition is not expected.	lasm is acronym for "Link Active State Machine". A given component Link Active State Machine entry into Async Input Race States can only be reached by observing a race between the two input signals. In other words, entry into Async Input Race states for a given component can happen only when the connected link partner component observes a Banned Output Signal race condition. A given component Link Active State Machine entry into Async Input Race state implies that the connected link partner copmonent has entered Banned Output Race state. When a component’s Link Active State Machine entry into Async Input Race state is observed this check will fail, if not the check will pass. This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 0.	When the component Link Active State Machine doesn't enter into Async Input Race State.	When the component Link Active State Machine entry into Async Input Race State is observed. The check will fail for below Link Active State Machine transitions: TX_ACTIVATE RX_STOP to TX_RUN+ RX_STOP TX_ACTIVATE RX_RUN to TX_ACTIVATE RX_DEACTIVATE+ TX_DEACTIVATE RX_RUN to TX_STOP+ RX_RUN TX_DEACTIVATE RX_STOP to TX_DEACTIVATE RX_ACTIVATE+	RN and SN	This check will be constructed and executed only when the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 0. Use case: For a given component, the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected can be set to 0 (which inturn enables this check) for below cases: An error needs to be thrown when the component's Link Active State Machine to enter into Async Input Race State An error needs to be thrown when the connected link partner component's Link Active State Machine to enter into Banned Output Race State .	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_in_banned_output_race_state_timeout_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Banned Output Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by local component.	lasm is acronym for "Link Active State Machine". A given components Link Active State Machine entry into Banned Output Race states can happen when there is Async Input Signal race condition at the connected link partner component. The component observing Link Active States corresponding to Banned Output race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component. When a component’s state machine stays in Banned Output Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued. This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.	When the component observing Link active State Machine in Banned Output race states moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.	When the component observing Link active State Machine in Banned Output race states not moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.	RN	By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout to a value greater than or equal to 1 for this check to be performed. This check uses the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, which must be programmed taking into consideration all other link active state machine delays. The Link Active State Machine delays that user needs to pay attention to are delay controls(to move to next valid state) in Banned Output Race states: svt_chi_node_configuration :: txla_req_assertion_when_rx_in_run_state_delay svt_chi_node_configuration :: txla_req_deassertion_when_rx_in_stop_state_delay svt_chi_node_configuration :: rxla_ack_assertion_when_tx_in_deactivate_state_delay svt_chi_node_configuration :: rxla_ack_deassertion_when_tx_in_activate_state_delay	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_in_async_input_race_state_timeout_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Async Input Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by link partner component.	lasm is acronym for "Link Active State Machine". A given components Link Active State Machine entry into Async Input Race states can happen when there is a Banned Output Signal race condition at the connected link partner component. The component observing Link Active States corresponding to Async Input race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component. When a component’s state machine stays in Async Input Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued. This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.	When the component observing Link active State Machine in Async Input race states moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.	When the component observing Link active State Machine in Async Input race states not moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.	RN	By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout to a value greater than or equal to 1 for this check to be performed. This check uses the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, which must be programmed taking into consideration all other link active state machine delays. As the component's Link active State Machine movement from Async Input race state to next valid state depends on the link partner component's movement from Banned Output Race states to next valid state, the link partner component delays to move from Banned Output Race states to next valid state should be programmed appropriately.	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	illegal_tx_rx_state_transition_combinations_from_banned_output_race_state	ARM-IHI0050E.b:14.6.3 Expected transitions	Combination of Tx and Rx link active state machine together from banned output race combination must be valid	Check to monitor the illegal Tx and Rx link active state combinations from the banned output race states for a given node Legal Tx and Rx link active state combinations from the banned output race states are: TXSTOP/RXRUN to TXACT/RXRUN TXRUN/RXSTOP to TXDEACT/RXSTOP TXDEACT/RXACT to TXDEACT/RXRUN TXACT/RXDEACT to TXACT/RXSTOP	Valid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.	Invalid combination for Tx and Rx state machine, The combination of Tx and Rx state at a given point is not as per ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	illegal_tx_rx_state_transition_combinations	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : Stop/Stop to Run/Run state paths Description : Combination of Tx and Rx link active state machine together must be valid	Check to monitor the following illegal Tx and Rx link active state combinations for a given node: TXSTOP/RXRUN TXRUN/RXSTOP TXDEACT/RXACT TXACT/RXDEACT	Valid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.	Invalid combination for Tx and Rx state machine, The combination of Tx and Rx state at a given point is not as per ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	rx_illegal_state_transition	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Rx link active state machine must be valid	Illegal transition of the Receiver Interface State. This check monitors the RXLINKACTIVEREQ and RXLINKACTIVEACK signals and records illegal state transitions.	Valid state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.	Illegal state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	tx_illegal_state_transition	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Tx link active state machine must be valid	Illegal transition of the Transmitter Interface State. This check monitors the TXLINKACTIVEREQ and TXLINKACTIVEACK signals and records illegal state transitions.	Valid state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.	Illegal state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_lcredit_count_in_tx_stop_state_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : The Transmitter has no credits and must not send any flits Description : All the applicable lcredit counter should be zero in tx stop state	When Tx is in stop state all the applicable lcredit counters should be 0. The Interconnect should not deassert the TXLINKACTIVEACK signal before it has recieved back all the lcredits. RN: TXREQ VC: txreq_lcrd_count should be 0. TXRSP VC: txrsp_lcrd_count should be 0. TXDAT VC: txdat_lcrd_count should be 0. SN: TXRSP VC: txrsp_lcrd_count should be 0. TXDAT VC: txdat_lcrd_count should be 0.	All the applicable lcredit counters are 0 in tx stop state.	All the applicable lcredit counters are non zero in tx stop state.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	invalid_lcredit_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : The Receiver must not send any credits Description : The receiver must not send lcredit in stop and activate state.	The receiver must not send lcredit in stop and activate state.	The receiver doeas not send lcredit in stop and activate state.	The receiver send lcredit in stop and activate state.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	tx_lcredit_used_same_cycle_which_recieved	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : An L-Credit cannot be used in the cycle it is received Description : An L-credit cannot be used in the cycle it is received.	Flits must not be transmitted on the same cycle that a credit is received	Flits transmitted on the subsequent cycle than that on which the credit is received	Flits transmitted on the same cycle that a credit is received	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	rx_no_lcredit_sent_for_flit_transfer	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : On exit from reset, credits are held by the Receiver and must be passed to the Transmitter before flit transfer can begin Description : A flit can be sent on its virtual channel only if a corresponding L-credit is available at the transmitter and the link is active.	Credits must be available for every transmitted Flit	FLITV is asserted while there are one or more link credits available for the corresponding channel.	FLITV is asserted even though there are no L-credits available for the corresponding channel.	RN and SN		ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	tx_no_lcredit_for_flit_transfer	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : On exit from reset, credits are held by the Receiver and must be passed to the Transmitter before flit transfer can begin Description : A flit can be sent on its virtual channel only if a corresponding L-credit is available at the transmitter and the link is active.	Credits must be available for every transmitted Flit	Credits are available before flit transfer.	Credits are not available before flit transfer.	RN and SN		ERROR	svt_chi_link_err_check
CHI System	coherent rsp	coherent_resp_start_conditions_check	ARM-IHI0050E.b: 4.3 Snoop request types	Monitor Check that the response to a coherent transaction is not started before appropriate RN-Fs are snooped	Checks that the response to a coherent transaction is not started before the appropriate RN-Fs are snooped. This check is applicable only when svt_chi_system_configuration :: perform_expected_snoops_checks is set to 1.	Scenario 1: snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 0 for the HN, and snoops corresponding to a coherent request are broadcasted to all RN-Fs in the system. Scenario 2: snoop_filter_enable is set to 1, snoop_filter_based_snooping_enable is set to 0 for the HN, and snoops corresponding to a coherent request are broadcasted to all RN-Fs in the system. Scenario 3: snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to EXPECT_SNOOP, and snoops corresponding to a coherent request are sent to the RN-Fs which have a copy of the cache. Scenario 4: snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to DO_NOT_EXPECT_SNOOP, and snoops corresponding to a coherent request are sent to the RN-Fs which have cached the line in UC/UD/SD state.	Scenario 1: snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 0 for the HN, and snoops corresponding to a coherent request are not broadcasted to all RN-Fs in the system. Scenario 2: snoop_filter_enable is set to 1, snoop_filter_based_snooping_enable is set to 0 for the HN, and snoops corresponding to a coherent request are not broadcasted to all RN-Fs in the system. Scenario 3: snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to EXPECT_SNOOP, and snoops corresponding to a coherent request are not sent to one or more of RN-Fs which have a copy of the cache. Scenario 4: snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to DO_NOT_EXPECT_SNOOP, and snoops corresponding to a coherent request are not sent to one or more of RN-Fs which have cached the line in UC/UD/SD state.		The Snoop filter and Snooping based on Snoop filter Enable parameters must be programmed appropriately using svt_chi_system_configuration :: set_hn_snoop_filter_enable and svt_chi_system_configuration :: set_hn_snoop_filter_based_snooping_enable respectively. In case the Interconnect is designed such that it does not snoop RN-Fs in SC state, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state must be set to DO_NOT_EXPECT_SNOOP. Expected snoopee info is also dependent on user programming of domain settings, through svt_chi_system_configuration :: create_new_domain API. For a given RN-F that is expected to be snooped based on domain settings, if the RN-F has SYSCO interface feature enabled and the SYSCOREQ deasserion is observed while the coherent request was in progress, such RN-F will not be expected to be snooped. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.	ERROR	svt_chi_system_err_check
CHI System	Exclusive Access	exclusive_chi_transaction_type_check	ARM-IHI0050E.b: 6.3 Exclusive transactions	Monitor check that observed exclusive transaction is one of the allowed coherent/non-coherent exclusive load/store transaction types.	Checks that before processing any exclusive transactions from RN if that transaction is part of an allowed transaction type for an exclusive access. Following are the permitted transaction types to have svt_chi_base_transaction :: is_exclusive set to 1: CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER) Prefetchtgt(is_exclusive is a don't care field for prefetchtgt so it is permitted to take any value) This check is performed when an RN transaction is started.	Exclusive Access attribute is set to 1 for the transaction types CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER). PrefetchTgt(CHI-B OR LATER)	Exclusive Access attribute is set to 1 for the transaction types other than CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER). PrefetchTgt(CHI-B OR LATER)	RN	This check is constructed only when configuration parameters exclusive_access_enable (svt_chi_node_configuration :: exclusive_access_enable) and exclusive_monitor_enable (svt_chi_node_configuration :: exclusive_monitor_enable) are set to 1.	ERROR	svt_chi_system_err_check
CHI System	Exclusive Access	exclusive_store_resp_check	ARM-IHI0050E.b: 6.2 Exclusive monitors	Monitor check that the resposne for exclusive store transaction matches the expected response for the given lpid and address.	Checks that the response for exclusive store transaction(CleanUnique, MakeReadUnique, WriteNoSnp*) matches the expected response(svt_chi_transaction :: response_resp_err_status in case of CleanUnique and WriteNoSnp, svt_chi_common_transaction :: final_state in case of MakeReadUnique) for the given lpid and address. The expected response is determined by the exclusive monitor. This check is executed when the store transaction is complete.	The response for exclusive store transaction(CleanUnique, MakeReadUnique, WriteNoSnp*) matches with the expected response as determinted by the exclusive monitor.	The response for exclusive store transaction(CleanUnique, MakeReadUnique, WriteNoSnp*) doesn't match with the expected response as determinted by the exclusive monitor.	RN	This check is constructed only when configuration parameters exclusive_access_enable (svt_chi_node_configuration :: exclusive_access_enable) and exclusive_monitor_enable (svt_chi_node_configuration :: exclusive_monitor_enable) are set to 1.	ERROR	svt_chi_system_err_check
CHI System	Exclusive Access	exclusive_load_resp_check	ARM-IHI0050E.b: 6.2 Exclusive monitors	Monitor check that the resposne for exclusive load transaction matches the expected response for the given lpid and address.	Checks that the response for exclusive load transaction(ReadNoSnp, ReadShared, ReadClean, ReadNotSharedDirty, ReadPreferUnique) matches the expected response(svt_chi_transaction :: data_resp_err_status) for the given lpid and address. The expected response is determined by the exclusive monitor. This check is executed when the load transaction is complete.	The response for exclusive load transaction matches with the expected response as determinted by the exclusive monitor.	The response for exclusive load transaction doesn't match with the expected response as determinted by the exclusive monitor.	RN	This check is constructed only when configuration parameters exclusive_access_enable (svt_chi_node_configuration :: exclusive_access_enable) and exclusive_monitor_enable (svt_chi_node_configuration :: exclusive_monitor_enable) are set to 1.	ERROR	svt_chi_system_err_check
CHI System	data integrity	slave_data_integrity_check	SYNOPSYS DEFINED	Monitor Check that the data observed in the subordinate VIP agent transaction from Home NodeHN to Subordinate matches with the expected data present in the subordinate VIP agent memory, when the subordinate VIP agent transaction ends successfully.	Checks that the data observed in the subordinate VIP agent transaction from Home Node(HN) to Subordinat, matches with the expected data present in the subordinate VIP agent memory, when the subordinate VIP agent transaction ends successfully. The subordinate can be a CHI SN or an AXI subordindate. In case of the transaction that is routed to AXI subordiniate, this check is performed under the following conditions: The CHI system monitor (that is part of a CHI system ENV) and the AXI subordinate agent (that is part of an AXI system ENV) are part of an AMBA system ENV The mapping between CHI SN agents and AXI subordinate agents is provided through the API set_axi_slave_to_chi_sn_map, of AMBA system configuration class. Methodology used is UVM This check is performed when there are no overlapping cacheline address transactions to the same subordinate. .	The data observed in the subordinate VIP agent transaction matches with the expected data in the subordinate VIP agent memory	The data observed in the subordinate VIP agent transaction does not match with the expected data in the subordinate VIP agent memory	SN	This check is constructed only when at least one SN is present in the CHI system (svt_chi_system_configuration :: num_sn > 0) In case of active mode AXI subordinate or CHI SN VIP agent, it is required to use a corresponding memory based response sequence, such as svt_axi_slave_memory_sequence or svt_chi_sn_memory_response_seuqnece respectively. If that is not the case, many of the system monitoring aspects including this check are not applicable and users are expected to disable system monitor.	ERROR	svt_chi_system_err_check
CHI System	dvm	interconnect_dvm_snoop_timing_check	ARM-IHI0050E.b: 8.1 DVM transaction flow	Monitor Check that the interconnect sends DVM Snoops only after DBIDResp is issued to the initiating RN and NCBWrData is received for the corresponding DVM request.	Checks that the interconnect issues DBIDResp and waits for the WriteData for a DVM request before issuing SnpDVMOp requests.	Interconnect sends SnpDVMOp request after DBIDResp and NonCopyBackWriteData are seen for the corresponding DVM request.	Scenario 1: Interconnect sends SnpDVMOp request before DBIDResp is seen for the corresponding DVM request. Scenario 2: Interconnect sends SnpDVMOp request before NonCopyBackWriteData is seen for the corresponding DVM request.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_system_err_check
CHI System	dvm	valid_dvm_response_from_interconnect_check	ARM-IHI0050E.b: 8.1 DVM transaction flow	Monitor Check that the Comp response for a DVMOp requestnon-sync,sync indicates an Error resposne if any of the associated snoops has Error response.	Checks that the interconnect sends correct response to the DVMOp(non-sync,sync) requests from then initiating RNs based on the response received from the SnpDvmop(non-sync,sync) from the snooped Rns. This check ensures that this comp response to the DVMOp request(non-sync,sync) is sent as Error resposne if any of the associated snoops has Error response.	Interconnect sends comp Error response to original DVMOp request if any of the associated SnpDVMOp transactions has error response	Interconnect sends comp OK response to original DVMOp request while one or more associated SnpDVMOp transactions receive comp Error response.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1). This check depends on user programming the RN-F/RN-D indices correctly through svt_chi_system_configuration :: create_new_domain API. In above description, RN-D refers to an I/O coherent device that is DVM capable, such as ACE-Lite+DVM manager.	ERROR	svt_chi_system_err_check
CHI System	dvm	interconnect_dvm_response_timing_check	ARM-IHI0050E.b: 8.1 DVM transaction flow	Monitor Check that the interconnect waits for the responses for all corresponding SnpDVMOpnon-sync,sync requests before responding to original DVMOpnon-sync,sync transaction.	Checks that the interconnect waits for the responses to SnpDVMOp(non-sync,sync) requests from then snooped RNs before sending a comp response to original DVMOp request(non-sync,sync). This check ensures that this comp response to the DVMOp request(non-sync,sync) is sent only after all associated snoops are complete. This check will only be performed when there are no error responses seen in the Data/Response flits corresponding to the DVMOp transaction. This is because the Interconnect behaviour in case of error responses in DVMOp transactions is implementation defined.	Interconnect sends comp response to original DVMOp request only after all the associated SnpDVMOp transactions are complete.	Interconnect sends comp response to original DVMOp request while one or more associated SnpDVMOp transactions are yet to receive comp response.	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_system_err_check
CHI System	dvm	interconnect_dvm_sync_snoop_transaction_association_check	ARM-IHI0050E.b: 8.1 DVM transaction flow	Monitor Check that interconnect broadcasts SnpDVMOpsync transactions to all other RNs that are DVM snoopable when it receives a DVMOpsync request transaction from an RN.	Checks that interconnect broadcasts SnpDVMOp(sync) transactions to all other RNs that are DVM snoopable when it receives a DVMOp(sync) request transaction from an RN. This check will only be performed when there are no error responses seen in the Data/Response flits corresponding to the DVMOp transaction. This is because the Interconnect behaviour in case of error responses in DVMOp transactions is implementation defined.	SnpDVMOp(sync) transactions corresponding to DVMOp(sync) request are broadcasted by interconnect to all RNs that are DVM snoopable, other than the initiating RN	SnpDVMOp(sync) transactions corresponding to DVMOp(sync) request are not broadcasted by interconnect to one or more RNs that are DVM snoopable, other than the initiating RN	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).	ERROR	svt_chi_system_err_check
CHI System	dvm	interconnect_dvm_operation_snoop_transaction_association_check	ARM-IHI0050E.b: 8.1 DVM transaction flow	Monitor Check that interconnect broadcasts SnpDVMOpnon-sync transactions to all other RNs that are DVM snoopable when it receives a DVMOpnon-sync request transaction from an RN.	Checks that interconnect broadcasts SnpDVMOp(non-sync) transactions to all other RNs that are DVM snoopable when it receives a DVMOp(non-sync) request transaction from an RN.	SnpDVMOp(non-sync) transactions corresponding to DVMOp(non-sync) request are broadcasted by interconnect to all RNs that are DVM snoopable, other than the initiating RN	SnpDVMOp(non-sync) transactions corresponding to DVMOp(non-sync) request are not broadcasted by interconnect to one or more RNs that are DVM snoopable, other than the initiating RN	RN-F and RN-D	This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1). This check depends on user programming the RN-F/RN-D indices correctly through svt_chi_system_configuration :: create_new_domain API. For a given RN-F/RN-D that is expected to be snooped based on domain settings, if the RN-F/RN-D has SYSCO interface feature enabled and the SYSCOREQ deasserion is observed while the DVM request was in progress, such RN-F/RN-D will not be expected to be snooped. In above description, RN-D refers to an I/O coherent device that is DVM capable, such as ACE-Lite+DVM manager.	ERROR	svt_chi_system_err_check
CHI System	Domain and snoop	coherent_snoop_domain_match_check	ARM-IHI0050E.b: 2.9.6 Snoop Attribute	Monitor Check that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master	Checks that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master . This check is performed when the snoop transaction is received at RN-F node , . The check compares the domain of the snoop transaction with domain of the initiating RN-F,RN-I(s) coherent transaction.	when domain of the snoop transaction received at node is within the same domain of the coherent transactions sent by the Initiating RN node.	when domain of the snoop transaction received at node is not within the same domain of the coherent transactions sent by the Initiating RN node.	RN-F,RN-I	Expected snoopee info is also dependent on user programming of domain settings, through svt_chi_system_configuration :: create_new_domain API. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_copyback_write_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent write request are correctly ordered by HN	Checks that hazard condition between a copyback request and a coherent write request to the same cacheline(copyback-write hazard) are correctly handled by HN. While there is a pending copyback request, if a Write request is received to the same cacheline, the coherent write request is processed only after the completion of the copyback transaction. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when master-slave association is done for a given copyback transaction and there was a Hazard condition with a subsequent coherent write transaction. This check doesn't include coherent transactions from ACE-Lite master	Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write and the subsequent coherent write is not in progress.	Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write but the subsequent coherent write is already in progress	RN-F	This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_write_copyback_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a copyback request are correctly ordered by HN	Checks that hazard condition between a coherent write request and a Copyback request to the same cacheline(write-copyback hazard) are correctly handled by HN. While there is a pending coherent write request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent write transaction. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent copyback transaction. This check doesn't include coherent transactions from ACE-Lite master	Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback and the subsequent copyback is not in progress.	Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback but the subsequent copyback is already in progress	RN-F	This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_copyback_read_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent read request are correctly ordered by HN	Checks that hazard condition between a copyback request and a coherent read request to the same cacheline(copyback-read hazard) are correctly handled by HN across the system. While there is a pending copyback request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the copyback transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. This check is executed when master-slave association is done for a given coherent copyback transaction and there was a Hazard condition with a subsequent coherent read transaction. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read and the subsequent coherent read is not in progress.	Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read but the subsequent coherent read is already in progress	RN-F	This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_read_copyback_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a copyback request are correctly ordered by HN	Checks that hazard condition between a coherent read request and a Copyback request to the same cacheline(read-copyback hazard) are correctly handled by HN across the system. While there is a pending coherent read request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent read transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. This check is executed when master-slave association is done for a given coherent RN read transaction and there was a Hazard condition with a subsequent copyback transaction. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback and the subsequent copyback is not in progress.	Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coback but the subsequent copyback write is already in progress	RN-F	This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_copyback_write_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent write request are correctly ordered by HN	Checks that hazard condition between a copyback request and a coherent write request to the same cacheline(copyback-write hazard) are correctly handled by HN. While there is a pending copyback request, if a Write request is received to the same cacheline, the coherent write request is processed only after the completion of the copyback transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the coherent write transaction is completed and copyback-write hazard was detected when it was started. This check doesn't include coherent transactions from ACE-Lite master	Coherent copyback transaction is completed while no other coherent write transactions to the same cacheline are in progress.	Coherent copyback transaction is completed while there is a coherent write transaction to the same cacheline in progress.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_write_copyback_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a copyback request are correctly ordered by HN	Checks that hazard condition between a coherent write request and a Copyback request to the same cacheline(write-copyback hazard) are correctly handled by HN. While there is a pending coherent write request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent write transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the copyback transaction is completed and write-copyback hazard was detected when it was started. This check doesn't include coherent transactions from ACE-Lite master	Coherent write transaction is completed while no other coherent copyback transactions to the same cacheline are in progress.	Coherent write transaction is completed while there is a coherent copyback transaction to the same cacheline in progress.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_copyback_read_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent read request are correctly ordered by HN	Checks that hazard condition between a copyback request and a coherent read request to the same cacheline(copyback-read hazard) are correctly handled by HN. While there is a pending copyback request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the copyback transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the coherent read transaction is completed and copyback-read hazard was detected when it was started. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent copyback transaction is completed while no other coherent read transactions to the same cacheline are in progress.	Coherent copyback transaction is completed while there is a coherent read transaction to the same cacheline in progress.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_read_copyback_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a copyback request are correctly ordered by HN	Checks that hazard condition between a coherent read request and a Copyback request to the same cacheline(read-copyback hazard) are correctly handled by HN. While there is a pending coherent read request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent read transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the copyback transaction is completed and read-copyback hazard was detected when it was started. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent read transaction is completed while no other coherent copyback transactions to the same cacheline are in progress.	Coherent read transaction is completed while there is a coherent copyback transaction to the same cacheline in progress.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	coherent rsp	cache_state_of_xact_resp_check	ARM-IHI0050E.b: 4.7 Cache state transitions at a Requester	Monitor Check that no peer RN has cached the line when the Cache state is UC/UD in the Comp/CompData response of coherent transactions	Checks that no peer RN has cached the line when the Cache state is UC/UD in the Comp/CompData of coherent transactions.The checker relies on the Snoop filter in the System monitor to check if any peer RNs might have cached the line	The final state in the Comp/CompData response of coherent transactions is UC/UD and the cache state at each of the peer RN-Fs is Invalid as per the Snoop filter	The final state in the Comp/CompData response of coherent transactions is UC/UD and the cache state of one or more peer RN-Fs is not Invalid as per the Snoop filter		This check is executed when DCT flow is not exercised or when snoop_requests_snoop_filter_update_policy == BASED_ON_SNOOP_REQUEST Expected snoopee info is also dependent on user programming of domain settings, through svt_chi_system_configuration :: create_new_domain API	ERROR	svt_chi_system_err_check
CHI System	coherent and snoop	coherent_snoop_type_match_check	ARM-IHI0050E.b: Table 4-24 Expected snoop requests per Request from an RN	Monitor Check that the snoop transaction type corresponds to the coherent transaction type of initiating master	Checks that the associated snoop transaction type corresponds to the coherent transaction type from initiating RN as per: Table 4-1 of CHI Issue A specification Table 4-3 of CHI Issue B specification for the supported coherent and snoop types This check is performed when coherent transaction is complete, and when a given snoop transaction is associated that is: not sent to initiating RN (snoop_not_sent_to_initiating_master_check not failed) only one snoop is outstanding at the snooped RN to the given cache line address not aborted	Associated snoop transaction type matches with the corresponding coherent transaction type as per the spec reference mentioned in the check description	Associated snoop transaction type does not match with the corresponding coherent transaction type as per the spec reference mentioned in the check description	RN-F	This check is constructed only when at least one RN-F is present in the CHI system. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.	ERROR	svt_chi_system_err_check
CHI System	coherent and snoop	snoop_not_sent_to_initiating_master_check	ARM-IHI0050E.b: 4.4 Request transactions and corresponding Snoop requests	Monitor Check that a snoop is not sent to the initiating master	Checks that an associated snoop transaction is not sent to the RN, that initiated corresponding coherent transaction. This check is performed once coherent transaction is complete, and snoop transaction is assoiated to coherent transaction. Note that this check doesn't include DVM transactions.	The associated snoop transaction is not received the same RN that initiated corresponding coherent transaction.	The associated snoop transaction is received by the same RN that initiated corresponding coherent transaction.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.	ERROR	svt_chi_system_err_check
CHI System	coherent and snoop	overlapping_addr_sequencing_check	ARM-IHI0050E.b: 4.11.2 At the ICNHN-F node	Monitor Check that if two masters initiate requests to access the same cache line simultaneously, one master is sequenced after the other	Checks that if more than one RN initiate requests to access the same cache line simultaneously, one RN is sequenced after the other. If more than one RN initiate requests to access the same cache line simultaneously, the interconnect is expected to process these simultaneous requests one after another. In the case that this results in a scenario that is not corresponding to the check svt_chi_system_err_check :: snoop_not_sent_to_initiating_master_check, then the following details are applicable.	One or none snoop Requests with same cache line address is received at a given RN, AND None of the fail condition scenarios described under fail scenarios are applicable.	Scenario 1: More than one Snoop request with same cache line address is received at a given RN, AND More than one active Request with same cache line address is still active, THEN It implies that there is an error in sequencing the transactions to same address. Scenario 2: More than one Snoop request with same cache line address is received at a given RN, AND One or none active Requests with same cache line address are still active, THEN It implies that there is an error in issuing multiple snoop transactions to a given RN	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	coherent and snoop	snoop_addr_matches_coherent_addr_check	ARM-IHI0050E.b: 4.3 Snoop request types	Monitor Check that the address of a snoop transaction must match one of the outstanding coherent transactions	Checks that the address of a snoop transaction must match one of the outstanding coherent transactions This check is performed when the snoop transaction starts, even before coherent to snoop transaction association is done. Note that this doesn't check for snoop transaction type that corresponds to coherent transaction type The coherent transaction types that are checked for matching address are all the types excluding the following: WriteNoSnp, ReadNoSnp, WriteBack, WriteClean*, Evict, WriteEvictFull.	The address of snoop transaction matches to one of the outstanding snoopable transactions	The address of snoop transaction matches to none of the outstanding snoopable transactions	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	snoop rsp	only_one_snoop_returns_data_check	ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee	Monitor Check that only one snoop transaction returns data	Checks that for a given coherent transaction, only one of the associated snooped RNs responded to the snoop requests with data (svt_chi_snoop_transaction :: snp_rsp_datatransfer = 1). This check is performed when the coherent transaction is complete.	When only one of the associated snooped RN's responded to snoop request with data.	When more than one associated snooped RN's responded to snoop request with data.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.	ERROR	svt_chi_system_err_check
CHI System	snoop rsp	snoop_resp_passdirty_check	ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee	Monitor Check that no two associated snooped RNs responded to snoop transactions with PassDirtyresp[2] in the snoop responses asserted.	Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with PassDirty(resp[2] - svt_chi_common_transaction :: resp_pass_dirty) asserted to HN. This check is performed when the coherent transaction is complete.	When only one of the associated snooped RN's responded to snoop request with PassDirty asserted.	When more than one associated snooped RN's responded to snoop request with PassDirty asserted.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	snoop rsp	snoop_resp_wasunique_check	ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee	Monitor Check that no two associated snooped RNs responded to snoop transactions with cache line state as Unique.	Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with 'final cache line state as Unique'(WasUnique response asserted) at the respective snooped RNs. This check is performed when the coherent transaction is complete.	When only one of the associated snooped RN responded to snoop request with final cache line state as Unique in the snoop response.	When more than one associated snooped RN's responded to snoop request with final cache line state as Unique in the snoop response.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	coherent and snoop	coherent_xact_with_no_snoop_check	ARM-IHI0050E.b: 4.4 Request transactions and corresponding Snoop requests	Monitor Check that non-coherent requests READNOSNOOP,WRITENOSNOOP -- Except in case of invisibile cache mode at HN-F L3 , copyback requests WRITEBACK,WRITECLEAN,WRITEEVICTFULL and EVICT do not cause a snoop of cached RNs.	Checks that READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN*, WRITEEVICTFULL and EVICT transactions do not lead to snooping of peer RN-Fs. This check is performed when the snoop transaction starts. The check compares the address of the snoop transaction with outstanding coherent transactions. The check does not compare the snoop transaction type with coherent transaction type. Note that, in case of Invisible Cahe Mode at HN, it's possible to have Snoops for non-coherent transactions, please refer to svt_chi_system_configuration :: set_hn_invisible_cache_mode_enable for more details. In this case, the check factors in the set_hn_invisible_cache_mode_enable() settings along with Snoop Filter entries to validate the correctness of observed snoops for the non-coherent requests.	There are outstanding snoopable transactions of the type (other than the transaction types described in check description), with matching address as that of the snoop transaction	There are outstanding only non-snoopable transactions(the transaction types described in check description), with matching address as that of the snoop transaction	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	coherent and snoop	coherent_and_snoop_data_match_check	ARM-IHI0050E.b: 4.3 Snoop request types	Monitor Check that data returned to initiating RN matches with the full cacheline data received from associated snoop transaction	Checks that data returned to initiating RN matches with the data received from associated snoop transaction under following scenarios: Scenario 1: Full cacheline data is returned for one of the associated snoop transaction Scenario 2: Partial cacheline data is returned for one of the associated snoop transaction and HN-F L3 has the cacheline This check is not performed in case of partial cacheline data is returned for one of the snoop transaction and HN-F L3 doesn't have the cacheline. This check is applicable when : coherent transaction has data response and there are associated snoop transactions This check is performed when the coherent transaction is complete	Scenario 1: full cacheline data returned for one of the associated snoop transaction matches with data in response to RN Scenario 2: Partial cacheline data returned for one of the associated snoop transaction merged with HN-F L3 data matches with data in resposne to RN	Scenario 1: full cacheline data returned for one of the associated snoop transaction doesn't match with data in response to RN Scenario 2: Partial cacheline data returned for one of the associated snoop transaction merged with HN-F L3 data doesn't match with data in resposne to RN	RN-F	This check is constructed only when at least one RN-F is present in the CHI system. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.	ERROR	svt_chi_system_err_check
CHI System	data integrity	snoop_data_integrity_check	ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee	Monitor Check that snoop response data from snooped RN matches with system monitor HN-F L3 view when the final state resp[1:0] in the SnpRspData flits is set to UC/SC/I.	Checks that data in snoop transaction is consistent with system monitor HN-F L3 view when the snoop transaction completes. This check is performed when the coherent transaction is complete and system monitor has already associated the snoop transactions. This check is not applicable in case the snoop transaction returns the dirty data.	The data in snoop transaction matches with system monitor HN-F L3 view when the snoop transaction completes	The data in snoop transaction doesn't match with system monitor HN-F L3 view when the snoop transaction completes	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	data integrity	copyback_data_integrity_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	Monitor Check that CopyBack write data from RN matches with system monitor HN-F L3 view when the current state resp[1:0] in the CopyBack write DAT flits is set to UC/SC.	Checks that data in transaction is consistent with data in system monitor HN-F L3 view, when the CopyBack transaction completes. This check is applicable when the current state in the CopyBack transaction is UC/SC and there are no overlapping transactions to the same cacheline. In case the current state is dirty, system monitor HN-F L3 view will be updated with the CopyBack write data. There is no need to compare the CopyBack write data with system monitor HN-F L3 view in such a case. In case the current state is I, interconnect is expected to ignore/drop the CopyBack write data. System monitor HN-F L3 view will not be updated with the CopyBack write data in this case. Also there is no need to compare CopyBack write data with system monitor HN-F L3 view. Current State indicates the cacheline state at the RN when the data is sent (resp[1:0]).	For a given cacheline address, when current state in the CopyBack DAT flits is clean, and the system monitor HN-F L3 view data matches with CopyBack write data.	For a given cacheline address, when current state in the CopyBack DAT flits is clean, and the system monitor HN-F L3 view data doesn't match with CopyBack write data.	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	Streaming order	single_rn_optimized_streaming_order_check	ARM-IHI0050E.b: 2.8.5	Monitor Check that not more than one RN is configured to use the optimized streaming ordered WriteUnique/writeNoSnp flow, in the system.	Checks that not more than one RN is configured to use the optimized streaming ordered WriteUnique flow. OrderWriteObservation is enabled for WriteUnique transactions when svt_chi_transaction :: xact_type is WRITEUNIQUEFULL/WRITEUNIQUEPTL, with svt_chi_base_transaction :: order_type == REQ_ORDERING_REQUIRED and svt_chi_base_transaction :: exp_comp_ack set to 1. Optimized streaming ordered WriteUnique is enabled through setting svt_chi_node_configuration :: optimized_streaming_ordered_writeunique_enable=1. This Check is performed when the transaction is started.	When OrderWriteObservation ordered WriteUnique transactions are observed as started from any of the RN's, with svt_chi_node_configuration :: optimized_streaming_ordered_writeunique_enable set to 1 for none or one of the RN agents.	When OrderWriteObservation ordered WriteUnique transactions are observed as started from any of the RN's, with svt_chi_node_configuration :: optimized_streaming_ordered_writeunique_enable set to 1 for more than one RN agent.	RN	Applicable only when there is at least two RNs are present in the CHI system (svt_chi_system_configuration :: num_rn > 1). This check is performed When the following type transactions are observed: WriteUnique transactions with svt_chi_base_transaction :: order_type == REQ_ORDERING_REQUIRED and svt_chi_base_transaction :: exp_comp_ack set to 1.	WARNING	svt_chi_system_err_check
CHI System	Mismatched Memory attributes	same_memory_snoop_attributes_for_addr_check	ARM-IHI0050E.b: 2.9.7 Mismatched Memory attributes	Monitor Check that All outstanding transactions targetting the same address must have the same MemAttr bits Device, Cacheable and SnpAttr bit. All the agents should maintain a consistent view of the attributes of any region of memory addresses	All the nodes should maintain a consistent view of the attributes of any region of memory addresses. When software rules checking is enabled, all outstanding transactions targetting the same address are expected to have the same MemAttr bits Device, Cacheable and SnpAttr bit.	A request is observed with memory or snoop attributes that same as outstanding request to the same address.	A request is observed with memory or snoop attributes that differ from an outstanding request to the same address.	RN and SN	This check is applicable only when: svt_chi_system_configuration :: software_rules_based_checks_enable is set to 1 invisible_cache_mode_enable is set to 0	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_copyback_copyback_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a copyback request and another copyback request are correctly ordered by HN	Checks that hazard condition between a copyback and another copyback request to the same cacheline(copyback-copyback hazard) are correctly ordered by HN across the system. There should not be more than one copyback transactions to the same cacheline that are in progress at any given point in time A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when master-slave association is done for a given RN copyback transaction and there was a Hazard condition with a subsequent copyback transaction. This check doesn't include copyback transactions from ACE-Lite master	Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback and the subsequent coherent copyback is not in progress.	Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback but the subsequent copyback is already in progress	RN	This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_read_read_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent read request and another coherent read request are correctly ordered by HN	Checks that hazard condition between a coherent read request and another coherent read request to the same cacheline(read-read hazard) are correctly ordered by HN across the system. There should not be more than one coherent read transactions to the same cacheline that are in progress at any given point in time. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when master-slave association is done for a given coherent RN Read transaction and there was a Hazard condition with a subsequent coherent Read transaction. This check doesn't include coherent read transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent Read and the subsequent coherent Read is not in progress.	Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent Read but the subsequent coherent Read is already in progress	RN	This check is constructed only when at least one RN (svt_chi_system_configuration :: num_rn > 0) is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_write_write_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent write request and another coherent write request are correctly ordered by HN	Checks that hazard condition between a coherent write request and another coherent write request to the same cacheline(write-write hazard) are correctly ordered by HN across the system. There should not be more than one coherent write transactions to the same cacheline that are in progress at any given point in time A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent coherent write transaction. This check doesn't include coherent write transactions from ACE-Lite master	Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write and the subsequent coherent write is not in progress.	Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write but the subsequent coherent write is already in progress	RN	This check is constructed only when at least one RN (svt_chi_system_configuration :: num_rn > 0) is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_write_read_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent read request are correctly ordered by HN	Checks that hazard condition between a coherent write request and a coherent read request to the same cacheline(write-read hazard) are correctly handled by HN. While there is a pending write request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the write transaction. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent coherent read transaction. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read and the subsequent coherent read is not in progress.	Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read but the subsequent coherent read is already in progress	RN	This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_read_write_hazard_after_slave_xact_association_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent write request are correctly ordered by HN	Checks that hazard condition between a coherent read request and a coherent write request to the same cacheline(read-write hazard) are correctly handled by HN across the system. While there is a pending coherent read request, if a write request is received to the same cacheline, the write request is processed only after the completion of the coherent read transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete. This check is executed when master-slave association is done for a given coherent RN read transaction and there was a Hazard condition with a subsequent coherent write transaction. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write and the subsequent coherent write is not in progress.	Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write but the subsequent coherent write is already in progress	RN	This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1. The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_read_read_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent read request and another coherent read request are correctly ordered by HN	Checks that hazard condition between a coherent read request and another coherent read request to the same cacheline(read-read hazard) are correctly ordered by HN There should not be more than one coherent read transactions to the same cacheline that are in progress at any given point in time In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the coherent read transaction is completed and a read-read hazard condition was detected when it was started This check doesn't include coherent read transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent read transaction is completed while there are no other coherent read transactions to the same cacheline in progress.	Coherent read transaction is completed while another coherent read transaction to the same cacheline is in progress.	RN	This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_req_compack_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor check that - for a given cacheline, hazard condition between a Coherent request and CompAck is handled correctly by the HN	Checks that hazard condition between a pending CompAck and another coherent request to same cacheline are correctly ordered by HN. When HN receives a new RN request transaction to a cacheline while there's a pending transaction to the same cacheline that is yet to receive a CompAck, HN must not process the new request till the CompAck for the outstanding transaction is received. This check is not applicable for the coherent requests from ACE-Lite master as CompAck is not present in ACE-Lite protocol. This check is performed when a coherent request receives a response from HN	HN sends a response to the coherent request when there are no ongoing coherent requests to the same cacheline that are waiting to receive a CompAck	HN sends a response to the coherent request when there are any ongoing coherent requests to the same cacheline that are waiting to receive a CompAck	RN-F	This check is constructed only when at least one RN-F is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_write_write_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent write request and another coherent write request are correctly ordered by HN	Checks that hazard condition between a coherent write request and another coherent write request to the same cacheline(write-write hazard) are correctly ordered by HN There should not be more than one coherent write transactions to the same cacheline that are in progress at any given point in time In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the coherent write transaction is completed and a write-write hazard condition was detected when it was started This check doesn't include coherent write transactions from ACE-Lite master	Coherent write transaction is completed while there are no other coherent write transactions to the same cacheline in progress.	Coherent write transaction is completed while another coherent write transaction to the same cacheline is in progress.	RN	This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_write_read_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent read request are correctly ordered by HN	Checks that hazard condition between a coherent write request and a coherent read request to the same cacheline(write-read hazard) are correctly handled by HN. While there is a pending write request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the write transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the coherent read transaction is completed and write-read hazard was detected when it was started. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent write transaction is completed while no other coherent read transactions to the same cacheline are in progress.	Coherent write transaction is completed while there is a coherent read transaction to the same cacheline in progress.	RN	This check is constructed only when at least one RN is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	hazard	coherent_read_write_hazard_check	ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F	Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent write request are correctly ordered by HN	Checks that hazard condition between a coherent read request and a coherent write request to the same cacheline(read-write hazard) are correctly handled by HN. While there is a pending coherent read request, if a write request is received to the same cacheline, the write request is processed only after the completion of the coherent read transaction. In progress transaction refers to a transaction which is outstanding and has received a request response from the HN. This check is executed when the write transaction is completed and read-write hazard was detected when it was started. This check doesn't include coherent transactions from ACE-Lite master Coherent read transactions include dataless transactions	Coherent read transaction is completed while no other coherent write transactions to the same cacheline are in progress.	Coherent read transaction is completed while there is a coherent write transaction to the same cacheline in progress.	RN	This check is constructed only when at least one RN is present in the CHI system	ERROR	svt_chi_system_err_check
CHI System	Transaction ordering	slave_xacts_ordering_for_ordered_rn_xact_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	Monitor Check that the associated slave xacts of ordered RN transaction should be started after all the associated slave xacts of earlier issued ordered RN xact	The interconnect must maintain the order in which slave transactions are issued corresponding to ordered RN transactions from an RN to same address/address range	In CHI Issue C or earlier: The associated slave transactions of Ordered RN transaction should be started after all the associated slave transactions of earlier issued Ordered RN transaction. In CHI Issue D or later: The associated slave transactions of Request_Ordered RN transaction should be started after all the associated slave transactions of earlier issued Request_Ordered RN transaction. The associated slave transactions of Endpoint_Ordered RN transaction should be started after all the associated slave transactions of earlier issued Endpoint_Ordered RN transaction.	In CHI Issue C or earlier: Any of the associated slave transactions of Ordered RN transaction is started before the associated slave transactions of earlier issued Ordered RN transaction. In CHI Issue D or later: Any of the associated slave transactions of Request_Ordered RN transaction is started before the associated slave transactions of earlier issued Request_Ordered RN transaction. Any of the associated slave transactions of Endpoint_Ordered RN transaction is started before the associated slave transactions of earlier issued Endpoint_Ordered RN transaction.	RN and SN	This check is applicable only when: svt_chi_system_configuration :: slave_xact_to_rn_xact_correlation_enable is set to 1, and svt_chi_system_configuration :: ordering_checks_enable is set to 1. L3 is disabled for the target HN (should be specified via svt_chi_system_configuration :: set_hn_l3_cache_enable) Note: User must use svt_chi_system_monitor_callback :: master_xact_fully_associated_to_slave_xacts or svt_chi_system_monitor_callback :: new_system_transaction_started callbacks to set svt_chi_system_transaction :: ep_range_indx of system xact for Endpoint ordering. Default value of svt_chi_system_transaction :: ep_range_indx = -1;	ERROR	svt_chi_system_err_check
CHI System	Propagation of Attr	memory_attributes_propagation_check	ARM-IHI0050E.b: 2.9.3 Memory Attributes	Monitor Check that all the memory attributes of RN transaction are propagated to slaves	The MemAttr bits EWA, Device, Cacheable, and Allocate, must be preserved on a request from HN to SN that is sent in response to a request to HN. This check is performed after master-slave association is complete.	Interconnect propagates memory attributes of RN request to slaves.	Interconnect doesn't propagate memory attributes of RN request to slaves.	RN and SN	This check is applicable only when: svt_chi_system_configuration :: slave_xact_to_rn_xact_correlation_enable is set to 1 svt_chi_system_configuration :: memattr_propagation_checks_enable is set to 1 L3 is disabled for the target HN (should be specified via svt_chi_system_configuration :: set_hn_l3_cache_enable) The master and the associated slave transactions are both native CHI transactions.	ERROR	svt_chi_system_err_check
CHI System	coherent rsp	coherent_resp_passdirty_check	ARM-IHI0050E.b: 13.10.44 Response status, Resp	Monitor Check that the PassDirty response to initiating RN is correct	Checks that the PassDirty response(resp[2]) in the coherent response to initiating RN-F is correct. In case of ReadShared, ReadUnique, ReadNotSharedDirty(CHI-B OR LATER): If PassDirty was asserted for any snoop response received by the interconnect, and the interconnect has not asserted PassDirty in the coherent response to initiating RN, it's possible that Interconnect has taken the responsibility of updating the L3 cache or main memory. Note that this check does not verify if the interconnect updated L3 or main memory with dirty data. However, in this case, if the HN is not able to properly handle the dirty data, a subsequent read to same cacheline would result into read_data_integrity_check failure. This check is performed when the coherent transaction is complete.	Scenario 1: For ReadShared, ReadUnique and ReadNotSharedDirty: other than the scenarios where PassDirty is asserted in any of the associated snoop responses AND PassDirty is not asserted in the coherent response. If the PassDirty is asserted by interconnect in coherent response without any PassDirty asserted snoop responses/no associated snoops, its possible that interconnect has the line cached in L3 in dirty state, and is passing on the PassDirty to initiating RN. Scenario 2: For othr transaction types, when PassDirty is not asserted in coherent response to RN	For coherent transaction types other than ReadShared, ReadUnique and ReadNotSharedDirty, when PassDirty is asserted in coherent response from HN to initiating RN.	RN	This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)	ERROR	svt_chi_system_err_check
CHI System	coherent rsp	coherent_resp_isshared_check	ARM-IHI0050E.b: 13.10.44 Response status, Resp	Monitor Check that the final state in the coherent response to the initiating RN is set to Shared as expected	Checks the correctness of 'the final state in the coherent response to be Shared State or not'(IsShared response), for the following coherent transaction types from HN to initiating RN-F is correct: ReadClean, ReadShared ReadNotSharedDirty, ReadSpec (CHI-B OR LATER) This check is performed when the coherent transaction is complete	Scenarios other than the fail condition described	If the IsShared response is asserted in any of the associated snoops (by Snooped RN to HN), but IsShared response is not asserted in the coherent response (by HN to initiating RN)	RN	This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)	ERROR	svt_chi_system_err_check
CHI System	data integrity	read_data_integrity_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	Monitor Check that observed/received read data at RN matches with expected data from system monitor when: the snooped RNs return the data in clean state OR none of the snooped RNs return any data OR there are no snoops. System monitor establishes expected data based on observed RN requests with write data & RN snoop transactions with data, but does not depend on any subordinate transactions.	Checks that data in read transaction is consistent with system monitor HN(HN-F L3/HN-I memory) when the read transaction completes at RN. This check is applicable when the snooped RNs return the data in clean state or none of the snooped RNs return any data.	The data in RN read transaction matches with system monitor HN view when the RN read transaction completes.	The data in RN read transaction doesn't match with system monitor HN view when the RN read transaction completes.	RN	This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0). This check will not be performed when a hazard Write is detected for the Read transaction. The data bytes that are marked as poisoned, either in the transaction data or in the system monitor view, are ignored and not used for comparison. The data bytes that are have parity errors, are ignored and not used for comparison.	ERROR	svt_chi_system_err_check
CHI System	ABF	multiple_abf_requests_targeted_to_same_addr_and_to_same_target	SYNOPSYS DEFINED	Monitor Checks that there are no more than one address based flush requests to same address and to same target.	Checks that only one snoop transaction is issued to a given RN targeting a particular cacheline, as a result of Address based flush operation. This check will be performed if the address in the snoop transaction lies in range svt_chi_hn_status :: min_abf_addr and svt_chi_hn_status :: max_abf_addr.	If there exists only one snoop transaction as a result of Address based flushing operation issued to same cache line and to same target .	If there exists multiple snoop transactions as a result of Address based flushing operation issued to same cache line and to same target	Active RN	This check is applicable only when: the macro svt_chi_system_configuration :: abf_enable is set to 1.	ERROR	svt_chi_system_err_check
CHI System	routing	slave_transaction_routing_check	SYNOPSYS DEFINED	Monitor Check that transaction is routed to the correct slave based on the address of the transaction request	Checks that a transaction is routed correctly to a slave port based on address. This check is performed on the transactions routed from CHI interconnect to a CHI SN or an AXI slave, when the transactions are started at the slave. In case the transaction is routed to AXI slave, this check is performed under following conditions: The CHI system monitor (that is part of a CHI system ENV) and the AXI slave (that is part of an AXI system ENV) are part of an AMBA system ENV The mapping between CHI SNs and AXI slaves is provided through the APIs of AMBA system configuration Methodology used is UVM	The transaction is routed to the expected Slave, the check passes	The transaction is routed to an unexpected Slave, the check fails	SN	Note: When multiple SNs are mapped to single HN, users are expected to override either the svt_chi_system_configuration :: get_slave_node_id_for_addr for calculating slave_node_id and set svt_chi_system_configuration :: calculate_slave_id_based_on_xact_handle bit to 0 or override svt_chi_system_configuration :: get_slave_node_id_for_xact for calculating SN node id and set svt_chi_system_configuration :: calculate_slave_id_based_on_xact_handle bit to 1. For more details on svt_chi_system_configuration :: get_slave_node_id_for_addr or svt_chi_system_configuration :: get_slave_node_id_for_xact or svt_chi_system_configuration :: calculate_slave_id_based_on_xact_handle, please refer to corresponding class reference documenation. This check is constructed only when at least one SN is present in the CHI system (svt_chi_system_configuration :: num_sn > 0).	ERROR	svt_chi_system_err_check

Group

Sub Group

Protocol Check Instance name

Reference

Description

Check Intent

Pass Condition

Fail Condition

Applicable Device Type

Additional Information

Error Category

Protocol Check Class

CHI Protocol Layer

Node performance metrics

perf_min_write_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of write transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of write transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_write_throughput

The throughput of write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_min_write_throughput.

The throughput of write transactions in the specified interval is less than svt_chi_node_configuration :: perf_min_write_throughput.

RN and SN

Users can set the interval by programming svt_chi_node_configuration :: perf_recording_interval.
Alternately, users can set svt_chi_node_configuration :: perf_recording_interval to -1 and make use of svt_chi_node_perf_status :: start_performance_monitoring and svt_chi_node_perf_status :: stop_performance_monitoring to specify the interval.

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_write_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of write transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of write transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_write_throughput

The throughput of write transactions in the specified interval is less than svt_chi_node_configuration :: perf_max_write_throughput.

The throughput of write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_max_write_throughput.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_min_read_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of read transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of read transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_read_throughput

The throughput of read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_min_read_throughput.

The throughput of read transactions in the specified interval is less than svt_chi_node_configuration :: perf_min_read_throughput.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_read_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of read transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of read transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_read_throughput

The throughput of read transactions in the specified interval is less than svt_chi_node_configuration :: perf_max_read_throughput.

The throughput of read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_max_read_throughput.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_min_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of read transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of read transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_read_xact_latency

The average latency of Read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_min_read_xact_latency.

The average latency of Read transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_min_read_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_max_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of read transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of read transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_read_xact_latency

The average latency of Read transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_max_read_xact_latency.

The average latency of Read transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_max_read_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_min_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a read transaction is more than or equal to the configured min value

Checks that the latency of a read transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_read_xact_latency

The latency of a Read transaction is greater than svt_chi_node_configuration :: perf_min_read_xact_latency.

The latency of a Read transaction is less than than svt_chi_node_configuration :: perf_min_read_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a read transaction is less than or equal to the configured max value

Checks that the latency of a read transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_read_xact_latency

The latency of a Read transaction is less than than svt_chi_node_configuration :: perf_max_read_xact_latency.

The latency of a Read transaction is greater than than svt_chi_node_configuration :: perf_max_read_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_min_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of write transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of write transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_write_xact_latency

The average latency of Write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_min_write_xact_latency.

The average latency of Write transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_min_write_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_max_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of write transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of write transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_write_xact_latency

The average latency of Write transactions in the specified interval is less than svt_chi_node_configuration :: perf_avg_max_write_xact_latency.

The average latency of Write transactions in the specified interval is greater than svt_chi_node_configuration :: perf_avg_max_write_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_min_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a write transaction is more than or equal to the configured min value

Checks that the latency of a write transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_write_xact_latency

The latency of a Write transaction is greater than svt_chi_node_configuration :: perf_min_write_xact_latency.

The latency of a Write transaction is less than svt_chi_node_configuration :: perf_min_write_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a write transaction is less than or equal to the configured max value

Checks that the latency of a write transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_write_xact_latency

The latency of a Write transaction is less than svt_chi_node_configuration :: perf_max_write_xact_latency.

The latency of a Write transaction is greater than svt_chi_node_configuration :: perf_max_write_xact_latency.

RN and SN

ERROR

CHI Protocol Layer

Snoop Transaction timeout check

snp_transaction_inactivity_timeout_check

SYNOPSYS DEFINED

Check that a Snoop transaction ends within the programmed number of clock cycles.

Checks that a given Snoop transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: snp_xact_inactivity_timeout.
Vip will continue to process the snoop transaction even the snoop transaction has timedout. The timeout of the snoop transaction doesn't have any impact on the procesing or completion of the snoop transaction.
The timer started for snoop transaction will continue to increment even there is a link deactivation when snoop transaction is outstanidng.
This check is currently not designed to handle the cases when there is a dynamic reset.

The snoop transaction ends within the programmed number of clock cycles.

The snoop transaction does not end within the programmed number of clock cycles.

RN-F, RN-D(when svt_chi_node_configuration :: dvm_enable is set to 1)

This check is constructed only when configuration parameters snp_xact_inactivity_timeout (svt_chi_node_configuration :: snp_xact_inactivity_timeout) set to non zero values.

ERROR

CHI Protocol Layer

Transaction timeout check

transaction_inactivity_timeout_check

SYNOPSYS DEFINED

Check that a transaction ends within the programmed number of clock cycles.

Checks that a given transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: xact_inactivity_timeout.
Vip will continue to process the transaction even the transaction has timedout. The timeout of the transaction doesn't have any impact on the procesing or completion of the transaction.
The timer started for a transaction will continue to increment even there is a link deactivation when transaction is outstanidng.
This check is currently not designed to handle the cases when there is a dynamic reset.

The transaction ends within the programmed number of clock cycles.

The transaction does not end within the programmed number of clock cycles.

RN,SN

This check is constructed only when configuration parameters xact_inactivity_timeout (svt_chi_node_configuration :: xact_inactivity_timeout) set to non zero values.

ERROR

CHI Protocol Layer

exclusive access legal data_size transfer check

non_coherent_excl_access_legal_data_size_transfer_check

ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations

Check that the number of bytes to be transferred in an exclusive access must be a legal data transfer size, that is, 1, 2,4, 8, 16, 32, or 64 bytes.

The Data size of an Exclusive transaction is one of the values specified in the description.

The Data size of an Exclusive transaction is set to a value apart from the ones mentioned in the description.

RN-F

This check is constructed only when configuration parameters exclusive_access_enable (svt_chi_node_configuration :: exclusive_access_enable) and exclusive_monitor_enable (svt_chi_node_configuration :: exclusive_monitor_enable) are set to 1.

ERROR

CHI Protocol Layer

exclusive access address aligned to total bytes check

non_coherent_excl_access_aligned_total_bytes_transaction_check

ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations

Check that the address of an exclusive access must be aligned to the total number of bytes in the transaction.

The address of an exclusive transaction is aligned to the Data size.

The address of an exclusive transaction is not aligned to the Data size.

RN-F

ERROR

CHI Protocol Layer

non-coherent exclusive access same lpid check

non_coherent_excl_read_multiple_entry_for_same_lpid_check

ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations

Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time.

Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time.
Multiple exclusive transactions to Non-snoopable memory locations, either read or write, to the same or different addresses, from the same LP must not be outstanding at the same time.

An Exclusive Read transaction is received while there are no outstanding Exclusive Reads with the same LPID.

An Exclusive Read transaction is received but there already is an outstanding Exclusive Read with the same LPID.

RN-F

ERROR

CHI Protocol Layer

SACTIVE signal validity

valid_rxsactive_signal_check

ARM-IHI0050E.b: 14.7 Protocol layer activity indication

RXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received at the link partner node.

RXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received at the link partner node.
A transaction that is given a RetryAck response is considered to be in progress, so RXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned.
The check is performed under following conditions: while the link is active and there is no active reset --
- Whenever there is a flit activity observed(TX*FLITV/RX*FLITV asserted), RXSACTIVE must be sampled as HIGH. Otherwise the check fails.
  - Following are the specific conditions under which this check is performed:
    - In case of SN: if REQ flit is received, then rxsactive must be HIGH at the same clock
    - In case of RN: The same clock where the CompAck RSP is observed, this must be high
    - In case of RN: The same clock where SNPRSP is sampled by all receiving/observing components, this must be high
    - In case of RN: The same clock where SNP flit is observed, this must be HIGH
    - In the same cycle the RSP flit is received/observed, this must be high
    - In the same cycle the Read Data flit is received/observed, this must be high
    - In the same cycle the Snp Data flit is received/observed, this must be high
    - In the same cycle the Write Data flit is received/observed, this must be high
- Whenever the signal RXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity at the link partner node. Otherwise the check fails.
  - Following is the definition of 'pending protocol layer activity':
    - Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits)
    - Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions)
    - Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)

One of the FLITV signals is asserted and the conditions mentioned in the description are satisfied.

One of the FLITV signals is asserted and any of the conditions mentioned in the description are violated.

RN and SN

svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK This check will not be constructed when svt_chi_node_configuration :: use_external_node_prot_monitor is set to 1.

ERROR

CHI Protocol Layer

SACTIVE signal validity

valid_txsactive_signal_check

ARM-IHI0050E.b: 14.7 Protocol layer activity indication

TXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received.

TXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received.
A transaction that is given a RetryAck response is considered to be in progress, so TXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned.
Applicable when : the agent is in PASSIVE mode (svt_chi_node_configuration :: is_active = 0), and svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK
The check is performed under following conditions: while the link is active and there is no active reset --
- Whenever there is a flit activity observed(TX*FLITV/RX*FLITV asserted), TXSACTIVE must be sampled as HIGH. Otherwise the check fails.
  - Following are the specific conditions under which this check is performed:
    - REQ flit is received by PASSIVE agent, then txsactive must be HIGH at:
      - at the same clock, in case of RN
    - In case of RN: the same clock where CompAack RSP flit is observed, this must be high
    - In case of RN: The same clock where SNPRSP is observed, this must be high
    - In the same cycle the RSP flit is received/observed, this must be high
    - In the same cycle the Read Data flit is received/observed, this must be high
    - In the same cycle the Snp Data flit is received/observed, this must be high
    - In the same cycle the Write Data flit is received/observed, this must be high
- Whenever the signal TXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity. Otherwise the check fails.
  - Following is the definition of 'pending protocol layer activity':
    - Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits)
    - Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions)
    - Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)

One of the FLITV signals is asserted and the conditions mentioned in the description are satisfied.

One of the FLITV signals is asserted and any of the conditions mentioned in the description are violated.

Passive RN and Passive SN

svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK. This check will not be constructed when svt_chi_node_configuration :: use_external_node_prot_monitor is set to 1.

ERROR

CHI Protocol Layer

associate flit to xact

associate_readreceipt_to_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

If the request Order field indicates that ordering is required then a ReadReceipt response must be returned on the CRSP channel when order has been established

Check that the Ordering field of the transaction corresponding to the readreceipt is set.

A ReadReceipt response is received for an Ordered Read transaction.

SCENARIO 1:
A ReadReceipt is received for a Read transaction whose request order field was set to "NO ORDERING REQUIRED".
SCENARIO 2:
A ReadReceipt is received, at a CHI Issue C RN, for an Ordered Read transaction which has already received RESPSEPDATA.

RN and Passive SN

If the request Order field indicates that ordering is required then a ReadReceipt response must be returned on the CRSP channel when order has been established.

ERROR

CHI Protocol Layer

barrier xact

valid_resp_err_status_for_barrier_xact_check

ARM-IHI0050A: 9.4.4 Other transactions

A Barrier transaction response must not include an error response.

Check that there are no error responses in case of Barrier transactions .
A Barrier transaction response must not include an error response.

RespErr field in the Comp response of a Barrier transaction is set to OK.

RespErr field in the Comp response of a Barrier transaction is set to a value other than OK.

Passive RN and Passive SN-I

Barrier support is enabled (svt_chi_node_configuration :: barrier_enable == 1).

ERROR

CHI Protocol Layer

snp req validity

valid_rn_d_snoop_flit_check

ARM-IHI0050E.b: Table B-2 Snoop communicating nodes

Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.

Check that only DVMOp related snoop transactions are seen on the Snoop Channel in case of RN-D.
Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.

A SnpDVMOp is received for an RN-D node.

A Snoop transaction, other than a SnpDVMOp, is received for an RN-D node.

RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

dat flit valid

readunique_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadUnique transaction.
The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the CompData of a ReadUnique transaction is set to UD or UC.

Final cache state in the CompData of a ReadUnique transaction is set to SD, SC or I.

RN-F

ERROR

CHI Protocol Layer

dat flit valid

readshared_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadShared transaction.
The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the CompData of a ReadShared transaction is set to UC, UD, SC or SD.

Final cache state in the CompData of a ReadShared transaction is set to I.

RN-F

ERROR

CHI Protocol Layer

dat flit valid

readclean_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadClean transaction.
The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the CompData of a ReadClean transaction is set to UC or SC.

Final cache state in the CompData of a ReadClean transaction is set to I, UD or SD.

RN-F

ERROR

CHI Protocol Layer

resp flit valid

cleanunique_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a CleanUnique transaction.
The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Comp response of a CleanUnique transaction is set to UC.

Final cache state in the Comp response of a CleanUnique transaction is set to a value other than UC.

RN-F

ERROR

CHI Protocol Layer

resp flit valid

makeunique_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a MakeUnique transaction.
The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Comp response of a MakeUnique transaction is set to UC.

Final cache state in the Comp response of a MakeUnique transaction is set to a value other than UC.

RN-F

ERROR

CHI Protocol Layer

resp flit valid

evict_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a Evict transaction.
The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Comp response of an Evict transaction is set to I.

Final cache state in the Comp response of an Evict transaction is set to a value other than I.

RN-F

ERROR

CHI Protocol Layer

dat flit valid

readunique_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.

Check that the associated Compdata packet has valid resp_err value for ReadUnique transaction.
The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.

The RespErr field in the associated Compdata flits of a ReadUnique transaction are as per Table 9-2 in the CHI Specification.

The RespErr field in the associated Compdata flits of a ReadUnique transaction are set to EXOK.

RN-F

ERROR

CHI Protocol Layer

dat flit valid

readshared_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Compdata packet has valid resp_err value for ReadShared transaction.

The RespErr field in the associated Compdata flits of a ReadShared transaction are as per Table 9-2 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the ReadShared request was set to 1.

The RespErr field in the associated Compdata flits are set to EXOK but the Exclusive attribute in the ReadShared request was set to 0.

RN-F

ERROR

CHI Protocol Layer

dat flit valid

readclean_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Compdata packet has valid resp_err value for ReadClean transaction.

The RespErr field in the associated Compdata flits of a ReadClean transaction are as per Table 9-2 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the ReadClean request was set to 1.

The RespErr field in the associated Compdata flits are set to EXOK but the Exclusive attribute in the ReadClean request was set to 0.

RN-F

ERROR

CHI Protocol Layer

resp flit valid

cleanunique_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Comp response packet has valid resp_err value for CleanUnique transaction.

The RespErr field in the associated Comp response flits of a CleanUnique transaction are as per Table 9-3 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the CleanUnique request was set to 1.

The RespErr field in the associated Comp response flits are set to EXOK but the Exclusive attribute in the CleanUnique request was set to 0.

RN-F

ERROR

CHI Protocol Layer

resp flit valid

makeunique_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.

Check that the associated Comp response packet has valid resp_err value for MakeUnique transaction.
The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.

The RespErr field in the associated Comp response flits of a MakeUnique transaction are as per Table 9-3 in the CHI Specification.

The RespErr field in the associated Comp response flits of a MakeUnique transaction are set to EXOK.

RN-F

ERROR

CHI Protocol Layer

resp flit valid

evict_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.

Check that the associated Comp response packet has valid resp_err value for Evict transaction.
The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.

The RespErr field in the associated Comp response flits of an Evict transaction are as per Table 9-3 in the CHI Specification.

The RespErr field in the associated Comp response flits of an Evict transaction are set to EXOK.

RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

writeevict_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction.

Check that the associated response and data packets has valid resp_err value for WriteEvict transaction.

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction.
The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteEvict transaction. Note that this is applicable only for CHI Issue F or later specification.

The RespErr field in the associated Write data flits of a WriteEvict transaction are as per Table 9-7 in the CHI Issue F Specification. The RespErr field in the associated response flits of a WriteEvict transaction are as per Table 9-6 in the CHI Issue F Specification.

The RespErr field in the associated Write data flits of a WriteEvict transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteEvict transaction violate the legal values specified in Table 9-6 in the CHI Issue F Specification.

RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

writeclean_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction.

Check that the associated response and data packets has valid resp_err value for WriteClean transaction.

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction.
The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteClean transaction. Note that this is applicable only for CHI Issue F or later specification.

The RespErr field in the associated Write data flits of a WriteClean transaction are as per Table 9-7 in the CHI Issue F Specification. The RespErr field in the associated response flits of a WriteClean transaction are as per Table 9-6 in the CHI Issue F Specification.

The RespErr field in the associated Write data flits of a WriteClean transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteClean transaction violate the legal values specified in Table 9-6 in the CHI Issue F Specification.

RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

writeback_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction.

Check that the associated response and data packets has valid resp_err value for WriteBack transaction.

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction.
The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteBack transaction. Note that this is applicable only for CHI Issue F or later specification.

The RespErr field in the associated Write data flits of a WriteBack transaction are as per Table 9-7 in the CHI Issue F Specification. The RespErr field in the associated response flits of a WriteBack transaction are as per Table 9-6 in the CHI Issue F Specification.

The RespErr field in the associated Write data flits of a WriteBack transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteBack transaction violate the legal values specified in Table 9-6 in the CHI Issue F Specification.

RN-F

ERROR

CHI Protocol Layer

request validity

cache_transitioned_to_dirty_from_uce_for_read

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache transitioned to dirty stateUD/UDP from UCE.

Check if the RN has transitioned from UCE to UD/UDP state while there is an ongoing READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions. This check will flag an error in case the cache is updated via frontdoor or backdoor accesses to move from UCE to dirty state while there is an outstanding Read. .

If the RN has not transitioned to UD/UDP state from UCE state for READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions.

If the RN has transitioned to UD/UDP state from UCE state for READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions.

Active RN

This check is constructed only when partial_cache states are enabled at RN (svt_chi_node_configuration partial_cache_line_states_enable == 1).

ERROR

CHI Protocol Layer

ordering check

new_req_before_compdbid_resp_for_copyback_to_same_cacheline_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.

Check that a request to a cache line is issued when there are no outstanding Copyback transactions that are expecting CompDBIDResp.

An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.

A request flit is received and there are no pending Copybacks to the same address that are yet to receive CompDBIDResp.

A request flit is received and there is an outstanding Copyback to the same address which is yet to receive CompDBIDResp.

Passive RN-F

This check is applicable for all the Copyback transactions except WriteEvictorEvict transaction which are introduced in CHI ISSUE E. Similar kind of check for WriteEvictorEvict transaction is new_req_before_comp_or_compdbid_resp_for_copyback_writes_with_optional_data_to_same_cacheline_check. When the marco SVT_CHI_ISSUE_F_ENABLE is defined and svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_F or later, this check will look at the outstanding copyback write transaction with CAH set to 0, however the check new_req_before_comp_or_compdbid_resp_for_copyback_with_cah_set_and_to_same_cacheline_check will look at the outstanding copyback write transaction with CAH set to 1.

ERROR

CHI Protocol Layer

resp flit valid

snpmakeinvalid_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp has valid cache state for SnpMakeInvalid transaction.
The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Final cache state in the SnpResp of a SnpMakeInvalid transaction is set to I.

Final cache state in the SnpResp of a SnpMakeInvalid transaction is set to UC, UD, SC or SD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleaninvalid_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanInvalid transaction.
The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpCleanInvalid transaction is set to I.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpCleanInvalid transaction is set I.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpCleanInvalid transaction is set to UC, UD, SC or SD.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpCleanInvalid transaction is set to UC, UD, SC or SD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleanshared_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanShared transaction.
The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpCleanShared transaction is set to UC, SC or I.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpCleanShared transaction is set UC, SC or I.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpCleanShared transaction is set to UD or SD.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpCleanShared transaction is set UD or SD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpunique_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpUnique transaction.
The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpUnique transaction is set to I.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpUnique transaction is set I.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpUnique transaction is set to UC, UD, SC or SD.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpUnique transaction is set UC, UD, SC or SD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpshared_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpShared transaction.
The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpShared transaction is set to SC or I.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpShared transaction is set to SD, SC or I.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpShared transaction is set to UC, UD or SD.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpShared transaction is set to UC or UD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpclean_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpClean transaction.
The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpClean transaction is set to SC or I.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpClean transaction is set to SD, SC or I.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpClean transaction is set to UC, UD or SD.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpClean transaction is set to UC or UD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snponce_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpOnce transaction.
The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.

SCENARIO 1 :
Final cache state in the SnpResp of a SnpOnce transaction is set to UC, SC or I.
SCENARIO 2 :
Final cache state in the SnpRespData of a SnpOnce transaction is set to UC, SC, UD, SD or I.

Final cache state in the SnpResp of a SnpOnce transaction is set to UD or SD.

Passive RN-F

ERROR

CHI Protocol Layer

resp flit valid

snpmakeinvalid_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.

Check that the associated SnpResp packet has valid resp_err value for SnpMakeInvalid transaction.
The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.

SCENARIO 1:
RespErr field in SnpResp of a SnpMakeInvalid transaction is set to OK or NDERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpMakeInvalid transaction is set to OK or DERR.

SCENARIO 1:
RespErr field in SnpResp of a SnpMakeInvalid transaction is set to EXOK or DERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpMakeInvalid transaction is set to EXOK or NDERR.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleaninvalid_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanInvalid transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.

SCENARIO 1:
RespErr field in SnpResp of a SnpCleanInvalid transaction is set to OK or NDERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpCleanInvalid transaction is set to OK or DERR.

SCENARIO 1:
RespErr field in SnpResp of a SnpCleanInvalid transaction is set to EXOK or DERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpCleanInvalid transaction is set to EXOK or NDERR.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleanshared_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanShared transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.

SCENARIO 1:
RespErr field in SnpResp of a SnpCleanShared transaction is set to OK or NDERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpCleanShared transaction is set to OK or DERR.

SCENARIO 1:
RespErr field in SnpResp of a SnpCleanShared transaction is set to EXOK or DERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpCleanShared transaction is set to EXOK or NDERR.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpunique_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpUnique transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.

SCENARIO 1:
RespErr field in SnpResp of a SnpUnique transaction is set to OK or NDERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpUnique transaction is set to OK or DERR.

SCENARIO 1:
RespErr field in SnpResp of a SnpUnique transaction is set to EXOK or DERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpUnique transaction is set to EXOK or NDERR.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpshared_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpShared transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.

SCENARIO 1:
RespErr field in SnpResp of a SnpShared transaction is set to OK or NDERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpShared transaction is set to OK or DERR.

SCENARIO 1:
RespErr field in SnpResp of a SnpShared transaction is set to EXOK or DERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpShared transaction is set to EXOK or NDERR.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snpclean_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.5 Other transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpClean transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.

SCENARIO 1:
RespErr field in SnpResp of a SnpClean transaction is set to OK or NDERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpClean transaction is set to OK or DERR.

SCENARIO 1:
RespErr field in SnpResp of a SnpClean transaction is set to EXOK or DERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpClean transaction is set to EXOK or NDERR.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

snponce_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpOnce transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.

SCENARIO 1:
RespErr field in SnpResp of a SnpOnce transaction is set to OK or NDERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpOnce transaction is set to OK or DERR.

SCENARIO 1:
RespErr field in SnpResp of a SnpOnce transaction is set to EXOK or DERR.
SCENARIO 2:
RespErr field in SnpRespData of a SnpOnce transaction is set to EXOK or NDERR.

Passive RN-F

ERROR

CHI Protocol Layer

associate flit to xact

associate_snprspdata_flit_with_snp_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.

Check that the Transaction ID, SourceID and TargetID fields are set correctly in SnpResp Data flits.

The TgtID must be set to the the SrcID of the Snoop request. The TxnID must be set to the same value as the TxnID of the Snoop request.

Scenario 1:
A SnpRespData is received whose TgtID and TxnID match with the SrcID and TxnID of one of the outstanding Snoop requests.
Scenario 2:
In a CHI-B or later system, a SnpRespDataFwded response is received whose TgtID and TxnID match with the SrcID and TxnID of one of the outstanding Forward type Snoop requests.

Scenario 1:
A SnpRespData is received but there are no Snoop requests whose SrcID and TxnID match with the TgtID and TxnID of the SnpRespData flit.
Scenario 2:
In a CHI-B or later system, a SnpRespDataFwded response is received but there are no Forward type Snoops SrcID and TxnID match with the TgtID and TxnID of the SnpRespDataFwded flit.

Passive RN-F

ERROR

CHI Protocol Layer

resp flit validity

valid_snprsp_flit_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.

Check that the Transaction ID, SourceID and TargetID fields are set correctly in Snoop response flits.

The TgtID must be set to the the SrcID of the Snoop request. The TxnID is set to the same value as the TxnID of the Snoop request.

A SnpResp is observed corresponding to one of the outstanding Snoop requests at the RN

A SnpResp is observed but there are no outstanding Snoop requests with matching SourceID and TxnID values

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

writeevict_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteEvict transaction.
The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state of the Write data flits in a WriteEvict transaction is UC, SC or I.

Final cache state of the Write data flits in a WriteEvict transaction is UD or SD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

writeclean_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteClean transaction.
The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state of the Write data flits in a WriteCleanPtl transaction is either UD or I.

Final cache state of the Write data flits in a WriteCleanPtl transaction is either UC, SC or SD.

Passive RN-F

ERROR

CHI Protocol Layer

resp and dat flit valid

writeback_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteBack transaction.
The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state of the Write data flits in a WriteBackPtl transaction is either UD or I.
Final cache state of the Write data flits in a WriteBackPtl transaction is either UC or SC or SD and byte_enable is set to all 1's.

Final cache state of the Write data flits in a WriteBackPtl transaction is UC, SC or SD and byte_enable is not set to all 1's.

Passive RN-F

ERROR

CHI Protocol Layer

dat flit valid

valid_dat_flit_type_for_snp_xact_check

ARM-IHI0050E.b: 4.5 Response types

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

Data flit type must be set to one of the permitted values for the Snoop Request

SCENARIO 1:
A SnpRespData or SnpRespDataPtl response is observed for a non-forward type Snoop request.
SCENARIO 2:
A SnpRespDataFwded, CompData or SnpRespDataPtl response is observed for a forward type Snoop request.

SCENARIO 1:
A data response other than SnpRespData and SnpRespDataPtl is observed for a non-forward type Snoop request.
SCENARIO 2:
A data response other than SnpRespDataFwded, CompData and SnpRespDataPtl is observed for a forward type Snoop request.

Passive RN-F

ERROR

CHI Protocol Layer

dat flit valid

valid_cbwrdata_flit_for_xact_check

ARM-IHI0050E.b: 4.5.2 WriteData response

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

COPYBACKWRDATA is valid only in case of WriteBack, WriteClean and WriteEvict type transactions

A CopyBackWrData flit is received for a WriteBack, WriteClean or WriteEvict transaction.

A CopyBackWrData flit is received for a transaction type other than WriteBack, WriteClean and WriteEvict.

Passive RN-F

ERROR

CHI Protocol Layer

snp req validity

new_snp_req_before_compack_of_coherent_xact_which_received_comp_to_same_cacheline_check

ARM-IHI0050E.b: 4.11 Hazard conditions

The completer can send out the Snoop requests to an RN-F only when there are no outstanding coherent transactions from that particular RN-F targetting the same cache line that received completion response and has not yet received the CompAck/WrData

Check that for an RN-F node, Snoop request is observed when there are no outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck or Write Data.
Once a completion is received for a transaction, the completer must not send a snoop request to the same cache line until it receives:

A CompAck for any Read and Dataless requests except for ReadOnce* and ReadNoSnp.
A WriteData response for CopyBack and Atomic requests.
For WriteUnique, a WriteData response and, if applicable, CompAck.

A Snoop request flit is received and there are no outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck/WrData.

A Snoop request flit is received and there are outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck/WrData.

RN-F

ERROR

CHI Protocol Layer

snp req validity

new_snp_req_before_completion_of_previous_snp_xact_to_same_cacheline_check

ARM-IHI0050E.b: 4.11 Hazard conditions

The completer can send out the Snoop requests to an RN-F only when there are no outstanding Snoop transactions targetting the same cache line to that particular RN-F

Check that for an RN-F node, Snoop request is observed when there are no outstanding Snoop transactions targetting the same cache line.

A Snoop request flit is received and there are no outstanding Snoop transactions targetting the same cache line.

A Snoop request flit is received and there are one or more outstanding Snoop transactions targetting the same cache line.

RN-F

ERROR

CHI Protocol Layer

dvm xact

valid_order_of_dvmop_rspflits_check

ARM-IHI0050E.b: 2.3.7 DVM transactions

Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete

Check that the order of the responses sent by the Completer is correct in case of DVMOp transactions.
Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete. When the spec_revision is ISSUE_D or later and the DVMOp is a Non-sync DVMOp, then the interconnect is permitted but not required to wait for WriteData before sending the Comp. Currently VIP does not support early COMP support for DVM transaction.

A Comp response is received after the DBIDResp/WriteData flit.

A Comp response is received before DBIDResp/WriteData flit.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

dvm xact

valid_snpdvmop_part_check

ARM-IHI0050E.b: 8.1.3 Flow control

SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID

Check that both parts of a SnpDVMOp request are received at the RN.

SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID

At the end of the simulation, there are no SnpDVMOp transactions for which only one part of the SnpDVMOp request was received.

At the end of the simulation, there are one or more SnpDVMOp transactions for which only one part of the SnpDVMOp request was received.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

dvm xact

single_outstanding_snpdvmop_per_txn_id_check

ARM-IHI0050E.b: 2.4 Transaction identifier fields

The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID

Check that the TxnID of a SnpDVMOp must be unique for a given Requester.

The TxnID must be unique for a given Requester.
The Requester can reuse the ID only after it has received all responses associated with
a previous transaction that has used the same TxnID

A SnpDVMOp request is received and there are no outstanding SnpDVMOp requests with the same TxnID value.

A SnpDVMOp request is received but there is already an outstanding SnpDVMOp request with the same TxnID value.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

dvm xact

single_outstanding_snpdvmop_sync_check

ARM-IHI0050E.b: 8.1.3 Flow control

Only one SnpDVMOpSync transaction can be outstanding from an MN to an RN.

Check that there is only one outstanding DVMOp sync transaction at a given point in time.
Only one SnpDVMOp(Sync) transaction can be outstanding from an MN to an RN.

A SnpDVMOp(Sync) request is received and there are no outstanding SnpDVMOp(Sync) requests at the RN.

A SnpDVMOp(Sync) request is received but there are already outstanding SnpDVMOp(Sync) requests at the RN.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

resp flit valid

valid_resp_err_status_for_dvmop_xact_check

ARM-IHI0050E.b: 9.4.5 Other transactions

For DVMOP transaction, resp_err_status field of the associated Comp RSP flit must have one of the following values: 1NORMAL_OKAY 2NON_DATA_ERROR 3in case of chi_spec_revision >= ISSUE_B,DATA_ERROR.

Check that the comp response has valid resp_err value for DVMop transaction.
The associated Comp response should take one of the following resp_err values: 1)NORMAL_OKAY 2)NON_DATA_ERROR 3)in case of svt_chi_node_configuration :: chi_spec_revision >= ISSUE_B,DATA_ERROR for DVMop transaction.

If svt_chi_node_configuration :: chi_spec_revision>=ISSUE_B RespErr field in the Comp response of a DVMOp transaction is set to NORMAL_OKAY or NON_DATA_ERROR or DATA_ERROR.
If svt_chi_node_configuration :: chi_spec_revision==ISSUE_A RespErr field in the Comp response of a DVMOp transaction is set to NORMAL_OKAY or NON_DATA_ERROR.

If svt_chi_node_configuration :: chi_spec_revision>=ISSUE_B RespErr field in the Comp response of a DVMOp transaction is set to EXCLUSIVE_OKAY.
If svt_chi_node_configuration :: chi_spec_revision==ISSUE_A RespErr field in the Comp response of a DVMOp transaction is set to EXCLUSIVE_OKAY or DATA_ERROR.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

resp flit validity

valid_rspflit_for_dvmop_check

ARM-IHI0050E.b: 4.5.1 Completion response

A Comp response, with the Resp field set to zero, is always used for DVM transaction completion

Check that only Comp Response is used for DVMOp transactions, and not CompDBIDResp
When the spec_revision is ISSUE_D or later the Completer is permitted to opportunistically combine Comp and DBIDResp into CompDBIDResp response. This is applicable only in case of early comp support. Currently VIP does not support early COMP support for DVM transaction. A Comp response, with the Resp field set to zero, is always used for Barrier and DVM transaction completion.

A Comp response is received for a DVMOp transaction.

A CompDBIDResp flit is received for a DVMOp transaction.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

resp flit valid

snpdvmop_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.5 Other transactions

The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.

Check that the associated SnpResp packet has valid resp_err value for SnpDVMop transaction.
The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.

RespErr field in SnpResp of a SnpDVMOp transaction is set to OK or NDERR.

RespErr field in SnpResp of a SnpDVMOp transaction is set to EXOK or DERR.

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

resp flit valid

snpresp_for_snpdvmop_sync_only_after_completion_of_prior_snpdvmop_check

ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no prior SnpDVMOp transactions that are yet to receive a SnpResp from the RN.

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

A SnpResp flit is observed for a SnpDVMOp(sync) and there aren't any prior SnpDVMOp transactions that are yet to receive SnpResp.

A SnpResp flit is observed for a SnpDVMOp(sync) while there are prior SnpDVMOp transactions that are yet to receive SnpResp.

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1)

ERROR

CHI Protocol Layer

resp flit valid

snpresp_for_snpdvmop_sync_only_after_completion_of_all_non_dvm_sync_check

ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no outstanding DVMOp transactions at the RN.

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

A SnpResp flit is observed for a SnpDVMOp(sync) and there are no outstanding DVMOp transactions at the RN

A SnpResp flit is observed for a SnpDVMOp(sync) while there are outstanding DVMOp transactions at the RN

Passive RN-F and Passive RN-D

This is an optional check and is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1) and svt_chi_node_configuration :: snp_dvmop_sync_response_policy is set to WAIT_FOR_ALL_OUTSTANDING_DVM_NON_SYNC_TO_COMPLETE.

ERROR

CHI Protocol Layer

resp flit validity

valid_snprsp_for_snpdvmop_check

ARM-IHI0050E.b: 8.1.3 Flow control

An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction.

Check that the SnpDVMOpResp is observed only after both SnpDVMOp request packets.

An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction. The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively.

A SnpResp flit is observed for a SnpDVMOp transaction, after both parts of the SnpDVMOp request are received

A SnpResp flit is observed for a SnpDVMOp transaction, while only one part of the SnpDVMOp request is received

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

dvm xact

valid_snpdvmop_req_part_num_check

ARM-IHI0050E.b: 8.2 DVM Operation types

Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.

Check that the part numbers of the SnpDVMOp request packets are set correctly.
Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.

SnpDVMOp_Part1 and SnpDVMOp_Part2 request flits corresponding to a DVM Snoop transaction are received and the part numbers are set correctly.

Two SnpDVMOp_Part request flits corresponding to a DVM Snoop transaction are received but the part numbers of the two parts are the same.

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

dvm xact

single_outstanding_dvmop_sync_request_check

SYNOPSYS DEFINED

There can only be one outstanding DVMOpSync transaction from an RN at any point in time.

Check that there are no outstanding DVMOp(Sync) transactions when a DVMOp(Sync) request is received.
SYNOPSYS DEFINED
Not more than one DVMOp(Sync) transaction is expected to be outstanding from an RN at any given point in time, when svt_chi_node_configuration :: allow_multiple_dvm_sync_oustanding_xacts is set to 0.

A DVMOp(sync) request is received and there are no outstanding DVM(Sync) requests at the RN.

A DVMOp(sync) request is received but there already is an outstanding DVM(Sync) requests at the RN.

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1) and svt_chi_node_configuration :: allow_multiple_dvm_sync_oustanding_xacts is set to 0.

ERROR

CHI Protocol Layer

dvm xact

unused_bits_in_dvm_write_data_check

ARM-IHI0050E.b: 8.1.4 DVMOp field value restrictions

All the unused bits in the write data of a DVMOp transaction must be set to zero.

Check that the unused bits in the Write data of a DVMOp transaction are set to zero.

All the bits in the DVMOp write data that are not valid or unused are set to zero.

SCENARIO 1:
Bits corresponding to data[55:51] are set to a non-zero values.
SCENARIO 2:
VA Valid is 0, but the bits corresponding to data[50:4] are set to non-zero values.
SCENARIO 3:
VA Valid is set to 1 in the DVMOp transaction request that is Invalidate by PA, but bits corresponding to data[50:(44-2)] are set to non-zero values.
SCENARIO 4:
VA Valid is set to 1 in the DVMOp transaction request that is not Invalidate by PA, but bits corresponding to data[50:(((44 == 44)?49:((44 == 45)?51:53))-2)] are set to non-zero values.
SCENARIO 5:
In case of CHI-A, bits corresponding to data[63:56] are set to non-zero values.
SCENARIO 6:
In case of CHI-B or greater revisions, VMID Valid in the DVMOp transaction request is set to 0 but the bits corresponding to data[63:56] are set to non-zero values.
SCENARIO 7:
In case of CHI-D or earlier revisions, the bits corresponding to data[3:0] are set to non-zero values.
SCENARIO 8:
In case of CHI-E or greater revisions, for a DVM operation that is not Invalidate by VA type TLBI, the bits corresponding to data[3:0] are set to non-zero values.

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI Protocol Layer

dvm xact

expected_dvmop_sync_request_check

ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow

All previous DVMOp requests whose completion needs to be guaranteed by the DVMOpSync must have received a Comp response before the RN can send a DVMOpSync.

Check that there are no outstanding DVMOp(Non-sync) transactions when a DVMOp(Sync) request is received.

All previous DVMOp requests whose completion needs to be guaranteed by the DVMOp(Sync) must have received a Comp response before the RN can send a DVMOp(Sync).

When svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_ALL_NON_SYNC_TO_COMPLETE and a DVMOp(sync) request is received and there are no outstanding DVM(Non-sync) requests at the RN. When svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_NON_SYNC_FROM_SAME_LPID_TO_COMPLETE and a DVMOp(sync) request is received and there are no outstanding DVM(Non-sync) requests with the same LPID at the RN.

When svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_ALL_NON_SYNC_TO_COMPLETE and a DVMOp(sync) request is received but there are one or more outstanding DVM(Non-sync) requests at the RN. svt_chi_node_configuration :: dvm_sync_transmission_policy is set to WAIT_FOR_NON_SYNC_FROM_SAME_LPID_TO_COMPLETE and a DVMOp(sync) request is received but there are one or more outstanding DVM(Non-sync) requests with the same LPID at the RN.

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1) and svt_chi_node_configuration :: dvm_sync_transmission_policy is set to a value other than DO_NOT_WAIT_FOR_NON_SYNC_TO_COMPLETE.

ERROR

CHI Protocol Layer

barrier xact

normal_non_cacheable_or_device_writes_between_barriers_check

ARM-IHI0050A: 7.5.1

It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.

Check that Normal Non-cacheable or Device type writes were received, prior to the current Barrier and after the previous Barrier transaction

It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.

A Barrier transaction is received and there were normal,non-cacheable or Device type Writes seen before the Barrier, and after the previous Barrier if any.

A Barrier transaction is received and there were no normal,non-cacheable or Device type Writes seen before the Barrier, and after the previous Barrier if any.

Passive RN

This check is constructed only when Barrier support is enabled in the passive RN node (svt_chi_node_configuration :: barrier_enable == 1)

WARNING

CHI Protocol Layer

barrier xact

comp_received_for_normal_non_cacheable_or_device_writes_before_barrier_check

ARM-IHI0050A: 7.5 Barriers

An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request

Check that there are no outstanding Normal Non-cacheable or Device type writes, that are targeting an HN-I, which haven't received a Comp Repsonse, before a Barrier is issued by an RN.

An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request.

A Barrier is received and there are no pending normal,non-cacheable or Device type Writes to the same address that are yet to receive Comp Response

A Barrier is received and there are one or more pending normal,non-cacheable or Device type Writes to the same address that are yet to receive Comp Response

Passive RN

This check is constructed only when Barrier support is enabled in the passive RN node (svt_chi_node_configuration :: barrier_enable == 1)

ERROR

CHI Protocol Layer

request validity

expected_tgt_id_in_rn_xact_check

ARM-IHI0050E.b: 3.3.1 Target ID determination for Request messages

The Target ID in the request sent by the RN must be set as per the SAM, when target ID remapping is not expected at the Interconnect

Check that the Target ID field in the transaction request is set to the node ID of the HN as per the RN SAM.

When Target ID is not expected to be remapped at the Interconnect, RN must program the tgt_id of the request flit to the correct value as per the SAM.

A request is received with the tgt_id set to the expected HN node ID.

A request is received with the tgt_id set to a value other than the expected HN node ID.

Passive RN

This check is applicable only when svt_chi_system_configuration :: expect_target_id_remapping_by_interconnect is set to 0.

ERROR

CHI Protocol Layer

Compack timing

owo_writeunique_compack_timing_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

CompAck for an OWO WriteUnique must be sent once the Comp for all previous OWO WriteUnique transactions are received and comp When chi_spec_revision is less than or equal to ISSUE_C/Comp or DBIDResp or CompDBIDReespWhen chi_spec_revision is ISSUE_D or later for current WriteUnique transaction is received.

Check that the CompAck response for an ordered WriteUnique transaction is sent only afer following conditions are met:

Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transaction are received.
When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Comp response for the current OWO WriteUnique is received.

CompAck response for an ordered WriteUnique transaction is sent only after following conditions are met:

Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transactions are received.
When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Comp response for the current OWO WriteUnique is received

Check will fail for any one or both of the below cases:

CompAck response for an ordered WriteUnique transaction is sent before Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transactions are received.
When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, CompAck response for an ordered WriteUnique transaction is sent before DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, CompAck response for an ordered WriteUnique transaction is sent before Comp response for the current OWO WriteUnique is received.

Passive RN

This check is applicable only when svt_chi_node_configuration :: streaming_ordered_writeunique_enable set to 1 and svt_chi_node_configuration :: num_req_order_streams set to 1.
This check is performed only on OWO WriteUnique transactions for which order field set to REQ_ORDERING_REQUIRED and exp_comp_Ack is set to 1.

ERROR

CHI Protocol Layer

request validity

new_req_before_completion_of_previous_cmo_xacts_to_same_cacheline_check

ARM-IHI0050E.b: 4.2.2 Dataless transactions

Transaction intended for a particular address that can allocate data in Requester caches must not be sent to the interconnect before a previous CMO sent to the same address has completed.

Check that an allocating read request is issued when there are no outstanding CMO transactions to the same cache line.

An allocating read request flit is received and there are no pending CMOs to the same cache line.

An allocating read request flit is received and there is an outstanding CMO to the same cache line.

Passive RN

Propogation of CMOs to Slave nodes is currently not supported by the VIP. Therefore, this check is not applicable for SN.

ERROR

CHI Protocol Layer

request validity

cmo_xact_before_completion_of_previous_xacts_to_same_cacheline_check

ARM-IHI0050E.b: 4.2.2 Dataless transactions

A CMO intended for a particular address must not be sent before all previous requests, targeting the same cacheline, that can allocate data in the requester cache ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique are complete.

Check that a CMO request is issued when there are no outstanding transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches:

ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique

A CMO request flit is received and there are no pending transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches:

ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique

A CMO request flit is received and there are one or more pending transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches:

ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique

Passive RN

Propagation of CMOs to Slave nodes is currently not supported by the VIP. Therefore, this check is not applicable for SN.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeunique_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteUnique transaction.
The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Write data flits of a WriteUnique transaction is set to I.

Final cache state in the Write data flits of a WriteUnique transaction is set to a value other than I.

Passive RN

ERROR

CHI Protocol Layer

resp flit valid

expected_compack_check

ARM-IHI0050E.b: 2.3 Transaction structure

CompAck must be observed only after Comp or all CompData responses are received.

Check that the CompAck response is sent only afer Comp* or CompData response.

CompAck, if part of the transaction, must be observed only after Comp* or CompData responses are received.

A CompAck response is received for a transaction with ExpCompAck set and whose data phase is complete.
For OWO Write transactions(svt_chi_base_transaction :: exp_comp_ack set to 1 and svt_chi_base_transaction :: order_type set to REQ_ORDERING_REQUIRED),:

When svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Compack must be send out after reception of Comp response.
When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, Compack must be send out after reception of one of the response Comp or DBIDResp or CompDBIDResp.

In case of WriteEvictorEvict transaction, the check will pass when CompAck response is received after the reception of Comp response. In case of Copyback transactions with cah set to 1, the check will pass when CompAck response is received after the reception of Comp response.

A CompAck response is received for a transaction with ExpCompAck set but whose data phase is not yet complete.
For OWO Write transactions(svt_chi_base_transaction :: exp_comp_ack set to 1 and svt_chi_base_transaction :: order_type set to REQ_ORDERING_REQUIRED),:

When svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Compack send out before reception of Comp response.
When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, Compack received before reception of one of the responses Comp or DBIDResp or CompDBIDResp.

In case of WriteEvictorEvict transaction, the check will fail when CompAck response is received before the reception of any response from the Completer. In case of Copyback transactions with cah set to 1, the check will fail when CompAck response is received before the reception of any response from the Completer.

Passive RN

The data phase status can be known by looking at the data_status field in the transaction handle:

data_status == INITIAL implies the data transfer hasn't yet begun for the transaction
data_status == PARTIAL_ACCEPT implies the data transfer for the transaction is in progress
data_status == ACCEPT implies the data transfer is complete.

ERROR

CHI Protocol Layer

resp flit validity

valid_compack_rsp_flit_check

ARM-IHI0050E.b: 2.6.1 Read transactions

The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively. The TxnID is set to the same value as the DBID value provided in the read data response.

Check that the TransactionID, TargetID and SourceID fields are set correctly in the CompAck response.

The TgtID and SrcID must be set to the the SrcID and TgtID of the read data/comp/dbidresp/compdbidresp respectively. The TxnID is set to the same value as the DBID value provided in the read data/comp/dbidresp/compdbidresp response.

A CompAck response is received and there's an outstanding transaction with ExpCompAck asserted, whose Source ID, Target ID and DBID match with the TargetID, Source ID and TxnID of the CompAck respectively.

A CompAck response is received when there are no outstanding transactions with expcompack asserted, whose Source ID, Target ID and DBID match with the TargetID, Source ID and TxnID of the CompAck respectively.

Passive RN

ERROR

CHI Protocol Layer

single req order stream

single_req_order_stream_check

ARM-IHI0050E.b: 2.8 Ordering

The ordering requirements must be met for preceding active transactions with ReqOrder asserted before initiating next ordered transaction

Check that single ordered stream of requests from RN are ordered as per Request Ordering rules.
Request Ordering Rules update from CHI Issue D onwards:

In CHI Issue C or earlier, the Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range and includes the guarantee of Request Order.
In CHI Issue D or later, there will be no ordering guarantees between two ordered transactions from the same source that have different ordering requirements. In other words, Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range, but doesn’t include the guarantee of Request Order.

In CHI Issue C or earlier:

When a new Ordered transaction is observed and there are either no preceding Ordered transactions or there are preceding Ordered transactions whose ordering conditions are already met.

In CHI Issue D or later:

When a new Request_Ordered transaction is observed and there are either no preceding Request_Ordered transactions or there are preceding Request_Ordered transactions whose ordering conditions are already met.
When a new Endpoint_Ordered transaction is observed and there are either no preceding Endpoint_Ordered transactions or there are preceding Endpoint_Ordered transactions whose ordering conditions are already met.

In CHI Issue C or earlier:

When a new Ordered transaction is observed and there are preceding Ordered transactions whose ordering requirements are not yet met.

In CHI Issue D or later:

When a new Request_Ordered transaction is observed and there are preceding Request_Ordered transactions whose ordering requirements are not yet met.
When a new Endpoint_Ordered transaction is observed and there are preceding Endpoint_Ordered transactions whose ordering requirements are not yet met.

Passive RN

svt_chi_node_configuration :: num_req_order_streams should reflect the number of request order streams that the RN has.
The passive RN agent performs this check only when the number of request order streams is one, ie, svt_chi_node_configuration :: num_req_order_streams is set to 1. This is because the stream ID to which a given transaction belongs is not transmitted on the interface. So it is important to make sure that the passive RN agent is configured appropriately for this.
The passive RN agent can track the transactions those have the ReqOrder information transmitted on the interface, that is available through svt_chi_base_transaction :: order_type. Note that the CopyBack type transactions do not transmit the ReqOrder information on the interface through REQ VC Flit.

ERROR

CHI Protocol Layer

resp and dat flit valid

expected_remapped_tgt_id_in_response_check

ARM-IHI0050E.b: 3.3.1 Target ID determination for Request messages

The Target ID in the request must be remapped correctly as per the SAM and the Source ID of the subsequent response flits must be set to the remapped Target ID value

Check that the Target ID is remapped correctly at the Interconnect.

When Target ID remapping is expected at the Interconnect, the Target ID field in the received request must be remapped correctly as per the SAM.
This check is performed when target ID is remapped by the Interconnect and the SAM is specified correctly in the system configuration.

Remapped Target ID received in the response from the Interconnect matches the HN node ID as per the SAM.

Remapped Target ID received in the response from the Interconnect does not match the HN node ID as per the SAM.

This check is applicable only when svt_chi_system_configuration :: expect_target_id_remapping_by_interconnect and svt_chi_system_configuration :: rn_sam_specified_with_exp_tgt_id_remap_at_icn_enabled are set to 1.

ERROR

CHI Protocol Layer

resp flit validity

valid_pcrdgrant_check

ARM-IHI0050E.b: 2.11 Request Retry

PcrdGrant is not seen without any outstanding transaction

Checks PcrdGrant is not seen without any outstanding transaction.

PcrdGrant is seen and there are outstanding transaction.

PcrdGrant is seen without any outstanding transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeunique_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUnique transaction.

Check that the associated response and data packets has valid resp_err value for WriteUnique transaction.
The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUnique transaction.

The RespErr field in the associated Write data flits of a WriteUnique transaction are as per Table 9-5 in the CHI Specification. The RespErr field in the associated response flits of a WriteUnique transaction are as per Table 9-4 in the CHI Specification.

The RespErr field in the associated Write data flits of a WriteUnique transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteUnique transaction violate the legal values specified in Table 9-4 in the CHI Specification.

ERROR

CHI Protocol Layer

dat flit valid

readonce_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadOnce transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadOnce transaction.
The cache state in the associated CompData flits of a ReadOnce transaction should indicate a valid value when the RespErr field does not indicate any errors.

In case of a CHI-A node:
final cache state in the CompData of a ReadOnce transaction is set to I.
In case of a CHI-B or later node:
final cache state in the CompData of a ReadOnce transaction is set to I or UC when DMT is not used.
final cache state in the CompData of a ReadOnce transaction is set to UC when DMT is used.

In case of a CHI-A node:
final cache state in the CompData of a ReadOnce transaction is set to a value other than I.
In case of a CHI-B or later node:
final cache state in the CompData of a ReadOnce transaction is set to a value other than I or UC when DMT is not used.
final cache state in the CompData of a ReadOnce transaction is set to a value other than UC when DMT is used.

ERROR

CHI Protocol Layer

dat flit valid

readonce_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated compdata packet's resp_err field should not take EXOK value for ReadOnce transaction.

Check that the associated Compdata packet has valid resp_err value for ReadOnce transaction.
The associated compdata packet's resp_err field should not take EXOK value for ReadOnce transaction.

The RespErr field in the associated Compdata flits of a ReadOnce transaction are as per Table 9-2 in the CHI Specification.

The RespErr field in the associated Compdata flits of a ReadOnce transaction are set to EXOK.

ERROR

CHI Protocol Layer

resp flit valid

makeinvalid_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a MakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a MakeInvalid transaction.
The cache state in the associated comp response of a MakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Comp response of a MakeInvalid transaction is set to I.

Final cache state in the Comp response of a MakeInvalid transaction is set to a value other than I.

RN, Passive SN

ERROR

CHI Protocol Layer

resp flit valid

cleaninvalid_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a CleanInvalid transaction.
The cache state in the associated comp response of a CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Comp response of a CleanInvalid transaction is set to I.

Final cache state in the Comp response of a CleanInvalid transaction is set to a value other than I.

RN, Passive SN

ERROR

CHI Protocol Layer

resp flit valid

cleanshared_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a CleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a CleanShared transaction.
The cache state in the associated comp response of a CleanShared transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Comp response of a CleanShared transaction is set to UC, SC or I.

Final cache state in the Comp response of a CleanShared transaction is set to UD or SD.

RN, Passive SN

ERROR

CHI Protocol Layer

resp flit valid

makeinvalid_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for MakeInvalid transaction.

Check that the associated Comp response packet has valid resp_err value for MakeInvalid transaction.
The associated comp response packet's resp_err field should not take EXOK value for MakeInvalid transaction.

The RespErr field in the associated Comp response flits of a MakeInvalid transaction are as per Table 9-3 in the CHI Specification.

The RespErr field in the associated Comp response flits of a MakeInvalid transaction are set to EXOK.

RN, Passive SN

ERROR

CHI Protocol Layer

resp flit valid

cleaninvalid_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for CleanInvalid transaction.

Check that the associated Comp response packet has valid resp_err value for CleanInvalid transaction.
The associated comp response packet's resp_err field should not take EXOK value for CleanInvalid transaction.

The RespErr field in the associated Comp response flits of a CleanInvalid transaction are as per Table 9-3 in the CHI Specification.

The RespErr field in the associated Comp response flits of a CleanInvalid transaction are set to EXOK.

RN, Passive SN

ERROR

CHI Protocol Layer

resp flit valid

cleanshared_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for CleanShared transaction.

Check that the associated Comp response packet has valid resp_err value for CleanShared transaction.
The associated comp response packet's resp_err field should not take EXOK value for CleanShared transaction.

The RespErr field in the associated Comp response flits of a CleanShared transaction are as per Table 9-3 in the CHI Specification.

The RespErr field in the associated Comp response flits of a CleanShared transaction are set to EXOK.

RN, Passive SN

ERROR

CHI Protocol Layer

dat flit valid

valid_resp_for_data_packet_check

ARM-IHI0050E.b: 4.5 Response types

The Resp field in a response must have the same value for every packet of a data message regardless of whether or not there is an error condition.

Check that the resp field has the same value for all data flits of a multi-flit data transfer .
The resp field in a response must have the same value for every packet of a data message regardless of whether or not there is an error condition.

The Resp field in the data flits corresponding to a transaction are all set to the same value.

The Resp field in the data flits corresponding to a transaction are not set to the same value.

RN and Passive SN

ERROR

CHI Protocol Layer

dat flit valid

single_xact_mix_ok_exok_response_check

ARM-IHI0050E.b: 9.2 Error response fields

A single transaction is not permitted to mix OK and EXOK responses.

Check that a single transaction does not mix OK and EXOK responses within its data packets .
A single transaction is not permitted to mix OK and EXOK responses.

The RespErr field in the data flits corresponding to a transaction are all set to the same value.

The RespErr field in the data flits corresponding to a transaction are not set to the same value.

RN and passive SN

ERROR

CHI Protocol Layer

dat flit field

valid_ccid_in_dat_flit_check

ARM-IHI0050E.b: 2.10.6 Critical Chunk Identifier

CCID of all the data packets belonging to a transaction must be the same and equal to addr[5:4] of the corresponding Request

Check that the CCID field value in the data flit is set correctly.

CCID of all the data packets belonging to a transaction must be the same and equal to addr[5:4] of the corresponding Request.

The CCID field in the Data flit does not match with addr[5:4] of the corresponding transaction.

The CCID field in the Data flit are equal to addr[5:4] of the corresponding transaction.

RN and SN

ERROR

CHI Protocol Layer

dat flit valid

dbid_value_must_be_same_across_read_data_flits_check

ARM-IHI0050E.b: 2.5.9 Data Buffer ID

DBID must take the same value in all read data flits corresponding to a Read transaction with ExpCompAck set to 1

For a Read transaction, if the DBID is valid then the DBID field must take same value in all the corresponding read data flits. DBID is valid if ExpCompAck is set to 1 for the corresponding Read transaction.

A same DBID field value is observed in all the read data flits (CompData or DataSepResp) corresponding to a Read request with ExpCompAck set to 1.

A difference in DBID field value is observed across the read data flits (CompData or DataSepResp) corresponding to a Read request with ExpCompAck set to 1.

ERROR

CHI Protocol Layer

resp flit valid

separate_dbidresp_and_comp_must_include_same_dbid_value_check

ARM-IHI0050E.b: 2.5 Details of transaction identifier fields

A Comp response message sent separate from a DBIDResp or DBIDRespOrd message for a Write transaction must include the same DBID field value in the Comp and DBIDResp or DBIDRespOrd message

A Comp response sent separate from a DBIDResp or DBIDRespOrd response for a write transaction (except Atomic transactions) must include the same DBID field value in the Comp and DBIDResp or DBIDRespOrd message.
Applicable only in case of non-copyback Write transactions and non-copyback Combined Write plus CMO transactions as the copyback transactions always include a combined CompDBIDResp response. Applicable only if the Direct Write Data transfer is not exercised for the Write transaction.

A same DBID field value is observed in Comp and DBIDResp or DBIDRespOrd reponses for a non-copyback Write transaction or non-copyback Combined Write plus CMO transaction with separate comp and DBIDResp or DBIDRespOrd reponses.

A different DBID field value is observed in Comp and DBIDResp or DBIDRespOrd reponses for a non-copyback Write transaction or non-copyback Combined Write plus CMO transaction with separate comp and DBIDResp or DBIDRespOrd reponses.

RN and Passive SN

ERROR

CHI Protocol Layer

resp flit valid

rsp_flit_dbid_check

ARM-IHI0050E.b: Table A-8 Response message field mappings

DBID field of the observed RSP flit must be valid

Check that the DBID field value of the following RSP flits is as follows.
RSP flits:

Comp/DBID/CompDBIDResp: DBID field must be unique for a given transaction and can be reused only after the transaction completes

In case of WriteNoSnpZero and WriteUniqueZero transactions dbid field in Comp/DBID/COMPSBISREesp is inapplicable and can take any value.

For Dataless transactions with ExpCompAck asserted, the DBID field in the Comp response is unique and there are no other outstanding non-DMT and non-DCT transactions that have received the same DBID value.
For Read transactions with ExpCompAck asserted, the DBID field in the RespSepData response is unique and there are no other outstanding non-DMT and non-DCT transactions that have received the same DBID value.
For Write transactions(except WriteNoSnpZero and WriteUniqueZero), the DBID field in Comp (for Issue B or lower revisions) or DBIDResp or CompDBIDResp is unique and there are no other outstanding non-DMT and non-DCT transactions that have received the same DBID value.

For Dataless transactions with ExpCompAck asserted, the DBID field in the Comp response is not unique; there is already an outstanding non-DMT and non-DCT transaction with the same DBID value.
For Read transactions with ExpCompAck asserted, the DBID field in the RespSepData response is not unique; there is already an outstanding non-DMT and non-DCT transaction with the same DBID value.
For Write transactions(except WriteNoSnpZero and WriteUniqueZero), the DBID field in Comp (for Issue B or lower revisions) DBIDResp or CompDBIDResp is not unique; there is already an outstanding non-DMT and non-DCT transaction with the same DBID value.

RN and SN

ERROR

CHI Protocol Layer

dat flit valid

readnosnp_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadNoSnp transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadNoSnp transaction.
The cache state in the associated CompData flits of a ReadNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.

In case of a CHI-A node:
final cache state in the CompData of a ReadNoSnp transaction is set to I.
In case of a CHI-B or later node:
final cache state in the CompData of a ReadNoSnp transaction is set to I or UC when DMT is not used.
final cache state in the CompData of a ReadNoSnp transaction is set to UC when DMT is used.

In case of a CHI-A node:
final cache state in the CompData of a ReadNoSnp transaction is set to a value other than I.
In case of a CHI-B or later node:
final cache state in the CompData of a ReadNoSnp transaction is set to a value other than I or UC when DMT is not used.
final cache state in the CompData of a ReadNoSnp transaction is set to a value other than UC when DMT is used.

RN and Passive SN

ERROR

CHI Protocol Layer

dat flit valid

readnosnp_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Compdata packet has valid resp_err value for ReadNoSnp transaction.
The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

The RespErr field in the associated Compdata flits of a ReadNoSnp transaction are as per Table 9-2 in the CHI Specification. If RespErr is EXOK, the exclusive attribute in the ReadNoSnp request was set to 1.

The RespErr field in the associated Compdata flits are set to EXOK but the Exclusive attribute in the ReadNoSnp request was set to 0.

RN and Passive SN

ERROR

CHI Protocol Layer

resp flit validity

valid_compdbid_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that CompDBID Response flit is seen only in case of Write/CopyBack or AtomicStore transactions.
The Response flit type must correspond to one of the permitted values depending on the type of the transaction

CompDBIDResp is received for a WriteNoSnp*, WriteUnique*, CopyBack or AtomicStore request.

CompDBIDResp is received for a Read, dataless, DVMop or AtomicLoad/Swap/Compare request.

RN and Passive SN

ERROR

CHI Protocol Layer

resp flit validity

valid_dbid_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that DBID Response flit is seen only in case of non-Copyback Write transactions.
The Response flit type must correspond to one of the permitted values depending on the type of the transaction

DBIDResp is received for a WriteNoSnp or WriteUnique request.

DBIDResp is received for a Copyback request.

RN and Passive SN

ERROR

CHI Protocol Layer

resp flit validity

valid_comp_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5.1 Completion response

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that Comp Response flit is seen only in case of non-Snoop transactions.
The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Comp response is received for a dataless, DVMOp, WriteEvictorEvict or a non-Copyback Write transaction.

Comp response is received for a Read or a Copyback transaction(except WriteEvictorEvict).

RN and Passive SN

ERROR

CHI Protocol Layer

associate flit to xact

expected_rsp_flit_for_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The number of Response flits received for a transaction must match the number of responses, specified in the spec, for that transaction type.

Check that the transaction for which the coherent response is received has not already received a coherent response

The number of Response flits received for a transaction must match the number of responses, specified in the spec, for that transaction type.

A response flit is received for one of the outstanding transactions which is yet to receive a coherent response.

A response flit is received for one of the outstanding transactions which has already received all applicable coherent responses (resp_status == ACCEPT).

RN and Passive SN

ERROR

CHI Protocol Layer

associate flit to xact

associate_rsp_flit_to_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID of the response flit must be match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

Check that the Transaction ID, SourceID and TargetID fields are set correctly in the Response flits.

The SrcID and TgtID of the response flit must match the TgtID and SrcID of the request while the Txn ID of the response flit must be the same as that of the Request

A response flit is received for one of the outstanding transactions which is yet to receive a coherent response.

A response flit is received but there are no outstanding transactions whose SrcID,TgtID and TxnID match the TgtID,SrcID and TxnID of the response.

RN and Passive SN

In case svt_chi_system_configuration :: expect_target_id_remapping_by_interconnect is set to 1, the SrcID of the response flit will not be compared with the TgtID of the outstanding requests at the RN.

ERROR

CHI Protocol Layer

associate flit to xact

expected_num_read_data_flits_check

ARM-IHI0050E.b: 2.10.4 Data packetization

The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

Check that the number of Read Data flits is equal to the expected value
The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

A Read Data flit is received for a Read transaction whose data phase is not yet complete (data_status is either INITIAL or PARTIAL_ACCEPT)

A Read Data flit is received for a Read transaction whose data phase is complete (data_status == ACCEPT)

RN and Passive SN

ERROR

CHI Protocol Layer

associate flit to xact

associate_read_dat_flit_with_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID of the Read data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

Check that the Transaction ID, SourceID and TargetID fields are set correctly in Read Data flits.

When SVT_CHI_ISSUE_B_ENABLE or SVT_CHI_ISSUE_C_ENABLE macro is not defined:
The TgtID of the Read data flit must match the SrcID of the Request
The SrcID of the Read data flit must match the TgtID of the Request
The TxnID of the Read data flit must be the same as that of the Request

When SVT_CHI_ISSUE_B_ENABLE or SVT_CHI_ISSUE_C_ENABLE macro is defined:
For RN: The TgtID of the Read data flit must match the SrcID of the Request irrespective of spec revision
For SN/HN: The TgtID of the Read data flit must match the SrcID of the Request for spec revision ISSUE_A
For SN/HN: The TgtID of the Read data flit must match the ReturnNID of the Request for spec revision ISSUE_B or later
For RN: The SrcID of the Read data flit must match the TgtID of the Request for ISSUE_A
For RN: The HomeNID of the Read data flit must match the TgtID of the Request for ISSUE_B or later
For SN/HN: The SrcID of the Read data flit must match the TgtID of the Request irrespective of spec revision
For RN: The TxnID of the Read data flit must be the same as that of the Request irrespective of spec revision
For SN/HN: The TxnID of the Read data flit must be the same as that of the Request for spec revision ISSUE_A
For SN/HN: The TxnID of the Read data flit must be the same as that of the ReturnTxnID Request for spec revision ISSUE_B or later

A CompData flit is received for one of the outstanding Read transactions whose data phase isn't complete yet.

In case of a CHI-A node, a CompData flit is received but there are no outstanding transactions whose TgtID,SrcID and TxnID match with the SrcID,TgtID and TxnID of the CompData. In case of CHI-B or later RN, a CompData flit is received but there are no outstanding transactions whose TgtID,SrcID and TxnID match with the HomeNID,TgtID and TxnID of the CompData. In case of CHI-B or later SN, a CompData flit is received but there are no outstanding transactions whose TgtID,ReturnNID and ReturnTxnID match with the HomeNID,TgtID and TxnID of the CompData.

RN and Passive SN

ERROR

CHI Protocol Layer

dat flit valid

valid_compdata_flit_for_xact_check

ARM-IHI0050E.b: 4.5.1 Completion response

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

COMPDATA is valid only in case of Read type transactions

A CompData flit is received for a Read transaction.

A CompData flit is received for a non-Read type transaction.

RN and Passive SN

ERROR

CHI Protocol Layer

request validity

new_req_before_completion_of_previous_read_write_xact_to_same_cacheline_check

ARM-IHI0050E.b: 2.9.4 Transaction attribute combinations

Read and Write transactions from the same source to addresses that overlap must remain ordered.

Check that a Read, Write, Dataless or Atomic request is issued when there are no outstanding Read or Write transactions to the same cache line.

"Outstanding Read" refers to all Read as well as dataless transactions other than CMOs.
"Outstanding Write" refers to all Write and Atomic transactions.

A Read, Write, Dataless or Atomic request flit is received and there are no outstanding Read, Write, Dataless or Atomic transactions to the same cache line.

A Read, Write, Dataless or Atomic request flit is received and there are one or more outstanding Read, Write, Dataless or Atomic transactions to the same cache line.

Passive RN, SN

In case there are multiple sources within an RN, it cannot be determined if the requests are issued by the same source based on the request fields. Therefore, this check will not be performed at passive RN when svt_chi_node_configuration :: multiple_req_sources_within_rn_node is set to 1.
In case DMT Reads are issued at the SN, it is possible that the Interconnect de-allocates the Reads before SN sends CompData to the RN. In such a case, it is possible that the Interconnect issues a second request to the same address while the CompData of the previous DMT Read is in progress or is yet to be sent to the RN. Therefore, this check will not consider DMT Reads at the SN while looking for outstanding transactions to a given cacheline.

ERROR

CHI Protocol Layer

request validity

expected_xact_type_check

SYNOPSYS DEFINED

Only supported transaction types must be issued to a given node.

Check that only supported transaction types are received for a given node.
SYNOPSYS DEFINED:

DVMOp transactions are epected to be seen only for RNs with svt_chi_node_configuration :: dvm_enable set to 1
CHI-B or later specific transactions (RNSD, ROMI, ROCI, CSP, PrefetchTgt, AtomicOps) are expected to be seen only for a CHI-B or later compliant RN.
CHI-E or later specific transactions (Write*Zero, WriteEvictorEivct,...) are expected to be seen only for a CHI-E or later compliant RN.
CHI-F or later specific transactions (CleanInvalidPopa, WriteNoSnpDef, WriteBackFull_CleanInvalidPopa, WriteNoSnpFull_CleanInvalidPopa, WriteNoSnpPtl_CleanInvalidPopa) are expected to be seen only for a CHI-F or later compliant RN.
CHI-F transaction WriteNoSnpDef is currently unsupported by all CHI VIP components.
VIP currently does not support PrefetchTgt transactions.

Scenario 1:
A request other than PrefetchTgt, ReadNotSharedDirty, ROMI, ROCI, PrefetchTgt and AtomicOps is seen for a CHI-A RN-F.
Scenario 2:
A request other than PrefetchTgt is seen for a CHI-B or later RN-F.
Scenario 3:
A ReadNoSnp or WriteNoSnp transaction is received by an SN.
Scenario 4:
A DVMOp transaction is seen for an RN-F or RN-D whose svt_chi_node_configuration :: dvm_enable is set to 1.
Scenario 5:
ReadNoSnpSep is seen by an SN for a CHI-C or later.
Scenario 6:
ReadNoSnpSep is send from an HN with sep read and sep resp enabled.
Scenario 7:
CHI ISSUE E specific transaction request is seen for a CHI-E or later compliant RN.
Scenario 8:
CHI ISSUE F specific transaction request is seen for a CHI-F or later compliant RN.
Scenario 9:
CHI ISSUE F WriteNoSnpDef request is NOT observed on any CHI VIP component.

Scenario 1:
A PrefetchTgt, ReadNotSharedDirty, ROMI, ROCI, PrefetchTgt or AtomicOps transaction request is seen for a CHI-A RN-F.
Scenario 2:
A PrefetchTgt transaction request is seen for a CHI-B or later RN-F.
Scenario 3:
A transaction of type other than WriteNoSnp and ReadNoSnp is received by an SN.
Scenario 4:
A DVMOp transaction is seen for an RN whose svt_chi_node_configuration :: dvm_enable is 0.
Scenario 5:
A DVMOp transaction is seen for an RN-I.
Scenario 6:
ReadNoSnpSep is seen by an SN for a CHI-B or before.
Scenario 7:
ReadNoSnpSep is send from an HN with sep read and sep resp disabled.
Scenario 8:
CHI ISSUE E specific transaction request is seen for a CHI-D or earlier compliant RN.
Scenario 9:
CHI ISSUE F specific transaction request is seen for a CHI-E or earlier compliant RN.
Scenario 10:
CHI ISSUE F WriteNoSnpDef request is observed at a CHI VIP component.

Passive RN and SN

VIP CHI-F or later transactions are currently not supported by CHI VIP components.
VIP CHI-E or later SN currently does not support combined write and (P)CMO transactions.
VIP CHI-E or later SN currently supports Atomics only with TAG_OP as TAG_INVALID.
The check will be updated once support for these transactions is added.

ERROR

CHI Protocol Layer

retry xact

valid_pcrdreturn_check

ARM-IHI0050E.b: 2.3.8 Retry

PcrdReturn transaction can only be sent after the reception of a PcrdGrant flit

Check that PCrdReturn is sent only after RetryAck and PCrdGrant flits are received from the Target node.
PcrdReturn transaction can only be sent after the reception of a PcrdGrant flit

A PCrdReturn transaction is seen after the prior reception of PCrdGrant and RetryAck, with the SrcID and PCrdType set to the same value as the TgtID and PCrdType of the PCrdReturn.

A PCrdReturn transaction is seen but there were no corresponding PCrdGrant and RetryAck, whose SrcID and PCrdType match the TgtID and PCrdType of the PCrdReturn.

Passive RN and SN

ERROR

CHI Protocol Layer

retry xact

valid_retry_xact_check

ARM-IHI0050E.b: 2.3.8 Retry

The transaction with credit must only be sent by the Requester after both the RetryAck response and an appropriate PCrdGrant response are received

Check that the transaction is retried only after RetryAck and PCrdGrant responses are received from the Target node.
The transaction with credit must only be sent by the Requester after both the RetryAck response and an appropriate PCrdGrant response are received, and the transaction attributes other than PCrdType, AllowRetry and QoS must be the same as the original request.

A retry transaction is seen after the prior reception of PCrdGrant and RetryAck, with the SrcID and PCrdType set to the same value as the TgtID and PCrdType of the retry transaction, and,
The valid appliacble attributes of the retry transaction match with those of the original request.

A retry transaction is seen but there were no corresponding PCrdGrant and RetryAck, whose SrcID and PCrdType match the TgtID and PCrdType of the retry transaction, or,
One or more applicable attributes of the retry transaction do not match with those of the Original request.

RN and Passive SN

ERROR

CHI Protocol Layer

retry xact

valid_retry_xact_after_pcrdcgrant_check

ARM-IHI0050E.b: 2.11 Request Retry

The transaction must only be retried by the Requester when a PCrdGrant is received with the correct PCrdType.

The transaction must only be retried by the Requester when a PCrdGrant is received with the correct PCrdType

A retry transaction is received while there are available granted credits for the PCrdType.

A retry transaction is received while there are no available granted credits for the PCrdType,ie, the retry tranaction is received without the recpetion of a PCrdGrant with the same PCrdType

Passive RN and SN

ERROR

CHI Protocol Layer

retry xact

valid_p_crd_type_in_pcrdreturn_flit_check

ARM-IHI0050E.b: 2.11.2 Transaction Retry mechanism

A PCrdReturn transaction must have the credit type set to the value of the credit type that is being returned

Check that the credit type field in a PCrdReturn transaction is set correctly.
Before the PCrdReturn flit, a PCrdGrant must have been received with the same PCrdType

A PCrdReturn flit is seen after the reception of a corresponding PCrdGrant with the same PCrdType value.

A PCrdReturn flit is seen without prior reception of a PCrdGrant with the same PCrdType value.

Passive RN and SN

ERROR

CHI Protocol Layer

associate flit to xact

associate_write_dat_flit_with_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID of the Write data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

Check that the Transaction ID, SourceID and TargetID fields are set correctly in Write Data flits.

The SrcID of the Write data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

A Write Data flit is received for one of the outstanding transactions whose data phase isn't yet complete (data_status is either INITIAL or PARTIAL_ACCEPT).

A Write Data flit is received but there are no outstanding transactions whose SrcID,TgtID and TxnID match the SrcID, TgtID and TxnID of the Write Data.

Passive RN and SN

ERROR

CHI Protocol Layer

associate flit to xact

valid_byte_enable_for_write_data_check

ARM-IHI0050E.b: 2.10.3 Byte Enables

For all Write transactions, byte enables that are not within the data window, specified by Addr and Size, must be deasserted.

Check that the Byte Enables are set correctly for Write Data

For all Write transactions, byte enables that are not within the data window, specified by Addr and Size, must be deasserted.
For DVMOp transactions, only the least significant 8 bits must be asserted.
For all Atomic transactions, byte enables that are not within the data window,specified by Addr and Size ,muts be deasserted.

SCENARIO 1:
For a full cacheline Write transaction, all Byte Enable bits are asserted.
SCENARIO 2:
For a partial cacheline Write, none of the Byte Enable bits outside of the data window are set.
SCENARIO 3:
When chi_spec_revision is ISSUE_B or greater, the cache state in the CopyBackWriteData is set to I and all BE bits are set to zero.
SCENARIO 4:
For a DVMOp, Byte Enable is set to 'hff.
SCENARIO 5:
For Atomic Transactions,all Byte enables are asserted within the data window,and byte enables outside the data window are set to zero.

SCENARIO 1:
For a full cacheline Write transaction, one or more Byte Enable bits are deasserted.
SCENARIO 2:
For a partial cacheline Write, any of the Byte Enable bits outside of the data window are set.
SCENARIO 3:
When chi_spec_revision is ISSUE_B or greater, the cache state in the CopyBackWriteData is set to I but one or more Byte Enable bits are asserted.
SCENARIO 4:
For a DVMOp, Byte Enable is not set to 'hff.
SCENARIO 5:
For Atomic Transactions,one or more Byte enables outside the data window are set to one.

Passive RN and SN

ERROR

CHI Protocol Layer

associate flit to xact

expected_num_write_data_flits_check

ARM-IHI0050E.b: 2.10.4 Data packetization

The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

Check that the number of Write Data flits is equal to the expected value
The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

A Write Data flit is received and there is an active xact with matching src_id, tgt_id and txn_id whose data_status is either INITIAL or PARTIAL_ACCEPT.

A Write Data flit is received and there is an active xact with matching src_id, tgt_id and txn_id whose data_status is ACCEPT.

Passive RN and SN

ERROR

CHI Protocol Layer

associate flit to xact

write_dat_xfer_after_dbid_check

ARM-IHI0050E.b: 2.3 Transaction structure

WriteData must only be sent by the Requester after either DBIDResp or CompDBIDResp is received.

Check that the Write Data flits are transmitted only after CompDBIDResp/DBIDResp.

A Write Data flit is received and there is an active xact with matching src_id, tgt_id and txn_id which has received a DBIDResp/CompDBIDResp

A Write Data flit is received and there is an active transaction with matching src_id, tgt_id and txn_id which hasn't yet received a DBIDResp/CompDBIDResp

Passive RN and SN

ERROR

CHI Protocol Layer

dat flit valid

writenosnp_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteNoSnp transaction.
The cache state in the associated Write data flits of a WriteNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.

Final cache state in the Write data flits of a WriteNoSnp transaction is set to I.

Final cache state in the Write data flits of a WriteNoSnp transaction is set to a value other than I.

Passive RN and SN

ERROR

CHI Protocol Layer

dat flit valid

valid_noncbwrdata_flit_for_xact_check

ARM-IHI0050E.b: 4.5.2 WriteData response

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

NONCOPYBACKWRDATA is valid only in case of WriteNoSnoop, WriteUnique and DVMOp type transactions

A NonCopyBackWrData flit is received for a WriteNoSnoop, WriteUnique or DVMOp type transaction.

A CopyBackWrData flit is received for a transaction type other than WriteNoSnoop, WriteUnique and DVMOp.

Passive RN and SN

ERROR

CHI Protocol Layer

request validity

single_outstanding_req_per_txn_id_check

ARM-IHI0050E.b: 2.5.2 Transaction ID

The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID

Check that there are no multiple outstanding transactions from the same source with the same transaction IDs.

The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID

SCENARIO 1:
A request is received at an RN, and there are no outstanding transactions with the same TxnID.
SCENARIO 2:
A request is received at an SN, and there are no outstanding non-DMT transactions with the same TxnID.

SCENARIO 1:
A request is received at an RN, but there already is an outstanding request with the same TxnID.
SCENARIO 2:
A request is received at an SN, but there already is an outstanding non-DMT request with the same TxnID.

Passive RN and SN

ERROR

CHI Protocol Layer

dat flit field

dat_flit_dbid_check

ARM-IHI0050E.b: Table A-9 Data message field mappings

DBID field of the observed DAT flit must be valid

Check that the DBID field value of the following DAT flits is as follows.
DAT flits:

SnpRespData, SnpRespDataPtl, NonCopyBackWrData, CopyBackWrData: In case of CHI-A nodes, DBID field must be zeroes or must be set to TxnID of originating request. For SnpRespData*, originating request is the Snoop request.
CompData: DBID field must be unique for a given non-DMT and non-DCT Read transaction with ExpCompAck asserted and can be reused only after the transaction completes.

SCENARIO 1:
For Write/Snoop transactions, the DBID of the observed Data flit is either zero or equal to the TxnID of the associated transaction.
SCENARIO 2:
For Read transactions with ExpCompAck asserted, the DBID of the observed Data flits is unique and there are no other Outstanding non-DMT and non-DCT transactions that have received read data with the same DBID value.

In case of Write/Snoop transactions, the DBID of the observed Data flit is neither zero or equal to the TxnID of the associated transaction.
In case of non-DMT and non-DCT Read transactions with ExpCompAck asserted, the DBID of the observed Data flits is not unique; there already is an outstanding non-DMT and non-DCT transaction that has received read data with the same DBID value.

RN and SN

ERROR

CHI Protocol Layer

dat flit field

tx_dat_flit_data_id_check

ARM-IHI0050E.b: 13.10.50 Data Identifier, DataID

data_id of the observed Tx DAT flit must be valid

Check the DataId field value of transmitted DAT flits from the monitored DUT.
This is determined based on data width of DAT VC along with data size of the corresponding transaction.
Note that this check, in case CCF Wrap Order is set to True at the sender, checks that the first data flit transmitted corresponds to the critical chunk indicated by CCID (,ie, the data_id of the first data flit matches the CCID value). For the subsequent flits, the check ensures that the data_id values are set correctly.
In case CCF Wrap Order is set to False at the sender, this check only verifies that the data_id takes one of the legal values prescribed in Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b)
Following are the Tx DAT flit types considered by this check.
. If the monitored DUT is RN:

CopyBackWrData
NonCopyBackWrData
SnpRespData
SnpRespDataPtl

If the monitored DUT is SN:

CompData

DataID value in the data flit transmitted by the active RN/SN agent is as per Table 11-29 (ARM-IHI0050A), Table 12-41 (ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).

DataID value in the data flit transmitted by the active RN/SN agent violates the legal values specified in Table 11-29 (ARM-IHI0050A), Table 12-41 (ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).

Passive RN and Passive SN

ERROR

CHI Protocol Layer

dat flit field

rx_dat_flit_data_id_check

ARM-IHI0050E.b: 13.10.50 Data Identifier, DataID

data_id of the observed Rx DAT flit must be valid

Check the DataId field value of received DAT flits by the monitored DUT.
This is determined based on data width of DAT VC along with data size of the corresponding transaction.
Note that this check, in case of in-order Interconnect, checks that the first data flit transmitted corresponds to the critical chunk indicated by CCID (,ie, the data_id of the first data flit matches the CCID value). For the subsequent flits, the check ensures that the data_id values are set correctly.
Incase of out-of-order interconnect, this check only verifies that the Data_ID takes one of the legal values prescribed in Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).
Following are the Rx DAT flit types considered by this check.
. If the monitored DUT is RN:

CompData

If the monitored DUT is SN:

NonCopyBackWrData

DataID value in the data flit received by the RN/SN agent is as per Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).

DataID value in the data flit received by the RN/SN agent violates the legal values specified in Table 11-29 (ARM-IHI0050A), Table 12-41 (ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).

RN and SN

ERROR

CHI Protocol Layer

dvm outstanding transactions

num_non_dvm_snoop_exceeded_configured_value_check

SYNOPSYS DEFINED

The number of outstanding non-dvm snoop should not exceed the configured value.

Check that the number of outstanding non-dvm snoop transactions have not reached the value configured in svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact.

The number of outstanding non-dvm snoop transactions are less than the value configured in svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact.

The number of outstanding non-dvm snoop transactions have reached the value configured in svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact.

Active RN-F/RN-D

This check is applicable only when svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact is set to value other than -1. This is synopsys defined check.

ERROR

CHI Protocol Layer

dvm outstanding transactions

num_dvm_snoop_exceeded_configured_value_check

SYNOPSYS DEFINED

The number of outstanding dvm snoop should not exceed the configured value.

Check that the number of outstanding dvm snoop transactions have not reached the value configured in svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact.

The number of outstanding dvm snoop transactions are less than the value configured in svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact.

The number of outstanding dvm snoop transactions have reached the value configured in svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact.

Active RN-F/RN-D

This check is applicable only when svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact is set to value other than -1. This is synopsys defined check.

ERROR

CHI Protocol Layer

retry xact

end_of_simulation_outstanding_protocol_credit_check

SYNOPSYS DEFINED

There shouldn't be any outstanding protocol credits at the end of simulation. Protocol credits must be utilized by retrying the original transaction or by PCRDRETURN

Check that there shouldn't be any outstanding protocol credits at the end of simulation. Protocol credits must be utilized by retrying the original transaction or returned via PCRDRETURN.

There are no outstanding protocol credits at the end of simulation.

There are outstanding protocol credits at the end of simulation.

RN and SN

This check is applicable only when svt_chi_node_configuration :: end_of_simulation_checks_enable is set to 1.

ERROR

CHI Protocol Layer

resp and dat flit valid

writenosnp_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated data packet's resp_err field should not take EXOK or NDERR value for WriteNoSnp transaction. The resp_err field in the associated response should not take EXOKAY for a non-Exclusive WriteNoSnp transaction

Check that the associated response and data packets has valid resp_err value for WriteNoSnp transaction.
The associated data packet's resp_err field should not take EXOK or NDERR value for WriteNoSnp transaction.

The RespErr field in the associated Write data flits of a WriteNoSnp transaction are as per Table 9-5 in the CHI Specification. The RespErr field in the associated response flits of a WriteNoSnp transaction are as per Table 9-4 in the CHI Specification.

The RespErr field in the associated Write data flits of a WriteNoSnp transaction are set to EXOK or NDERR. The RespErr field in the associated response flits of a WriteNoSnp transaction violate the legal values specified in Table 9-4 in the CHI Specification.

RN and SN

ERROR

CHI Link Layer

signal validity

valid_rxdatflit_signal_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit. Description : RXDATFLIT must not be X/Z when RXDATFLITV is asserted

RXDATFLIT must not be X/Z when RXDATFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

RXDATFLIT doest not take X/Z value when RXDATFLITV is asserted

one or more bit in RXDATFLIT is set to X/Z value when RXDATFLITV is asserted

RN and SN

Currently this check is performed on entire RXDATFLIT.

if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of RXDATFLIT.
if svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_B or later: RXDATFLIT bits corresponding to datacheck and poison fields are also applicable.

ERROR

CHI Link Layer

signal validity

valid_txdatflit_signal_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit. Description : TXDATFLIT must not be X/Z when TXDATFLITV is asserted

TXDATFLIT must not be X/Z when TXDATFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

TXDATFLIT doest not take X/Z value when TXDATFLITV is asserted

one or more bit in TXDATFLIT is set to X/Z value when TXDATFLITV is asserted

Passive RN and Passive SN

Currently this check is performed on entire TXDATFLIT.

if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of TXDATFLIT.
if svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_B or later: TXDATFLIT bits corresponding to datacheck and poison fields are also applicable.

ERROR

CHI Link Layer

signal validity

valid_reqflit_signal_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit. Description : REQFLIT must not be X/Z when REQFLITV is asserted

REQFLIT must not be X/Z when REQFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

REQFLIT doest not take X/Z value when REQFLITV is asserted

one or more bit in REQFLIT is set to X/Z value when REQFLITV is asserted

Passive RN and SN

Currently this check is performed on entire REQFLIT.

if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of REQFLIT.

ERROR

CHI Link Layer

During reset

signal_valid_txdatlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATLCRDV must be 0 during reset

TXDATLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXDATLCRDV is 0 during reset.

TXDATLCRDV is non zero during reset.

RN and SN

ERROR

CHI Link Layer

During reset

signal_valid_rxdatflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATFLITV must be 0 during reset

RXDATFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXDATFLITV is 0 during reset.

RXDATFLITV is non zero during reset.

RN and SN

ERROR

CHI Link Layer

During reset

signal_valid_txrsplcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPLCRDV must be 0 during reset

TXRSPLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXRSPLCRDV is 0 during reset.

TXRSPLCRDV is non zero during reset.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxreqlcrdv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request L-Credit Valid Description : RXREQLCRDV must not be X/Z

RXREQLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXREQLCRDV is not X/Z.

RXREQLCRDV is X/Z.

Passive SN

ERROR

CHI Link Layer

During reset

signal_valid_rxreqlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQLCRDV must be 0 during reset

RXREQLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXREQLCRDV is 0 during reset.

RXREQLCRDV is non zero during reset.

Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxsnpflitv_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop Flit Valid Description : RXSNPFLITV must not be X/Z

RXSNPFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXSNPFLITV is not X/Z.

RXSNPFLITV is X/Z.

ERROR

CHI Link Layer

signal validity

signal_valid_rxsnpflitpend_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop Flit Pending Description : RXSNPFLITPEND must not be X/Z

RXSNPFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXSNPFLITPEND is not X/Z.

RXSNPFLITPEND is X/Z.

ERROR

CHI Link Layer

signal validity

signal_valid_rxrspflitv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Valid Description : RXRSPFLITV must not be X/Z

RXRSPFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXRSPFLITV is not X/Z.

RXRSPFLITV is X/Z.

ERROR

CHI Link Layer

signal validity

signal_valid_rxrspflitpend_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Pending Description : RXRSPFLITPEND must not be X/Z

RXRSPFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXRSPFLITPEND is not X/Z.

RXRSPFLITPEND is X/Z.

ERROR

CHI Link Layer

signal validity

signal_valid_txreqlcrdv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request L-Credit Valid Description : TXREQLCRDV must not be X/Z

TXREQLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXREQLCRDV is not X/Z.

TXREQLCRDV is X/Z.

ERROR

CHI Link Layer

signal validity

valid_rxrspflit_signal_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit. Description : RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted

RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

RXRSPFLIT doest not take X/Z value when RXRSPFLITV is asserted

one or more bit in RXRSPFLIT is set to X/Z value when RXRSPFLITV is asserted

Currently this check is performed on entire RXRSPFLIT.

if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of RXRSPFLIT.

ERROR

CHI Link Layer

During reset

signal_valid_rxrspflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPFLITV must be 0 during reset

RXRSPFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXRSPFLITV is 0 during reset.

RXRSPFLITV is non zero during reset.

ERROR

CHI Link Layer

During reset

signal_valid_txreqlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQLCRDV must be 0 during reset

TXREQLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXREQLCRDV is 0 during reset.

TXREQLCRDV is non zero during reset.

ERROR

CHI Link Layer

signal validity

signal_valid_rxreqflitv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Valid Description : RXREQFLITV must not be X/Z

RXREQFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXREQFLITV is not X/Z.

RXREQFLITV is X/Z.

ERROR

CHI Link Layer

signal validity

signal_valid_rxreqflitpend_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Pending Description : RXREQFLITPEND must not be X/Z

RXREQFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXREQFLITPEND is not X/Z.

RXREQFLITPEND is X/Z.

ERROR

CHI Link Layer

During reset

signal_valid_rxreqflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQFLITV must be 0 during reset

RXREQFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXREQFLITV is 0 during reset.

RXREQFLITV is non zero during reset.

ERROR

CHI Link Layer

signal validity

signal_valid_rxrsplcrdv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response L-Credit Valid Description : RXRSPLCRDV must not be X/Z

RXRSPLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXRSPLCRDV is not X/Z.

RXRSPLCRDV is X/Z.

Passive RN

ERROR

CHI Link Layer

signal validity

signal_valid_txreqflitv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Valid Description : TXREQFLITV must not be X/Z

TXREQFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXREQFLITV is not X/Z.

TXREQFLITV is X/Z.

Passive RN

ERROR

CHI Link Layer

signal validity

signal_valid_rxsnplcrdv_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop L-Credit Valid Description : RXSNPLCRDV must not be X/Z

RXSNPLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXSNPLCRDV is not X/Z.

RXSNPLCRDV is X/Z.

Passive RN

ERROR

CHI Link Layer

signal validity

signal_valid_txreqflitpend_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Pending Description : TXREQFLITPEND must not be X/Z

TXREQFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXREQFLITPEND is not X/Z.

TXREQFLITPEND is X/Z.

Passive RN

ERROR

CHI Link Layer

During reset

signal_valid_rxrsplcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPLCRDV must be 0 during reset

RXRSPLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXRSPLCRDV is 0 during reset.

RXRSPLCRDV is non zero during reset.

Passive RN

ERROR

CHI Link Layer

During reset

signal_valid_txreqflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQFLITV must be 0 during reset

TXREQFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXREQFLITV is 0 during reset.

TXREQFLITV is non zero during reset.

Passive RN

ERROR

CHI Link Layer

During reset

signal_valid_rxlinkactivereq_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEREQ must be 0 during reset

RXLINKACTIVEREQ must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXLINKACTIVEREQ is 0 during reset.

RXLINKACTIVEREQ is non zero during reset.

RN and SN

ERROR

CHI Link Layer

During reset

signal_valid_txlinkactiveack_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEACK must be 0 during reset

TXLINKACTIVEACK must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXLINKACTIVEACK is 0 during reset.

TXLINKACTIVEACK is non zero during reset.

RN and SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxlinkactivereq_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEREQ must not be X/Z

RXLINKACTIVEREQ must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXLINKACTIVEREQ is not X/Z.

RXLINKACTIVEREQ is X/Z.

RN and SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxdatflitv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Valid Description : RXDATFLITV must not be X/Z

RXDATFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXDATFLITV is not X/Z.

RXDATFLITV is X/Z.

RN and SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxdatflitpend_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Pending Description : RXDATFLITPEND must not be X/Z

RXDATFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXDATFLITPEND is not X/Z.

RXDATFLITPEND is X/Z.

RN and SN

ERROR

CHI Link Layer

signal validity

signal_valid_txrsplcrdv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response L-Credit Valid Description : TXRSPLCRDV must not be X/Z

TXRSPLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXRSPLCRDV is not X/Z.

TXRSPLCRDV is X/Z.

RN and SN

ERROR

CHI Link Layer

signal validity

signal_valid_txdatlcrdv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data L-Credit Valid Description : TXDATLCRDV must not be X/Z

TXDATLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXDATLCRDV is not X/Z.

TXDATLCRDV is X/Z.

RN and SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxsactive_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : RXSACTIVE signal Description : RXSACTIVE must not be X/Z

RXSACTIVE must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXSACTIVE is not X/Z.

RXSACTIVE is X/Z.

RN and SN

ERROR

CHI Link Layer

signal validity

signal_valid_txlinkactiveack_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEACK must not be X/Z

TXLINKACTIVEACK must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXLINKACTIVEACK is not X/Z.

TXLINKACTIVEACK is X/Z.

RN and SN

ERROR

CHI Link Layer

signal validity

valid_txrspflit_signal_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit. Description : TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted

TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

TXRSPFLIT doest not take X/Z value when TXRSPFLITV is asserted

one or more bit in TXRSPFLIT is set to X/Z value when TXRSPFLITV is asserted

Passive RN and Passive SN

Currently this check is performed on entire TXRSPFLIT.

if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of TXRSPFLIT.

ERROR

CHI Link Layer

During reset

signal_valid_rxdatlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATLCRDV must be 0 during reset

RXDATLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXDATLCRDV is 0 during reset.

RXDATLCRDV is non zero during reset.

Passive RN and Passive SN

ERROR

CHI Link Layer

During reset

signal_valid_txdatflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATFLITV must be 0 during reset

TXDATFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXDATFLITV is 0 during reset.

TXDATFLITV is non zero during reset.

Passive RN and Passive SN

ERROR

CHI Link Layer

During reset

signal_valid_txrspflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPFLITV must be 0 during reset

TXRSPFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXRSPFLITV is 0 during reset.

TXRSPFLITV is non zero during reset.

Passive RN and Passive SN

ERROR

CHI Link Layer

During reset

signal_valid_rxlinkactiveack_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEACK must be 0 during reset

RXLINKACTIVEACK must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXLINKACTIVEACK is 0 during reset.

RXLINKACTIVEACK is non zero during reset.

Passive RN and Passive SN

ERROR

CHI Link Layer

During reset

signal_valid_txlinkactivereq_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEREQ must be 0 during reset

TXLINKACTIVEREQ must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

TXLINKACTIVEREQ is 0 during reset.

TXLINKACTIVEREQ is non zero during reset.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxdatlcrdv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data L-Credit Valid Description : RXDATLCRDV must not be X/Z

RXDATLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXDATLCRDV is not X/Z.

RXDATLCRDV is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_txrspflitv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Valid Description : TXRSPFLITV must not be X/Z

TXRSPFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXRSPFLITV is not X/Z.

TXRSPFLITV is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_txrspflitpend_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Pending Description : TXRSPFLITPEND must not be X/Z

TXRSPFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXRSPFLITPEND is not X/Z.

TXRSPFLITPEND is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_txdatflitv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Valid Description : TXDATFLITV must not be X/Z

TXDATFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXDATFLITV is not X/Z.

TXDATFLITV is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_txdatflitpend_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Pending Description : TXDATFLITPEND must not be X/Z

TXDATFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXDATFLITPEND is not X/Z.

TXDATFLITPEND is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_rxlinkactiveack_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEACK must not be X/Z

RXLINKACTIVEACK must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

RXLINKACTIVEACK is not X/Z.

RXLINKACTIVEACK is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_txsactive_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : TXSACTIVE signal Description : TXSACTIVE must not be X/Z

TXSACTIVE must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXSACTIVE is not X/Z.

TXSACTIVE is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

signal validity

signal_valid_txlinkactivereq_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEREQ must not be X/Z

TXLINKACTIVEREQ must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

TXLINKACTIVEREQ is not X/Z.

TXLINKACTIVEREQ is X/Z.

Passive RN and Passive SN

ERROR

CHI Link Layer

l-credit

valid_lcredit_range_check

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : The minimum number of L-Credits that a Receiver can provide is one.The maximum number of L-Credits that a Receiver can provide is 15 Description : The l-credit must be within the valid range

The minimum number of L-Credits that a receiver can provide is one. The maximum number of L-Credits that a receiver can provide is defined as follows based on vc_id
- RXREQ: svt_chi_node_configuration :: rx_req_vc_flit_buffer_size
- RXDAT: svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size
- RXRSP: svt_chi_node_configuration :: rx_rsp_vc_flit_buffer_size
- RXSNP: svt_chi_node_configuration :: rx_snp_vc_flit_buffer_size

L-credit value falls within the valid range as described above

L-credit value falls outside the valid range as described above

Passive RN and Passive SN

ERROR

CHI Link Layer

link deactivation

tx_link_deactive_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner Description : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner

Link deactivation must complete in a timely manner in response to a received request.

Link goes to deactivate state in response to deactivation well within the value specified in svt_chi_node_configuration :: tx_link_deactivation_timeout.

If the number of cycles exceeds the value specified in svt_chi_node_configuration :: tx_link_deactivation_timeout,the check errors out.

Passive RN and Passive SN

This check uses the value of svt_chi_node_configuration :: tx_link_deactivation_timeout.

ERROR

CHI Link Layer

link activation

tx_link_active_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner Description : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner

Link activation must complete in a timely manner in response to a received request.

Link goes to activate state in response to activation well within the value specified in svt_chi_node_configuration :: tx_link_activation_timeout.

If the number of cycles exceeds the value specified in svt_chi_node_configuration :: tx_link_activation_timeout,the check errors out.

Passive RN and Passive SN

This check uses the value of svt_chi_node_configuration :: tx_link_activation_timeout.

ERROR

CHI Link Layer

link activation

tx_link_not_active_during_flit_transfer

ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake

Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be sent on its virtual channel only if the link is active.

Flits must not be transmitted while the link is not active

Flits transmitted while the link is active.

Flits transmitted while the link is not active.

Passive RN and Passive SN

ERROR

CHI Link Layer

link deactivation

rx_link_deactive_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If a component moves the TXLINK to the DEACTIVATE state, which it controls, it can expect the RXLINK to also move to the DEACTIVATE state, in a timely manner Description : If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner

Link deactivation must complete in a timely manner in response to a received request. If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner.

Link goes to deactivate state in response to deactivation well within the value specified in svt_chi_node_configuration :: rx_link_deactivation_timeout

If the number of cycles exceeds the value specified in svt_chi_node_configuration :: rx_link_deactivation_timeout,the check errors out.

RN and SN

This check uses the value of svt_chi_node_configuration :: rx_link_deactivation_timeout. By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: rx_link_deactivation_timeout to a value greater than or equal to 0 for this check to be performed.

ERROR

CHI Link Layer

link activation

rx_link_active_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If a component moves the TXLINK to the ACTIVATE state, which it controls, it can expect the RXLINK to also move to the ACTIVATE state, in a timely manner Description : If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner

Link activation must complete in a timely manner in response to a received request. If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner.

Link goes to activate state in response to activation well within the value specified in svt_chi_node_configuration :: rx_link_activation_timeout.

If the number of cycles exceeds the value specified in svt_chi_node_configuration :: rx_link_activation_timeout,the check errors out.

RN and SN

This check uses the value of svt_chi_node_configuration :: rx_link_activation_timeout. By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: rx_link_activation_timeout to a value greater than or equal to 0 for this check to be performed.

ERROR

CHI Link Layer

link activation

rx_link_not_active_during_flit_reception

ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake

Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be observed on its RX virtual channel only if the corresponding link is active.

Flits must be observed only when the link is active

Flits observed while the link is active.

Flits observed while the link is not active.

RN and SN

ERROR

CHI Link Layer

dat flit valid

invalid_data_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : DAT channel opcodes encoding Description : Check for Reserved opcode bits for Data VC commands

Reserved (opcodes) Data VC commands cannot be used.

Data flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-14, ARM-IHI0050B: 12.9.15 Table 12-18, ARM-IHI0050E.b: 13.10.17 Table 13-16.

Data flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-14, ARM-IHI0050B: 12.9.15 Table 12-18, ARM-IHI0050E.b: 13.10.17 Table 13-16.

RN and Passive SN

ERROR

CHI Link Layer

dat flit valid

data_flit_lcrdreturn_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : DatLCrdReturn Description : Check fields for a DataLCrdReturn flit

Data VC message fields must be set to valid values for a DataLCrdReturn transaction

if ( dat_vc_flit_opcode == DATLCREDIT) and all the fields take legal values

if ( dat_vc_flit_opcode == DATLCREDIT) and one or more of the fields take an unexpected value

RN and SN

At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value.
At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_lcrdreturn_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : RspLCrdReturn Description : Check fields for a RspLCrdReturn flit

Response VC message fields must be set to valid values for a RspLCrdReturn transaction

if ( rsp_vc_flit_opcode == RSPLCREDIT) and all the fields take legal values

if ( rsp_vc_flit_opcode == RSPLCREDIT) and one or more of the fields take an unexpected value

RN and SN

ERROR

CHI Link Layer

req flit valid

req_flit_lcrdreturn_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReqLCrdReturn Description : Check fields for a ReqLCrdReturn flit

Request VC message fields must be set to valid values for a ReqLCrdReturn transaction

if ( req_vc_flit_opcode == REQLCREDIT) and all the fields take legal values

if ( req_vc_flit_opcode == REQLCREDIT) and one or more of the fields take an unexpected value

RN and SN

ERROR

CHI Link Layer

rsp flit valid

invalid_rsp_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : RSP channel opcodes encoding Description : Check for Reserved opcode bits for Response VC commands

Reserved (opcodes) Response VC commands cannot be used.

Response flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-12, ARM-IHI0050B: 12.9.15 Table 12-16, ARM-IHI0050E.b 13.10.17 Table 13-14.

Response flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-12, ARM-IHI0050B: 12.9.15 Table 12-16, ARM-IHI0050E.b 13.10.17 Table 13-14.

RN and Passive SN

ERROR

CHI Link Layer

dat flit valid

data_flit_compdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : CompData Description : Check fields for data VC flit of a CompData transaction

Data VC message fields must be set to valid values for a CompData transaction.

if ( dat_vc_flit_opcode == COMPDATA), the communicating node pairs are allowed as per the spec and all the fields take legal values

if ( dat_vc_flit_opcode == COMPDATA) and one or more of the fields take an unexpected value or the communicating pairs are in violation with the spec

RN and Passive SN

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_pcrdgrant_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : PCrdGrant Description : Check fields for response VC flit of a PCrdGrant transaction

Response VC message fields must be set to valid values for a PCrdGrant transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

RN and Passive SN

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_dbidresp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : DBIDResp Description : Check fields for response VC flit of a DBIDResp transaction

Response VC message fields must be set to valid values for a DBIDResp transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

RN and Passive SN

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_compdbidresp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : CompDBIDResp Description : Check fields for response VC flit of a CompDBIDResp transaction

Response VC message fields must be set to valid values for a CompDBIDResp transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

RN and Passive SN

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_comp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : Comp Description : Check fields for response VC flit of a Comp transaction

Response VC message fields must be set to valid values for a Comp transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

RN and Passive SN

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_retryack_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : RetryAck Description : Check fields for response VC flit of a RetryAck transaction

Response VC message fields must be set to valid values for a RetryAck transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

RN and Passive SN

ERROR

CHI Link Layer

req flit valid

valid_xact_attributes_combination_check

ARM-IHI0050E.b:2.9.4 Transaction attribute combinations

Spec Text : Legal combinations of MemAttr, SnpAttr, and Order field values Description : check combinations of MemAttr, SnpAttr, LikelyShared and Order for a transaction

Transaction attributes in the Request VC message must take valid combinations.

Valid combination of MemAttr, SnpAttr, LikelyShared and order field for a transaction.

Invalid combination of MemAttr, SnpAttr, LikelyShared and order field for a transaction.

Passive RN and SN

ERROR

CHI Link Layer

req flit valid

invalid_req_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : REQ channel opcodes Description : Check for Reserved opcode bits for Request VC commands

Reserved (opcodes) Request VC commands cannot be used.

Request flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-11, ARM-IHI0050B: 12.9.15 Table 12-14, ARM-IHI0050E.b: 13.10.17 Table 13-12.

Request flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-11, ARM-IHI0050B: 12.9.15 Table 12-14, ARM-IHI0050E.b: 13.10.17 Table 13-12.

Passive RN and SN

ERROR

CHI Link Layer

dat flit valid

data_flit_noncopybackwrdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : NonCopyBackWrData Description : Check fields for data VC flit of a NonCopyBackWrData transaction

Data VC message fields must be set to valid values for a NonCopyBackWrData transaction.

All the fields in the data flit are as per Data message field mappings of the CHI Specification

One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification

Passive RN and SN

ERROR

CHI Link Layer

req flit valid

req_flit_readnosnp_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadNoSnp Description : Check fields for request VC flit of a ReadNoSnp transaction

Request VC message fields must be set to valid values for a ReadNoSnp transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN and SN

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpFull Description : Check fields for request VC flit of a WriteNoSnpFull transaction

Request VC message fields must be set to valid values for a WriteNoSnpFull transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN and SN

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpptl_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpPtl Description : Check fields for request VC flit of a WriteNoSnpPtl transaction

Request VC message fields must be set to valid values for a WriteNoSnpPtl transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN and SN

ERROR

CHI Link Layer

req flit valid

req_flit_pcrdreturn_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : PCrdReturn Description : Check fields for request VC flit of a PCrdReturn transaction

Request VC message fields must be set to valid values for a PCrdReturn transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN and SN

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_compack_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : CompAck Description : Check fields for response VC flit of a CompAck transaction

Response VC message fields must be set to valid values for a CompAck transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

Passive RN

ERROR

CHI Link Layer

req flit valid

req_flit_readonce_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadOnce Description : Check fields for request VC flit of a ReadOnce transaction

Request VC message fields must be set to valid values for a ReadOnce transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniquefull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniqueFull Description : Check fields for request VC flit of a WriteUniqueFull transaction

Request VC message fields must be set to valid values for a WriteUniqueFull transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniqueptl_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniquePtl Description : Check fields for request VC flit of a WriteUniquePtl transaction

Request VC message fields must be set to valid values for a WriteUniquePtl transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN

ERROR

CHI Link Layer

req flit valid

req_flit_makeinvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : MakeInvalid Description : Check fields for request VC flit of a MakeInvalid transaction

Request VC message fields must be set to valid values for a MakeInvalid value for transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN, SN

ERROR

CHI Link Layer

req flit valid

req_flit_cleaninvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanInvalid Description : Check fields for request VC flit of a CleanInvalid transaction

Request VC message fields must be set to valid values for a CleanInvalid value for transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN, SN

ERROR

CHI Link Layer

req flit valid

req_flit_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanShared Description : Check fields for request VC flit of a CleanShared transaction

Request VC message fields must be set to valid values for a CleanShared transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN, SN

ERROR

CHI Link Layer

snp flit valid

invalid_snp_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : SNP channel opcodes encoding Description : Check for Reserved opcode bits for Snoop VC commands

Reserved (opcodes) Snoop VC commands cannot be used.

Snoop flit opcode is set to one of the valid values as defined in ARM-IHI0050A: 11.9.5 Table 11-13, ARM-IHI0050B: 12.9.15 Table 12-17, ARM-IHI0050B: 13.10.17 Table 13-15, ARM-IHI0050B: 13.10.17 Table 13-15.

Snoop flit uses the reserved opcode values as defined in ARM-IHI0050A: 11.9.5 Table 11-13, ARM-IHI0050B: 12.9.15 Table 12-17, ARM-IHI0050B: 13.10.17 Table 13-15, ARM-IHI0050B: 13.10.17 Table 13-15.

RN-F and RN-D

ERROR

CHI Link Layer

snp flit valid

snoop_flit_lcrdreturn_check

ARM-IHI0050E.b:A.4 Snoop Request message field mappings

Spec Text : SnpLCrdReturn Description : Check fields for a SnpLCrdReturn flit

Data VC message fields must be set to valid values for a SnoopLCrdReturn transaction

if ( snp_vc_flit_opcode == SNPLCREDIT) and all the fields take legal values

if ( snp_vc_flit_opcode == SNPLCREDIT) and one or more of the fields take an unexpected value

RN-F and RN-D

ERROR

CHI Link Layer

signal validity

valid_snpflit_signal_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop Flit. Description : SNPFLIT must not be X/Z when SNPFLITV is asserted

SNPFLIT must not be X/Z when SNPFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

SNPFLIT doest not take X/Z value when SNPFLITV is asserted

one or more bit in SNPFLIT is set to X/Z value when SNPFLITV is asserted

RN-F and RN-D

Currently this check is performed on entire SNPFLIT.

if svt_chi_node_configuration :: bypass_checking_of_x_z_on_dont_care_fields is set to 1, this check will not be performed on the dont care fields of SNPFLIT.

ERROR

CHI Link Layer

During reset

signal_valid_rxsnpflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPFLITV must be 0 during reset

RXSNPFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXSNPFLITV is 0 during reset.

RXSNPFLITV is non zero during reset.

RN-F and RN-D

ERROR

CHI Link Layer

snp flit valid

snoop_flit_snpdvmop_check

ARM-IHI0050E.b:A.4 Snoop Request message field mappings

Spec Text : SnpDVMOp Description : Check fields for snoop VC flit of a SnpDVMOp transaction

Snoop VC message fields must be set to valid values for a SnpDVMOp transaction.

All the fields in the snoop flit are as per Snoop request message field mappings of the CHI Specification

One or more fields in the snoop flit violate the legal values specified in Snoop request message field mappings of the CHI Specification

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1)..

ERROR

CHI Link Layer

During reset

signal_valid_rxsnplcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPLCRDV must be 0 during reset

RXSNPLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

RXSNPLCRDV is 0 during reset.

RXSNPLCRDV is non zero during reset.

Passive RN-F and Passive RN-D

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_snpresp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : SnpResp Description : Check fields for response VC flit of a SnpRsp transaction

Response VC message fields must be set to valid values for a SnpRsp transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

Passive RN-F and Passive RN-D

ERROR

CHI Link Layer

req flit valid

req_flit_dvmop_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : DVMOp Description : Check fields for request VC flit of a DVMOp transaction

Request VC message fields must be set to valid values for a DVMOp transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F and Passive RN-D

This check is constructed only when DVM support is enabled in the passive RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).. At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value.
At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_readreceipt_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : ReadReceipt Description : Check fields for response VC flit of a ReadReceipt transaction

Response VC message fields must be set to valid values for a ReadReceipt transaction.

All the fields in the response flit are as per Response message field mappings of the CHI Specification

One or more fields in the response flit violate the legal values specified in Response message field mappings of the CHI Specification

RN and Passive SN-I

ERROR

CHI Link Layer

req flit valid

req_flit_ecbarrier_check

ARM-IHI0050A:A.1 Request message field mappings

Check fields for request VC flit of a ECBarrier transaction

Request VC message fields must be set to valid values for a ECBarrier transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN and SN-I

This check is constructed only when svt_chi_node_configuration :: chi_spec_revision is set to svt_chi_node_configuration :: ISSUE_A. At RN, one of the fields that this check looks at is the SrcID in the request flit wherein it expects the SrcID in the request matches the Node ID configured for the RN. If the SrcID in the request is expected or permitted to take values other than the Node ID of the RN, the configuration svt_chi_node_configuration :: random_src_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the SrcID field as it could take any value.
At SN, one of the fields that this check looks at is the TgtID in the request flit wherein it expectes the TgtID field to match withe Node ID of the SN. If the TgtID in the request is expected to take values other than the Node ID of the SN, the configuration svt_chi_node_configuration :: random_tgt_id_enable must be set to 1. When this configuration is set to 1 ,no checks will be perfomed on the TgtID field as it could take any value.

ERROR

CHI Link Layer

req flit valid

req_flit_eobarrier_check

ARM-IHI0050A:A.1 Request message field mappings

Check fields for request VC flit of a EOBarrier transaction

Request VC message fields must be set to valid values for a EOBarrier transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN and SN-I

ERROR

CHI Link Layer

snp flit valid

snoop_flit_snpreq_check

ARM-IHI0050E.b:A.4 Snoop Request message field mappings

Spec Text : Snoop Request message Description : Check fields for snoop VC flit of a Snoop transaction

Snoop VC message fields must be set to valid values for a Snoop transaction (non-DVMOp).

if a non-DVM Snoop request is received and the communicating node pairs are allowed as per the spec and also all the fields take legal values

if a non-DVM Snoop request is received, and, either the communicating node pairs are not permitted by the spec or any of the fields take an invalid value

RN-F

ERROR

CHI Link Layer

dat flit valid

data_flit_snprespdataptl_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : SnpRespDataPtl Description : Check fields for data VC flit of a SnpRespDataPtl transaction

Data VC message fields must be set to valid values for a SnpRespDataPtl transaction.

All the fields in the data flit are as per Data message field mappings of the CHI Specification

One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

dat flit valid

data_flit_copybackwrdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : CopyBackWrData Description : Check fields for data VC flit of a CopyBackWrData transaction

Data VC message fields must be set to valid values for a CopyBackWrData transaction.

All the fields in the data flit are as per Data message field mappings of the CHI Specification

One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

dat flit valid

data_flit_snprespdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : SnpRespData Description : Check fields for data VC flit of a SnpRespData transaction

Data VC message fields must be set to valid values for a SnpRespData transaction.

All the fields in the data flit are as per Data message field mappings of the CHI Specification

One or more fields in the data flit violate the legal values specified in Data message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_evict_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : Evict Description : Check fields for request VC flit of a Evict transaction

Request VC message fields must be set to valid values for a Evict transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_writecleanptl_check

ARM-IHI0050A:A.1 Request message field mappings

Check fields for request VC flit of a WriteCleanPtl transaction

Request VC message fields must be set to valid values for a WriteCleanPtl transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_writebackptl_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteBackPtl Description : Check fields for request VC flit of a WriteBackPtl transaction

Request VC message fields must be set to valid values for a WriteBackPtl transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_writeevictfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteEvictFull Description : Check fields for request VC flit of a WriteEvictFull transaction

Request VC message fields must be set to valid values for a WriteEvictFull transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_writecleanfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteCleanFull Description : Check fields for request VC flit of a WriteCleanFull transaction

Request VC message fields must be set to valid values for a WriteCleanFull transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_writebackfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteBackFull Description : Check fields for request VC flit of a WriteBackFull transaction

Request VC message fields must be set to valid values for a WriteBackFull transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_makeunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : MakeUnique Description : Check fields for request VC flit of a MakeUnique transaction

Request VC message fields must be set to valid values for a MakeUnique transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_cleanunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanUnique Description : Check fields for request VC flit of a CleanUnique transaction

Request VC message fields must be set to valid values for a CleanUnique transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_readunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadUnique Description : Check fields for request VC flit of a ReadUnique transaction

Request VC message fields must be set to valid values for a ReadUnique transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_readclean_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadClean Description : Check fields for request VC flit of a ReadClean transaction

Request VC message fields must be set to valid values for a ReadClean transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

req flit valid

req_flit_readshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadShared Description : check fields for request VC flit of a ReadShared transaction

Request VC message fields must be set to valid values for a ReadShared transaction.

All the fields in the request flit are as per Request message field mappings of the CHI Specification

One or more fields in the request flit violate the legal values specified in Request message field mappings of the CHI Specification

Passive RN-F

ERROR

CHI Link Layer

l-credit

valid_num_prot_flits_in_txlasm_deactivate_state_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : The Transmitter must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit Description : The Transmitter in Deactivate state is allowed to transmit protocol flits For each additional credit received it must send an L-Credit return flit to return the credit.

The maximum number of protocol flits that a transmitter (per channel) can send in Deactivate state is the number of l-credits available at the time of entry into Deactivate state.
In other words, The Transmitter in Deactivate state must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit.

The number of protocol flits observed during transmitter deactivate state is less than or equal to the maximum allowed value, as mentioned in the description.

The number of protocol flits observed during transmitter deactivate state is greater than the maximum allowed value.

Passive RN

Applicable only when svt_chi_node_configuration :: allow_protocol_flits_transmission_in_tx_lasm_deactivate_state configuration is set to 1

ERROR

CHI Link Layer

l-credit

valid_lcredit_count_in_rx_stop_state_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : Before entering a low power state, the sending of payload flits must be stopped and all credits must be returned to the Receiver Description : The reciever must ensure that it has received all the lcredits before moving to the stop state

The reciever must ensure that it has received all the lcredits before moving to the stop state i.e before deasserting the RXLINKACTIVEACK signal. Applicable channels:

RN_I: RXRSP VC and RXDAT VC
RN_F/RN_D: RXSNP VC, RXRSP VC and RXDAT VC
SN: RXREQ VC and RXDAT VC

All the lcredits are reveiced before moving to the stop state.

All the lcredits are not reveiced before moving to the stop state.

Passive RN and SN

ERROR

CHI Link Layer

l-credit

rx_no_lcredit_issued_for_flit_type

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : When the link is active, the Receiver must provide L-Credits in a timely manner without requiring any action on the part of the Transmitter Description : When the link is active, the receiver at each virtual channel must distribute L-credits for all its flit buffers in a timely manner without requiring any action on the part of the transmitter.

Checks if credits are sent, in a timely manner, by the corresponding active node.
While the number of available L-Credits is less than the configured number of L-Credits (rx_\*_vc_flit_buffer_size in svt_chi_node_configuration), an L-Credit should be returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.

while the number of available L-Credits is less than the configured number of L-Credits (rx_*_vc_flit_buffer_size in svt_chi_node_configuration), an L-Credit is returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.

while the number of available L-Credits is less than the configured number of L-Credits (rx_*_vc_flit_buffer_size in svt_chi_node_configuration), no L-Credits are returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.

Passive RN and Passive SN

ERROR

CHI Link Layer

port interleaving

port_interleaving_check

SYNOPSYS DEFINED:SYNOPSYS DEFINED

Monitor checks that if interleaved port is expected port for the given flit

Checks if address does fall to correct interleaved port.
Valid when node cfg svt_chi_node_configuration :: port_interleaving_enable = 1.
Applicable for snoop transactions in case of active and passive RN.
Applicable for RN transactions in case of passive RN.

address does fall to correct interleaved port.

address does not fall to correct interleaved port.

ERROR

CHI Link Layer

signal validity

valid_flitpend_and_flitv_signal_check

ARM-IHI0050E.b:14.4 Flit level clock gating

Spec Text : It is required that the signal is asserted exactly one cycle before a flit is sent from the Transmitter Description : FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter

FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter

FLITPEND is asserted exactly one clock cycle before FLTIV is asserted.

FLITPEND is not asserted exactly one clock cycle before FLTIV is asserted.

RN and SN

ERROR

CHI Link Layer

link active sm

lasm_entry_into_banned_output_race_state_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : The red states can only be reached by observing a race between two output signals. A race between two outputs is not permitted at the edge of a component and therefore the transition into these states is labeled with Banned Output Race Description : The component's Link Active State Machine entry into Banned Output Race state condition is not expected.

lasm is acronym for "Link Active State Machine".
A given component's Link Active State Machine entry into Banned Output Race states can happen when there is a race condition at the output signals of the local component.
A given component's Link Active State Machine entry into Banned Output Race states results in the connected link partner component being entering Async Input Race States.
When a component’s Link Active State Machine entry into Banned Output Race state is observed this check will fail, if not the check will pass.
This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected is set to 0.

When the component Link Active State Machine doesn't enter into Banned Output Race State.

When the component Link Active State Machine entry into Banned Output Race State is observed. The check will fail for below Link Active State Machine transitions:

TX_STOP RX_ACTIVATE to TX_STOP RX_RUN+
TX_RUN RX_ACTIVATE to TX_DEACTIVATE+ RX_ACTIVATE
TX_RUN RX_DEACTIVATE to TX_RUN RX_STOP+
TX_STOP RX_DEACTIVATE to TX_ACTIVATE+ RX_DEACTIVATE

Passive RN and Passive SN

This check will be constructed and executed only when the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected is set to 0.
Use case:

For a given component, the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected can be set to 0 (which inturn enables this check) for below cases:
- An error needs to be thrown when the component's Link Active State Machine to enter into Banned Output Race State
- An error needs to be thrown when the connected link partner component's Link Active State Machine to enter into Async Input Race State

ERROR

CHI Link Layer

link active sm

illegal_tx_rx_state_transition_combinations_from_async_input_race_state

ARM-IHI0050E.b:14.6.3 Expected transitions

Combination of Tx and Rx link active state machine together from async input race combination must be valid

Check to monitor the illegal Tx and Rx link active state combinations from the async input race states for a given node
Legal Tx and Rx link active state combinations from the async input race states are:
- TXRUN+/RXSTOP to TXRUN/RXACT
- TXACT/RXDEACT+ to TXRUN/RXDEACT
- TXSTOP+/RXRUN to TXSTOP/RXDEACT
- TXDEACT/RXACT+ to TXSTOP/RXDEACT

Link Active State Machine from an async input race state moves to a valid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.

Link Active State Machine from an async input race state moves to a invalid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.

RN and SN

This check will be constructed and executed only when the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 1.

ERROR

CHI Link Layer

link active sm

lasm_entry_into_async_input_race_state_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : The yellow states can only be reached by observing a race between two input signals. The transition into these states is labeled with Async Input Race Description : The component's Link Active State Machine entry into Async Input Race state condition is not expected.

lasm is acronym for "Link Active State Machine".
A given component Link Active State Machine entry into Async Input Race States can only be reached by observing a race between the two input signals.
In other words, entry into Async Input Race states for a given component can happen only when the connected link partner component observes a Banned Output Signal race condition.
A given component Link Active State Machine entry into Async Input Race state implies that the connected link partner copmonent has entered Banned Output Race state.
When a component’s Link Active State Machine entry into Async Input Race state is observed this check will fail, if not the check will pass.
This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 0.

When the component Link Active State Machine doesn't enter into Async Input Race State.

When the component Link Active State Machine entry into Async Input Race State is observed. The check will fail for below Link Active State Machine transitions:

TX_ACTIVATE RX_STOP to TX_RUN+ RX_STOP
TX_ACTIVATE RX_RUN to TX_ACTIVATE RX_DEACTIVATE+
TX_DEACTIVATE RX_RUN to TX_STOP+ RX_RUN
TX_DEACTIVATE RX_STOP to TX_DEACTIVATE RX_ACTIVATE+

RN and SN

This check will be constructed and executed only when the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 0.
Use case:

For a given component, the node configuration parameter svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected can be set to 0 (which inturn enables this check) for below cases:
- An error needs to be thrown when the component's Link Active State Machine to enter into Async Input Race State
- An error needs to be thrown when the connected link partner component's Link Active State Machine to enter into Banned Output Race State

ERROR

CHI Link Layer

link active sm

lasm_in_banned_output_race_state_timeout_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Banned Output Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by local component.

lasm is acronym for "Link Active State Machine".
A given components Link Active State Machine entry into Banned Output Race states can happen when there is Async Input Signal race condition at the connected link partner component.
The component observing Link Active States corresponding to Banned Output race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component.
When a component’s state machine stays in Banned Output Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued.
This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.

When the component observing Link active State Machine in Banned Output race states moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.

When the component observing Link active State Machine in Banned Output race states not moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.

By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout to a value greater than or equal to 1 for this check to be performed.
This check uses the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, which must be programmed taking into consideration all other link active state machine delays. The Link Active State Machine delays that user needs to pay attention to are delay controls(to move to next valid state) in Banned Output Race states:

ERROR

CHI Link Layer

link active sm

lasm_in_async_input_race_state_timeout_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Async Input Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by link partner component.

lasm is acronym for "Link Active State Machine".
A given components Link Active State Machine entry into Async Input Race states can happen when there is a Banned Output Signal race condition at the connected link partner component.
The component observing Link Active States corresponding to Async Input race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component.
When a component’s state machine stays in Async Input Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued.
This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.

When the component observing Link active State Machine in Async Input race states moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.

When the component observing Link active State Machine in Async Input race states not moved to next valid state within the value specified in svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout.

By default this check is not executed, must program the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout to a value greater than or equal to 1 for this check to be performed.
This check uses the node configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, which must be programmed taking into consideration all other link active state machine delays. As the component's Link active State Machine movement from Async Input race state to next valid state depends on the link partner component's movement from Banned Output Race states to next valid state, the link partner component delays to move from Banned Output Race states to next valid state should be programmed appropriately.

ERROR

CHI Link Layer

link active sm

illegal_tx_rx_state_transition_combinations_from_banned_output_race_state

ARM-IHI0050E.b:14.6.3 Expected transitions

Combination of Tx and Rx link active state machine together from banned output race combination must be valid

Check to monitor the illegal Tx and Rx link active state combinations from the banned output race states for a given node
Legal Tx and Rx link active state combinations from the banned output race states are:
- TXSTOP/RXRUN to TXACT/RXRUN
- TXRUN/RXSTOP to TXDEACT/RXSTOP
- TXDEACT/RXACT to TXDEACT/RXRUN
- TXACT/RXDEACT to TXACT/RXSTOP

Valid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.

Invalid combination for Tx and Rx state machine, The combination of Tx and Rx state at a given point is not as per ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.

RN and SN

ERROR

CHI Link Layer

link active sm

illegal_tx_rx_state_transition_combinations

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : Stop/Stop to Run/Run state paths Description : Combination of Tx and Rx link active state machine together must be valid

Check to monitor the following illegal Tx and Rx link active state combinations for a given node:
- TXSTOP/RXRUN
- TXRUN/RXSTOP
- TXDEACT/RXACT
- TXACT/RXDEACT

Valid combination for Tx and Rx state machine as defined in ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.

Invalid combination for Tx and Rx state machine, The combination of Tx and Rx state at a given point is not as per ARM-IHI0050A: 12.6.3, ARM-IHI0050B: 13.6.3, ARM-IHI0050E.b: 14.6.3.

RN and SN

ERROR

CHI Link Layer

link active sm

rx_illegal_state_transition

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Rx link active state machine must be valid

Illegal transition of the Receiver Interface State.
This check monitors the RXLINKACTIVEREQ and RXLINKACTIVEACK signals and records illegal state transitions.

Valid state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.

Illegal state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.

RN and SN

ERROR

CHI Link Layer

link active sm

tx_illegal_state_transition

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Tx link active state machine must be valid

Illegal transition of the Transmitter Interface State.
This check monitors the TXLINKACTIVEREQ and TXLINKACTIVEACK signals and records illegal state transitions.

Valid state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.

Illegal state transition as per ARM-IHI0050A: 12.5.1 Table 12-2, ARM-IHI0050B: 13.5.1 Table 13-2, ARM-IHI0050E.b: 14.5.1 Table 14-2.

RN and SN

ERROR

CHI Link Layer

l-credit

valid_lcredit_count_in_tx_stop_state_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : The Transmitter has no credits and must not send any flits Description : All the applicable lcredit counter should be zero in tx stop state

When Tx is in stop state all the applicable lcredit counters should be 0. The Interconnect should not deassert the TXLINKACTIVEACK signal before it has recieved back all the lcredits.

RN:
- TXREQ VC: txreq_lcrd_count should be 0.
- TXRSP VC: txrsp_lcrd_count should be 0.
- TXDAT VC: txdat_lcrd_count should be 0.

SN:
- TXRSP VC: txrsp_lcrd_count should be 0.
- TXDAT VC: txdat_lcrd_count should be 0.

All the applicable lcredit counters are 0 in tx stop state.

All the applicable lcredit counters are non zero in tx stop state.

RN and SN

ERROR

CHI Link Layer

l-credit

invalid_lcredit_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : The Receiver must not send any credits Description : The receiver must not send lcredit in stop and activate state.

The receiver must not send lcredit in stop and activate state.

The receiver doeas not send lcredit in stop and activate state.

The receiver send lcredit in stop and activate state.

RN and SN

ERROR

CHI Link Layer

l-credit

tx_lcredit_used_same_cycle_which_recieved

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : An L-Credit cannot be used in the cycle it is received Description : An L-credit cannot be used in the cycle it is received.

Flits must not be transmitted on the same cycle that a credit is received

Flits transmitted on the subsequent cycle than that on which the credit is received

Flits transmitted on the same cycle that a credit is received

RN and SN

ERROR

CHI Link Layer

l-credit

rx_no_lcredit_sent_for_flit_transfer

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : On exit from reset, credits are held by the Receiver and must be passed to the Transmitter before flit transfer can begin Description : A flit can be sent on its virtual channel only if a corresponding L-credit is available at the transmitter and the link is active.

Credits must be available for every transmitted Flit

FLITV is asserted while there are one or more link credits available for the corresponding channel.

FLITV is asserted even though there are no L-credits available for the corresponding channel.

RN and SN

ERROR

CHI Link Layer

l-credit

tx_no_lcredit_for_flit_transfer

ARM-IHI0050E.b:14.2 Link layer Credit

Credits must be available for every transmitted Flit

Credits are available before flit transfer.

Credits are not available before flit transfer.

RN and SN

ERROR

CHI System

coherent rsp

coherent_resp_start_conditions_check

ARM-IHI0050E.b: 4.3 Snoop request types

Monitor Check that the response to a coherent transaction is not started before appropriate RN-Fs are snooped

Checks that the response to a coherent transaction is not started before the appropriate RN-Fs are snooped.
This check is applicable only when svt_chi_system_configuration :: perform_expected_snoops_checks is set to 1.

Scenario 1:
snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 0 for the HN, and snoops corresponding to a coherent request are broadcasted to all RN-Fs in the system.
Scenario 2:
snoop_filter_enable is set to 1, snoop_filter_based_snooping_enable is set to 0 for the HN, and snoops corresponding to a coherent request are broadcasted to all RN-Fs in the system.
Scenario 3:
snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to EXPECT_SNOOP, and snoops corresponding to a coherent request are sent to the RN-Fs which have a copy of the cache.
Scenario 4:
snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to DO_NOT_EXPECT_SNOOP, and snoops corresponding to a coherent request are sent to the RN-Fs which have cached the line in UC/UD/SD state.

Scenario 1:
snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 0 for the HN, and snoops corresponding to a coherent request are not broadcasted to all RN-Fs in the system.
Scenario 2:
snoop_filter_enable is set to 1, snoop_filter_based_snooping_enable is set to 0 for the HN, and snoops corresponding to a coherent request are not broadcasted to all RN-Fs in the system.
Scenario 3:
snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to EXPECT_SNOOP, and snoops corresponding to a coherent request are not sent to one or more of RN-Fs which have a copy of the cache.
Scenario 4:
snoop_filter_enable and snoop_filter_based_snooping_enable are both set to 1 for the HN, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state is set to DO_NOT_EXPECT_SNOOP, and snoops corresponding to a coherent request are not sent to one or more of RN-Fs which have cached the line in UC/UD/SD state.

The Snoop filter and Snooping based on Snoop filter Enable parameters must be programmed appropriately using svt_chi_system_configuration :: set_hn_snoop_filter_enable and svt_chi_system_configuration :: set_hn_snoop_filter_based_snooping_enable respectively.
In case the Interconnect is designed such that it does not snoop RN-Fs in SC state, svt_chi_system_configuration :: snoop_filter_policy_on_sc_state must be set to DO_NOT_EXPECT_SNOOP.
Expected snoopee info is also dependent on user programming of domain settings, through svt_chi_system_configuration :: create_new_domain API.
For a given RN-F that is expected to be snooped based on domain settings, if the RN-F has SYSCO interface feature enabled and the SYSCOREQ deasserion is observed while the coherent request was in progress, such RN-F will not be expected to be snooped.
This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.

ERROR

CHI System

Exclusive Access

exclusive_chi_transaction_type_check

ARM-IHI0050E.b: 6.3 Exclusive transactions

Monitor check that observed exclusive transaction is one of the allowed coherent/non-coherent exclusive load/store transaction types.

Checks that before processing any exclusive transactions from RN if that transaction is part of an allowed transaction type for an exclusive access.
Following are the permitted transaction types to have svt_chi_base_transaction :: is_exclusive set to 1: CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER) Prefetchtgt(is_exclusive is a don't care field for prefetchtgt so it is permitted to take any value)
This check is performed when an RN transaction is started.

Exclusive Access attribute is set to 1 for the transaction types CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER). PrefetchTgt(CHI-B OR LATER)

Exclusive Access attribute is set to 1 for the transaction types other than CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER). PrefetchTgt(CHI-B OR LATER)

ERROR

CHI System

Exclusive Access

exclusive_store_resp_check

ARM-IHI0050E.b: 6.2 Exclusive monitors

Monitor check that the resposne for exclusive store transaction matches the expected response for the given lpid and address.

Checks that the response for exclusive store transaction(CleanUnique, MakeReadUnique, WriteNoSnp*) matches the expected response(svt_chi_transaction :: response_resp_err_status in case of CleanUnique and WriteNoSnp, svt_chi_common_transaction :: final_state in case of MakeReadUnique) for the given lpid and address.
The expected response is determined by the exclusive monitor.
This check is executed when the store transaction is complete.

The response for exclusive store transaction(CleanUnique, MakeReadUnique, WriteNoSnp*) matches with the expected response as determinted by the exclusive monitor.

The response for exclusive store transaction(CleanUnique, MakeReadUnique, WriteNoSnp*) doesn't match with the expected response as determinted by the exclusive monitor.

ERROR

CHI System

Exclusive Access

exclusive_load_resp_check

ARM-IHI0050E.b: 6.2 Exclusive monitors

Monitor check that the resposne for exclusive load transaction matches the expected response for the given lpid and address.

Checks that the response for exclusive load transaction(ReadNoSnp, ReadShared, ReadClean, ReadNotSharedDirty, ReadPreferUnique) matches the expected response(svt_chi_transaction :: data_resp_err_status) for the given lpid and address.
The expected response is determined by the exclusive monitor.
This check is executed when the load transaction is complete.

The response for exclusive load transaction matches with the expected response as determinted by the exclusive monitor.

The response for exclusive load transaction doesn't match with the expected response as determinted by the exclusive monitor.

ERROR

CHI System

data integrity

slave_data_integrity_check

SYNOPSYS DEFINED

Monitor Check that the data observed in the subordinate VIP agent transaction from Home NodeHN to Subordinate matches with the expected data present in the subordinate VIP agent memory, when the subordinate VIP agent transaction ends successfully.

Checks that the data observed in the subordinate VIP agent transaction from Home Node(HN) to Subordinat, matches with the expected data present in the subordinate VIP agent memory, when the subordinate VIP agent transaction ends successfully. The subordinate can be a CHI SN or an AXI subordindate. In case of the transaction that is routed to AXI subordiniate, this check is performed under the following conditions:

The CHI system monitor (that is part of a CHI system ENV) and the AXI subordinate agent (that is part of an AXI system ENV) are part of an AMBA system ENV
The mapping between CHI SN agents and AXI subordinate agents is provided through the API set_axi_slave_to_chi_sn_map, of AMBA system configuration class.
Methodology used is UVM

This check is performed when there are no overlapping cacheline address transactions to the same subordinate. .

The data observed in the subordinate VIP agent transaction matches with the expected data in the subordinate VIP agent memory

The data observed in the subordinate VIP agent transaction does not match with the expected data in the subordinate VIP agent memory

This check is constructed only when at least one SN is present in the CHI system (svt_chi_system_configuration :: num_sn > 0)
In case of active mode AXI subordinate or CHI SN VIP agent, it is required to use a corresponding memory based response sequence, such as svt_axi_slave_memory_sequence or svt_chi_sn_memory_response_seuqnece respectively. If that is not the case, many of the system monitoring aspects including this check are not applicable and users are expected to disable system monitor.

ERROR

CHI System

dvm

interconnect_dvm_snoop_timing_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that the interconnect sends DVM Snoops only after DBIDResp is issued to the initiating RN and NCBWrData is received for the corresponding DVM request.

Checks that the interconnect issues DBIDResp and waits for the WriteData for a DVM request before issuing SnpDVMOp requests.

Interconnect sends SnpDVMOp request after DBIDResp and NonCopyBackWriteData are seen for the corresponding DVM request.

Scenario 1:
Interconnect sends SnpDVMOp request before DBIDResp is seen for the corresponding DVM request.
Scenario 2:
Interconnect sends SnpDVMOp request before NonCopyBackWriteData is seen for the corresponding DVM request.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI System

dvm

valid_dvm_response_from_interconnect_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that the Comp response for a DVMOp requestnon-sync,sync indicates an Error resposne if any of the associated snoops has Error response.

Checks that the interconnect sends correct response to the DVMOp(non-sync,sync) requests from then initiating RNs based on the response received from the SnpDvmop(non-sync,sync) from the snooped Rns. This check ensures that this comp response to the DVMOp request(non-sync,sync) is sent as Error resposne if any of the associated snoops has Error response.

Interconnect sends comp Error response to original DVMOp request if any of the associated SnpDVMOp transactions has error response

Interconnect sends comp OK response to original DVMOp request while one or more associated SnpDVMOp transactions receive comp Error response.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).
This check depends on user programming the RN-F/RN-D indices correctly through svt_chi_system_configuration :: create_new_domain API.
In above description, RN-D refers to an I/O coherent device that is DVM capable, such as ACE-Lite+DVM manager.

ERROR

CHI System

dvm

interconnect_dvm_response_timing_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that the interconnect waits for the responses for all corresponding SnpDVMOpnon-sync,sync requests before responding to original DVMOpnon-sync,sync transaction.

Checks that the interconnect waits for the responses to SnpDVMOp(non-sync,sync) requests from then snooped RNs before sending a comp response to original DVMOp request(non-sync,sync). This check ensures that this comp response to the DVMOp request(non-sync,sync) is sent only after all associated snoops are complete.
This check will only be performed when there are no error responses seen in the Data/Response flits corresponding to the DVMOp transaction. This is because the Interconnect behaviour in case of error responses in DVMOp transactions is implementation defined.

Interconnect sends comp response to original DVMOp request only after all the associated SnpDVMOp transactions are complete.

Interconnect sends comp response to original DVMOp request while one or more associated SnpDVMOp transactions are yet to receive comp response.

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI System

dvm

interconnect_dvm_sync_snoop_transaction_association_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that interconnect broadcasts SnpDVMOpsync transactions to all other RNs that are DVM snoopable when it receives a DVMOpsync request transaction from an RN.

Checks that interconnect broadcasts SnpDVMOp(sync) transactions to all other RNs that are DVM snoopable when it receives a DVMOp(sync) request transaction from an RN.
This check will only be performed when there are no error responses seen in the Data/Response flits corresponding to the DVMOp transaction. This is because the Interconnect behaviour in case of error responses in DVMOp transactions is implementation defined.

SnpDVMOp(sync) transactions corresponding to DVMOp(sync) request are broadcasted by interconnect to all RNs that are DVM snoopable, other than the initiating RN

SnpDVMOp(sync) transactions corresponding to DVMOp(sync) request are not broadcasted by interconnect to one or more RNs that are DVM snoopable, other than the initiating RN

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).

ERROR

CHI System

dvm

interconnect_dvm_operation_snoop_transaction_association_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that interconnect broadcasts SnpDVMOpnon-sync transactions to all other RNs that are DVM snoopable when it receives a DVMOpnon-sync request transaction from an RN.

Checks that interconnect broadcasts SnpDVMOp(non-sync) transactions to all other RNs that are DVM snoopable when it receives a DVMOp(non-sync) request transaction from an RN.

SnpDVMOp(non-sync) transactions corresponding to DVMOp(non-sync) request are broadcasted by interconnect to all RNs that are DVM snoopable, other than the initiating RN

SnpDVMOp(non-sync) transactions corresponding to DVMOp(non-sync) request are not broadcasted by interconnect to one or more RNs that are DVM snoopable, other than the initiating RN

RN-F and RN-D

This check is constructed only when DVM support is enabled in the RN-F/RN-D node (svt_chi_node_configuration :: dvm_enable == 1).
This check depends on user programming the RN-F/RN-D indices correctly through svt_chi_system_configuration :: create_new_domain API.
For a given RN-F/RN-D that is expected to be snooped based on domain settings, if the RN-F/RN-D has SYSCO interface feature enabled and the SYSCOREQ deasserion is observed while the DVM request was in progress, such RN-F/RN-D will not be expected to be snooped.
In above description, RN-D refers to an I/O coherent device that is DVM capable, such as ACE-Lite+DVM manager.

ERROR

CHI System

Domain and snoop

coherent_snoop_domain_match_check

ARM-IHI0050E.b: 2.9.6 Snoop Attribute

Monitor Check that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master

Checks that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master .
This check is performed when the snoop transaction is received at RN-F node , .
The check compares the domain of the snoop transaction with domain of the initiating RN-F,RN-I(s) coherent transaction.

when domain of the snoop transaction received at node is within the same domain of the coherent transactions sent by the Initiating RN node.

when domain of the snoop transaction received at node is not within the same domain of the coherent transactions sent by the Initiating RN node.

RN-F,RN-I

Expected snoopee info is also dependent on user programming of domain settings, through svt_chi_system_configuration :: create_new_domain API. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.

ERROR

CHI System

hazard

coherent_copyback_write_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent write request to the same cacheline(copyback-write hazard) are correctly handled by HN.
While there is a pending copyback request, if a Write request is received to the same cacheline, the coherent write request is processed only after the completion of the copyback transaction.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given copyback transaction and there was a Hazard condition with a subsequent coherent write transaction.
This check doesn't include coherent transactions from ACE-Lite master

Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write and the subsequent coherent write is not in progress.

Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write but the subsequent coherent write is already in progress

RN-F

This check is constructed only when at least one RN-F is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1.
The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.

ERROR

CHI System

hazard

coherent_write_copyback_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a Copyback request to the same cacheline(write-copyback hazard) are correctly handled by HN.
While there is a pending coherent write request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent write transaction.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent copyback transaction.
This check doesn't include coherent transactions from ACE-Lite master

Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback and the subsequent copyback is not in progress.

Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback but the subsequent copyback is already in progress

RN-F

ERROR

CHI System

hazard

coherent_copyback_read_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent read request to the same cacheline(copyback-read hazard) are correctly handled by HN across the system.
While there is a pending copyback request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent copyback transaction and there was a Hazard condition with a subsequent coherent read transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read and the subsequent coherent read is not in progress.

Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read but the subsequent coherent read is already in progress

RN-F

ERROR

CHI System

hazard

coherent_read_copyback_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a Copyback request to the same cacheline(read-copyback hazard) are correctly handled by HN across the system.
While there is a pending coherent read request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN read transaction and there was a Hazard condition with a subsequent copyback transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback and the subsequent copyback is not in progress.

Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coback but the subsequent copyback write is already in progress

RN-F

ERROR

CHI System

hazard

coherent_copyback_write_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent write request to the same cacheline(copyback-write hazard) are correctly handled by HN.
While there is a pending copyback request, if a Write request is received to the same cacheline, the coherent write request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and copyback-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

Coherent copyback transaction is completed while no other coherent write transactions to the same cacheline are in progress.

Coherent copyback transaction is completed while there is a coherent write transaction to the same cacheline in progress.

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

hazard

coherent_write_copyback_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a Copyback request to the same cacheline(write-copyback hazard) are correctly handled by HN.
While there is a pending coherent write request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the copyback transaction is completed and write-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

Coherent write transaction is completed while no other coherent copyback transactions to the same cacheline are in progress.

Coherent write transaction is completed while there is a coherent copyback transaction to the same cacheline in progress.

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

hazard

coherent_copyback_read_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent read request to the same cacheline(copyback-read hazard) are correctly handled by HN.
While there is a pending copyback request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and copyback-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent copyback transaction is completed while no other coherent read transactions to the same cacheline are in progress.

Coherent copyback transaction is completed while there is a coherent read transaction to the same cacheline in progress.

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

hazard

coherent_read_copyback_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a Copyback request to the same cacheline(read-copyback hazard) are correctly handled by HN.
While there is a pending coherent read request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the copyback transaction is completed and read-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent read transaction is completed while no other coherent copyback transactions to the same cacheline are in progress.

Coherent read transaction is completed while there is a coherent copyback transaction to the same cacheline in progress.

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

coherent rsp

cache_state_of_xact_resp_check

ARM-IHI0050E.b: 4.7 Cache state transitions at a Requester

Monitor Check that no peer RN has cached the line when the Cache state is UC/UD in the Comp/CompData response of coherent transactions

Checks that no peer RN has cached the line when the Cache state is UC/UD in the Comp/CompData of coherent transactions.The checker relies on the Snoop filter in the System monitor to check if any peer RNs might have cached the line

The final state in the Comp/CompData response of coherent transactions is UC/UD and the cache state at each of the peer RN-Fs is Invalid as per the Snoop filter

The final state in the Comp/CompData response of coherent transactions is UC/UD and the cache state of one or more peer RN-Fs is not Invalid as per the Snoop filter

This check is executed when DCT flow is not exercised or when snoop_requests_snoop_filter_update_policy == BASED_ON_SNOOP_REQUEST
Expected snoopee info is also dependent on user programming of domain settings, through svt_chi_system_configuration :: create_new_domain API

ERROR

CHI System

coherent and snoop

coherent_snoop_type_match_check

ARM-IHI0050E.b: Table 4-24 Expected snoop requests per Request from an RN

Monitor Check that the snoop transaction type corresponds to the coherent transaction type of initiating master

Checks that the associated snoop transaction type corresponds to the coherent transaction type from initiating RN as per:
- Table 4-1 of CHI Issue A specification
- Table 4-3 of CHI Issue B specification for the supported coherent and snoop types
This check is performed when coherent transaction is complete, and when a given snoop transaction is associated that is:
- not sent to initiating RN (snoop_not_sent_to_initiating_master_check not failed)
- only one snoop is outstanding at the snooped RN to the given cache line address
- not aborted

Associated snoop transaction type matches with the corresponding coherent transaction type as per the spec reference mentioned in the check description

Associated snoop transaction type does not match with the corresponding coherent transaction type as per the spec reference mentioned in the check description

RN-F

This check is constructed only when at least one RN-F is present in the CHI system. This check can be performed reliably only when the coherent-snoop association performed by the System monitor is accurate. One of the fundamental requirements for the coherent-snoop association to happen accurately is that the macro SVT_CHI_ALLOWED_SNOOP_XACT is defined to match the expected Snooping behavior of the Interconnect. This is a user redefinable macro whose default VIP definition can be found in svt_chi_common_defines.svi. Please review the default definition and redefine the macro in case the expected snoop types from the Interconnect do not match with the snoop types defined in the default definition of the macro.

ERROR

CHI System

coherent and snoop

snoop_not_sent_to_initiating_master_check

ARM-IHI0050E.b: 4.4 Request transactions and corresponding Snoop requests

Monitor Check that a snoop is not sent to the initiating master

Checks that an associated snoop transaction is not sent to the RN, that initiated corresponding coherent transaction.
This check is performed once coherent transaction is complete, and snoop transaction is assoiated to coherent transaction.
Note that this check doesn't include DVM transactions.

The associated snoop transaction is not received the same RN that initiated corresponding coherent transaction.

The associated snoop transaction is received by the same RN that initiated corresponding coherent transaction.

RN-F

ERROR

CHI System

coherent and snoop

overlapping_addr_sequencing_check

ARM-IHI0050E.b: 4.11.2 At the ICNHN-F node

Monitor Check that if two masters initiate requests to access the same cache line simultaneously, one master is sequenced after the other

Checks that if more than one RN initiate requests to access the same cache line simultaneously, one RN is sequenced after the other. If more than one RN initiate requests to access the same cache line simultaneously, the interconnect is expected to process these simultaneous requests one after another. In the case that this results in a scenario that is not corresponding to the check svt_chi_system_err_check :: snoop_not_sent_to_initiating_master_check, then the following details are applicable.

One or none snoop Requests with same cache line address is received at a given RN, AND None of the fail condition scenarios described under fail scenarios are applicable.

Scenario 1:
More than one Snoop request with same cache line address is received at a given RN, AND
More than one active Request with same cache line address is still active, THEN
It implies that there is an error in sequencing the transactions to same address.
Scenario 2:
More than one Snoop request with same cache line address is received at a given RN, AND
One or none active Requests with same cache line address are still active, THEN
It implies that there is an error in issuing multiple snoop transactions to a given RN

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

coherent and snoop

snoop_addr_matches_coherent_addr_check

ARM-IHI0050E.b: 4.3 Snoop request types

Monitor Check that the address of a snoop transaction must match one of the outstanding coherent transactions

Checks that the address of a snoop transaction must match one of the outstanding coherent transactions
This check is performed when the snoop transaction starts, even before coherent to snoop transaction association is done.
Note that this doesn't check for snoop transaction type that corresponds to coherent transaction type
The coherent transaction types that are checked for matching address are all the types excluding the following: WriteNoSnp*, ReadNoSnp, WriteBack*, WriteClean*, Evict, WriteEvictFull.

The address of snoop transaction matches to one of the outstanding snoopable transactions

The address of snoop transaction matches to none of the outstanding snoopable transactions

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

snoop rsp

only_one_snoop_returns_data_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that only one snoop transaction returns data

Checks that for a given coherent transaction, only one of the associated snooped RNs responded to the snoop requests with data (svt_chi_snoop_transaction :: snp_rsp_datatransfer = 1).
This check is performed when the coherent transaction is complete.

When only one of the associated snooped RN's responded to snoop request with data.

When more than one associated snooped RN's responded to snoop request with data.

RN-F

ERROR

CHI System

snoop rsp

snoop_resp_passdirty_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that no two associated snooped RNs responded to snoop transactions with PassDirtyresp[2] in the snoop responses asserted.

Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with PassDirty(resp[2] - svt_chi_common_transaction :: resp_pass_dirty) asserted to HN.
This check is performed when the coherent transaction is complete.

When only one of the associated snooped RN's responded to snoop request with PassDirty asserted.

When more than one associated snooped RN's responded to snoop request with PassDirty asserted.

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

snoop rsp

snoop_resp_wasunique_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that no two associated snooped RNs responded to snoop transactions with cache line state as Unique.

Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with 'final cache line state as Unique'(WasUnique response asserted) at the respective snooped RNs.
This check is performed when the coherent transaction is complete.

When only one of the associated snooped RN responded to snoop request with final cache line state as Unique in the snoop response.

When more than one associated snooped RN's responded to snoop request with final cache line state as Unique in the snoop response.

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

coherent and snoop

coherent_xact_with_no_snoop_check

ARM-IHI0050E.b: 4.4 Request transactions and corresponding Snoop requests

Monitor Check that non-coherent requests READNOSNOOP,WRITENOSNOOP -- Except in case of invisibile cache mode at HN-F L3 , copyback requests WRITEBACK,WRITECLEAN,WRITEEVICTFULL and EVICT do not cause a snoop of cached RNs.

Checks that READNOSNOOP,WRITENOSNOOP*,WRITEBACK*,WRITECLEAN*, WRITEEVICTFULL and EVICT transactions do not lead to snooping of peer RN-Fs.
This check is performed when the snoop transaction starts.
The check compares the address of the snoop transaction with outstanding coherent transactions.
The check does not compare the snoop transaction type with coherent transaction type.
Note that, in case of Invisible Cahe Mode at HN, it's possible to have Snoops for non-coherent transactions, please refer to svt_chi_system_configuration :: set_hn_invisible_cache_mode_enable for more details. In this case, the check factors in the set_hn_invisible_cache_mode_enable() settings along with Snoop Filter entries to validate the correctness of observed snoops for the non-coherent requests.

There are outstanding snoopable transactions of the type (other than the transaction types described in check description), with matching address as that of the snoop transaction

There are outstanding only non-snoopable transactions(the transaction types described in check description), with matching address as that of the snoop transaction

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

coherent and snoop

coherent_and_snoop_data_match_check

ARM-IHI0050E.b: 4.3 Snoop request types

Monitor Check that data returned to initiating RN matches with the full cacheline data received from associated snoop transaction

Checks that data returned to initiating RN matches with the data received from associated snoop transaction under following scenarios:
- Scenario 1: Full cacheline data is returned for one of the associated snoop transaction
- Scenario 2: Partial cacheline data is returned for one of the associated snoop transaction and HN-F L3 has the cacheline
This check is not performed in case of partial cacheline data is returned for one of the snoop transaction and HN-F L3 doesn't have the cacheline.
This check is applicable when : coherent transaction has data response and there are associated snoop transactions
This check is performed when the coherent transaction is complete

Scenario 1: full cacheline data returned for one of the associated snoop transaction matches with data in response to RN
Scenario 2: Partial cacheline data returned for one of the associated snoop transaction merged with HN-F L3 data matches with data in resposne to RN

Scenario 1: full cacheline data returned for one of the associated snoop transaction doesn't match with data in response to RN
Scenario 2: Partial cacheline data returned for one of the associated snoop transaction merged with HN-F L3 data doesn't match with data in resposne to RN

RN-F

ERROR

CHI System

data integrity

snoop_data_integrity_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that snoop response data from snooped RN matches with system monitor HN-F L3 view when the final state resp[1:0] in the SnpRspData flits is set to UC/SC/I.

Checks that data in snoop transaction is consistent with system monitor HN-F L3 view when the snoop transaction completes.
This check is performed when the coherent transaction is complete and system monitor has already associated the snoop transactions.
This check is not applicable in case the snoop transaction returns the dirty data.

The data in snoop transaction matches with system monitor HN-F L3 view when the snoop transaction completes

The data in snoop transaction doesn't match with system monitor HN-F L3 view when the snoop transaction completes

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

data integrity

copyback_data_integrity_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

Monitor Check that CopyBack write data from RN matches with system monitor HN-F L3 view when the current state resp[1:0] in the CopyBack write DAT flits is set to UC/SC.

Checks that data in transaction is consistent with data in system monitor HN-F L3 view, when the CopyBack transaction completes.
This check is applicable when the current state in the CopyBack transaction is UC/SC and there are no overlapping transactions to the same cacheline.
In case the current state is dirty, system monitor HN-F L3 view will be updated with the CopyBack write data. There is no need to compare the CopyBack write data with system monitor HN-F L3 view in such a case.
In case the current state is I, interconnect is expected to ignore/drop the CopyBack write data. System monitor HN-F L3 view will not be updated with the CopyBack write data in this case. Also there is no need to compare CopyBack write data with system monitor HN-F L3 view.
Current State indicates the cacheline state at the RN when the data is sent (resp[1:0]).

For a given cacheline address, when current state in the CopyBack DAT flits is clean, and the system monitor HN-F L3 view data matches with CopyBack write data.

For a given cacheline address, when current state in the CopyBack DAT flits is clean, and the system monitor HN-F L3 view data doesn't match with CopyBack write data.

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

Streaming order

single_rn_optimized_streaming_order_check

ARM-IHI0050E.b: 2.8.5

Monitor Check that not more than one RN is configured to use the optimized streaming ordered WriteUnique/writeNoSnp flow, in the system.

Checks that not more than one RN is configured to use the optimized streaming ordered WriteUnique flow.

OrderWriteObservation is enabled for WriteUnique transactions when svt_chi_transaction :: xact_type is WRITEUNIQUEFULL/WRITEUNIQUEPTL, with svt_chi_base_transaction :: order_type == REQ_ORDERING_REQUIRED and svt_chi_base_transaction :: exp_comp_ack set to 1.
Optimized streaming ordered WriteUnique is enabled through setting svt_chi_node_configuration :: optimized_streaming_ordered_writeunique_enable=1.
This Check is performed when the transaction is started.

When OrderWriteObservation ordered WriteUnique transactions are observed as started from any of the RN's, with svt_chi_node_configuration :: optimized_streaming_ordered_writeunique_enable set to 1 for none or one of the RN agents.

Applicable only when there is at least two RNs are present in the CHI system (svt_chi_system_configuration :: num_rn > 1).
This check is performed When the following type transactions are observed:

WriteUnique transactions with svt_chi_base_transaction :: order_type == REQ_ORDERING_REQUIRED and svt_chi_base_transaction :: exp_comp_ack set to 1.

WARNING

CHI System

Mismatched Memory attributes

same_memory_snoop_attributes_for_addr_check

ARM-IHI0050E.b: 2.9.7 Mismatched Memory attributes

Monitor Check that All outstanding transactions targetting the same address must have the same MemAttr bits Device, Cacheable and SnpAttr bit. All the agents should maintain a consistent view of the attributes of any region of memory addresses

All the nodes should maintain a consistent view of the attributes of any region of memory addresses.
When software rules checking is enabled, all outstanding transactions targetting the same address are expected to have the same MemAttr bits Device, Cacheable and SnpAttr bit.

A request is observed with memory or snoop attributes that same as outstanding request to the same address.

A request is observed with memory or snoop attributes that differ from an outstanding request to the same address.

RN and SN

This check is applicable only when:

svt_chi_system_configuration :: software_rules_based_checks_enable is set to 1
invisible_cache_mode_enable is set to 0

ERROR

CHI System

hazard

coherent_copyback_copyback_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and another copyback request are correctly ordered by HN

Checks that hazard condition between a copyback and another copyback request to the same cacheline(copyback-copyback hazard) are correctly ordered by HN across the system.
There should not be more than one copyback transactions to the same cacheline that are in progress at any given point in time A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given RN copyback transaction and there was a Hazard condition with a subsequent copyback transaction.
This check doesn't include copyback transactions from ACE-Lite master

Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback and the subsequent coherent copyback is not in progress.

Copyback transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent copyback but the subsequent copyback is already in progress

ERROR

CHI System

hazard

coherent_read_read_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and another coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent read request and another coherent read request to the same cacheline(read-read hazard) are correctly ordered by HN across the system.
There should not be more than one coherent read transactions to the same cacheline that are in progress at any given point in time. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN Read transaction and there was a Hazard condition with a subsequent coherent Read transaction.
This check doesn't include coherent read transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent Read and the subsequent coherent Read is not in progress.

Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent Read but the subsequent coherent Read is already in progress

This check is constructed only when at least one RN (svt_chi_system_configuration :: num_rn > 0) is present in the CHI system and svt_chi_system_configuration :: post_slave_xact_association_hazard_checks_enable is set to 1.
The check is performed only when L3 is disabled at the target HN as the master slave transaction correlation cannot be performed reliably when L3 is enabled.

ERROR

CHI System

hazard

coherent_write_write_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and another coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent write request and another coherent write request to the same cacheline(write-write hazard) are correctly ordered by HN across the system.
There should not be more than one coherent write transactions to the same cacheline that are in progress at any given point in time A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent coherent write transaction.
This check doesn't include coherent write transactions from ACE-Lite master

Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write and the subsequent coherent write is not in progress.

Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write but the subsequent coherent write is already in progress

ERROR

CHI System

hazard

coherent_write_read_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent read request to the same cacheline(write-read hazard) are correctly handled by HN.
While there is a pending write request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the write transaction.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent coherent read transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read and the subsequent coherent read is not in progress.

Coherent write transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent read but the subsequent coherent read is already in progress

ERROR

CHI System

hazard

coherent_read_write_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent write request to the same cacheline(read-write hazard) are correctly handled by HN across the system.
While there is a pending coherent read request, if a write request is received to the same cacheline, the write request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN read transaction and there was a Hazard condition with a subsequent coherent write transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write and the subsequent coherent write is not in progress.

Coherent read transaction is complete, corresponding slave transaction is complete and associated, a Hazard condition was detected with a subsequent coherent write but the subsequent coherent write is already in progress

ERROR

CHI System

hazard

coherent_read_read_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and another coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent read request and another coherent read request to the same cacheline(read-read hazard) are correctly ordered by HN
There should not be more than one coherent read transactions to the same cacheline that are in progress at any given point in time
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and a read-read hazard condition was detected when it was started
This check doesn't include coherent read transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent read transaction is completed while there are no other coherent read transactions to the same cacheline in progress.

Coherent read transaction is completed while another coherent read transaction to the same cacheline is in progress.

This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)

ERROR

CHI System

hazard

coherent_req_compack_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor check that - for a given cacheline, hazard condition between a Coherent request and CompAck is handled correctly by the HN

Checks that hazard condition between a pending CompAck and another coherent request to same cacheline are correctly ordered by HN.
When HN receives a new RN request transaction to a cacheline while there's a pending transaction to the same cacheline that is yet to receive a CompAck, HN must not process the new request till the CompAck for the outstanding transaction is received.
This check is not applicable for the coherent requests from ACE-Lite master as CompAck is not present in ACE-Lite protocol.
This check is performed when a coherent request receives a response from HN

HN sends a response to the coherent request when there are no ongoing coherent requests to the same cacheline that are waiting to receive a CompAck

HN sends a response to the coherent request when there are any ongoing coherent requests to the same cacheline that are waiting to receive a CompAck

RN-F

This check is constructed only when at least one RN-F is present in the CHI system

ERROR

CHI System

hazard

coherent_write_write_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and another coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent write request and another coherent write request to the same cacheline(write-write hazard) are correctly ordered by HN
There should not be more than one coherent write transactions to the same cacheline that are in progress at any given point in time
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and a write-write hazard condition was detected when it was started
This check doesn't include coherent write transactions from ACE-Lite master

Coherent write transaction is completed while there are no other coherent write transactions to the same cacheline in progress.

Coherent write transaction is completed while another coherent write transaction to the same cacheline is in progress.

This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)

ERROR

CHI System

hazard

coherent_write_read_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent read request to the same cacheline(write-read hazard) are correctly handled by HN.
While there is a pending write request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and write-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent write transaction is completed while no other coherent read transactions to the same cacheline are in progress.

Coherent write transaction is completed while there is a coherent read transaction to the same cacheline in progress.

This check is constructed only when at least one RN is present in the CHI system

ERROR

CHI System

hazard

coherent_read_write_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent write request to the same cacheline(read-write hazard) are correctly handled by HN.
While there is a pending coherent read request, if a write request is received to the same cacheline, the write request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the write transaction is completed and read-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

Coherent read transaction is completed while no other coherent write transactions to the same cacheline are in progress.

Coherent read transaction is completed while there is a coherent write transaction to the same cacheline in progress.

This check is constructed only when at least one RN is present in the CHI system

ERROR

CHI System

Transaction ordering

slave_xacts_ordering_for_ordered_rn_xact_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

Monitor Check that the associated slave xacts of ordered RN transaction should be started after all the associated slave xacts of earlier issued ordered RN xact

The interconnect must maintain the order in which slave transactions are issued corresponding to ordered RN transactions from an RN to same address/address range

In CHI Issue C or earlier:

The associated slave transactions of Ordered RN transaction should be started after all the associated slave transactions of earlier issued Ordered RN transaction.

In CHI Issue D or later:

The associated slave transactions of Request_Ordered RN transaction should be started after all the associated slave transactions of earlier issued Request_Ordered RN transaction.
The associated slave transactions of Endpoint_Ordered RN transaction should be started after all the associated slave transactions of earlier issued Endpoint_Ordered RN transaction.

In CHI Issue C or earlier:

Any of the associated slave transactions of Ordered RN transaction is started before the associated slave transactions of earlier issued Ordered RN transaction.

In CHI Issue D or later:

Any of the associated slave transactions of Request_Ordered RN transaction is started before the associated slave transactions of earlier issued Request_Ordered RN transaction.
Any of the associated slave transactions of Endpoint_Ordered RN transaction is started before the associated slave transactions of earlier issued Endpoint_Ordered RN transaction.

RN and SN

This check is applicable only when:

svt_chi_system_configuration :: slave_xact_to_rn_xact_correlation_enable is set to 1, and
svt_chi_system_configuration :: ordering_checks_enable is set to 1.
L3 is disabled for the target HN (should be specified via svt_chi_system_configuration :: set_hn_l3_cache_enable)

Note: User must use svt_chi_system_monitor_callback :: master_xact_fully_associated_to_slave_xacts or svt_chi_system_monitor_callback :: new_system_transaction_started callbacks to set svt_chi_system_transaction :: ep_range_indx of system xact for Endpoint ordering.
Default value of svt_chi_system_transaction :: ep_range_indx = -1;

ERROR

CHI System

Propagation of Attr

memory_attributes_propagation_check

ARM-IHI0050E.b: 2.9.3 Memory Attributes

Monitor Check that all the memory attributes of RN transaction are propagated to slaves

The MemAttr bits EWA, Device, Cacheable, and Allocate, must be preserved on a request from HN to SN that is sent in response to a request to HN.
This check is performed after master-slave association is complete.

Interconnect propagates memory attributes of RN request to slaves.

Interconnect doesn't propagate memory attributes of RN request to slaves.

RN and SN

This check is applicable only when:

svt_chi_system_configuration :: slave_xact_to_rn_xact_correlation_enable is set to 1
svt_chi_system_configuration :: memattr_propagation_checks_enable is set to 1
L3 is disabled for the target HN (should be specified via svt_chi_system_configuration :: set_hn_l3_cache_enable)
The master and the associated slave transactions are both native CHI transactions.

ERROR

CHI System

coherent rsp

coherent_resp_passdirty_check

ARM-IHI0050E.b: 13.10.44 Response status, Resp

Monitor Check that the PassDirty response to initiating RN is correct

Checks that the PassDirty response(resp[2]) in the coherent response to initiating RN-F is correct.
In case of ReadShared, ReadUnique, ReadNotSharedDirty(CHI-B OR LATER): If PassDirty was asserted for any snoop response received by the interconnect, and the interconnect has not asserted PassDirty in the coherent response to initiating RN, it's possible that Interconnect has taken the responsibility of updating the L3 cache or main memory. Note that this check does not verify if the interconnect updated L3 or main memory with dirty data. However, in this case, if the HN is not able to properly handle the dirty data, a subsequent read to same cacheline would result into read_data_integrity_check failure.
This check is performed when the coherent transaction is complete.

Scenario 1:
For ReadShared, ReadUnique and ReadNotSharedDirty: other than the scenarios where PassDirty is asserted in any of the associated snoop responses AND PassDirty is not asserted in the coherent response. If the PassDirty is asserted by interconnect in coherent response without any PassDirty asserted snoop responses/no associated snoops, its possible that interconnect has the line cached in L3 in dirty state, and is passing on the PassDirty to initiating RN.
Scenario 2:
For othr transaction types, when PassDirty is not asserted in coherent response to RN

For coherent transaction types other than ReadShared, ReadUnique and ReadNotSharedDirty, when PassDirty is asserted in coherent response from HN to initiating RN.

This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)

ERROR

CHI System

coherent rsp

coherent_resp_isshared_check

ARM-IHI0050E.b: 13.10.44 Response status, Resp

Monitor Check that the final state in the coherent response to the initiating RN is set to Shared as expected

Checks the correctness of 'the final state in the coherent response to be Shared State or not'(IsShared response), for the following coherent transaction types from HN to initiating RN-F is correct:
- ReadClean, ReadShared
- ReadNotSharedDirty, ReadSpec (CHI-B OR LATER)
This check is performed when the coherent transaction is complete

Scenarios other than the fail condition described

If the IsShared response is asserted in any of the associated snoops (by Snooped RN to HN), but IsShared response is not asserted in the coherent response (by HN to initiating RN)

This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0)

ERROR

CHI System

data integrity

read_data_integrity_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

Monitor Check that observed/received read data at RN matches with expected data from system monitor when: the snooped RNs return the data in clean state OR none of the snooped RNs return any data OR there are no snoops. System monitor establishes expected data based on observed RN requests with write data & RN snoop transactions with data, but does not depend on any subordinate transactions.

Checks that data in read transaction is consistent with system monitor HN(HN-F L3/HN-I memory) when the read transaction completes at RN.
This check is applicable when the snooped RNs return the data in clean state or none of the snooped RNs return any data.

The data in RN read transaction matches with system monitor HN view when the RN read transaction completes.

The data in RN read transaction doesn't match with system monitor HN view when the RN read transaction completes.

This check is constructed only when at least one RN is present in the CHI system (svt_chi_system_configuration :: num_rn > 0).
This check will not be performed when a hazard Write is detected for the Read transaction.
The data bytes that are marked as poisoned, either in the transaction data or in the system monitor view, are ignored and not used for comparison.
The data bytes that are have parity errors, are ignored and not used for comparison.

ERROR

CHI System

ABF

multiple_abf_requests_targeted_to_same_addr_and_to_same_target

SYNOPSYS DEFINED

Monitor Checks that there are no more than one address based flush requests to same address and to same target.

Checks that only one snoop transaction is issued to a given RN targeting a particular cacheline, as a result of Address based flush operation.
This check will be performed if the address in the snoop transaction lies in range svt_chi_hn_status :: min_abf_addr and svt_chi_hn_status :: max_abf_addr.

If there exists only one snoop transaction as a result of Address based flushing operation issued to same cache line and to same target .

If there exists multiple snoop transactions as a result of Address based flushing operation issued to same cache line and to same target

Active RN

This check is applicable only when:

the macro svt_chi_system_configuration :: abf_enable is set to 1.

ERROR

CHI System

routing

slave_transaction_routing_check

SYNOPSYS DEFINED

Monitor Check that transaction is routed to the correct slave based on the address of the transaction request

Checks that a transaction is routed correctly to a slave port based on address. This check is performed on the transactions routed from CHI interconnect to a CHI SN or an AXI slave, when the transactions are started at the slave. In case the transaction is routed to AXI slave, this check is performed under following conditions:

The CHI system monitor (that is part of a CHI system ENV) and the AXI slave (that is part of an AXI system ENV) are part of an AMBA system ENV
The mapping between CHI SNs and AXI slaves is provided through the APIs of AMBA system configuration
Methodology used is UVM

The transaction is routed to the expected Slave, the check passes

The transaction is routed to an unexpected Slave, the check fails

Note:

When multiple SNs are mapped to single HN, users are expected to override either the svt_chi_system_configuration :: get_slave_node_id_for_addr for calculating slave_node_id and set svt_chi_system_configuration :: calculate_slave_id_based_on_xact_handle bit to 0 or override svt_chi_system_configuration :: get_slave_node_id_for_xact for calculating SN node id and set svt_chi_system_configuration :: calculate_slave_id_based_on_xact_handle bit to 1.
For more details on svt_chi_system_configuration :: get_slave_node_id_for_addr or svt_chi_system_configuration :: get_slave_node_id_for_xact or svt_chi_system_configuration :: calculate_slave_id_based_on_xact_handle, please refer to corresponding class reference documenation.
This check is constructed only when at least one SN is present in the CHI system (svt_chi_system_configuration :: num_sn > 0).

ERROR

VIP Smartsearch

AMBA CHI-A SVT VMM Documentation - Protocol Checks Defined in VIP

Product: amba_svt - Protocol Checks Details:

All Group Sub Group Protocol Check Instance name Reference Description Check Intent Pass Condition Fail Condition Applicable Device Type Additional Information Error Category Protocol Check Class

VIP Smartsearch

AMBA CHI-A SVT VMM Documentation - Protocol Checks Defined in VIP

Product: amba_svt - Protocol Checks Details:

Show/Hide All Group Sub Group Protocol Check Instance name Reference Description Check Intent Pass Condition Fail Condition Applicable Device Type Additional Information Error Category Protocol Check Class

All Group Sub Group Protocol Check Instance name Reference Description Check Intent Pass Condition Fail Condition Applicable Device Type Additional Information Error Category Protocol Check Class