AHB SVT UVM Documentation - Interfaces Reference

Product	Interface Group	Interfaces
amba_svt	Default Group	svt_ahb_master_if
svt_ahb_slave_if
svt_ahb_if	svt_ahb_slave_if, svt_ahb_master_if
svt_ahb_param_if
svt_ahb_master_param_if
svt_ahb_slave_param_if

interface svt_ahb_slave_if ( input logic common_hclk, input logic common_hresetn, input logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] haddr_bus, input logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] hburst_bus, input logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH+SVT_AHB_HMASTER_PORT_WIDTH-1):0] hmaster_bus, input logic hmastlock_bus, input logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] hprot_bus, input logic hnonsec_bus, input logic hexcl_bus, input logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] hsize_bus, input logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] htrans_bus, input logic [(SVT_AHB_HWSTRB_WIDTH-1):0] hwstrb_bus, input logic htranschk_bus, input logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0] haddrchk_bus, input logic hctrlchk1_bus, input logic hctrlchk2_bus, input logic hprotchk_bus, input logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0] hwstrbchk_bus, input logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] hwdatachk_bus, input logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0] control_huserchk_bus, input logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] hwdata_huserchk_bus, input logic hready_inchk_bus, input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hwdata_bus, input logic hwrite_bus, input logic hready_bus, input logic [SVT_AHB_MAX_USER_WIDTH-1:0] control_huser_bus, input logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] hwdata_huser_bus ) General description: The slave interface svt_ahb_slave_if defines the AHB signals appropriate for a single port, along with the modports needed for the AHB slave and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Ports
bit	is_active
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hrdata
logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]	hresp
logic	hexokay
logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]	haddr
logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]	hburst
logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]	hprot
logic	hnonsec
logic	hexcl
logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]	hsize
logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]	htrans
logic [(SVT_AHB_HWSTRB_WIDTH-1):0]	hwstrb
logic	htranschk
logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0]	haddrchk
logic	hctrlchk1
logic	hctrlchk2
logic	hprotchk
logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0]	hwstrbchk
logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0]	hwdatachk
logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0]	hrdatachk
logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0]	control_huserchk
logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0]	resp_huserchk
logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0]	hwdata_huserchk
logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0]	hrdata_huserchk
logic	hreadychk
logic	hready_inchk
logic	hselchk
logic	hrespchk
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hwdata
logic	hwrite
logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH+SVT_AHB_HMASTER_PORT_WIDTH-1):0]	hmaster
logic	hmastlock
logic [(SVT_AHB_MAX_HSEL_WIDTH-1):0]	hsel
logic	hready_in
logic	hready
logic [(SVT_AHB_MAX_NUM_MASTERS-1):0]	hsplit
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	addr_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	data_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	xact_beat_num
logic [SVT_AHB_MAX_USER_WIDTH-1:0]	control_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hwdata_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hrdata_huser
logic [SVT_AHB_MAX_RESP_USER_WIDTH-1:0]	resp_huser
string	full_name

Modports
modport svt_ahb_slave_modport ( input internal_hresetn, clocking ahb_slave_cb ) Modport used to connect the VIP Slave to AHB interface signals.

modport svt_ahb_bus_modport ( input hrdata, input hready, input hresp, input hexokay, input resp_huser, input hrdatachk, input hreadychk, input hrespchk, input resp_huserchk, input hrdata_huserchk, output hselchk, input hsplit, input hrdata_huser, output hsel, clocking ahb_bus_cb ) Modport used to connect the VIP Bus to AHB master interface signals. Asynchronous signals are required for multiplexing functionality

modport svt_ahb_monitor_modport ( input internal_hresetn, clocking ahb_monitor_cb ) Modport used to connect the VIP Monitor to AHB interface signals.

modport svt_ahb_slave_async_modport ( input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hexcl, input hsel, input hsize, input htrans, input hwstrb, input hwdata, input hwrite, input hready_in, input control_huser, input hwdata_huser, output hrdata, output hready, output hresp, output hexokay, output resp_huser, output hsplit, output hrdata_huser, input is_active ) Asynchronous modport suitable for SV Slave Bind interface

modport svt_ahb_debug_modport ( output addr_phase_xact_num, output data_phase_xact_num, output xact_beat_num ) Modport used to connect the VIP Debug Port.

Clocking blocks
clocking ahb_slave_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hexcl, input hsel, input hsize, input htrans, input hwstrb, input htranschk, input haddrchk, input hctrlchk1, input hctrlchk2, input hprotchk, input hwstrbchk, input hwdatachk, input control_huserchk, input hwdata_huserchk, input hselchk, input hready_inchk, output hrdatachk, output hreadychk, output hrespchk, output resp_huserchk, output hrdata_huserchk, input hwdata, input hwrite, input hready_in, input control_huser, input hwdata_huser, output hrdata, output hready, output hresp, output hexokay, output resp_huser, output hsplit, output hrdata_huser Clocking block that defines the VIP AHB Bus-Slave Interface signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge common_hclk ) default input #0.01 output #0.01 input hrdata, input hready, input hresp, input hexokay, input resp_huser, input hrdatachk, input hreadychk, input hrespchk, input resp_huserchk, input hrdata_huserchk, output hselchk, input hsplit, input hrdata_huser, output hsel Clocking block that defines the VIP AHB slave Interface signal synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hexcl, input hsel, input hsize, input htrans, input hwstrb, input htranschk, input haddrchk, input hctrlchk1, input hctrlchk2, input hprotchk, input hwstrbchk, input hwdatachk, input control_huserchk, input hwdata_huserchk, input hrdata_huserchk, input resp_huserchk, input hrdatachk, input hreadychk, input hready_inchk, input hrespchk, input hselchk, input hwdata, input hwrite, input hrdata, input hready, input hready_in, input hresp, input hexokay, input hsplit, input control_huser, input hwdata_huser, input hrdata_huser, input resp_huser Clocking block that defines the AHB Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_ahb_if ()

General description:

AHB VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_ahb_if is defined. The top level interface contains reset signal for the bus, and an array of master & slave interfaces. The top level interface can be used for connecting the master & slave components to the AHB Bus. By default, 16 master and 16 slave interfaces are defined in the top level interface. Currently, the maximum number of master and slave interfaces supported is 128. The number of master and slave interfaces in top level interface can be controlled using macros SVT_AHB_MAX_NUM_MASTERS_{0..128} and SVT_AHB_MAX_NUM_SLAVES_{0..128} respectively. For example, if you want to use 8 master interfaces and 10 slave interfaces, you can define following macros when compiling the VIP:

SVT_AHB_MAX_NUM_MASTERS_8

SVT_AHB_MAX_NUM_SLAVES_10
Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces:

Interface Name	Interface Description
svt_ahb_master_if	Master Interface used by master VIP component
svt_ahb_slave_if	Slave Interface used by slave VIP component

Clock signal description:

Signal Name	Signal Description
hclk	This clock signal belongs to the top level AHB Interface. User is expected to connect clock signal in testbench to this hclk signal in the top level interface. This clock is used by all the AHB master and slave VIP components.

Clock connection examples:
assign ahb_if.hclk = SystemClock;

Reset signal description:

Signal Name	Signal Description
hresetn	This reset signal belongs to the top level AHB Interface. User is expected to connect reset signal in testbench to this hclk signal in the top level interface. This reset is used by all the AHB master and slave VIP components.

Reset connection examples:
assign ahb_if.hresetn = SystemResetn;

Sub-interfaces

svt_ahb_master_if

master_if

svt_ahb_slave_if

slave_if

Ports

logic

hclk

logic

hresetn

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]

hrdata_bus

logic

hready_bus

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]

hresp_bus

logic

hexokay_bus

logic [SVT_AHB_MAX_RESP_USER_WIDTH-1:0]

resp_huser_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]

hrdata_huser_bus

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]

haddr_bus

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]

hburst_bus

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]

hprot_bus

logic

hnonsec_bus

logic

hexcl_bus

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]

hsize_bus

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]

htrans_bus

logic [(SVT_AHB_HWSTRB_WIDTH-1):0]

hwstrb_bus

logic

htranschk_bus

logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0]

haddrchk_bus

logic

hctrlchk1_bus

logic

hctrlchk2_bus

logic

hprotchk_bus

logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0]

hwstrbchk_bus

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0]

hwdatachk_bus

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0]

hrdatachk_bus

logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0]

control_huserchk_bus

logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0]

resp_huserchk_bus

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0]

hwdata_huserchk_bus

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0]

hrdata_huserchk_bus

logic

hrespchk_bus

logic

hreadychk_bus

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]

hwdata_bus

logic

hwrite_bus

logic [SVT_AHB_MAX_USER_WIDTH-1:0]

control_huser_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]

hwdata_huser_bus

logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH+SVT_AHB_HMASTER_PORT_WIDTH-1):0]

hmaster_bus

logic

hmastlock_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

curr_hmaster

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

prev_hmaster

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]

curr_sel_slave

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]

prev_sel_slave

logic [SVT_AHB_MAX_NUM_MASTERS-1:0]

hsplit_bus

string

full_name

Modports

modport svt_ahb_bus_modport

(

input hresetn,
output hrdata_bus,
output hready_bus,
output hresp_bus,
output hexokay_bus,
output resp_huser_bus,
output haddr_bus,
output hburst_bus,
output hprot_bus,
output hnonsec_bus,
output hexcl_bus,
output hsize_bus,
output htrans_bus,
output hwdata_bus,
output hwstrb_bus,
output haddrchk_bus,
output hprotchk_bus,
output control_huserchk_bus,
output hwdata_huserchk_bus,
output hrdata_huserchk_bus,
output hwstrbchk_bus,
output htranschk_bus,
output hwdatachk_bus,
output resp_huserchk_bus,
output hrespchk_bus,
output hctrlchk1_bus,
output hctrlchk2_bus,
output hrdatachk_bus,
output hreadychk_bus,
output hwrite_bus,
output control_huser_bus,
output hmaster_bus,
output hmastlock_bus,
output hwdata_huser_bus,
output hrdata_huser_bus,
clocking ahb_bus_reset_cb,
clocking ahb_bus_cb

)

Modport used to connect the reset signal to VIP AHB Bus The signals corresponding to following need to be asynchronous

The address, control, write data from granted master to all slaves
The response, read data from selected slave to all masters

modport svt_ahb_monitor_modport

(

input hresetn,
input hrdata_bus,
input hready_bus,
input hresp_bus,
input hexokay_bus,
input resp_huser_bus,
input haddr_bus,
input hburst_bus,
input hprot_bus,
input hnonsec_bus,
input hexcl_bus,
input hsize_bus,
input htrans_bus,
input hwdata_bus,
input hwstrb_bus,
input htranschk_bus,
input haddrchk_bus,
input hctrlchk1_bus,
input hctrlchk2_bus,
input hprotchk_bus,
input hwstrbchk_bus,
input hwdatachk_bus,
input control_huserchk_bus,
input hwdata_huserchk_bus,
input hrdata_huserchk_bus,
input resp_huserchk_bus,
input hrdatachk_bus,
input hreadychk_bus,
input hrespchk_bus,
input hwrite_bus,
input control_huser_bus,
input hmaster_bus,
input hmastlock_bus,
input hwdata_huser_bus,
input hrdata_huser_bus,
clocking ahb_bus_reset_cb,
clocking ahb_monitor_cb

)

Monitor modport for the bus signals. The Modport includes the clocking blocks for synchronous sampling. It also includes the signals directly for asynnchronous sampling wherever it is required.

modport svt_ahb_debug_modport

(

output curr_hmaster,
output prev_hmaster,
output curr_sel_slave,
output prev_sel_slave,
output hsplit_bus

)

Debug modport

Clocking blocks

clocking ahb_bus_reset_cb @ ( posedge hclk )
default input #0.01 output #0.01

input hresetn

Clocking block that defines the VIP AHB Bus Interface reset signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge hclk )
default input #0.01 output #0.01

output hmaster_bus,
output hmastlock_bus

Clocking block that defines the VIP AHB Bus Interface bus to all slaves signals synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge hclk )
default input #0.01 output #0.01

input hrdata_bus,
input hready_bus,
input hresp_bus,
input hexokay_bus,
input resp_huser_bus,
input haddr_bus,
input hburst_bus,
input hprot_bus,
input hnonsec_bus,
input hexcl_bus,
input hsize_bus,
input htrans_bus,
input hwdata_bus,
input hwstrb_bus,
input htranschk_bus,
input haddrchk_bus,
input hctrlchk1_bus,
input hctrlchk2_bus,
input hprotchk_bus,
input hwstrbchk_bus,
input hwdatachk_bus,
input control_huserchk_bus,
input hwdata_huserchk_bus,
input hrdata_huserchk_bus,
input resp_huserchk_bus,
input hrdatachk_bus,
input hreadychk_bus,
input hrespchk_bus,
input hwrite_bus,
input control_huser_bus,
input hmaster_bus,
input hmastlock_bus,
input hwdata_huser_bus,
input hrdata_huser_bus

Clocking block that defines the VIP AHB Bus Interface bus to all slaves signals synchronization and directionality.

Functions

virtual AHB_MASTER_IF function

get_master_if (int idx)

void function

set_enable_signal_log ()

string function

get_full_name ()

interface svt_ahb_param_if

(

int SVT_AHB_HADDR_PORT_WIDTH_PARAM,
int SVT_AHB_DATA_WIDTH_PARAM,
int SVT_AHB_CONTROL_HUSER_PORT_WIDTH_PARAM,
int SVT_AHB_HRESP_PORT_WIDTH_PARAM,
int SVT_AHB_HBURST_PORT_WIDTH_PARAM,
int SVT_AHB_HPROT_PORT_WIDTH_PARAM,
int SVT_AHB_HSIZE_PORT_WIDTH_PARAM,
int SVT_AHB_HTRANS_PORT_WIDTH_PARAM,
int SVT_AHB_HMASTER_PORT_WIDTH_PARAM,
int SVT_AHB_HWSTRB_WIDTH_PARAM,
int SVT_AHB_RESP_HUSER_WIDTH_PARAM,
int SVT_AHB_HSPLIT_PORT_WIDTH_PARAM,
int SVT_AHB_DATA_HUSER_PORT_WIDTH_PARAM,
svt_ahb_if ahb_if

)

General description:

AHB VIP provides the SystemVerilog parametrized interface which can be used to connect the VIP to the DUT. A top level parametrized interface svt_ahb_param_if is defined. The top level parametrized interface contains the reset signal, clock signal and the multiplexed signals from the AHB Bus.

Clock signal description:

Signal Name	Signal Description
hclk	This clock signal belongs to the top level AHB Parameterized Interface. User is expected to connect clock signal in testbench to this hclk signal in the top level parametrized interface. This clock is used by all the AHB master and slave VIP components when common clock mode is enabled. This is also used by the system Monitor, bus VIP components.

Clock connection examples:
assign ahb_param_if.hclk = SystemClock;

Reset signal description:

Signal Name	Signal Description
hresetn	This reset signal belongs to the top level AHB Parameterized Interface. User is expected to connect reset signal in testbench to this hresetn signal in the top level parametrized interface. This reset is used by all the AHB master and slave VIP components when common reset mode is enabled. This is also used by the system Monitor, bus VIP components.

Reset connection examples:
assign ahb_param_if.hresetn = SystemResetn;

Parameter description:
The signal width of AHB parameterized interface can be parameterized to match DUT signal widths. The default value of all the parameters are same as the MAX signal widths defined in svt_ahb_port_defines.svi or svt_ahb_user_defines.svi. The parameter values should not exceed the MAX signal width values defined in svt_ahb_port_defines.svi or redefined by user in svt_ahb_user_defines.svi.

Parameter Name	Parameter Description
SVT_AHB_HADDR_PORT_WIDTH_PARAM	Address width (HADDR).
SVT_AHB_DATA_WIDTH_PARAM	Read and Write data width (HRDATA,HWDATA).
SVT_AHB_CONTROL_HUSER_PORT_WIDTH_PARAM	Control user signal width (CONTROL_HUSER).
SVT_AHB_HRESP_PORT_WIDTH_PARAM	Response signal width (HRESP).
SVT_AHB_HBURST_PORT_WIDTH_PARAM	Burst Type signal width (HBURST).
SVT_AHB_HPROT_PORT_WIDTH_PARAM	Protection signal width (HPROT).
SVT_AHB_HSIZE_PORT_WIDTH_PARAM	Burst size signal width (HSIZE).
SVT_AHB_HTRANS_PORT_WIDTH_PARAM	Trans type signal width (HTRANS).
SVT_AHB_HMASTER_PORT_WIDTH_PARAM	hmaster signal width (HMASTER).
SVT_AHB_HSPLIT_PORT_WIDTH_PARAM	hsplit signal width (HSPLIT).

Ports

logic

hclk

logic

hresetn

logic [1:0]

hrdata_bus

logic

hready_bus

logic [-1:0]

hresp_bus

logic

hexokay_bus

logic [-1:0]

resp_huser_bus

logic [-1:0]

haddr_bus

logic [-1:0]

hburst_bus

logic [-1:0]

hprot_bus

logic

hnonsec_bus

logic

hexcl_bus

logic [-1:0]

hsize_bus

logic [-1:0]

htrans_bus

logic [-1:0]

hwdata_bus

logic [-1:0]

hwstrb_bus

logic

hwrite_bus

logic [-1:0]

control_huser_bus

logic [-1:0]

hmaster_bus

logic

hmastlock_bus

logic [-1:0]

hsplit_bus

logic [-1:0]

hwdata_huser_bus

logic [-1:0]

hrdata_huser_bus

interface svt_ahb_master_param_if

(

int SVT_AHB_HADDR_PORT_WIDTH_PARAM,
int SVT_AHB_HMASTER_PORT_WIDTH_PARAM,
int SVT_AHB_HWSTRB_WIDTH_PARAM,
int SVT_AHB_DATA_WIDTH_PARAM,
int SVT_AHB_CONTROL_HUSER_PORT_WIDTH_PARAM,
int SVT_AHB_HBURST_PORT_WIDTH_PARAM,
int SVT_AHB_HPROT_PORT_WIDTH_PARAM,
int SVT_AHB_HSIZE_PORT_WIDTH_PARAM,
int SVT_AHB_HTRANS_PORT_WIDTH_PARAM,
int SVT_AHB_DATA_HUSER_PORT_WIDTH_PARAM,
svt_ahb_master_if master_if

)

General description:

The AHB master parameterized interface svt_ahb_master_param_if defines the AHB signals appropriate for a single AHB master port. Master parameterized interface connects AHB Master VIP to DUT. The width of signals within the parameterized interface can be parameterized to match signal widths of DUT. The default value of all the parameters are same as the MAX signal widths defined in svt_ahb_port_defines.svi or svt_ahb_user_defines.svi. Master parameterized interface works in conjunction with top level parameterized interface svt_ahb_param_if.

Clock signal description:

Signal Name	Signal Description
aclk	If all AHB interfaces in the system are expected to run on a different clock, user can use the hclk signal in the master interfaces. Set the configuration parameter svt_ahb_system_configuration :: common_clock_mode to 0. In this case, connect the hclk signal in each master interface to the appropriate master specific clock in the testbench.

Reset signal description:

Signal Name	Signal Description
aclk	If all AHB interfaces in the system are expected to run on a different reset, user can use the hresetn signal in the master interfaces. Set the configuration parameter svt_ahb_system_configuration :: common_reset_mode to 0. In this case, connect the hresetn signal in each master interface to the appropriate master specific reset in the testbench.

Parameter description:
The signal width of master parameterized interface can be parameterized to match DUT signal widths. The default value of all the parameters are same as the MAX signal widths defined in svt_ahb_port_defines.svi or svt_ahb_user_defines.svi. The parameter values should not exceed the MAX signal width values defined in svt_ahb_port_defines.svi or redefined by user in svt_ahb_user_defines.svi.

Parameter Name	Parameter Description
SVT_AHB_HADDR_PORT_WIDTH_PARAM	Address width (HADDR).
SVT_AHB_DATA_WIDTH_PARAM	Read and Write data width (HRDATA,HWDATA).
SVT_AHB_CONTROL_HUSER_PORT_WIDTH_PARAM	Control user signal width (CONTROL_HUSER).
SVT_AHB_HBURST_PORT_WIDTH_PARAM	Burst Type signal width (HBURST).
SVT_AHB_HPROT_PORT_WIDTH_PARAM	Protection signal width (HPROT).
SVT_AHB_HSIZE_PORT_WIDTH_PARAM	Burst size signal width (HSIZE).
SVT_AHB_HTRANS_PORT_WIDTH_PARAM	Trans type signal width (HTRANS).

AHB signal description:
This sub-interface supports signals for AHB,AHB-Lite. The names of the signals match the names specified in the AHB specification. Please refer to the AHB specification for specific description of any of the signals.

Ports

logic

hclk

logic

hresetn

logic

hgrant

logic [1:0]

haddr

logic [-1:0]

hmaster

logic [-1:0]

hburst

logic

hbusreq

logic

hlock

logic [-1:0]

hprot

logic

hnonsec

logic

hexcl

logic [-1:0]

hsize

logic [-1:0]

htrans

logic [-1:0]

hwdata

logic [-1:0]

hbstrb

logic

hwrite

logic [-1:0]

control_huser

logic [-1:0]

hwdata_huser

interface svt_ahb_slave_param_if

(

int SVT_AHB_DATA_WIDTH_PARAM,
int SVT_AHB_HRESP_PORT_WIDTH_PARAM,
int SVT_AHB_HSPLIT_PORT_WIDTH_PARAM,
int SVT_AHB_DATA_HUSER_PORT_WIDTH_PARAM,
int SVT_AHB_RESP_HUSER_WIDTH_PARAM,
int SVT_AHB_HSEL_PORT_WIDTH_PARAM,
svt_ahb_slave_if slave_if

)

General description:

The AHB Slave parameterized interface svt_ahb_slave_param_if defines the AHB signals appropriate for a single AHB Slave port. Slave parameterized interface connects AHB Slave VIP to DUT. The width of signals within the parameterized interface can be parameterized to match signal widths of DUT. The default value of all the parameters are same as the MAX signal widths defined in svt_ahb_port_defines.svi or svt_ahb_user_defines.svi. Slave parameterized interface works in conjunction with top level parameterized interface svt_ahb_param_if.

Clock signal description:

Signal Name	Signal Description
aclk	If all AHB interfaces in the system are expected to run on a different clock, user can use the hclk signal in the slave interfaces. Set the configuration parameter svt_ahb_system_configuration :: common_clock_mode to 0. In this case, connect the hclk signal in each slave interface to the appropriate slave specific clock in the testbench.

Reset signal description:

Signal Name	Signal Description
aclk	If all AHB interfaces in the system are expected to run on a different reset, user can use the hresetn signal in the slave interfaces. Set the configuration parameter svt_ahb_system_configuration :: common_reset_mode to 0. In this case, connect the hresetn signal in each slave interface to the appropriate slave specific reset in the testbench.

Parameter description:
The signal width of slave parameterized interface can be parameterized to match DUT signal widths. The default value of all the parameters are same as the MAX signal widths defined in svt_ahb_port_defines.svi or svt_ahb_user_defines.svi. The parameter values should not exceed the MAX signal width values defined in svt_ahb_port_defines.svi or redefined by user in svt_ahb_user_defines.svi.

Parameter Name	Parameter Description
SVT_AHB_DATA_WIDTH_PARAM	Read and Write data width (HRDATA,HWDATA).
SVT_AHB_HRESP_PORT_WIDTH_PARAM	Response signal width (HRESP).
SVT_AHB_HSPLIT_PORT_WIDTH_PARAM	hsplit signal width (HSPLIT).

AHB signal description:
This sub-interface supports signals for AHB,AHB-Lite. The names of the signals match the names specified in the AHB specification. Please refer to the AHB specification for specific description of any of the signals.

Ports

logic

hclk

logic

hresetn

logic [0:0]

hrdata

logic [-1:0]

hresp

logic [-1:0]

hsel

logic

hready

logic [-1:0]

hsplit

logic [-1:0]

hrdata_huser

logic [-1:0]

resp_huser

function void
svt_ahb_master_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_ahb_master_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_ahb_master_if signal
input logic common_hclk

interface svt_ahb_master_if signal
input logic common_hresetn

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hrdata_bus

interface svt_ahb_master_if signal
input logic hready_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] hresp_bus

interface svt_ahb_master_if signal
input logic hexokay_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_RESP_USER_WIDTH-1):0] resp_huser_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0] resp_huserchk_bus

interface svt_ahb_master_if signal
input logic hrespchk_bus

interface svt_ahb_master_if signal
input logic hreadychk_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] hrdatachk_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] hrdata_huserchk_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_DATA_USER_WIDTH-1):0] hrdata_huser_bus

bit attribute
svt_ahb_master_if::is_active = 1

logic attribute
svt_ahb_master_if::hclk

User clock In multiple clock mode, user is expected to drive this signal

logic attribute
svt_ahb_master_if::hresetn

User reset In multiple reset mode, user is expected to drive this signal

logic attribute
svt_ahb_master_if::hgrant

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_master_if::hrdata

logic attribute
svt_ahb_master_if::hready

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hresp

logic attribute
svt_ahb_master_if::hexokay

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] attribute
svt_ahb_master_if::haddr

logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hmaster

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hburst

logic attribute
svt_ahb_master_if::hbusreq

logic attribute
svt_ahb_master_if::hexcl

logic attribute
svt_ahb_master_if::hlock

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hprot

logic attribute
svt_ahb_master_if::hnonsec

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hsize

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::htrans

logic [(SVT_AHB_HWSTRB_WIDTH-1):0] attribute
svt_ahb_master_if::hwstrb

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_master_if::hwdata

logic attribute
svt_ahb_master_if::hwrite

logic attribute
svt_ahb_master_if::htranschk

logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0] attribute
svt_ahb_master_if::haddrchk

logic attribute
svt_ahb_master_if::hctrlchk1

logic attribute
svt_ahb_master_if::hctrlchk2

logic attribute
svt_ahb_master_if::hprotchk

logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0] attribute
svt_ahb_master_if::hwstrbchk

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] attribute
svt_ahb_master_if::hwdatachk

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] attribute
svt_ahb_master_if::hrdatachk

logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0] attribute
svt_ahb_master_if::control_huserchk

logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0] attribute
svt_ahb_master_if::resp_huserchk

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] attribute
svt_ahb_master_if::hwdata_huserchk

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] attribute
svt_ahb_master_if::hrdata_huserchk

logic attribute
svt_ahb_master_if::hreadychk

logic attribute
svt_ahb_master_if::hrespchk

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::addr_phase_xact_num

Debug port signals

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::data_phase_xact_num

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::xact_beat_num

logic [SVT_AHB_MAX_USER_WIDTH-1:0] attribute
svt_ahb_master_if::control_huser

AHB sideband signals

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_master_if::hwdata_huser

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_master_if::hrdata_huser

logic [SVT_AHB_MAX_RESP_USER_WIDTH-1:0] attribute
svt_ahb_master_if::resp_huser

string attribute
svt_ahb_master_if::full_name

Full path to this interface or module instance

function void
svt_ahb_slave_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_ahb_slave_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_ahb_slave_if signal
input logic common_hclk

interface svt_ahb_slave_if signal
input logic common_hresetn

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] haddr_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] hburst_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH+SVT_AHB_HMASTER_PORT_WIDTH-1):0] hmaster_bus

interface svt_ahb_slave_if signal
input logic hmastlock_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] hprot_bus

interface svt_ahb_slave_if signal
input logic hnonsec_bus

interface svt_ahb_slave_if signal
input logic hexcl_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] hsize_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] htrans_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HWSTRB_WIDTH-1):0] hwstrb_bus

interface svt_ahb_slave_if signal
input logic htranschk_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0] haddrchk_bus

interface svt_ahb_slave_if signal
input logic hctrlchk1_bus

interface svt_ahb_slave_if signal
input logic hctrlchk2_bus

interface svt_ahb_slave_if signal
input logic hprotchk_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0] hwstrbchk_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] hwdatachk_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0] control_huserchk_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] hwdata_huserchk_bus

interface svt_ahb_slave_if signal
input logic hready_inchk_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hwdata_bus

interface svt_ahb_slave_if signal
input logic hwrite_bus

interface svt_ahb_slave_if signal
input logic hready_bus

interface svt_ahb_slave_if signal
input logic [SVT_AHB_MAX_USER_WIDTH-1:0] control_huser_bus

interface svt_ahb_slave_if signal
input logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] hwdata_huser_bus

bit attribute
svt_ahb_slave_if::is_active = 1

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_slave_if::hrdata

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hresp

logic attribute
svt_ahb_slave_if::hexokay

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] attribute
svt_ahb_slave_if::haddr

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hburst

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hprot

logic attribute
svt_ahb_slave_if::hnonsec

logic attribute
svt_ahb_slave_if::hexcl

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hsize

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::htrans

logic [(SVT_AHB_HWSTRB_WIDTH-1):0] attribute
svt_ahb_slave_if::hwstrb

logic attribute
svt_ahb_slave_if::htranschk

logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0] attribute
svt_ahb_slave_if::haddrchk

logic attribute
svt_ahb_slave_if::hctrlchk1

logic attribute
svt_ahb_slave_if::hctrlchk2

logic attribute
svt_ahb_slave_if::hprotchk

logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0] attribute
svt_ahb_slave_if::hwstrbchk

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] attribute
svt_ahb_slave_if::hwdatachk

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] attribute
svt_ahb_slave_if::hrdatachk

logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0] attribute
svt_ahb_slave_if::control_huserchk

logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0] attribute
svt_ahb_slave_if::resp_huserchk

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] attribute
svt_ahb_slave_if::hwdata_huserchk

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] attribute
svt_ahb_slave_if::hrdata_huserchk

logic attribute
svt_ahb_slave_if::hreadychk

logic attribute
svt_ahb_slave_if::hready_inchk

logic attribute
svt_ahb_slave_if::hselchk

logic attribute
svt_ahb_slave_if::hrespchk

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_slave_if::hwdata

logic attribute
svt_ahb_slave_if::hwrite

logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH+SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hmaster

logic attribute
svt_ahb_slave_if::hmastlock

logic [(SVT_AHB_MAX_HSEL_WIDTH-1):0] attribute
svt_ahb_slave_if::hsel

logic attribute
svt_ahb_slave_if::hready_in

logic attribute
svt_ahb_slave_if::hready

logic [(SVT_AHB_MAX_NUM_MASTERS-1):0] attribute
svt_ahb_slave_if::hsplit

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::addr_phase_xact_num

Debug port signals

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::data_phase_xact_num

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::xact_beat_num

logic [SVT_AHB_MAX_USER_WIDTH-1:0] attribute
svt_ahb_slave_if::control_huser

AHB sideband signals

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_slave_if::hwdata_huser

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_slave_if::hrdata_huser

logic [SVT_AHB_MAX_RESP_USER_WIDTH-1:0] attribute
svt_ahb_slave_if::resp_huser

string attribute
svt_ahb_slave_if::full_name

Full path to this interface or module instance

function virtual AHB_MASTER_IF
svt_ahb_if::get_master_if

( int idx )

function void
svt_ahb_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_ahb_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

logic attribute
svt_ahb_if::hclk

logic attribute
svt_ahb_if::hresetn

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_if::hrdata_bus

Bus: Slave to Master Mux signals

logic attribute
svt_ahb_if::hready_bus

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] attribute
svt_ahb_if::hresp_bus

logic attribute
svt_ahb_if::hexokay_bus

logic [SVT_AHB_MAX_RESP_USER_WIDTH-1:0] attribute
svt_ahb_if::resp_huser_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_if::hrdata_huser_bus

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] attribute
svt_ahb_if::haddr_bus

Bus: Master to Slave Mux signals

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] attribute
svt_ahb_if::hburst_bus

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] attribute
svt_ahb_if::hprot_bus

logic attribute
svt_ahb_if::hnonsec_bus

logic attribute
svt_ahb_if::hexcl_bus

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] attribute
svt_ahb_if::hsize_bus

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] attribute
svt_ahb_if::htrans_bus

logic [(SVT_AHB_HWSTRB_WIDTH-1):0] attribute
svt_ahb_if::hwstrb_bus

logic attribute
svt_ahb_if::htranschk_bus

logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0] attribute
svt_ahb_if::haddrchk_bus

logic attribute
svt_ahb_if::hctrlchk1_bus

logic attribute
svt_ahb_if::hctrlchk2_bus

logic attribute
svt_ahb_if::hprotchk_bus

logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0] attribute
svt_ahb_if::hwstrbchk_bus

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] attribute
svt_ahb_if::hwdatachk_bus

logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] attribute
svt_ahb_if::hrdatachk_bus

logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0] attribute
svt_ahb_if::control_huserchk_bus

logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0] attribute
svt_ahb_if::resp_huserchk_bus

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] attribute
svt_ahb_if::hwdata_huserchk_bus

logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] attribute
svt_ahb_if::hrdata_huserchk_bus

logic attribute
svt_ahb_if::hrespchk_bus

logic attribute
svt_ahb_if::hreadychk_bus

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_if::hwdata_bus

logic attribute
svt_ahb_if::hwrite_bus

logic [SVT_AHB_MAX_USER_WIDTH-1:0] attribute
svt_ahb_if::control_huser_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_if::hwdata_huser_bus

logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH+SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_if::hmaster_bus

Bus: Following signals from bus to slave are common, generated by bus

logic attribute
svt_ahb_if::hmastlock_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_if::curr_hmaster

Debug port signals

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_if::prev_hmaster

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_if::curr_sel_slave

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_if::prev_sel_slave

logic [SVT_AHB_MAX_NUM_MASTERS-1:0] attribute
svt_ahb_if::hsplit_bus

svt_ahb_master_if attribute
svt_ahb_if::master_if

svt_ahb_slave_if attribute
svt_ahb_if::slave_if

string attribute
svt_ahb_if::full_name

Full path to this interface or module instance

interface svt_ahb_param_if signal
int SVT_AHB_HADDR_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_DATA_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_CONTROL_HUSER_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HRESP_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HBURST_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HPROT_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HSIZE_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HTRANS_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HMASTER_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HWSTRB_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_RESP_HUSER_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_HSPLIT_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
int SVT_AHB_DATA_HUSER_PORT_WIDTH_PARAM

interface svt_ahb_param_if signal
svt_ahb_if ahb_if

logic attribute
svt_ahb_param_if::hclk

logic attribute
svt_ahb_param_if::hresetn

logic [1:0] attribute
svt_ahb_param_if::hrdata_bus

Bus: Slave to Master Mux signals

logic attribute
svt_ahb_param_if::hready_bus

logic [-1:0] attribute
svt_ahb_param_if::hresp_bus

logic attribute
svt_ahb_param_if::hexokay_bus

logic [-1:0] attribute
svt_ahb_param_if::resp_huser_bus

logic [-1:0] attribute
svt_ahb_param_if::haddr_bus

Bus: Master to Slave Mux signals

logic [-1:0] attribute
svt_ahb_param_if::hburst_bus

logic [-1:0] attribute
svt_ahb_param_if::hprot_bus

logic attribute
svt_ahb_param_if::hnonsec_bus

logic attribute
svt_ahb_param_if::hexcl_bus

logic [-1:0] attribute
svt_ahb_param_if::hsize_bus

logic [-1:0] attribute
svt_ahb_param_if::htrans_bus

logic [-1:0] attribute
svt_ahb_param_if::hwdata_bus

logic [-1:0] attribute
svt_ahb_param_if::hwstrb_bus

logic attribute
svt_ahb_param_if::hwrite_bus

logic [-1:0] attribute
svt_ahb_param_if::control_huser_bus

logic [-1:0] attribute
svt_ahb_param_if::hmaster_bus

Bus: Following signals from bus to slave are common, generated by bus

logic attribute
svt_ahb_param_if::hmastlock_bus

logic [-1:0] attribute
svt_ahb_param_if::hsplit_bus

logic [-1:0] attribute
svt_ahb_param_if::hwdata_huser_bus

logic [-1:0] attribute
svt_ahb_param_if::hrdata_huser_bus

interface svt_ahb_master_param_if signal
int SVT_AHB_HADDR_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_HMASTER_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_HWSTRB_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_DATA_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_CONTROL_HUSER_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_HBURST_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_HPROT_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_HSIZE_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_HTRANS_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
int SVT_AHB_DATA_HUSER_PORT_WIDTH_PARAM

interface svt_ahb_master_param_if signal
svt_ahb_master_if master_if

logic attribute
svt_ahb_master_param_if::hclk

User clock In multiple clock mode, user is expected to drive this signal

logic attribute
svt_ahb_master_param_if::hresetn

User reset In multiple reset mode, user is expected to drive this signal

logic attribute
svt_ahb_master_param_if::hgrant

logic [1:0] attribute
svt_ahb_master_param_if::haddr

logic [-1:0] attribute
svt_ahb_master_param_if::hmaster

logic [-1:0] attribute
svt_ahb_master_param_if::hburst

logic attribute
svt_ahb_master_param_if::hbusreq

logic attribute
svt_ahb_master_param_if::hlock

logic [-1:0] attribute
svt_ahb_master_param_if::hprot

logic attribute
svt_ahb_master_param_if::hnonsec

logic attribute
svt_ahb_master_param_if::hexcl

logic [-1:0] attribute
svt_ahb_master_param_if::hsize

logic [-1:0] attribute
svt_ahb_master_param_if::htrans

logic [-1:0] attribute
svt_ahb_master_param_if::hwdata

logic [-1:0] attribute
svt_ahb_master_param_if::hbstrb

logic attribute
svt_ahb_master_param_if::hwrite

logic [-1:0] attribute
svt_ahb_master_param_if::control_huser

AHB sideband signals

logic [-1:0] attribute
svt_ahb_master_param_if::hwdata_huser

interface svt_ahb_slave_param_if signal
int SVT_AHB_DATA_WIDTH_PARAM

interface svt_ahb_slave_param_if signal
int SVT_AHB_HRESP_PORT_WIDTH_PARAM

interface svt_ahb_slave_param_if signal
int SVT_AHB_HSPLIT_PORT_WIDTH_PARAM

interface svt_ahb_slave_param_if signal
int SVT_AHB_DATA_HUSER_PORT_WIDTH_PARAM

interface svt_ahb_slave_param_if signal
int SVT_AHB_RESP_HUSER_WIDTH_PARAM

interface svt_ahb_slave_param_if signal
int SVT_AHB_HSEL_PORT_WIDTH_PARAM

interface svt_ahb_slave_param_if signal
svt_ahb_slave_if slave_if

logic attribute
svt_ahb_slave_param_if::hclk

User clock In multiple clock mode, user is expected to drive this signal

logic attribute
svt_ahb_slave_param_if::hresetn

User reset In multiple reset mode, user is expected to drive this signal

logic [0:0] attribute
svt_ahb_slave_param_if::hrdata

logic [-1:0] attribute
svt_ahb_slave_param_if::hresp

logic [-1:0] attribute
svt_ahb_slave_param_if::hsel

logic attribute
svt_ahb_slave_param_if::hready

logic [-1:0] attribute
svt_ahb_slave_param_if::hsplit

logic [-1:0] attribute
svt_ahb_slave_param_if::hrdata_huser

logic [-1:0] attribute
svt_ahb_slave_param_if::resp_huser

VIP Smartsearch

AHB SVT UVM Documentation - Interfaces Reference

Interface Definition Documentation

interface svt_ahb_master_if ( input logic common_hclk, input logic common_hresetn, input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hrdata_bus, input logic hready_bus, input logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] hresp_bus, input logic hexokay_bus, input logic [(SVT_AHB_MAX_RESP_USER_WIDTH-1):0] resp_huser_bus, input logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0] resp_huserchk_bus, input logic hrespchk_bus, input logic hreadychk_bus, input logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0] hrdatachk_bus, input logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0] hrdata_huserchk_bus, input logic [(SVT_AHB_MAX_DATA_USER_WIDTH-1):0] hrdata_huser_bus ) General description: The master interface svt_ahb_master_if defines the AHB signals appropriate for a single port, along with the modports needed for the AHB master and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Ports
bit	is_active
logic	hclk
logic	hresetn
logic	hgrant
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hrdata
logic	hready
logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]	hresp
logic	hexokay
logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]	haddr
logic [(SVT_AHB_EXCL_HMASTER_PORT_WIDTH-1):0]	hmaster
logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]	hburst
logic	hbusreq
logic	hexcl
logic	hlock
logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]	hprot
logic	hnonsec
logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]	hsize
logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]	htrans
logic [(SVT_AHB_HWSTRB_WIDTH-1):0]	hwstrb
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hwdata
logic	hwrite
logic	htranschk
logic [(SVT_AHB_MAX_ADDRCHK_WIDTH-1):0]	haddrchk
logic	hctrlchk1
logic	hctrlchk2
logic	hprotchk
logic [(SVT_AHB_MAX_WSTRBCHK_WIDTH-1):0]	hwstrbchk
logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0]	hwdatachk
logic [(SVT_AHB_MAX_DATACHK_WIDTH-1):0]	hrdatachk
logic [(SVT_AHB_MAX_CTRL_USERCHK_WIDTH-1):0]	control_huserchk
logic [(SVT_AHB_MAX_RESP_USERCHK_WIDTH-1):0]	resp_huserchk
logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0]	hwdata_huserchk
logic [(SVT_AHB_MAX_DATA_USERCHK_WIDTH-1):0]	hrdata_huserchk
logic	hreadychk
logic	hrespchk
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	addr_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	data_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	xact_beat_num
logic [SVT_AHB_MAX_USER_WIDTH-1:0]	control_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hwdata_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hrdata_huser
logic [SVT_AHB_MAX_RESP_USER_WIDTH-1:0]	resp_huser
string	full_name

Modports
modport svt_ahb_master_modport ( input internal_hresetn, clocking ahb_master_cb ) Modport used to connect the VIP Master to AHB interface signals.

modport svt_ahb_bus_modport ( input haddr, input hmaster, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hexcl, input hsize, input htrans, input hwstrb, input htranschk, input haddrchk, input hctrlchk1, input hctrlchk2, input hprotchk, input hwstrbchk, input hwdatachk, input control_huserchk, input hwdata_huserchk, input hwdata, input hwrite, input control_huser, input hwdata_huser, output hgrant, clocking ahb_bus_cb ) Modport used to connect the VIP Bus to AHB master interface signals. The asynchronous signals are required for multiplexing functionality.

modport svt_ahb_monitor_modport ( input internal_hresetn, clocking ahb_monitor_cb ) Modport used to connect the VIP Monitor to AHB interface signals.

modport svt_ahb_master_async_modport ( input hgrant, input hrdata, input hready, input hresp, input hexokay, input resp_huser, input hrdata_huser, output haddr, output hmaster, output hburst, output hbusreq, output hlock, output hprot, output hnonsec, output hexcl, output hsize, output htrans, output hwstrb, output hwdata, output hwrite, output control_huser, output hwdata_huser, input is_active ) Asynchronous modport suitable for SV Master Bind interface

modport svt_ahb_debug_modport ( output addr_phase_xact_num, output data_phase_xact_num, output xact_beat_num ) Modport used to connect the VIP Debug Port.

Clocking blocks
clocking ahb_master_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input hrdata, input hready, input hgrant, input hresp, input hexokay, input resp_huser, input hrdata_huser, output haddr, output hmaster, output hburst, output hbusreq, output hlock, output hprot, output hnonsec, output hexcl, output hsize, output htrans, output hwstrb, output htranschk, output haddrchk, output hctrlchk1, output hctrlchk2, output hprotchk, output hwstrbchk, output hwdatachk, input hrdatachk, input hreadychk, input hrespchk, output control_huserchk, output hwdata_huserchk, input resp_huserchk, input hrdata_huserchk, output hwdata, output hwrite, output control_huser, output hwdata_huser Clocking block that defines VIP AHB Master Interface signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge common_hclk ) default input #0.01 output #0.01 input haddr, input hmaster, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hexcl, input hsize, input htrans, input hwstrb, input htranschk, input haddrchk, input hctrlchk1, input hctrlchk2, input hprotchk, input hwstrbchk, input hwdatachk, input control_huserchk, input hwdata_huserchk, input hwdata, input hwrite, input control_huser, input hwdata_huser, output hgrant Clocking block that defines VIP AHB Bus-Master Interface signal synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input hgrant, input hrdata, input hready, input hresp, input hexokay, input resp_huser, input haddr, input hmaster, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hexcl, input hsize, input htrans, input hwstrb, input htranschk, input haddrchk, input hctrlchk1, input hctrlchk2, input hprotchk, input hwstrbchk, input hwdatachk, input control_huserchk, input hwdata_huserchk, input hrdata_huserchk, input resp_huserchk, input hrdatachk, input hreadychk, input hrespchk, input hwdata, input hwrite, input control_huser, input hwdata_huser, input hrdata_huser Clocking block that defines the AHB Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()