How to download VIP smartsearch?
DESIGNWARE_HOMEto required designware home location where VIP Smartsearch should be downloaded.
vip_smartsearch_<version>.runfile.
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
How to install VIP Smartsearch?
Please refer to the fileVIP_Smartsearch_installation_and_usage_guide.pdfin
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>for installation steps.
Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.Summary of Protocol Checks defined in AHB SVT UVM Documentation:
| Group | Sub Group | Protocol Check Instance name | Reference ▲▼ | Description |
|---|---|---|---|---|
| AHB System | Manager Subordinate Transaction Association | master_slave_xact_resp_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921 | Response signals should match between manager transaction and the corresponding subordinate transaction. |
| AHB System | Manager Subordinate Transaction Association | master_slave_xact_data_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921 | Data values should match between manager transaction and the corresponding subordinate transaction. |
| AHB System | Manager Subordinate Transaction Association | master_slave_xact_addr_ctrl_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921 | Address and control signals should match between manager transaction and the corresponding subordinate transaction. |
| AHB System | Dummy Manager | xact_not_idle_when_dummy_master_active | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus manager | Transfer type of the transaction is not IDLE when dummy manager is active. |
| AHB System | Locked Transfers in Arbiter | hmastlock_changed_during_incr | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked transfers | HMASTLOCK signal changed during INCR burst transfer. |
| AHB System | Locked Transfers in Arbiter | arbiter_asserted_hmastlock_without_hlock | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers | Arbiter asserted HMASTLOCK signal when the manager has not requested. |
| AHB System | Locked Transfers in Arbiter | arbiter_lock_last_grant | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers | Arbiter did not keep manager granted for an additional transfer after a locked sequence. |
| AHB System | Locked Transfers in Arbiter | arbiter_changed_hmaster_during_lock | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers | HMASTER signal changed during locked transfer. |
| AHB System | Granted Manager in Split Transfer in Arbiter | mask_hgrant_until_hsplit_assert | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12.1 Split transfer sequence | Manager should not be regranted until the subordinate is ready to complete the transfer and asserts HSPLIT. |
| AHB System | Granted Manager in Split Transfer in Arbiter | grant_to_default_master_during_allmaster_split | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus master | If all managers has received a SPLIT response then the default manager is granted the bus. |
| AHB System | Granted Manager in Arbiter | arbiter_changed_hmaster_during_wait | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.11.3 Granting bus access | HMASTER signal changed during waited state. |
| AHB System | Granted Manager in Arbiter | arbiter_asserted_hmaster_ne_granted_master | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access | HMASTER signal does not reflect the granted manager. |
| AHB System | Granted Manager in Arbiter | arbiter_asserted_multi_hgrant | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access | Arbiter asserted more than one HGRANT signal. |
| AHB System | Subordinate Selection in Decoder | decoder_not_asserted_any_hsel | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals | Decoder not asserted any HSEL signal. |
| AHB System | Subordinate Selection in Decoder | decoder_asserted_multi_hsel | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals | Decoder asserted more than one HSEL signal. |
| AHB System | Data Integrity | data_integrity_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921 | Transaction data inconsistent with subordinate memory. |
| AHB System | Routing | slave_transaction_routing_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.1 Interconnect | Transaction not routed to the correct subordinate based on system address map. |
| AHB_COMMON | Address Phase Timing | ahb_address_phase_extended | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 1.3 Operation | A Subordinate cannot request that the address phase is extended. |
| AHB_COMMON | During Reset | hready_out_from_bus_high_during_reset | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset | During reset, HREADY output from bus must be HIGH |
| AHB_COMMON | Performance Metrics | perf_min_write_throughput | SYNOPSYS DEFINED | Checks that the throughput of write transactions in a given interval is more than or equal to the configured min value |
| AHB_COMMON | Performance Metrics | perf_max_write_throughput | SYNOPSYS DEFINED | Checks that the throughput of write transactions in a given interval is less than or equal to the configured max value |
| AHB_COMMON | Performance Metrics | perf_min_read_throughput | SYNOPSYS DEFINED | Checks that the throughput of read transactions in a given interval is more than or equal to the configured min value |
| AHB_COMMON | Performance Metrics | perf_max_read_throughput | SYNOPSYS DEFINED | Checks that the throughput of read transactions in a given interval is less than or equal to the configured max value |
| AHB_COMMON | Performance Metrics | perf_avg_min_read_xact_latency | SYNOPSYS DEFINED | Checks that the average latency of read transactions in a given interval is more than or equal to the configured min value |
| AHB_COMMON | Performance Metrics | perf_avg_max_read_xact_latency | SYNOPSYS DEFINED | Checks that the average latency of read transactions in a given interval is less than or equal to the configured max value |
| AHB_COMMON | Performance Metrics | perf_min_read_xact_latency | SYNOPSYS DEFINED | Checks that the latency of a read transaction is more than or equal to the configured min value |
| AHB_COMMON | Performance Metrics | perf_max_read_xact_latency | SYNOPSYS DEFINED | Checks that the latency of a read transaction is less than or equal to the configured max value |
| AHB_COMMON | Performance Metrics | perf_avg_min_write_xact_latency | SYNOPSYS DEFINED | Checks that the average latency of write transactions in a given interval is more than or equal to the configured min value |
| AHB_COMMON | Performance Metrics | perf_avg_max_write_xact_latency | SYNOPSYS DEFINED | Checks that the average latency of write transactions in a given interval is less than or equal to the configured max value |
| AHB_COMMON | Performance Metrics | perf_min_write_xact_latency | SYNOPSYS DEFINED | Checks that the latency of a write transaction is more than or equal to the configured min value |
| AHB_COMMON | Performance Metrics | perf_max_write_xact_latency | SYNOPSYS DEFINED | Checks that the latency of a write transaction is less than or equal to the configured max value |
| AHB_COMMON | Signal Parity | ahb5_hrdatachk_parity_calculated_hrdata_parity_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921 | ahb5_hrdatachk received_parity_calculated_parity_check |
| AHB_COMMON | Signal Parity | ahb5_hwdatachk_parity_calculated_hwdata_parity_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921 | ahb5_hwdatachk received_parity_calculated_parity_check |
| AHB_COMMON | Signal Parity | ahb5_received_parity_calculated_parity_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921 | ahb5_received_parity_calculated_parity_check |
| AHB_COMMON | Signal Validity | signal_valid_hrdata_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HRDATA must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_hwdata_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HWDATA must not be X/Z |
| AHB_COMMON | Response Type | zero_wait_cycle_okay | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types | IDLE and BUSY transfers must receive zero wait cycle OKAY response. |
| AHB_COMMON | Two Cycle Response | two_cycle_error_resp | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response | ERROR response was not completed in two cycles. |
| AHB_COMMON | Response Type | non_okay_response_in_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.2 Transfer pending | Response other than OKAY response was received during wait state. |
| AHB_COMMON | Signal Validity | signal_valid_hresp_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HRESP must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_hready_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HREADY must not be X/Z |
| AHB_COMMON | Burst Length | burst_length_exceeded | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation | Burst length exceeded for fixed length burst. |
| AHB_COMMON | Locked Transfers | hlock_asserted_during_non_locked_xact | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.1 Signal description | Manager should not assert lock signal in the middle of a non-locked transaction. |
| AHB_COMMON | Signal Validity | signal_valid_hlock_check | AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list | HLOCK must not be X/Z |
| AHB_COMMON | Locked Transfers | different_subordinate_addr_region_during_locked_sequence | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked Transfers | It is required that all transfers in a locked sequence are to the same Subordinate address region. |
| AHB_COMMON | Transfer Type | htrans_not_changed_to_idle_during_error | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response | HTRANS did not change to IDLE during ERROR response. |
| AHB_COMMON | During Reset | htrans_idle_during_reset | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset | During reset, HTRANS must be IDLE2'b00 |
| AHB_COMMON | Transfer Type | seq_or_busy_before_nseq_during_xfer | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types | Manager started burst with SEQ or BUSY instead of NSEQ. |
| AHB_COMMON | Transfer Type | illegal_idle2seq | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types | Manager attempted SEQ transfer following IDLE. |
| AHB_COMMON | Transfer Type | illegal_idle2busy | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types | Manager attempted BUSY transfer following IDLE. |
| AHB_COMMON | Transfer Type | idle_changed_to_busy_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | Manager cancelled IDLE transfer during wait state and changed it to BUSY transfer. |
| AHB_COMMON | Transfer Type | idle_changed_to_seq_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | Manager cancelled IDLE transfer during wait state and changed it to SEQ transfer. |
| AHB_COMMON | Signal Stability | ctrl_or_addr_changed_during_busy | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types | Control signalsother than HTRANS or address changed during BUSY. |
| AHB_COMMON | Signal Stability | illegal_control_transition | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals | Control signals other than HTRANS changed during burst. |
| AHB_COMMON | Burst Address | ahb_valid_beat_address_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation | valid beat address check. |
| AHB_COMMON | Burst Address | illegal_address_transition | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation | Illegal address transition during burst. |
| AHB_COMMON | Burst Address | boundry_crossing_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation | Burst transfer crossed boundary |
| AHB_COMMON | Burst Address | one_k_boundry_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation | Burst transfer crossed 1 KB boundary. |
| AHB_COMMON | Transfer Size | hsize_too_big_for_data_width | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.3.3 Implementing a Manager on a wide bus | Manager attempted transfer size greater than data bus width. |
| AHB_COMMON | Early Burst Termination | burst_terminated_early_after_okay | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination | Manager terminated burst early after OKAY response. |
| AHB_COMMON | Signal Stability | hwdata_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.1.1 HWDATA | HWDATA changed during wait state. |
| AHB_COMMON | Signal Stability | ctrl_or_addr_changed_end_of_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | Control or address changed at the end of wait state. |
| AHB_COMMON | Signal Stability | ctrl_or_addr_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | Control or address changed during wait state. |
| AHB_COMMON | Signal Stability | htrans_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | HTRANS changed during wait state. |
| AHB_COMMON | Transfer Type | seq_or_busy_during_active_xact | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types | In active transaction, SEQ or BUSY transfer should only occur after NSEQ. |
| AHB_COMMON | Transfer Type | trans_during_single_is_nseq | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types | Transfer type of a SINGLE burst is not NSEQ |
| AHB_COMMON | Signal Validity | signal_valid_hprot_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HPROT must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_hburst_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HBURST must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_hsize_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HSIZE must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_htrans_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HTRANS must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_hwrite_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HWRITE must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_haddr_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HADDR must not be X/Z |
| AHB_COMMON | Signal Validity | hready_out_from_slave_not_X_or_Z_when_data_phase_not_pending | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.3 Subordinate signals | HREADY output from subordinate must be either HIGH or LOW when there is no pending data phase. |
| AHB_COMMON | During Reset | hready_out_from_slave_not_X_or_Z_during_reset | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset | During reset, HREADY output from subordinate must be either HIGH or LOW |
| AHB_COMMON | Response Type | illegal_default_slave_resp_to_nseq_seq | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.1 Default Subordinate | Default subordinate should provide ERROR response for NON_SEQ or SEQ transfer. |
| AHB_COMMON | Subordinate Selection | invalid_hsel_assert_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.2 Multiple Subordinate select | Invalid HSEL signal asserted for selected subordinate |
| AHB_COMMON | Signal Validity | signal_valid_hready_in_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HREADY_IN must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_hmastlock_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HMASTLOCK must not be X/Z |
| AHB_COMMON | Signal Validity | signal_valid_hmaster_range_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals | HMASTER should not be beyond SVT_AHB_MAX_NUM_MASTERS |
| AHB_COMMON | Signal Validity | signal_valid_hsel_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HSEL must not be X/Z |
| AHB5 User Signaling | Signal Validity | ahb5_signal_valid_hrdata_huser_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | hrdata_huser/HRUSER must not be X/Z |
| AHB5 User Signaling | Signal Validity | ahb5_signal_valid_hwdata_huser_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | hwdata_huser/HWUSER must not be X/Z |
| AHB5 User Signaling | Signal Validity | ahb5_signal_valid_resp_huser_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | resp_huser/HBUSER must not be X/Z |
| AHB5 User Signaling | Signal Stability | ahb5_hwdata_huser_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 11.2 User signal interconnect recommendations | hwdata_huser/HWUSER changed during wait state. |
| AHB5 User Signaling | Signal Validity | ahb5_signal_valid_control_huser_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | control_huser/HAUSER must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hrdata_huserchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | hrdata_huserchk/HRUSERCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hrdatachk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HRDATACHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_resp_huserchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | resp_huserchk/HBUSERCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hrespchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HRESPCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hreadychk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HREADYCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_hwdata_huserchk_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 11.2 User signal interconnect recommendations | hwdata_huserchk/HWUSERCHK changed during wait state. |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_hwstrbchk_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.5 Write strobes | HWSTRBCHK changed during wait state. |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_hwdatachk_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.1.1 HWDATA | HWDATACHK changed during wait state. |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_ctrl_or_addr_phase_parity_check_signals_changed_during_busy | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | Control or address related parity check signals changed during wait state. |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_ctrl_or_addr_phase_parity_check_signals_changed_end_of_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | Control or address related parity check signals changed during wait state. |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_ctrl_or_addr_phase_parity_check_signals_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | Control or address related parity check signals changed during wait state. |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_illegal_control_parity_check_signals_transition | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals | Control parity check signals other than HTRANSCHK changed during burst. |
| AHB5 Interface Parity Signals | Signal Stability | ahb5_htranschk_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers | HTRANSCHK changed during wait state. |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_control_huserchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | control_huserchk/HAUSERCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hwdata_huserchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | hwdata_huserchk/HWUSERCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hwdatachk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HWDATACHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hwstrbchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HWSTRBCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hprotchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HPROTCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hctrlchk2_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HCTRLCHK2 must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hctrlchk1_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HCTRLCHK1 must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_haddrchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HADDRCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_htranschk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HTRANSCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hready_inchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HREADY_INCHK must not be X/Z |
| AHB5 Interface Parity Signals | Signal Validity | ahb5_signal_valid_hselchk_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 12.5 Parity check signals | HSELCHK must not be X/Z |
| AHB5 Exclusive Transfers | Exclusive Response Signaling | ahb5_hexokay_asserted_when_hresp_asserted | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.3.1 Exclusive access response signaling | HEXOKAY must not be asserted in the same cycle as HRESP is asserted |
| AHB5 Exclusive Transfers | Exclusive Response Signaling | ahb5_hexokay_asserted_without_hready_asserted | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.3.1 Exclusive access response signaling | HEXOKAY must only be asserted in the same cycle as HREADY is asserted |
| AHB5 Exclusive Transfers | Signal Validity | signal_valid_hexokay_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HEXOKAY must not be X/Z |
| AHB5 Exclusive Transfers | Outstanding Exclusive Transfers | ahb5_outstanding_exclusive_xact_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that a manager is not staring a new exclusive transaction while there is an outstanding exclusive transaction pending. |
| AHB5 Exclusive Transfers | Outstanding Exclusive Transfers | ahb5_exclusive_xact_overlap_with_another_exclusive_sequence_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that a manager must not permit an Exclusive read transaction to be in progress at the same time as any transaction that registers that it is performing an Exclusive sequence |
| AHB5 Exclusive Transfers | Exclusive Access Pair | ahb5_exclusive_read_write_no_busy_transfer_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that no busy transfers is generated same for exclusive accesss READ and WRITE transactions. |
| AHB5 Exclusive Transfers | Exclusive Access Pair | ahb5_exclusive_read_write_prot_type_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that prot type is generated same for exclusive accesss READ and WRITE transactions. |
| AHB5 Exclusive Transfers | Exclusive Access Pair | ahb5_exclusive_read_write_burst_type_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that burst type is generated same for exclusive accesss READ and WRITE transactions. |
| AHB5 Exclusive Transfers | Exclusive Access Pair | ahb5_exclusive_read_write_burst_size_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that burst size is generated same for exclusive accesss READ and WRITE transactions. |
| AHB5 Exclusive Transfers | Exclusive Access Pair | ahb5_exclusive_read_write_burst_length_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that burst length is generated same for exclusive accesss READ and WRITE transactions. |
| AHB5 Exclusive Transfers | Exclusive Access Pair | ahb5_exclusive_read_write_id_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that the bits of the HMASTER signal that are used to identify the Exclusive-capable thread must be the same for all Exclusive transactions from the same Exclusive-capable thread. In other words, it checks that same exclusive thread is used for exclusive access READ and WRITE transactions |
| AHB5 Exclusive Transfers | Exclusive Access Pair | ahb5_exclusive_read_write_addr_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.4 Exclusive Transfer restrictions | Checks that address is generated same for exclusive accesss READ and WRITE transactions |
| AHB5 Exclusive Transfers | Signal Validity | signal_valid_hexcl_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HEXCL must not be X/Z |
| AHB5 Exclusive Transfers | Exclusive Response Signaling | ahb5_exclusive_write_response_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.3.1 Exclusive access response signaling | Checks that response generated for exclusive write accesss is correct |
| AHB5 Exclusive Transfers | Exclusive Response Signaling | ahb5_exclusive_read_response_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 10.3.1 Exclusive access response signaling | Checks that response generated for exclusive read accesss is correct |
| AHB_FULL | Two Cycle Response | two_cycle_retry_resp | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response | RETRY response was not completed in two cycles. |
| AHB_FULL | Two Cycle Response | two_cycle_split_resp | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response | SPLIT response was not completed in two cycles. |
| AHB_FULL | Transfer Type | htrans_not_idle_or_nseq_during_no_grant | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access | Manager should drive HTRANS to IDLE or NSEQ when it does not have access to the bus. |
| AHB_FULL | Transfer Type | htrans_not_changed_to_idle_during_retry | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response | HTRANS did not change to IDLE during RETRY response. |
| AHB_FULL | Transfer Type | htrans_not_changed_to_idle_during_split | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response | HTRANS did not change to IDLE during SPLIT response. |
| AHB_FULL | Signal Validity | signal_valid_hbusreq_check | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access | HBUSREQ must not be X/Z |
| AHB_FULL | Rebuild Transaction | rebuild_xact_with_valid_combination_of_bursts | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry | Manager should restart an interrupted burst with a valid combination of bursts. |
| AHB_FULL | Rebuild Transaction | rebuild_xact_with_expected_addr | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry | Manager should restart an interrupted burst from the address of the aborted beat. |
| AHB_FULL | Response Type | hsplit_asserted_for_non_split_master | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers | Subordinate should not assert HSPLIT corresponding to a manager it has not split earlier. |
| AHB_FULL | Response Type | hsplit_asserted_for_one_cycle | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers | Subordinate should assert a bit of HSPLIT only for one clock cycle |
| AHB_FULL | Transfer Type | htrans_not_changed_to_idle_during_retry | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response | HTRANS did not change to IDLE during RETRY response. |
| AHB_FULL | Transfer Type | htrans_not_changed_to_idle_during_split | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response | HTRANS did not change to IDLE during SPLIT response. |
| AHB_FULL | Bus Grant | illegal_hgrant_on_split_resp | AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers | Manager should lose the bus once it gets the split response from the subordinate. |
| AHB_FULL | Signal Validity | signal_valid_hgrant_check | AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list | HGRANT must not be X/Z |
| AHB_FULL | Signal Validity | signal_valid_hmaster_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HMASTER must not be X/Z |
| AHB_Lite | Response Type | ahb_lite_split_response | AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses | SPLIT response was received when configured as AHB Lite system. |
| AHB_Lite | Response Type | ahb_lite_retry_response | AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses | RETRY response was received when configured as AHB Lite system. |
| ARM11/AHB_V6 Exclusive Accesses | Two Cycle Response | two_cycle_xfail_resp | ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.3.1 Exclusive Access Protocol | XFAIL response was not completed in two cycles. |
| ARM11/AHB_V6 Unaligned Transfers | Valid Unaligned Transfer | valid_unaligned_transfer | ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1.2 Burst, Unaligned accesses and Byte Lane Strobes | HUNALIGN should be asserted for an unaligned transfer |
| ARM11/AHB_V6 Unaligned Transfers | Signal Stability | hunalign_changed_during_transfer | ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes | HUNALIGN should not change in middle of a transfer |
| ARM11/AHB_V6 Unaligned Transfers | Valid Byte Lane Strobes | valid_byte_lane_for_hbstrb | ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes | HRDATA/HWDATA byte lanes corresponding to HBSTRB should be selected |
| ARM11/AHB_V6 Unaligned Transfers | Signal Validity | signal_valid_hunalign_check | ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes | HUNALIGN must not be X/Z |
| ARM11/AHB_V6 Unaligned Transfers | Signal Validity | signal_valid_hbstrb_check | ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes | HBSTRB must not be X/Z |
| AHB5 Write Strobes | Signal Stability | ahb5_hwstrb_changed_during_wait_state | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.5 Write strobes | HWSTRB changed during wait state. |
| AHB5 Write Strobes | Signal Validity | ahb5_signal_valid_hwstrb_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HWSTRB must not be X/Z |
| AHB5 Extended Memory Types | Signal Validity | signal_valid_hprot_ex_range_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.9 Memory types | HPROT signal is not having the valid value |
| AHB5 Secure Transfers | Signal Validity | signal_valid_hnonsec_check | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules | HNONSEC must not be X/Z |
| AHB_Lite_Multilayer | Rebuild Transaction | rebuild_xact_with_valid_combination_of_bursts | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination | Manager should restart an interrupted burst with a valid combination of bursts. |
| AHB_Lite_Multilayer | Rebuild Transaction | rebuild_xact_with_expected_addr | AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination | Manager should restart an interrupted burst from the address of the aborted beat. |