AMBA SVT OVM Documentation - Interfaces Reference

Product	Interface Group	Interfaces
amba_svt	AXI Master interface. This is a sub-interface of svt_axi_if.	svt_axi_master_if
Default Group	svt_axi_lp_if
svt_ahb_master_if
svt_ahb_slave_if
svt_ahb_if	svt_ahb_slave_if, svt_ahb_master_if
svt_apb_slave_if
svt_apb_if	svt_apb_slave_if
AXI Slave interface. This is a sub-interface of svt_axi_if.	svt_axi_slave_if
Top Level interface for AXI VIP components within CHI VIP. This is a sub-interface of svt_chi_if.	svt_axi_if	svt_axi_slave_if, svt_axi_lp_if, svt_axi_master_if

interface svt_axi_slave_if

(

)

General description:

The slave interface svt_axi_slave_if defines the AXI signals appropriate for a single port, along with the modports needed for the AXI slave and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Clock signal description:

Signal Name	Signal Description
aclk	If all AXI interfaces in the system are expected to run on a different clock, user can use the aclk signal in the port interfaces. Set the configuration parameter svt_axi_system_configuration :: common_clock_mode to 0. In this case, connect the aclk signal in each port interface to the appropriate port specific clock in the testbench.

Debug port description:
In active and passive mode, the VIP assigns a unique number to each transaction. This number is also displayed in the messages issued by the VIP. The debug port reflects this unique transaction number. This makes it easy to fnd a particular transaction on the waveforms, by looking at the debug port signals. For example, if messages mentions that there is a error on transaction #100, used can jump to value #100 on debug port signals, to find the transaction. A seperate debug port is provided for each AXI channel, so that you can jump to the address phase, data phase or response phase of a given transaction, for example transaction #100.

Signal Name	Signal Description
read_addr_xact_num	Transaction number on read address channel. Used in active mode.
read_data_xact_num	Transaction number on read data channel. Used in active mode.
read_data_xfer_id	Data transfer number on read data channel. Used in active mode.
write_addr_xact_num	Transaction number on write address channel. Used in active mode.
write_data_xact_num	Transaction number on write data channel. Used in active mode.
write_data_xfer_id	Data transfer number on write data channel. Used in active mode.
write_resp_xact_num	Transaction number on write response channel. Used in active mode.
snoop_addr_xact_num	Transaction number on snoop address channel. Used in active mode.
snoop_data_xact_num	Transaction number on snoop data channel. Used in active mode.
snoop_data_xfer_id	Data transfer number on snoop data channel. Used in active mode.
snoop_resp_xact_num	Transaction number on snoop response channel. Used in active mode.
mon_read_addr_xact_num	Transaction number on read address channel. Used in passive mode.
mon_read_data_xact_num	Transaction number on read data channel. Used in passive mode.
mon_read_data_xfer_id	Data transfer number on read data channel. Used in passive mode.
mon_write_addr_xact_num	Transaction number on write address channel. Used in passive mode.
mon_write_data_xact_num	Transaction number on write data channel. Used in passive mode.
mon_write_data_xfer_id	Data transfer number on write data channel. Used in passive mode.
mon_write_resp_xact_num	Transaction number on write response channel. Used in passive mode.
mon_snoop_addr_xact_num	Transaction number on snoop address channel. Used in passive mode.
mon_snoop_data_xact_num	Transaction number on snoop data channel. Used in passive mode.
mon_snoop_data_xfer_id	Data transfer number on snoop data channel. Used in passive mode.
mon_snoop_resp_xact_num	Transaction number on snoop response channel. Used in passive mode.

AXI signal description:
This sub-interface supports signals for AXI3, AXI4, ACE and AXI4 Stream protocols. The names of the signals match the names specified in the AXI specification. Please refer to the AXI specification for specific description of any of the signals.

Ports

bit

is_active

bit

common_clock_mode

bit

clock_enable

logic

aclk

logic

aresetn

logic

awvalid

logic [SVT_AXI_MAX_ADDR_WIDTH-1:0]

awaddr

logic [SVT_AXI_MAX_BURST_LENGTH_WIDTH-1:0]

awlen

logic [SVT_AXI_SIZE_WIDTH-1:0]

awsize

logic [SVT_AXI_BURST_WIDTH-1:0]

awburst

logic [SVT_AXI_LOCK_WIDTH-1:0]

awlock

logic [SVT_AXI_CACHE_WIDTH-1:0]

awcache

logic [SVT_AXI_PROT_WIDTH-1:0]

awprot

logic [SVT_AXI_MAX_ID_WIDTH-1:0]

awid

logic

awready

logic

awidunq

logic [SVT_AXI_MAX_LOOP_W_WIDTH-1:0]

awloop

logic [SVT_AXI_MAX_NSAID_WIDTH-1:0]

awnsaid

logic [SVT_AXI_ACE_DOMAIN_WIDTH-1:0]

awdomain

logic [SVT_AXI_ACE_WSNOOP_WIDTH-1:0]

awsnoop

logic [SVT_AXI_ACE_WCMO_WIDTH-1:0]

awcmo

logic [SVT_AXI_ACE_BARRIER_WIDTH-1:0]

awbar

logic

awunique

logic [SVT_AXI_STASH_NID_WIDTH-1:0]

awstashnid

logic [SVT_AXI_STASH_LPID_WIDTH-1:0]

awstashlpid

logic

awstashnid_en

logic

awstashlpid_en

logic

awtrace

logic [SVT_AXI_MAX_MMUSECSID_WIDTH-1:0]

awmmusecsid

logic [SVT_AXI_MAX_MMUSID_WIDTH-1:0]

awmmusid

logic

awmmussidv

logic [SVT_AXI_MAX_MMUSSID_WIDTH-1:0]

awmmussid

logic

awmmuatst

logic [SVT_ACE5_ATOMIC_TYPE_WIDTH-1:0]

awatop

logic [SVT_AXI_MAX_MPAM_WIDTH-1:0]

awmpam

logic [SVT_AXI_TAGOP_WIDTH-1:0]

awtagop

logic

awvalidchk

logic

awreadychk

logic [1:0]

awidchk

logic [7:0]

awaddrchk

logic

awlenchk

logic

awctlchk0

logic

awctlchk1

logic

awctlchk2

logic

awctlchk3

logic

awnsaidchk

logic

awstashnidchk

logic

awstashlpidchk

logic

awmmuchk

logic

awloopchk

logic

awtracechk

logic

awmpamchk

logic [3:0]

awmmusidchk

logic [5:0]

awmmussidchk

logic

arvalid

logic [SVT_AXI_MAX_ADDR_WIDTH-1:0]

araddr

logic [SVT_AXI_MAX_BURST_LENGTH_WIDTH-1:0]

arlen

logic [SVT_AXI_SIZE_WIDTH-1:0]

arsize

logic [SVT_AXI_BURST_WIDTH-1:0]

arburst

logic [SVT_AXI_LOCK_WIDTH-1:0]

arlock

logic [SVT_AXI_CACHE_WIDTH-1:0]

arcache

logic [SVT_AXI_PROT_WIDTH-1:0]

arprot

logic [SVT_AXI_MAX_ID_WIDTH-1:0]

arid

logic

arready

logic

aridunq

logic [SVT_AXI_MAX_LOOP_R_WIDTH-1:0]

arloop

logic [SVT_AXI_MAX_NSAID_WIDTH-1:0]

arnsaid

logic [SVT_AXI_MAX_VMIDEXT_WIDTH-1:0]

arvmidext

logic [SVT_AXI_TAGOP_WIDTH-1:0]

artagop

logic [SVT_AXI_ACE_DOMAIN_WIDTH-1:0]

ardomain

logic [SVT_AXI_ACE_RSNOOP_WIDTH-1:0]

arsnoop

logic [SVT_AXI_ACE_BARRIER_WIDTH-1:0]

arbar

logic

artrace

logic [SVT_AXI_MAX_MMUSECSID_WIDTH-1:0]

armmusecsid

logic [SVT_AXI_MAX_MMUSID_WIDTH-1:0]

armmusid

logic

armmussidv

logic [SVT_AXI_MAX_MMUSSID_WIDTH-1:0]

armmussid

logic

armmuatst

logic [SVT_AXI_MAX_MPAM_WIDTH-1:0]

armpam

logic

arvalidchk

logic

arreadychk

logic [1:0]

aridchk

logic [7:0]

araddrchk

logic

arlenchk

logic

arctlchk0

logic

arctlchk1

logic

arctlchk2

logic

arctlchk3

logic

arnsaidchk

logic

armmuchk

logic

arloopchk

logic

artracechk

logic

armpamchk

logic [3:0]

armmusidchk

logic [5:0]

armmussidchk

logic

rvalid

logic

rlast

logic [SVT_AXI_MAX_DATA_WIDTH-1:0]

rdata

logic [SVT_AXI_RESP_WIDTH-1:0]

rresp

logic [SVT_AXI_MAX_ID_WIDTH-1:0]

rid

logic

rready

logic

rack

logic

rackchk

logic [SVT_AXI_MAX_LOOP_R_WIDTH-1:0]

rloop

logic [(SVT_AXI_MAX_DATA_WIDTH/8)-1:0]

rdatachk

logic [1:0]

rpoisonchk

logic

rtrace

logic [SVT_AXI_MAX_DATA_WIDTH/64-1:0]

rpoison

logic [SVT_AXI_MAX_TAG_WIDTH-1:0]

rtag

logic

ridunq

logic

rvalidchk

logic

rreadychk

logic [1:0]

ridchk

logic

rrespchk

logic

rlastchk

logic

rtracechk

logic

rloopchk

logic

rchunkchk

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0]

rtagchk

logic

wvalid

logic

wlast

logic [SVT_AXI_MAX_DATA_WIDTH-1:0]

wdata

logic [SVT_AXI_MAX_DATA_WIDTH/8-1:0]

wstrb

logic [SVT_AXI_MAX_ID_WIDTH-1:0]

wid

logic

wready

logic [(SVT_AXI_MAX_DATA_WIDTH/8)-1:0]

wdatachk

logic

wtrace

logic [SVT_AXI_MAX_DATA_WIDTH/64-1:0]

wpoison

logic [SVT_AXI_MAX_TAG_WIDTH-1:0]

wtag

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0]

wtagupdate

logic

wvalidchk

logic

wreadychk

logic [15:0]

wstrbchk

logic [1:0]

wpoisonchk

logic

wlastchk

logic

wtracechk

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0]

wtagchk

logic

bvalid

logic [SVT_AXI_RESP_WIDTH-1:0]

bresp

logic [SVT_AXI_MAX_ID_WIDTH-1:0]

bid

logic

bready

logic [SVT_AXI_MAX_LOOP_W_WIDTH-1:0]

bloop

logic

bvalidchk

logic

breadychk

logic [1:0]

bidchk

logic

brespchk

logic

btracechk

logic

bloopchk

logic

bidunq

logic

wack

logic

wackchk

logic

btrace

logic

awakeup

logic

awakeupchk

logic [SVT_AXI_MAX_TAG_MATCH_RESP_WIDTH-1:0]

btagmatch

logic

bcomp

logic

bpersist

logic [SVT_AXI_REGION_WIDTH-1:0]

awregion

logic [SVT_AXI_QOS_WIDTH-1:0]

awqos

logic [SVT_AXI_MAX_ADDR_USER_WIDTH-1:0]

awuser

logic [SVT_AXI_REGION_WIDTH-1:0]

arregion

logic [SVT_AXI_QOS_WIDTH-1:0]

arqos

logic [SVT_AXI_MAX_ADDR_USER_WIDTH-1:0]

aruser

logic [SVT_AXI_MAX_DATA_USER_WIDTH-1:0]

wuser

logic [SVT_AXI_MAX_DATA_USER_WIDTH-1:0]

ruser

logic [SVT_AXI_MAX_BRESP_USER_WIDTH-1:0]

buser

logic [3:0]

awuserchk

logic [0:0]

wuserchk

logic [3:0]

buserchk

logic [3:0]

aruserchk

logic [0:0]

ruserchk

logic

acvalid

logic

acwakeup

logic

acready

logic [SVT_AXI_ACE_SNOOP_ADDR_WIDTH-1:0]

acaddr

logic [SVT_AXI_ACE_SNOOP_TYPE_WIDTH-1:0]

acsnoop

logic [SVT_AXI_ACE_SNOOP_PROT_WIDTH-1:0]

acprot

logic [SVT_AXI_MAX_VMIDEXT_WIDTH-1:0]

acvmidext

logic

actrace

logic

acvalidchk

logic

acreadychk

logic [7:0]

acaddrchk

logic

acctlchk

logic

acvmidextchk

logic

actracechk

logic

acwakeupchk

logic

crvalid

logic

crready

logic [SVT_AXI_ACE_SNOOP_RESP_WIDTH-1:0]

crresp

logic

crtrace

logic

crreadychk

logic

crvalidchk

logic

crrespchk

logic

crtracechk

logic

cdvalid

logic

cdready

logic [SVT_AXI_ACE_SNOOP_DATA_WIDTH-1:0]

cddata

logic

cdlast

logic [SVT_AXI_ACE_SNOOP_DATA_WIDTH/64-1:0]

cdpoison

logic

cdtrace

logic [127:0]

cddatachk

logic

cdlastchk

logic [1:0]

cdpoisonchk

logic

cdtracechk

logic

cdreadychk

logic

cdvalidchk

logic

tvalid

logic

tready

logic [SVT_AXI_MAX_TDATA_WIDTH-1:0]

tdata

logic [SVT_AXI_TSTRB_WIDTH-1:0]

tstrb

logic [SVT_AXI_MAX_TDEST_WIDTH-1:0]

tdest

logic [SVT_AXI_TKEEP_WIDTH-1:0]

tkeep

logic

tlast

logic [SVT_AXI_MAX_TID_WIDTH-1:0]

tid

logic [SVT_AXI_MAX_TUSER_WIDTH-1:0]

tuser

logic

archunken

logic

rchunkv

logic [SVT_AXI_MAX_CHUNK_NUM_WIDTH-1:0]

rchunknum

logic [SVT_AXI_MAX_CHUNK_STROBE_WIDTH-1:0]

rchunkstrb

logic [31:0]

read_addr_xact_num

logic [31:0]

read_data_xact_num

logic [31:0]

read_data_xfer_id

logic [31:0]

write_addr_xact_num

logic [31:0]

write_data_xact_num

logic [31:0]

write_data_xfer_id

logic [31:0]

write_resp_xact_num

logic [31:0]

snoop_addr_xact_num

logic [31:0]

snoop_data_xact_num

logic [31:0]

snoop_data_xfer_id

logic [31:0]

snoop_resp_xact_num

logic [31:0]

mon_read_addr_xact_num

logic [31:0]

mon_read_data_xact_num

logic [31:0]

mon_read_data_xfer_id

logic [31:0]

mon_write_addr_xact_num

logic [31:0]

mon_write_data_xact_num

logic [31:0]

mon_write_data_xfer_id

logic [31:0]

mon_write_resp_xact_num

logic [31:0]

mon_snoop_addr_xact_num

logic [31:0]

mon_snoop_data_xact_num

logic [31:0]

mon_snoop_data_xfer_id

logic [31:0]

mon_snoop_resp_xact_num

string

full_name

Modports

modport svt_axi_slave_modport

(

input aresetn,
clocking axi_slave_cb

)

Modport used to connect the VIP Slave to AXI interface signals.

modport svt_axi_monitor_modport

(

input aresetn,
clocking axi_monitor_cb

)

Modport used to connect the VIP Monitor to AXI interface signals.

modport svt_axi_ic_modport

(

input aresetn,
clocking axi_master_cb

)

Modport used to connect the VIP Interconnect to AXI interface signals.

modport svt_axi_master_modport

(

output awid,
output awidunq,
output awstashnid,
output awstashnid_en,
output awstashlpid,
output awstashlpid_en,
output awmmusecsid,
output awmmusid,
output awmmussidv,
output awmmussid,
output awatop,
output awmpam,
output awmmuatst,
output awaddr,
output awtagop,
output awregion,
output awlen,
output awsize,
output awburst,
output awlock,
output awcache,
output awprot,
output awqos,
output awvalid,
output awtrace,
output awuser,
output awuserchk,
output awvalidchk,
output awidchk,
output awaddrchk,
output awlenchk,
output awctlchk0,
output awctlchk1,
output awctlchk2,
output awctlchk3,
output awnsaidchk,
output awstashnidchk,
output awstashlpidchk,
output awmmuchk,
output awloopchk,
output awtracechk,
output awmpamchk,
output awmmusidchk,
output awmmussidchk,
output awloop,
output awnsaid,
output wid,
output wdata,
output wtag,
output wtagupdate,
output wstrb,
output wpoison,
output wlast,
output wvalid,
output wtrace,
output wuser,
output wuserchk,
output wdatachk,
output wvalidchk,
output wstrbchk,
output wpoisonchk,
output wlastchk,
output wtracechk,
output wtagchk,
output bready,
output breadychk,
output arid,
output aridunq,
output araddr,
output artagop,
output arregion,
output arlen,
output arsize,
output arburst,
output arlock,
output arcache,
output arprot,
output arqos,
output arvalid,
output artrace,
output armmusecsid,
output armmusid,
output armmussidv,
output armmussid,
output armmuatst,
output armpam,
output aruser,
output aruserchk,
output arvalidchk,
output aridchk,
output araddrchk,
output arlenchk,
output arctlchk0,
output arctlchk1,
output arctlchk2,
output arctlchk3,
output arnsaidchk,
output armmuchk,
output arloopchk,
output artracechk,
output armpamchk,
output armmusidchk,
output armmussidchk,
output arloop,
output arnsaid,
output rready,
output rreadychk,
output arvmidext,
input aresetn,
input awready,
input awreadychk,
input wready,
input wreadychk,
input bid,
input bidunq,
input bresp,
input btagmatch,
input bcomp,
input bpersist,
input bvalid,
input btrace,
input buser,
input buserchk,
input bvalidchk,
input bidchk,
input brespchk,
input btracechk,
input bloopchk,
input arready,
input arreadychk,
input rid,
input ridunq,
input rdata,
input rtag,
input rpoison,
input rresp,
input rlast,
input rvalid,
input ruser,
input ruserchk,
input rtrace,
input rdatachk,
input rpoisonchk,
input rloop,
input bloop,
input rvalidchk,
input ridchk,
input rrespchk,
input rlastchk,
input rtracechk,
input rloopchk,
input rchunkchk,
input rtagchk,
output ardomain,
output arsnoop,
output arbar,
output awdomain,
output awsnoop,
output awcmo,
output awbar,
output awunique,
output acready,
output acreadychk,
output crvalid,
output crtrace,
output crresp,
output crvalidchk,
output crrespchk,
output crtracechk,
output cdvalid,
output cddata,
output cdlast,
output cdpoison,
output cdtrace,
output cddatachk,
output cdlastchk,
output cdpoisonchk,
output cdtracechk,
output cdvalidchk,
output wack,
output wackchk,
output rack,
output rackchk,
output awakeup,
output awakeupchk,
input acvalid,
input actrace,
input acwakeup,
input acaddr,
input acsnoop,
input acprot,
input acvmidext,
input acvalidchk,
input acaddrchk,
input acctlchk,
input acvmidextchk,
input actracechk,
input acwakeupchk,
input crready,
input crreadychk,
input cdready,
input cdreadychk,
output tvalid,
output tdata,
output tstrb,
output tkeep,
output tlast,
output tid,
output tdest,
output tuser,
input tready,
output archunken,
input rchunkv,
input rchunknum,
input rchunkstrb

)

Asynchronous modport suitable for connecting to a Master DUT

modport svt_axi_slave_async_modport

(

input awvalid,
input awtrace,
input awaddr,
input awtagop,
input awlen,
input awsize,
input awburst,
input awlock,
input awcache,
input awprot,
input awid,
input awidunq,
input awstashnid,
input awstashnid_en,
input awstashlpid,
input awstashlpid_en,
input awmmusecsid,
input awmmusid,
input awmmussidv,
input awmmussid,
input awatop,
input awmpam,
input awmmuatst,
output awready,
input awdomain,
input awsnoop,
input awcmo,
input awbar,
input awunique,
input awvalidchk,
output awreadychk,
input awidchk,
input awaddrchk,
input awlenchk,
input awctlchk0,
input awctlchk1,
input awctlchk2,
input awctlchk3,
input awnsaidchk,
input awstashnidchk,
input awstashlpidchk,
input awmmuchk,
input awloopchk,
input awtracechk,
input awmpamchk,
input awmmusidchk,
input awmmussidchk,
input awloop,
input awnsaid,
input arvalid,
input artrace,
input armmusecsid,
input armmusid,
input armmussidv,
input armmussid,
input armmuatst,
input armpam,
input araddr,
input artagop,
input arlen,
input arsize,
input arburst,
input arlock,
input arcache,
input arprot,
input arid,
input aridunq,
output arready,
input ardomain,
input arsnoop,
input arbar,
input arvmidext,
input arvalidchk,
output arreadychk,
input aridchk,
input araddrchk,
input arlenchk,
input arctlchk0,
input arctlchk1,
input arctlchk2,
input arctlchk3,
input arnsaidchk,
input armmuchk,
input arloopchk,
input artracechk,
input armpamchk,
input armmusidchk,
input armmussidchk,
input arloop,
input arnsaid,
output rvalid,
output rtrace,
output rlast,
output rdata,
output rtag,
output rpoison,
output rresp,
output rid,
output ridunq,
input rready,
input rack,
input rackchk,
output rdatachk,
output rpoisonchk,
output rvalidchk,
input rreadychk,
output ridchk,
output rrespchk,
output rlastchk,
output rtracechk,
output rloopchk,
output rchunkchk,
output rtagchk,
output rloop,
input wvalid,
input wtrace,
input wlast,
input wdata,
input wtag,
input wtagupdate,
input wstrb,
input wpoison,
input wid,
input wdatachk,
output wready,
input wvalidchk,
output wreadychk,
input wstrbchk,
input wpoisonchk,
input wlastchk,
input wtracechk,
input wtagchk,
output bvalid,
output btrace,
output bresp,
output btagmatch,
output bcomp,
output bpersist,
output bid,
output bidunq,
input bready,
output bvalidchk,
input breadychk,
output bidchk,
output brespchk,
output btracechk,
output bloopchk,
output bloop,
input wack,
input wackchk,
input awregion,
input awqos,
input awuser,
input awuserchk,
input arregion,
input arqos,
input aruser,
input aruserchk,
input wuser,
input wuserchk,
output ruser,
output ruserchk,
output buser,
output buserchk,
output acvalid,
input awakeup,
input awakeupchk,
output acwakeup,
output actrace,
input acready,
output acaddr,
output acsnoop,
output acprot,
output acvmidext,
input crvalid,
input crtrace,
output crready,
output acvalidchk,
input acreadychk,
output acaddrchk,
output acctlchk,
output acvmidextchk,
output actracechk,
output acwakeupchk,
input crresp,
output crreadychk,
input crvalidchk,
input crrespchk,
input crtracechk,
input cdvalid,
output cdready,
input cddata,
input cdlast,
input cdtrace,
input cdpoison,
input cddatachk,
input cdlastchk,
input cdtracechk,
input cdpoisonchk,
output cdreadychk,
input cdvalidchk,
input tvalid,
output tready,
input tdata,
input tstrb,
input tdest,
input tkeep,
input tlast,
input tid,
input tuser,
input is_active,
input archunken,
output rchunkv,
output rchunknum,
output rchunkstrb

)

Asynchronous modport suitable for SV Slave Bind interface

modport svt_axi_debug_modport

(

output read_addr_xact_num,
output read_data_xact_num,
output read_data_xfer_id,
output write_addr_xact_num,
output write_data_xact_num,
output write_data_xfer_id,
output write_resp_xact_num,
output snoop_addr_xact_num,
output snoop_data_xact_num,
output snoop_data_xfer_id,
output snoop_resp_xact_num,
output mon_read_addr_xact_num,
output mon_read_data_xact_num,
output mon_read_data_xfer_id,
output mon_write_addr_xact_num,
output mon_write_data_xact_num,
output mon_write_data_xfer_id,
output mon_write_resp_xact_num,
output mon_snoop_addr_xact_num,
output mon_snoop_data_xact_num,
output mon_snoop_data_xfer_id,
output mon_snoop_resp_xact_num

)

Modport used to connect the VIP Debug Port.

Clocking blocks

clocking axi_slave_cb @ ( posedge internal_aclk )
default input #0.01 output #0.01

input aresetn,
input awid,
input awidunq,
input awstashnid,
input awstashnid_en,
input awstashlpid,
input awstashlpid_en,
input awmmusecsid,
input awmmusid,
input awmmussidv,
input awmmussid,
input awatop,
input awmpam,
input awmmuatst,
input awaddr,
input awtagop,
input awregion,
input awlen,
input awsize,
input awburst,
input awlock,
input awcache,
input awprot,
input awqos,
input awvalid,
input awtrace,
input awuser,
input awuserchk,
output awready,
input awloop,
input awnsaid,
input awvalidchk,
output awreadychk,
input awidchk,
input awaddrchk,
input awlenchk,
input awctlchk0,
input awctlchk1,
input awctlchk2,
input awctlchk3,
input awnsaidchk,
input awstashnidchk,
input awstashlpidchk,
input awmmuchk,
input awloopchk,
input awtracechk,
input awmpamchk,
input awmmusidchk,
input awmmussidchk,
input wid,
input wdata,
input wtag,
input wtagupdate,
input wstrb,
input wpoison,
input wlast,
input wvalid,
input wtrace,
input wuser,
input wuserchk,
input wdatachk,
output wready,
input wvalidchk,
output wreadychk,
input wstrbchk,
input wpoisonchk,
input wlastchk,
input wtracechk,
input wtagchk,
output bid,
output bidunq,
output bresp,
output btagmatch,
output bcomp,
output bpersist,
output bvalid,
output btrace,
output buser,
output buserchk,
input bready,
output bloop,
output bvalidchk,
input breadychk,
output bidchk,
output brespchk,
output btracechk,
output bloopchk,
input arid,
input aridunq,
input araddr,
input artagop,
input arregion,
input arlen,
input arsize,
input arburst,
input arlock,
input arcache,
input arprot,
input arqos,
input arvalid,
input artrace,
input armmusecsid,
input armmusid,
input armmussidv,
input armmussid,
input armmuatst,
input armpam,
input aruser,
input aruserchk,
input arvmidext,
output arready,
input arvalidchk,
output arreadychk,
input aridchk,
input araddrchk,
input arlenchk,
input arctlchk0,
input arctlchk1,
input arctlchk2,
input arctlchk3,
input arnsaidchk,
input armmuchk,
input arloopchk,
input artracechk,
input armpamchk,
input armmusidchk,
input armmussidchk,
input arloop,
input arnsaid,
output rid,
output ridunq,
output rdata,
output rtag,
output rpoison,
output rresp,
output rlast,
output rvalid,
output rtrace,
output ruser,
output ruserchk,
output rdatachk,
output rpoisonchk,
input rready,
output rloop,
output rvalidchk,
input rreadychk,
output ridchk,
output rrespchk,
output rlastchk,
output rtracechk,
output rloopchk,
output rchunkchk,
output rtagchk,
output acvalid,
output acwakeup,
output actrace,
input acready,
output acaddr,
output acsnoop,
output acprot,
output acvmidext,
output acvalidchk,
input acreadychk,
output acaddrchk,
output acctlchk,
output acvmidextchk,
output actracechk,
output acwakeupchk,
input crvalid,
input crtrace,
output crready,
input crresp,
output crreadychk,
input crvalidchk,
input crrespchk,
input crtracechk,
input cdvalid,
output cdready,
input cddata,
input cdpoison,
input cdlast,
input cdtrace,
input cddatachk,
input cdpoisonchk,
input cdlastchk,
input cdtracechk,
output cdreadychk,
input cdvalidchk,
input tvalid,
input tdata,
input tstrb,
input tkeep,
input tlast,
input tid,
input tdest,
input tuser,
output tready,
input archunken,
output rchunkv,
output rchunknum,
output rchunkstrb

Clocking block that defines the VIP AXI slave Interface signal synchronization and directionality.

clocking axi_monitor_cb @ ( posedge internal_aclk )
default input #0.01 output #0.01

input aresetn,
input awid,
input awidunq,
input awstashnid,
input awstashnid_en,
input awstashlpid,
input awstashlpid_en,
input awmmusecsid,
input awmmusid,
input awmmussidv,
input awmmussid,
input awatop,
input awmpam,
input awmmuatst,
input awaddr,
input awtagop,
input awregion,
input awlen,
input awsize,
input awburst,
input awlock,
input awcache,
input awprot,
input awqos,
input awvalid,
input awtrace,
input awuser,
input awuserchk,
input awready,
input awloop,
input awnsaid,
input awvalidchk,
input awreadychk,
input awidchk,
input awaddrchk,
input awlenchk,
input awctlchk0,
input awctlchk1,
input awctlchk2,
input awctlchk3,
input awnsaidchk,
input awstashnidchk,
input awstashlpidchk,
input awmmuchk,
input awloopchk,
input awtracechk,
input awmpamchk,
input awmmusidchk,
input awmmussidchk,
input wid,
input wdata,
input wtag,
input wtagupdate,
input wstrb,
input wpoison,
input wlast,
input wvalid,
input wtrace,
input wuser,
input wuserchk,
input wready,
input wdatachk,
input wvalidchk,
input wreadychk,
input wstrbchk,
input wpoisonchk,
input wlastchk,
input wtracechk,
input wtagchk,
input bid,
input bidunq,
input bresp,
input btagmatch,
input bcomp,
input bpersist,
input bvalid,
input btrace,
input buser,
input buserchk,
input bready,
input bloop,
input bvalidchk,
input breadychk,
input bidchk,
input brespchk,
input btracechk,
input bloopchk,
input arid,
input aridunq,
input araddr,
input artagop,
input arregion,
input arlen,
input arsize,
input arburst,
input arlock,
input arcache,
input arprot,
input arqos,
input arvalid,
input artrace,
input armmusecsid,
input armmusid,
input armmussidv,
input armmussid,
input armmuatst,
input armpam,
input aruser,
input aruserchk,
input arready,
input arvmidext,
input arvalidchk,
input arreadychk,
input aridchk,
input araddrchk,
input arlenchk,
input arctlchk0,
input arctlchk1,
input arctlchk2,
input arctlchk3,
input arnsaidchk,
input armmuchk,
input arloopchk,
input artracechk,
input armpamchk,
input armmusidchk,
input armmussidchk,
input arloop,
input arnsaid,
input rid,
input ridunq,
input rdata,
input rtag,
input rpoison,
input rresp,
input rlast,
input rvalid,
input rtrace,
input ruser,
input ruserchk,
input rready,
input rdatachk,
input rpoisonchk,
input rloop,
input rvalidchk,
input rreadychk,
input ridchk,
input rrespchk,
input rlastchk,
input rtracechk,
input rloopchk,
input rchunkchk,
input rtagchk,
input ardomain,
input arsnoop,
input arbar,
input rack,
input rackchk,
input awdomain,
input awsnoop,
input awcmo,
input awbar,
input awunique,
input wack,
input wackchk,
input awakeup,
input awakeupchk,
input acvalid,
input acwakeup,
input actrace,
input acready,
input acaddr,
input acsnoop,
input acprot,
input acvmidext,
input acvalidchk,
input acreadychk,
input acaddrchk,
input acctlchk,
input acvmidextchk,
input actracechk,
input acwakeupchk,
input crvalid,
input crtrace,
input crready,
input crresp,
input crreadychk,
input crvalidchk,
input crrespchk,
input crtracechk,
input cdvalid,
input cdready,
input cddata,
input cdpoison,
input cdlast,
input cdtrace,
input cddatachk,
input cdpoisonchk,
input cdlastchk,
input cdtracechk,
input cdreadychk,
input cdvalidchk,
input tvalid,
input tdata,
input tstrb,
input tkeep,
input tlast,
input tid,
input tdest,
input tuser,
input tready,
input archunken,
input rchunkv,
input rchunknum,
input rchunkstrb

Clocking block that defines the AXI Monitor Interface signal synchronization and directionality.

clocking axi_master_cb @ ( posedge internal_aclk )
default input #0.01 output #0.01

input aresetn,
output awid,
output awidunq,
output awstashnid,
output awstashnid_en,
output awstashlpid,
output awstashlpid_en,
output awmmusecsid,
output awmmusid,
output awmmussidv,
output awmmussid,
output awatop,
output awmpam,
output awmmuatst,
output awaddr,
output awtagop,
output awregion,
output awlen,
output awsize,
output awburst,
output awlock,
output awcache,
output awprot,
output awqos,
output awvalid,
output awtrace,
output awuser,
output awuserchk,
input awready,
output awloop,
output awnsaid,
output awvalidchk,
input awreadychk,
output awidchk,
output awaddrchk,
output awlenchk,
output awctlchk0,
output awctlchk1,
output awctlchk2,
output awctlchk3,
output awnsaidchk,
output awstashnidchk,
output awstashlpidchk,
output awmmuchk,
output awloopchk,
output awtracechk,
output awmpamchk,
output awmmusidchk,
output awmmussidchk,
output wid,
output wdata,
output wtag,
output wtagupdate,
output wstrb,
output wpoison,
output wlast,
output wvalid,
output wtrace,
output wuser,
output wuserchk,
output wdatachk,
input wready,
output wvalidchk,
input wreadychk,
output wstrbchk,
output wpoisonchk,
output wlastchk,
output wtracechk,
output wtagchk,
input bid,
input bidunq,
input bresp,
input btagmatch,
input bcomp,
input bpersist,
input bvalid,
input btrace,
input buser,
input buserchk,
output bready,
input bloop,
input bvalidchk,
output breadychk,
input bidchk,
input brespchk,
input btracechk,
input bloopchk,
output arid,
output aridunq,
output araddr,
output artagop,
output arregion,
output arlen,
output arsize,
output arburst,
output arlock,
output arcache,
output arprot,
output arqos,
output arvalid,
output artrace,
output armmusecsid,
output armmusid,
output armmussidv,
output armmussid,
output armmuatst,
output armpam,
output aruser,
output aruserchk,
input arready,
output arvmidext,
output arvalidchk,
input arreadychk,
output aridchk,
output araddrchk,
output arlenchk,
output arctlchk0,
output arctlchk1,
output arctlchk2,
output arctlchk3,
output arnsaidchk,
output armmuchk,
output arloopchk,
output artracechk,
output armpamchk,
output armmusidchk,
output armmussidchk,
output arloop,
output arnsaid,
input rid,
input ridunq,
input rdata,
input rtag,
input rpoison,
input rresp,
input rlast,
input rvalid,
input rtrace,
input ruser,
input ruserchk,
input rdatachk,
input rpoisonchk,
output rready,
input rloop,
input rvalidchk,
output rreadychk,
input ridchk,
input rrespchk,
input rlastchk,
input rtracechk,
input rloopchk,
input rchunkchk,
input rtagchk,
output ardomain,
output arsnoop,
output arbar,
output rack,
output rackchk,
output awdomain,
output awsnoop,
output awcmo,
output awbar,
output awunique,
output wack,
output wackchk,
output awakeup,
output awakeupchk,
input acvalid,
input acwakeup,
input actrace,
output acready,
input acaddr,
input acsnoop,
input acprot,
input acvmidext,
input acvalidchk,
output acreadychk,
input acaddrchk,
input acctlchk,
input acvmidextchk,
input actracechk,
input acwakeupchk,
output crvalid,
output crtrace,
input crready,
output crresp,
input crreadychk,
output crvalidchk,
output crrespchk,
output crtracechk,
output cdvalid,
input cdready,
output cddata,
output cdpoison,
output cdlast,
output cdtrace,
output cddatachk,
output cdpoisonchk,
output cdlastchk,
output cdtracechk,
input cdreadychk,
output cdvalidchk,
output tvalid,
output tdata,
output tstrb,
output tkeep,
output tlast,
output tid,
output tdest,
output tuser,
input tready,
output archunken,
input rchunkv,
input rchunknum,
input rchunkstrb

Clocking block that defines VIP AXI Master Interface signal synchronization and directionality.

clocking axi_debug_cb @ ( posedge aclk )
default input #0.01 output #0.01

output read_addr_xact_num,
output read_data_xact_num,
output read_data_xfer_id,
output write_addr_xact_num,
output write_data_xact_num,
output write_data_xfer_id,
output write_resp_xact_num,
output snoop_addr_xact_num,
output snoop_data_xact_num,
output snoop_data_xfer_id,
output snoop_resp_xact_num,
output mon_read_addr_xact_num,
output mon_read_data_xact_num,
output mon_read_data_xfer_id,
output mon_write_addr_xact_num,
output mon_write_data_xact_num,
output mon_write_data_xfer_id,
output mon_write_resp_xact_num,
output mon_snoop_addr_xact_num,
output mon_snoop_data_xact_num,
output mon_snoop_data_xfer_id,
output mon_snoop_resp_xact_num

Clocking block that defines the AXI Debug Interface

Functions

void function

set_enable_signal_log ()

string function

get_full_name ()

interface svt_axi_if ()

General description:

AXI VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_axi_if is defined. The top level interface contains an array of master & slave interfaces. By default, 16 master and 16 slave interfaces are defined in the top level interface. Currently, the maximum master and slave interfaces supported is 450. The number of master and slave interfaces in top level interface can be controlled using macros SVT_AXI_MAX_NUM_MASTERS_{0..450} and SVT_AXI_MAX_NUM_SLAVES_{0..450} respectively. For example, if you want to use 8 master interfaces and 10 slave interfaces, you can define following macros when compiling the VIP:

SVT_AXI_MAX_NUM_MASTERS_8

SVT_AXI_MAX_NUM_SLAVES_10
Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces:

Interface Name	Interface Description
svt_axi_master_if	Master Interface used by master VIP component
svt_axi_slave_if	Slave Interface used by slave VIP component

Clock signal description:

Signal Name

Signal Description

common_aclk

If all AXI interfaces in the system are expected to run on a common clock, user can use the common clock mode. Common clock mode can be selected by setting configuration parameter svt_axi_system_configuration :: common_clock_mode to 1. This is the default mode of operation. When common clock mode is used, connect common_aclk signal to the top level clock signal in the testbench. Pleae note that if you are using the Interconnect VIP component, you are required to always connect common_aclk signalto a clock in the testbench, as Interconnect VIP component internally uses this clock for its operation.

aclk

This signal belongs to the master and slave sub-interfaces. If all AXI interfaces in the system are expected to run on a different clock, user can use the aclk signal in the port interfaces. Set the configuration parameter svt_axi_system_configuration :: common_clock_mode to 0. In this case, connect the aclk signal in each port interface to the appropriate port specific clock in the testbench.

Clock connection examples:

Usage with common clock:
assign axi_if.common_aclk = SystemClock;

Usage with port specific clock:
assign axi_if.master_if[0].aclk = master_clk;
assign axi_if.slave_if[0].aclk = slave_clk;

Interface signal connections:

If master VIP is active, then connect DUT slave port signals to master interface:
assign axi_if.master_if[0].awvalid = DUT_slave_intf.awvalid;

If master VIP is passive, then connect DUT master port signals to master interface:
assign axi_if.master_if[0].awvalid = DUT_master_intf.awvalid;

If slave VIP is active, then connect DUT master port signals to slave interface:
assign axi_if.slave_if[0].awready = DUT_master_intf.awready;

If slave VIP is passive, then connect DUT slave port signals to slave interface:
assign axi_if.slave_if[0].awready = DUT_slave_intf.awready;

Sub-interfaces

svt_axi_master_if

master_if

svt_axi_lp_if

lp_if

svt_axi_slave_if

slave_if

Ports

logic

common_aclk

logic

interconnect_resetn

string

full_name

Functions

void function

set_enable_signal_log ()

string function

get_full_name ()

interface svt_ahb_master_if ( input logic common_hclk, input logic common_hresetn, input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hrdata_bus, input logic hready_bus, input logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] hresp_bus, input logic [(SVT_AHB_MAX_DATA_USER_WIDTH-1):0] hrdata_huser_bus ) General description: The master interface svt_ahb_master_if defines the AHB signals appropriate for a single port, along with the modports needed for the AHB master and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Ports
bit	is_active
logic	hclk
logic	hresetn
logic	hgrant
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hrdata
logic	hready
logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]	hresp
logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]	haddr
logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]	hburst
logic	hbusreq
logic	hlock
logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]	hprot
logic	hnonsec
logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]	hsize
logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]	htrans
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hwdata
logic	hwrite
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	addr_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	data_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	xact_beat_num
logic [SVT_AHB_MAX_USER_WIDTH-1:0]	control_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hwdata_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hrdata_huser
string	full_name

Modports
modport svt_ahb_master_modport ( input internal_hresetn, clocking ahb_master_cb ) Modport used to connect the VIP Master to AHB interface signals.

modport svt_ahb_bus_modport ( input haddr, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hsize, input htrans, input hwdata, input hwrite, input control_huser, input hwdata_huser, output hgrant, clocking ahb_bus_cb ) Modport used to connect the VIP Bus to AHB master interface signals. The asynchronous signals are required for multiplexing functionality.

modport svt_ahb_monitor_modport ( input internal_hresetn, clocking ahb_monitor_cb ) Modport used to connect the VIP Monitor to AHB interface signals.

modport svt_ahb_master_async_modport ( input hgrant, input hrdata, input hready, input hresp, input hrdata_huser, output haddr, output hburst, output hbusreq, output hlock, output hprot, output hnonsec, output hsize, output htrans, output hwdata, output hwrite, output control_huser, output hwdata_huser, input is_active ) Asynchronous modport suitable for SV Master Bind interface

modport svt_ahb_debug_modport ( output addr_phase_xact_num, output data_phase_xact_num, output xact_beat_num ) Modport used to connect the VIP Debug Port.

Clocking blocks
clocking ahb_master_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input hrdata, input hready, input hgrant, input hresp, input hrdata_huser, output haddr, output hburst, output hbusreq, output hlock, output hprot, output hnonsec, output hsize, output htrans, output hwdata, output hwrite, output control_huser, output hwdata_huser Clocking block that defines VIP AHB Master Interface signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge common_hclk ) default input #0.01 output #0.01 input haddr, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hsize, input htrans, input hwdata, input hwrite, input control_huser, input hwdata_huser, output hgrant Clocking block that defines VIP AHB Bus-Master Interface signal synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input hgrant, input hrdata, input hready, input hresp, input haddr, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hsize, input htrans, input hwdata, input hwrite, input control_huser, input hwdata_huser, input hrdata_huser Clocking block that defines the AHB Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_ahb_slave_if ( input logic common_hclk, input logic common_hresetn, input logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] haddr_bus, input logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] hburst_bus, input logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] hmaster_bus, input logic hmastlock_bus, input logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] hprot_bus, input logic hnonsec_bus, input logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] hsize_bus, input logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] htrans_bus, input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hwdata_bus, input logic hwrite_bus, input logic hready_bus, input logic [SVT_AHB_MAX_USER_WIDTH-1:0] control_huser_bus, input logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] hwdata_huser_bus ) General description: The slave interface svt_ahb_slave_if defines the AHB signals appropriate for a single port, along with the modports needed for the AHB slave and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Ports
bit	is_active
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hrdata
logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]	hresp
logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]	haddr
logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]	hburst
logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]	hprot
logic	hnonsec
logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]	hsize
logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]	htrans
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hwdata
logic	hwrite
logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]	hmaster
logic	hmastlock
logic [(SVT_AHB_MAX_HSEL_WIDTH-1):0]	hsel
logic	hready_in
logic	hready
logic [(SVT_AHB_MAX_NUM_MASTERS-1):0]	hsplit
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	addr_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	data_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	xact_beat_num
logic [SVT_AHB_MAX_USER_WIDTH-1:0]	control_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hwdata_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hrdata_huser
string	full_name

Modports
modport svt_ahb_slave_modport ( input internal_hresetn, clocking ahb_slave_cb ) Modport used to connect the VIP Slave to AHB interface signals.

modport svt_ahb_bus_modport ( input hrdata, input hready, input hresp, input hsplit, input hrdata_huser, output hsel, clocking ahb_bus_cb ) Modport used to connect the VIP Bus to AHB master interface signals. Asynchronous signals are required for multiplexing functionality

modport svt_ahb_monitor_modport ( input internal_hresetn, clocking ahb_monitor_cb ) Modport used to connect the VIP Monitor to AHB interface signals.

modport svt_ahb_slave_async_modport ( input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hsel, input hsize, input htrans, input hwdata, input hwrite, input hready_in, input control_huser, input hwdata_huser, output hrdata, output hready, output hresp, output hsplit, output hrdata_huser, input is_active ) Asynchronous modport suitable for SV Slave Bind interface

modport svt_ahb_debug_modport ( output addr_phase_xact_num, output data_phase_xact_num, output xact_beat_num ) Modport used to connect the VIP Debug Port.

Clocking blocks
clocking ahb_slave_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hsel, input hsize, input htrans, input hwdata, input hwrite, input hready_in, input control_huser, input hwdata_huser, output hrdata, output hready, output hresp, output hsplit, output hrdata_huser Clocking block that defines the VIP AHB Bus-Slave Interface signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge common_hclk ) default input #0.01 output #0.01 input hrdata, input hready, input hresp, input hsplit, input hrdata_huser, output hsel Clocking block that defines the VIP AHB slave Interface signal synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hsel, input hsize, input htrans, input hwdata, input hwrite, input hrdata, input hready, input hready_in, input hresp, input hsplit, input control_huser, input hwdata_huser, input hrdata_huser Clocking block that defines the AHB Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_ahb_if ()

General description:

AHB VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_ahb_if is defined. The top level interface contains reset signal for the bus, and an array of master & slave interfaces. The top level interface can be used for connecting the master & slave components to the AHB Bus. By default, 16 master and 16 slave interfaces are defined in the top level interface. Currently, the maximum number of master and slave interfaces supported is 128. The number of master and slave interfaces in top level interface can be controlled using macros SVT_AHB_MAX_NUM_MASTERS_{0..128} and SVT_AHB_MAX_NUM_SLAVES_{0..128} respectively. For example, if you want to use 8 master interfaces and 10 slave interfaces, you can define following macros when compiling the VIP:

SVT_AHB_MAX_NUM_MASTERS_8

SVT_AHB_MAX_NUM_SLAVES_10
Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces:

Interface Name	Interface Description
svt_ahb_master_if	Master Interface used by master VIP component
svt_ahb_slave_if	Slave Interface used by slave VIP component

Clock signal description:

Signal Name	Signal Description
hclk	This clock signal belongs to the top level AHB Interface. User is expected to connect clock signal in testbench to this hclk signal in the top level interface. This clock is used by all the AHB master and slave VIP components.

Clock connection examples:
assign ahb_if.hclk = SystemClock;

Reset signal description:

Signal Name	Signal Description
hresetn	This reset signal belongs to the top level AHB Interface. User is expected to connect reset signal in testbench to this hclk signal in the top level interface. This reset is used by all the AHB master and slave VIP components.

Reset connection examples:
assign ahb_if.hresetn = SystemResetn;

Sub-interfaces

svt_ahb_master_if

master_if

svt_ahb_slave_if

slave_if

Ports

logic

hclk

logic

hresetn

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]

hrdata_bus

logic

hready_bus

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]

hresp_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]

hrdata_huser_bus

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]

haddr_bus

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]

hburst_bus

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]

hprot_bus

logic

hnonsec_bus

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]

hsize_bus

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]

htrans_bus

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]

hwdata_bus

logic

hwrite_bus

logic [SVT_AHB_MAX_USER_WIDTH-1:0]

control_huser_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]

hwdata_huser_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

hmaster_bus

logic

hmastlock_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

curr_hmaster

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

prev_hmaster

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]

curr_sel_slave

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]

prev_sel_slave

logic [SVT_AHB_MAX_NUM_MASTERS-1:0]

hsplit_bus

string

full_name

Modports

modport svt_ahb_bus_modport

(

input hresetn,
output hrdata_bus,
output hready_bus,
output hresp_bus,
output haddr_bus,
output hburst_bus,
output hprot_bus,
output hnonsec_bus,
output hsize_bus,
output htrans_bus,
output hwdata_bus,
output hwrite_bus,
output control_huser_bus,
output hmaster_bus,
output hmastlock_bus,
output hwdata_huser_bus,
output hrdata_huser_bus,
clocking ahb_bus_reset_cb,
clocking ahb_bus_cb

)

Modport used to connect the reset signal to VIP AHB Bus The signals corresponding to following need to be asynchronous

The address, control, write data from granted master to all slaves
The response, read data from selected slave to all masters

modport svt_ahb_monitor_modport

(

input hresetn,
input hrdata_bus,
input hready_bus,
input hresp_bus,
input haddr_bus,
input hburst_bus,
input hprot_bus,
input hnonsec_bus,
input hsize_bus,
input htrans_bus,
input hwdata_bus,
input hwrite_bus,
input control_huser_bus,
input hmaster_bus,
input hmastlock_bus,
input hwdata_huser_bus,
input hrdata_huser_bus,
clocking ahb_bus_reset_cb,
clocking ahb_monitor_cb

)

Monitor modport for the bus signals. The Modport includes the clocking blocks for synchronous sampling. It also includes the signals directly for asynnchronous sampling wherever it is required.

modport svt_ahb_debug_modport

(

output curr_hmaster,
output prev_hmaster,
output curr_sel_slave,
output prev_sel_slave,
output hsplit_bus

)

Debug modport

Clocking blocks

clocking ahb_bus_reset_cb @ ( posedge hclk )
default input #0.01 output #0.01

input hresetn

Clocking block that defines the VIP AHB Bus Interface reset signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge hclk )
default input #0.01 output #0.01

output hmaster_bus,
output hmastlock_bus

Clocking block that defines the VIP AHB Bus Interface bus to all slaves signals synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge hclk )
default input #0.01 output #0.01

input hrdata_bus,
input hready_bus,
input hresp_bus,
input haddr_bus,
input hburst_bus,
input hprot_bus,
input hnonsec_bus,
input hsize_bus,
input htrans_bus,
input hwdata_bus,
input hwrite_bus,
input control_huser_bus,
input hmaster_bus,
input hmastlock_bus,
input hwdata_huser_bus,
input hrdata_huser_bus

Clocking block that defines the VIP AHB Bus Interface bus to all slaves signals synchronization and directionality.

Functions

virtual AHB_MASTER_IF function

get_master_if (int idx)

void function

set_enable_signal_log ()

string function

get_full_name ()

interface svt_apb_slave_if () APB Slave Interface provides the SystemVerilog interface which can be used to connect the Slave VIP to a DUT. A top level interface svt_apb_if is defined. The top level interface contains the system level pins and an array of slave interfaces.

Ports
bit	is_active
logic	pclk
logic	presetn
logic	psel
logic	penable
logic	pwrite
logic [(SVT_APB_MAX_ADDR_WIDTH-1):0]	paddr
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	pwdata
logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0]	pstrb
logic [2:0]	pprot
logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0]	control_puser
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	prdata
logic	pready
logic	pslverr
logic [31:0]	xact_id
logic [31:0]	mon_xact_id
string	full_name

Modports
modport svt_apb_slave_modport ( clocking apb_slave_cb ) Modport used to connect the VIP Slave to APB interface signals.

modport svt_apb_monitor_modport ( input presetn, clocking apb_monitor_cb ) Modport used to connect the VIP Monitor to APB interface signals.

modport svt_apb_debug_modport ( output xact_id, output mon_xact_id ) Modport used to connect the VIP Debug Port.

modport svt_apb_slave_async_modport ( input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, output prdata, output pready, output pslverr ) Asynchronous modport suitable for SV Slave Bind interface

Clocking blocks
clocking apb_slave_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pstrb, input pprot, input control_puser, output prdata, output pready, output pslverr Clocking block that defines VIP APB Slave Interface signal synchronization and directionality.

clocking apb_monitor_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB System Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_apb_if () APB VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_apb_if is defined. The top level interface contains the system level pins and an array of slave interfaces. By default, 16 slave interfaces are defined in the top level interface. Currently, the maximum number of slave interfaces supported is 128. The number of slave interfaces in top level interface can be controlled using macro SVT_APB_MAX_NUM_SLAVES_{0..128}. For example, if you want to use 20 slave interfaces, you can define following macro when compiling the VIP: SVT_APB_MAX_NUM_SLAVES_20 Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces
svt_apb_slave_if	slave_if

Ports
bit	is_active
bit	disable_x_check_of_presetn
bit	disable_x_check_of_pclk
logic	pclk
logic	presetn
logic [(SVT_APB_MAX_NUM_SLAVES-1):0]	psel
logic	penable
logic	pwrite
logic [(SVT_APB_MAX_ADDR_WIDTH-1):0]	paddr
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	pwdata
logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0]	pstrb
logic [2:0]	pprot
logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0]	control_puser
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	prdata
logic	pready
logic	pslverr
logic [31:0]	xact_id
logic [31:0]	mon_xact_id
string	full_name

Modports
modport svt_apb_master_modport ( input presetn, clocking apb_master_cb ) Modport used to connect the VIP Master to APB interface signals.

modport svt_apb_monitor_modport ( input presetn, clocking apb_monitor_cb ) Modport used to connect the VIP Monitor to APB interface signals.

modport svt_apb_debug_modport ( output xact_id, output mon_xact_id ) Modport used to connect the VIP Debug Port.

modport svt_apb_master_async_modport ( input presetn, output psel, output penable, output pwrite, output paddr, output pwdata, output pstrb, output pprot, output control_puser, input prdata, input pready, input pslverr ) Asynchronous modport suitable for SV Master Bind interface

Clocking blocks
clocking apb_master_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, output psel, output penable, output pwrite, output paddr, output pwdata, output pstrb, output pprot, output control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB Master Interface signal synchronization and directionality.

clocking apb_monitor_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB System Monitor Interface signal synchronization and directionality.

Functions
virtual APB_SLAVE_IF function	get_slave_if (int idx)
void function	set_enable_signal_log ()
string function	get_full_name ()

function void
svt_axi_master_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_axi_master_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_axi_master_if signal
input logic common_aclk

bit attribute
svt_axi_master_if::is_active = 1

bit attribute
svt_axi_master_if::common_clock_mode = 1

bit attribute
svt_axi_master_if::clock_enable = 0

logic attribute
svt_axi_master_if::aclk

logic attribute
svt_axi_master_if::aresetn

logic attribute
svt_axi_master_if::awvalid

logic [SVT_AXI_MAX_ADDR_WIDTH-1:0] attribute
svt_axi_master_if::awaddr

logic [SVT_AXI_MAX_BURST_LENGTH_WIDTH-1:0] attribute
svt_axi_master_if::awlen

logic [SVT_AXI_SIZE_WIDTH-1:0] attribute
svt_axi_master_if::awsize

logic [SVT_AXI_BURST_WIDTH-1:0] attribute
svt_axi_master_if::awburst

logic [SVT_AXI_LOCK_WIDTH-1:0] attribute
svt_axi_master_if::awlock

logic [SVT_AXI_CACHE_WIDTH-1:0] attribute
svt_axi_master_if::awcache

logic [SVT_AXI_PROT_WIDTH-1:0] attribute
svt_axi_master_if::awprot

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_master_if::awid

logic attribute
svt_axi_master_if::awready

logic attribute
svt_axi_master_if::awidunq

logic [SVT_AXI_MAX_LOOP_W_WIDTH-1:0] attribute
svt_axi_master_if::awloop

logic [SVT_AXI_MAX_NSAID_WIDTH-1:0] attribute
svt_axi_master_if::awnsaid

logic [SVT_AXI_STASH_NID_WIDTH-1:0] attribute
svt_axi_master_if::awstashnid

logic [SVT_AXI_STASH_LPID_WIDTH-1:0] attribute
svt_axi_master_if::awstashlpid

logic attribute
svt_axi_master_if::awstashnid_en

logic attribute
svt_axi_master_if::awstashlpid_en

logic attribute
svt_axi_master_if::awtrace

logic [SVT_AXI_MAX_MMUSECSID_WIDTH-1:0] attribute
svt_axi_master_if::awmmusecsid

logic [SVT_AXI_MAX_MMUSID_WIDTH-1:0] attribute
svt_axi_master_if::awmmusid

logic attribute
svt_axi_master_if::awmmussidv

logic [SVT_AXI_MAX_MMUSSID_WIDTH-1:0] attribute
svt_axi_master_if::awmmussid

logic attribute
svt_axi_master_if::awmmuatst

logic [SVT_ACE5_ATOMIC_TYPE_WIDTH-1:0] attribute
svt_axi_master_if::awatop

logic [SVT_AXI_MAX_MPAM_WIDTH-1:0] attribute
svt_axi_master_if::awmpam

logic [SVT_AXI_TAGOP_WIDTH-1:0] attribute
svt_axi_master_if::awtagop

logic [SVT_AXI_ACE_DOMAIN_WIDTH-1:0] attribute
svt_axi_master_if::awdomain

logic [SVT_AXI_ACE_WSNOOP_WIDTH-1:0] attribute
svt_axi_master_if::awsnoop

logic [SVT_AXI_ACE_WCMO_WIDTH-1:0] attribute
svt_axi_master_if::awcmo

logic [SVT_AXI_ACE_BARRIER_WIDTH-1:0] attribute
svt_axi_master_if::awbar

logic attribute
svt_axi_master_if::awunique

logic attribute
svt_axi_master_if::awvalidchk

logic attribute
svt_axi_master_if::awreadychk

logic [1:0] attribute
svt_axi_master_if::awidchk

logic [7:0] attribute
svt_axi_master_if::awaddrchk

logic attribute
svt_axi_master_if::awlenchk

logic attribute
svt_axi_master_if::awctlchk0

logic attribute
svt_axi_master_if::awctlchk1

logic attribute
svt_axi_master_if::awctlchk2

logic attribute
svt_axi_master_if::awctlchk3

logic attribute
svt_axi_master_if::awnsaidchk

logic attribute
svt_axi_master_if::awstashnidchk

logic attribute
svt_axi_master_if::awstashlpidchk

logic attribute
svt_axi_master_if::awmmuchk

logic attribute
svt_axi_master_if::awloopchk

logic attribute
svt_axi_master_if::awtracechk

logic attribute
svt_axi_master_if::awmpamchk

logic [3:0] attribute
svt_axi_master_if::awmmusidchk

logic [5:0] attribute
svt_axi_master_if::awmmussidchk

logic attribute
svt_axi_master_if::arvalid

logic [SVT_AXI_MAX_ADDR_WIDTH-1:0] attribute
svt_axi_master_if::araddr

logic [SVT_AXI_MAX_BURST_LENGTH_WIDTH-1:0] attribute
svt_axi_master_if::arlen

logic [SVT_AXI_SIZE_WIDTH-1:0] attribute
svt_axi_master_if::arsize

logic [SVT_AXI_BURST_WIDTH-1:0] attribute
svt_axi_master_if::arburst

logic [SVT_AXI_LOCK_WIDTH-1:0] attribute
svt_axi_master_if::arlock

logic [SVT_AXI_CACHE_WIDTH-1:0] attribute
svt_axi_master_if::arcache

logic [SVT_AXI_PROT_WIDTH-1:0] attribute
svt_axi_master_if::arprot

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_master_if::arid

logic attribute
svt_axi_master_if::arready

logic attribute
svt_axi_master_if::aridunq

logic [SVT_AXI_MAX_LOOP_R_WIDTH-1:0] attribute
svt_axi_master_if::arloop

logic [SVT_AXI_MAX_NSAID_WIDTH-1:0] attribute
svt_axi_master_if::arnsaid

logic [SVT_AXI_MAX_VMIDEXT_WIDTH-1:0] attribute
svt_axi_master_if::arvmidext

logic [SVT_AXI_TAGOP_WIDTH-1:0] attribute
svt_axi_master_if::artagop

logic [SVT_AXI_ACE_DOMAIN_WIDTH-1:0] attribute
svt_axi_master_if::ardomain

logic [SVT_AXI_ACE_RSNOOP_WIDTH-1:0] attribute
svt_axi_master_if::arsnoop

logic [SVT_AXI_ACE_BARRIER_WIDTH-1:0] attribute
svt_axi_master_if::arbar

logic attribute
svt_axi_master_if::artrace

logic [SVT_AXI_MAX_MMUSECSID_WIDTH-1:0] attribute
svt_axi_master_if::armmusecsid

logic [SVT_AXI_MAX_MMUSID_WIDTH-1:0] attribute
svt_axi_master_if::armmusid

logic attribute
svt_axi_master_if::armmussidv

logic [SVT_AXI_MAX_MMUSSID_WIDTH-1:0] attribute
svt_axi_master_if::armmussid

logic attribute
svt_axi_master_if::armmuatst

logic [SVT_AXI_MAX_MPAM_WIDTH-1:0] attribute
svt_axi_master_if::armpam

logic attribute
svt_axi_master_if::arvalidchk

logic attribute
svt_axi_master_if::arreadychk

logic [1:0] attribute
svt_axi_master_if::aridchk

logic [7:0] attribute
svt_axi_master_if::araddrchk

logic attribute
svt_axi_master_if::arlenchk

logic attribute
svt_axi_master_if::arctlchk0

logic attribute
svt_axi_master_if::arctlchk1

logic attribute
svt_axi_master_if::arctlchk2

logic attribute
svt_axi_master_if::arctlchk3

logic attribute
svt_axi_master_if::arnsaidchk

logic attribute
svt_axi_master_if::armmuchk

logic attribute
svt_axi_master_if::arloopchk

logic attribute
svt_axi_master_if::artracechk

logic attribute
svt_axi_master_if::armpamchk

logic [3:0] attribute
svt_axi_master_if::armmusidchk

logic [5:0] attribute
svt_axi_master_if::armmussidchk

logic attribute
svt_axi_master_if::rvalid

logic attribute
svt_axi_master_if::rlast

logic [SVT_AXI_MAX_DATA_WIDTH-1:0] attribute
svt_axi_master_if::rdata

logic [SVT_AXI_RESP_WIDTH-1:0] attribute
svt_axi_master_if::rresp

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_master_if::rid

logic attribute
svt_axi_master_if::rready

logic attribute
svt_axi_master_if::rack

logic attribute
svt_axi_master_if::rackchk

logic [SVT_AXI_MAX_LOOP_R_WIDTH-1:0] attribute
svt_axi_master_if::rloop

logic [(SVT_AXI_MAX_DATA_WIDTH/8)-1:0] attribute
svt_axi_master_if::rdatachk

logic [1:0] attribute
svt_axi_master_if::rpoisonchk

logic [SVT_AXI_MAX_DATA_WIDTH/64-1:0] attribute
svt_axi_master_if::rpoison

logic attribute
svt_axi_master_if::rtrace

logic [SVT_AXI_MAX_TAG_WIDTH-1:0] attribute
svt_axi_master_if::rtag

logic attribute
svt_axi_master_if::ridunq

logic attribute
svt_axi_master_if::rvalidchk

logic attribute
svt_axi_master_if::rreadychk

logic [1:0] attribute
svt_axi_master_if::ridchk

logic attribute
svt_axi_master_if::rrespchk

logic attribute
svt_axi_master_if::rlastchk

logic attribute
svt_axi_master_if::rtracechk

logic attribute
svt_axi_master_if::rloopchk

logic attribute
svt_axi_master_if::rchunkchk

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0] attribute
svt_axi_master_if::rtagchk

logic attribute
svt_axi_master_if::wvalid

logic attribute
svt_axi_master_if::wlast

logic [SVT_AXI_MAX_DATA_WIDTH-1:0] attribute
svt_axi_master_if::wdata

logic [SVT_AXI_MAX_DATA_WIDTH/8-1:0] attribute
svt_axi_master_if::wstrb

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_master_if::wid

logic attribute
svt_axi_master_if::wready

logic [(SVT_AXI_MAX_DATA_WIDTH/8)-1:0] attribute
svt_axi_master_if::wdatachk

logic attribute
svt_axi_master_if::wtrace

logic [SVT_AXI_MAX_DATA_WIDTH/64-1:0] attribute
svt_axi_master_if::wpoison

logic [SVT_AXI_MAX_TAG_WIDTH-1:0] attribute
svt_axi_master_if::wtag

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0] attribute
svt_axi_master_if::wtagupdate

logic attribute
svt_axi_master_if::wvalidchk

logic attribute
svt_axi_master_if::wreadychk

logic [15:0] attribute
svt_axi_master_if::wstrbchk

logic [1:0] attribute
svt_axi_master_if::wpoisonchk

logic attribute
svt_axi_master_if::wlastchk

logic attribute
svt_axi_master_if::wtracechk

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0] attribute
svt_axi_master_if::wtagchk

logic attribute
svt_axi_master_if::bvalid

logic [SVT_AXI_RESP_WIDTH-1:0] attribute
svt_axi_master_if::bresp

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_master_if::bid

logic attribute
svt_axi_master_if::bready

logic [SVT_AXI_MAX_LOOP_W_WIDTH-1:0] attribute
svt_axi_master_if::bloop

logic attribute
svt_axi_master_if::bidunq

logic attribute
svt_axi_master_if::wack

logic attribute
svt_axi_master_if::wackchk

logic attribute
svt_axi_master_if::btrace

logic attribute
svt_axi_master_if::awakeup

logic attribute
svt_axi_master_if::awakeupchk

logic [SVT_AXI_MAX_TAG_MATCH_RESP_WIDTH-1:0] attribute
svt_axi_master_if::btagmatch

logic attribute
svt_axi_master_if::bcomp

logic attribute
svt_axi_master_if::bpersist

logic attribute
svt_axi_master_if::bvalidchk

logic attribute
svt_axi_master_if::breadychk

logic [1:0] attribute
svt_axi_master_if::bidchk

logic attribute
svt_axi_master_if::brespchk

logic attribute
svt_axi_master_if::btracechk

logic attribute
svt_axi_master_if::bloopchk

logic [SVT_AXI_REGION_WIDTH-1:0] attribute
svt_axi_master_if::awregion

logic [SVT_AXI_QOS_WIDTH-1:0] attribute
svt_axi_master_if::awqos

logic [SVT_AXI_MAX_ADDR_USER_WIDTH-1:0] attribute
svt_axi_master_if::awuser

logic [SVT_AXI_REGION_WIDTH-1:0] attribute
svt_axi_master_if::arregion

logic [SVT_AXI_QOS_WIDTH-1:0] attribute
svt_axi_master_if::arqos

logic [SVT_AXI_MAX_ADDR_USER_WIDTH-1:0] attribute
svt_axi_master_if::aruser

logic [SVT_AXI_MAX_DATA_USER_WIDTH-1:0] attribute
svt_axi_master_if::wuser

logic [SVT_AXI_MAX_DATA_USER_WIDTH-1:0] attribute
svt_axi_master_if::ruser

logic [SVT_AXI_MAX_BRESP_USER_WIDTH-1:0] attribute
svt_axi_master_if::buser

logic [3:0] attribute
svt_axi_master_if::awuserchk

logic [3:0] attribute
svt_axi_master_if::aruserchk

logic [0:0] attribute
svt_axi_master_if::wuserchk

logic [0:0] attribute
svt_axi_master_if::ruserchk

logic [3:0] attribute
svt_axi_master_if::buserchk

logic attribute
svt_axi_master_if::acvalid

logic attribute
svt_axi_master_if::acwakeup

logic attribute
svt_axi_master_if::actrace

logic attribute
svt_axi_master_if::acready

logic [SVT_AXI_ACE_SNOOP_ADDR_WIDTH-1:0] attribute
svt_axi_master_if::acaddr

logic [SVT_AXI_ACE_SNOOP_TYPE_WIDTH-1:0] attribute
svt_axi_master_if::acsnoop

logic [SVT_AXI_ACE_SNOOP_PROT_WIDTH-1:0] attribute
svt_axi_master_if::acprot

logic [SVT_AXI_MAX_VMIDEXT_WIDTH-1:0] attribute
svt_axi_master_if::acvmidext

logic attribute
svt_axi_master_if::acvalidchk

logic attribute
svt_axi_master_if::acreadychk

logic [7:0] attribute
svt_axi_master_if::acaddrchk

logic attribute
svt_axi_master_if::acctlchk

logic attribute
svt_axi_master_if::acvmidextchk

logic attribute
svt_axi_master_if::actracechk

logic attribute
svt_axi_master_if::acwakeupchk

logic attribute
svt_axi_master_if::crtrace

logic attribute
svt_axi_master_if::crvalid

logic attribute
svt_axi_master_if::crready

logic [SVT_AXI_ACE_SNOOP_RESP_WIDTH-1:0] attribute
svt_axi_master_if::crresp

logic attribute
svt_axi_master_if::crreadychk

logic attribute
svt_axi_master_if::crvalidchk

logic attribute
svt_axi_master_if::crrespchk

logic attribute
svt_axi_master_if::crtracechk

logic attribute
svt_axi_master_if::cdvalid

logic attribute
svt_axi_master_if::cdready

logic [SVT_AXI_ACE_SNOOP_DATA_WIDTH-1:0] attribute
svt_axi_master_if::cddata

logic [SVT_AXI_ACE_SNOOP_DATA_WIDTH/64-1:0] attribute
svt_axi_master_if::cdpoison

logic attribute
svt_axi_master_if::cdtrace

logic attribute
svt_axi_master_if::cdlast

logic attribute
svt_axi_master_if::cdreadychk

logic attribute
svt_axi_master_if::cdvalidchk

logic [127:0] attribute
svt_axi_master_if::cddatachk

logic [1:0] attribute
svt_axi_master_if::cdpoisonchk

logic attribute
svt_axi_master_if::cdtracechk

logic attribute
svt_axi_master_if::cdlastchk

logic attribute
svt_axi_master_if::tvalid

logic attribute
svt_axi_master_if::tready

logic [SVT_AXI_MAX_TDATA_WIDTH-1:0] attribute
svt_axi_master_if::tdata

logic [SVT_AXI_TSTRB_WIDTH-1:0] attribute
svt_axi_master_if::tstrb

logic [SVT_AXI_MAX_TDEST_WIDTH-1:0] attribute
svt_axi_master_if::tdest

logic [SVT_AXI_TKEEP_WIDTH-1:0] attribute
svt_axi_master_if::tkeep

logic attribute
svt_axi_master_if::tlast

logic [SVT_AXI_MAX_TID_WIDTH-1:0] attribute
svt_axi_master_if::tid

logic [SVT_AXI_MAX_TUSER_WIDTH-1:0] attribute
svt_axi_master_if::tuser

logic attribute
svt_axi_master_if::archunken

logic attribute
svt_axi_master_if::rchunkv

logic [SVT_AXI_MAX_CHUNK_NUM_WIDTH-1:0] attribute
svt_axi_master_if::rchunknum

logic [SVT_AXI_MAX_CHUNK_STROBE_WIDTH-1:0] attribute
svt_axi_master_if::rchunkstrb

logic [31:0] attribute
svt_axi_master_if::read_addr_xact_num

Debug port signals driven in active mode

logic [31:0] attribute
svt_axi_master_if::read_data_xact_num

logic [31:0] attribute
svt_axi_master_if::read_data_xfer_id

logic [31:0] attribute
svt_axi_master_if::write_addr_xact_num

logic [31:0] attribute
svt_axi_master_if::write_data_xact_num

logic [31:0] attribute
svt_axi_master_if::write_data_xfer_id

logic [31:0] attribute
svt_axi_master_if::write_resp_xact_num

logic [31:0] attribute
svt_axi_master_if::snoop_addr_xact_num

Debug ports for ACE interface

logic [31:0] attribute
svt_axi_master_if::snoop_data_xact_num

logic [31:0] attribute
svt_axi_master_if::snoop_data_xfer_id

logic [31:0] attribute
svt_axi_master_if::snoop_resp_xact_num

logic [31:0] attribute
svt_axi_master_if::mon_read_addr_xact_num

Debug port signals driven in passive mode

logic [31:0] attribute
svt_axi_master_if::mon_read_data_xact_num

logic [31:0] attribute
svt_axi_master_if::mon_read_data_xfer_id

logic [31:0] attribute
svt_axi_master_if::mon_write_addr_xact_num

logic [31:0] attribute
svt_axi_master_if::mon_write_data_xact_num

logic [31:0] attribute
svt_axi_master_if::mon_write_data_xfer_id

logic [31:0] attribute
svt_axi_master_if::mon_write_resp_xact_num

logic [31:0] attribute
svt_axi_master_if::mon_snoop_addr_xact_num

Debug ports for ACE interface

logic [31:0] attribute
svt_axi_master_if::mon_snoop_data_xact_num

logic [31:0] attribute
svt_axi_master_if::mon_snoop_data_xfer_id

logic [31:0] attribute
svt_axi_master_if::mon_snoop_resp_xact_num

string attribute
svt_axi_master_if::full_name

Full path to this interface or module instance

logic attribute
svt_axi_lp_if::aclk

logic attribute
svt_axi_lp_if::aresetn

logic attribute
svt_axi_lp_if::cactive

logic attribute
svt_axi_lp_if::csysreq

logic attribute
svt_axi_lp_if::csysack

function void
svt_axi_slave_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_axi_slave_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_axi_slave_if signal
input logic common_aclk

bit attribute
svt_axi_slave_if::is_active = 1

bit attribute
svt_axi_slave_if::common_clock_mode = 1

bit attribute
svt_axi_slave_if::clock_enable = 0

logic attribute
svt_axi_slave_if::aclk

logic attribute
svt_axi_slave_if::aresetn

logic attribute
svt_axi_slave_if::awvalid

logic [SVT_AXI_MAX_ADDR_WIDTH-1:0] attribute
svt_axi_slave_if::awaddr

logic [SVT_AXI_MAX_BURST_LENGTH_WIDTH-1:0] attribute
svt_axi_slave_if::awlen

logic [SVT_AXI_SIZE_WIDTH-1:0] attribute
svt_axi_slave_if::awsize

logic [SVT_AXI_BURST_WIDTH-1:0] attribute
svt_axi_slave_if::awburst

logic [SVT_AXI_LOCK_WIDTH-1:0] attribute
svt_axi_slave_if::awlock

logic [SVT_AXI_CACHE_WIDTH-1:0] attribute
svt_axi_slave_if::awcache

logic [SVT_AXI_PROT_WIDTH-1:0] attribute
svt_axi_slave_if::awprot

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_slave_if::awid

logic attribute
svt_axi_slave_if::awready

logic attribute
svt_axi_slave_if::awidunq

logic [SVT_AXI_MAX_LOOP_W_WIDTH-1:0] attribute
svt_axi_slave_if::awloop

logic [SVT_AXI_MAX_NSAID_WIDTH-1:0] attribute
svt_axi_slave_if::awnsaid

logic [SVT_AXI_ACE_DOMAIN_WIDTH-1:0] attribute
svt_axi_slave_if::awdomain

logic [SVT_AXI_ACE_WSNOOP_WIDTH-1:0] attribute
svt_axi_slave_if::awsnoop

logic [SVT_AXI_ACE_WCMO_WIDTH-1:0] attribute
svt_axi_slave_if::awcmo

logic [SVT_AXI_ACE_BARRIER_WIDTH-1:0] attribute
svt_axi_slave_if::awbar

logic attribute
svt_axi_slave_if::awunique

logic [SVT_AXI_STASH_NID_WIDTH-1:0] attribute
svt_axi_slave_if::awstashnid

logic [SVT_AXI_STASH_LPID_WIDTH-1:0] attribute
svt_axi_slave_if::awstashlpid

logic attribute
svt_axi_slave_if::awstashnid_en

logic attribute
svt_axi_slave_if::awstashlpid_en

logic attribute
svt_axi_slave_if::awtrace

logic [SVT_AXI_MAX_MMUSECSID_WIDTH-1:0] attribute
svt_axi_slave_if::awmmusecsid

logic [SVT_AXI_MAX_MMUSID_WIDTH-1:0] attribute
svt_axi_slave_if::awmmusid

logic attribute
svt_axi_slave_if::awmmussidv

logic [SVT_AXI_MAX_MMUSSID_WIDTH-1:0] attribute
svt_axi_slave_if::awmmussid

logic attribute
svt_axi_slave_if::awmmuatst

logic [SVT_ACE5_ATOMIC_TYPE_WIDTH-1:0] attribute
svt_axi_slave_if::awatop

logic [SVT_AXI_MAX_MPAM_WIDTH-1:0] attribute
svt_axi_slave_if::awmpam

logic [SVT_AXI_TAGOP_WIDTH-1:0] attribute
svt_axi_slave_if::awtagop

logic attribute
svt_axi_slave_if::awvalidchk

logic attribute
svt_axi_slave_if::awreadychk

logic [1:0] attribute
svt_axi_slave_if::awidchk

logic [7:0] attribute
svt_axi_slave_if::awaddrchk

logic attribute
svt_axi_slave_if::awlenchk

logic attribute
svt_axi_slave_if::awctlchk0

logic attribute
svt_axi_slave_if::awctlchk1

logic attribute
svt_axi_slave_if::awctlchk2

logic attribute
svt_axi_slave_if::awctlchk3

logic attribute
svt_axi_slave_if::awnsaidchk

logic attribute
svt_axi_slave_if::awstashnidchk

logic attribute
svt_axi_slave_if::awstashlpidchk

logic attribute
svt_axi_slave_if::awmmuchk

logic attribute
svt_axi_slave_if::awloopchk

logic attribute
svt_axi_slave_if::awtracechk

logic attribute
svt_axi_slave_if::awmpamchk

logic [3:0] attribute
svt_axi_slave_if::awmmusidchk

logic [5:0] attribute
svt_axi_slave_if::awmmussidchk

logic attribute
svt_axi_slave_if::arvalid

logic [SVT_AXI_MAX_ADDR_WIDTH-1:0] attribute
svt_axi_slave_if::araddr

logic [SVT_AXI_MAX_BURST_LENGTH_WIDTH-1:0] attribute
svt_axi_slave_if::arlen

logic [SVT_AXI_SIZE_WIDTH-1:0] attribute
svt_axi_slave_if::arsize

logic [SVT_AXI_BURST_WIDTH-1:0] attribute
svt_axi_slave_if::arburst

logic [SVT_AXI_LOCK_WIDTH-1:0] attribute
svt_axi_slave_if::arlock

logic [SVT_AXI_CACHE_WIDTH-1:0] attribute
svt_axi_slave_if::arcache

logic [SVT_AXI_PROT_WIDTH-1:0] attribute
svt_axi_slave_if::arprot

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_slave_if::arid

logic attribute
svt_axi_slave_if::arready

logic attribute
svt_axi_slave_if::aridunq

logic [SVT_AXI_MAX_LOOP_R_WIDTH-1:0] attribute
svt_axi_slave_if::arloop

logic [SVT_AXI_MAX_NSAID_WIDTH-1:0] attribute
svt_axi_slave_if::arnsaid

logic [SVT_AXI_MAX_VMIDEXT_WIDTH-1:0] attribute
svt_axi_slave_if::arvmidext

logic [SVT_AXI_TAGOP_WIDTH-1:0] attribute
svt_axi_slave_if::artagop

logic [SVT_AXI_ACE_DOMAIN_WIDTH-1:0] attribute
svt_axi_slave_if::ardomain

logic [SVT_AXI_ACE_RSNOOP_WIDTH-1:0] attribute
svt_axi_slave_if::arsnoop

logic [SVT_AXI_ACE_BARRIER_WIDTH-1:0] attribute
svt_axi_slave_if::arbar

logic attribute
svt_axi_slave_if::artrace

logic [SVT_AXI_MAX_MMUSECSID_WIDTH-1:0] attribute
svt_axi_slave_if::armmusecsid

logic [SVT_AXI_MAX_MMUSID_WIDTH-1:0] attribute
svt_axi_slave_if::armmusid

logic attribute
svt_axi_slave_if::armmussidv

logic [SVT_AXI_MAX_MMUSSID_WIDTH-1:0] attribute
svt_axi_slave_if::armmussid

logic attribute
svt_axi_slave_if::armmuatst

logic [SVT_AXI_MAX_MPAM_WIDTH-1:0] attribute
svt_axi_slave_if::armpam

logic attribute
svt_axi_slave_if::arvalidchk

logic attribute
svt_axi_slave_if::arreadychk

logic [1:0] attribute
svt_axi_slave_if::aridchk

logic [7:0] attribute
svt_axi_slave_if::araddrchk

logic attribute
svt_axi_slave_if::arlenchk

logic attribute
svt_axi_slave_if::arctlchk0

logic attribute
svt_axi_slave_if::arctlchk1

logic attribute
svt_axi_slave_if::arctlchk2

logic attribute
svt_axi_slave_if::arctlchk3

logic attribute
svt_axi_slave_if::arnsaidchk

logic attribute
svt_axi_slave_if::armmuchk

logic attribute
svt_axi_slave_if::arloopchk

logic attribute
svt_axi_slave_if::artracechk

logic attribute
svt_axi_slave_if::armpamchk

logic [3:0] attribute
svt_axi_slave_if::armmusidchk

logic [5:0] attribute
svt_axi_slave_if::armmussidchk

logic attribute
svt_axi_slave_if::rvalid

logic attribute
svt_axi_slave_if::rlast

logic [SVT_AXI_MAX_DATA_WIDTH-1:0] attribute
svt_axi_slave_if::rdata

logic [SVT_AXI_RESP_WIDTH-1:0] attribute
svt_axi_slave_if::rresp

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_slave_if::rid

logic attribute
svt_axi_slave_if::rready

logic attribute
svt_axi_slave_if::rack

logic attribute
svt_axi_slave_if::rackchk

logic [SVT_AXI_MAX_LOOP_R_WIDTH-1:0] attribute
svt_axi_slave_if::rloop

logic [(SVT_AXI_MAX_DATA_WIDTH/8)-1:0] attribute
svt_axi_slave_if::rdatachk

logic [1:0] attribute
svt_axi_slave_if::rpoisonchk

logic attribute
svt_axi_slave_if::rtrace

logic [SVT_AXI_MAX_DATA_WIDTH/64-1:0] attribute
svt_axi_slave_if::rpoison

logic [SVT_AXI_MAX_TAG_WIDTH-1:0] attribute
svt_axi_slave_if::rtag

logic attribute
svt_axi_slave_if::ridunq

logic attribute
svt_axi_slave_if::rvalidchk

logic attribute
svt_axi_slave_if::rreadychk

logic [1:0] attribute
svt_axi_slave_if::ridchk

logic attribute
svt_axi_slave_if::rrespchk

logic attribute
svt_axi_slave_if::rlastchk

logic attribute
svt_axi_slave_if::rtracechk

logic attribute
svt_axi_slave_if::rloopchk

logic attribute
svt_axi_slave_if::rchunkchk

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0] attribute
svt_axi_slave_if::rtagchk

logic attribute
svt_axi_slave_if::wvalid

logic attribute
svt_axi_slave_if::wlast

logic [SVT_AXI_MAX_DATA_WIDTH-1:0] attribute
svt_axi_slave_if::wdata

logic [SVT_AXI_MAX_DATA_WIDTH/8-1:0] attribute
svt_axi_slave_if::wstrb

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_slave_if::wid

logic attribute
svt_axi_slave_if::wready

logic [(SVT_AXI_MAX_DATA_WIDTH/8)-1:0] attribute
svt_axi_slave_if::wdatachk

logic attribute
svt_axi_slave_if::wtrace

logic [SVT_AXI_MAX_DATA_WIDTH/64-1:0] attribute
svt_axi_slave_if::wpoison

logic [SVT_AXI_MAX_TAG_WIDTH-1:0] attribute
svt_axi_slave_if::wtag

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0] attribute
svt_axi_slave_if::wtagupdate

logic attribute
svt_axi_slave_if::wvalidchk

logic attribute
svt_axi_slave_if::wreadychk

logic [15:0] attribute
svt_axi_slave_if::wstrbchk

logic [1:0] attribute
svt_axi_slave_if::wpoisonchk

logic attribute
svt_axi_slave_if::wlastchk

logic attribute
svt_axi_slave_if::wtracechk

logic [SVT_AXI_MAX_TAGUPDATE_WIDTH-1:0] attribute
svt_axi_slave_if::wtagchk

logic attribute
svt_axi_slave_if::bvalid

logic [SVT_AXI_RESP_WIDTH-1:0] attribute
svt_axi_slave_if::bresp

logic [SVT_AXI_MAX_ID_WIDTH-1:0] attribute
svt_axi_slave_if::bid

logic attribute
svt_axi_slave_if::bready

logic [SVT_AXI_MAX_LOOP_W_WIDTH-1:0] attribute
svt_axi_slave_if::bloop

logic attribute
svt_axi_slave_if::bvalidchk

logic attribute
svt_axi_slave_if::breadychk

logic [1:0] attribute
svt_axi_slave_if::bidchk

logic attribute
svt_axi_slave_if::brespchk

logic attribute
svt_axi_slave_if::btracechk

logic attribute
svt_axi_slave_if::bloopchk

logic attribute
svt_axi_slave_if::bidunq

logic attribute
svt_axi_slave_if::wack

logic attribute
svt_axi_slave_if::wackchk

logic attribute
svt_axi_slave_if::btrace

logic attribute
svt_axi_slave_if::awakeup

logic attribute
svt_axi_slave_if::awakeupchk

logic [SVT_AXI_MAX_TAG_MATCH_RESP_WIDTH-1:0] attribute
svt_axi_slave_if::btagmatch

logic attribute
svt_axi_slave_if::bcomp

logic attribute
svt_axi_slave_if::bpersist

logic [SVT_AXI_REGION_WIDTH-1:0] attribute
svt_axi_slave_if::awregion

logic [SVT_AXI_QOS_WIDTH-1:0] attribute
svt_axi_slave_if::awqos

logic [SVT_AXI_MAX_ADDR_USER_WIDTH-1:0] attribute
svt_axi_slave_if::awuser

logic [SVT_AXI_REGION_WIDTH-1:0] attribute
svt_axi_slave_if::arregion

logic [SVT_AXI_QOS_WIDTH-1:0] attribute
svt_axi_slave_if::arqos

logic [SVT_AXI_MAX_ADDR_USER_WIDTH-1:0] attribute
svt_axi_slave_if::aruser

logic [SVT_AXI_MAX_DATA_USER_WIDTH-1:0] attribute
svt_axi_slave_if::wuser

logic [SVT_AXI_MAX_DATA_USER_WIDTH-1:0] attribute
svt_axi_slave_if::ruser

logic [SVT_AXI_MAX_BRESP_USER_WIDTH-1:0] attribute
svt_axi_slave_if::buser

logic [3:0] attribute
svt_axi_slave_if::awuserchk

logic [0:0] attribute
svt_axi_slave_if::wuserchk

logic [3:0] attribute
svt_axi_slave_if::buserchk

logic [3:0] attribute
svt_axi_slave_if::aruserchk

logic [0:0] attribute
svt_axi_slave_if::ruserchk

logic attribute
svt_axi_slave_if::acvalid

logic attribute
svt_axi_slave_if::acwakeup

logic attribute
svt_axi_slave_if::acready

logic [SVT_AXI_ACE_SNOOP_ADDR_WIDTH-1:0] attribute
svt_axi_slave_if::acaddr

logic [SVT_AXI_ACE_SNOOP_TYPE_WIDTH-1:0] attribute
svt_axi_slave_if::acsnoop

logic [SVT_AXI_ACE_SNOOP_PROT_WIDTH-1:0] attribute
svt_axi_slave_if::acprot

logic [SVT_AXI_MAX_VMIDEXT_WIDTH-1:0] attribute
svt_axi_slave_if::acvmidext

logic attribute
svt_axi_slave_if::actrace

logic attribute
svt_axi_slave_if::acvalidchk

logic attribute
svt_axi_slave_if::acreadychk

logic [7:0] attribute
svt_axi_slave_if::acaddrchk

logic attribute
svt_axi_slave_if::acctlchk

logic attribute
svt_axi_slave_if::acvmidextchk

logic attribute
svt_axi_slave_if::actracechk

logic attribute
svt_axi_slave_if::acwakeupchk

logic attribute
svt_axi_slave_if::crvalid

logic attribute
svt_axi_slave_if::crready

logic [SVT_AXI_ACE_SNOOP_RESP_WIDTH-1:0] attribute
svt_axi_slave_if::crresp

logic attribute
svt_axi_slave_if::crtrace

logic attribute
svt_axi_slave_if::crreadychk

logic attribute
svt_axi_slave_if::crvalidchk

logic attribute
svt_axi_slave_if::crrespchk

logic attribute
svt_axi_slave_if::crtracechk

logic attribute
svt_axi_slave_if::cdvalid

logic attribute
svt_axi_slave_if::cdready

logic [SVT_AXI_ACE_SNOOP_DATA_WIDTH-1:0] attribute
svt_axi_slave_if::cddata

logic attribute
svt_axi_slave_if::cdlast

logic [SVT_AXI_ACE_SNOOP_DATA_WIDTH/64-1:0] attribute
svt_axi_slave_if::cdpoison

logic attribute
svt_axi_slave_if::cdtrace

logic [127:0] attribute
svt_axi_slave_if::cddatachk

logic attribute
svt_axi_slave_if::cdlastchk

logic [1:0] attribute
svt_axi_slave_if::cdpoisonchk

logic attribute
svt_axi_slave_if::cdtracechk

logic attribute
svt_axi_slave_if::cdreadychk

logic attribute
svt_axi_slave_if::cdvalidchk

logic attribute
svt_axi_slave_if::tvalid

logic attribute
svt_axi_slave_if::tready

logic [SVT_AXI_MAX_TDATA_WIDTH-1:0] attribute
svt_axi_slave_if::tdata

logic [SVT_AXI_TSTRB_WIDTH-1:0] attribute
svt_axi_slave_if::tstrb

logic [SVT_AXI_MAX_TDEST_WIDTH-1:0] attribute
svt_axi_slave_if::tdest

logic [SVT_AXI_TKEEP_WIDTH-1:0] attribute
svt_axi_slave_if::tkeep

logic attribute
svt_axi_slave_if::tlast

logic [SVT_AXI_MAX_TID_WIDTH-1:0] attribute
svt_axi_slave_if::tid

logic [SVT_AXI_MAX_TUSER_WIDTH-1:0] attribute
svt_axi_slave_if::tuser

logic attribute
svt_axi_slave_if::archunken

logic attribute
svt_axi_slave_if::rchunkv

logic [SVT_AXI_MAX_CHUNK_NUM_WIDTH-1:0] attribute
svt_axi_slave_if::rchunknum

logic [SVT_AXI_MAX_CHUNK_STROBE_WIDTH-1:0] attribute
svt_axi_slave_if::rchunkstrb

logic [31:0] attribute
svt_axi_slave_if::read_addr_xact_num

Debug port signals driven in active mode

logic [31:0] attribute
svt_axi_slave_if::read_data_xact_num

logic [31:0] attribute
svt_axi_slave_if::read_data_xfer_id

logic [31:0] attribute
svt_axi_slave_if::write_addr_xact_num

logic [31:0] attribute
svt_axi_slave_if::write_data_xact_num

logic [31:0] attribute
svt_axi_slave_if::write_data_xfer_id

logic [31:0] attribute
svt_axi_slave_if::write_resp_xact_num

logic [31:0] attribute
svt_axi_slave_if::snoop_addr_xact_num

Debug ports for ACE interface

logic [31:0] attribute
svt_axi_slave_if::snoop_data_xact_num

logic [31:0] attribute
svt_axi_slave_if::snoop_data_xfer_id

logic [31:0] attribute
svt_axi_slave_if::snoop_resp_xact_num

logic [31:0] attribute
svt_axi_slave_if::mon_read_addr_xact_num

Debug port signals driven in passive mode

logic [31:0] attribute
svt_axi_slave_if::mon_read_data_xact_num

logic [31:0] attribute
svt_axi_slave_if::mon_read_data_xfer_id

logic [31:0] attribute
svt_axi_slave_if::mon_write_addr_xact_num

logic [31:0] attribute
svt_axi_slave_if::mon_write_data_xact_num

logic [31:0] attribute
svt_axi_slave_if::mon_write_data_xfer_id

logic [31:0] attribute
svt_axi_slave_if::mon_write_resp_xact_num

logic [31:0] attribute
svt_axi_slave_if::mon_snoop_addr_xact_num

Debug ports for ACE interface

logic [31:0] attribute
svt_axi_slave_if::mon_snoop_data_xact_num

logic [31:0] attribute
svt_axi_slave_if::mon_snoop_data_xfer_id

logic [31:0] attribute
svt_axi_slave_if::mon_snoop_resp_xact_num

string attribute
svt_axi_slave_if::full_name

Full path to this interface or module instance

VIP Smartsearch

AMBA SVT OVM Documentation - Interfaces Reference

Interface Definition Documentation

interface svt_axi_lp_if () General description: The low power interface svt_axi_lp_if defines the AXI low power signals appropriate for a single port, along with the modports needed for the monitor VIP.

Ports
logic	aclk
logic	aresetn
logic	cactive
logic	csysreq
logic	csysack

Modports
modport svt_axi_lp_monitor_modport ( input aresetn, input cactive, input csysreq, input csysack, clocking axi_lp_monitor_cb ) Modport used to connect the VIP Monitor to AXI interface signals.

modport svt_axi_lp_async_modport ( input cactive, input csysreq, input csysack, input aclk, input aresetn ) Asynchronous modport

Clocking blocks
clocking axi_lp_monitor_cb @ ( posedge aclk ) default input #0.01 output #0.01 input aresetn, input cactive, input csysreq, input csysack Clocking block that defines the AXI low power monitor Interface signal synchronization and directionality.