VIP Smartsearch

VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.
How to download VIP smartsearch?
1. Get VIP Smartsearch (Available as a seperate run file).
2. Set environment variable
```
DESIGNWARE_HOME
```
  to required designware home location where VIP Smartsearch should be downloaded.
3. Run
```
vip_smartsearch_<version>.run
```
  file.
  VIP Smartsearch will be downloaded to the location
```
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
```

How to install VIP Smartsearch?

Please refer to the file

VIP_Smartsearch_installation_and_usage_guide.pdf

$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

for installation steps.

Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.
Mention your queries along with below details and send email to above email id.
Product: Verification IP
Sub Product: <vip_title>
Tool: VIP Smartsearch

Product Base	Group	Protocol Check Class
amba_svt	APB2	svt_apb_checker
APB3	svt_apb_checker
APB4 Protection Unit Support	svt_apb_checker
APB4 Write Strobes	svt_apb_checker
AHB System	svt_ahb_system_checker
AHB_COMMON	svt_ahb_checker
AHB_FULL	svt_ahb_checker
AHB_Lite	svt_ahb_checker
ARM11/AHB_V6 Exclusive Accesses	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	svt_ahb_checker
AHB5 Extended Memory Types	svt_ahb_checker
AHB5 Secure Transfers	svt_ahb_checker
AHB_Lite_Multilayer	svt_ahb_checker
SYSTEM: ACE	svt_axi_system_checker
SYSTEM: AXI3 Onwards	svt_axi_system_checker
PORT: AXI_LP	svt_axi_lp_checker
ACE	svt_axi_checker
AXI3	svt_axi_checker
ACE,ACE_Lite	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE,ACE5	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	svt_axi_checker
ACE5_LiteDVM	svt_axi_checker
AXI4,AXI5	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE5	svt_axi_checker
ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI3 Onwards	svt_axi_checker
AXI3,AXI4,AXI5,ACE5_Lite	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI4_STREAM,AXI5_STREAM	svt_axi_checker
None	svt_amba_system_checker

Product Base

Group

Protocol Check Class

APB4 Protection Unit Support

svt_ahb_system_checker

ARM11/AHB_V6 Exclusive Accesses

svt_ahb_checker

ARM11/AHB_V6 Unaligned Transfers

svt_ahb_checker

AHB5 Extended Memory Types

svt_ahb_checker

AHB5 Secure Transfers

svt_axi_system_checker

SYSTEM: AXI3 Onwards

svt_axi_system_checker

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

ACE,ACE5

svt_axi_checker

ACE,ACE5,ACE5_LiteDVM

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

ACE5

svt_axi_checker

ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI3 Onwards

svt_axi_checker

AXI3,AXI4,AXI5,ACE5_Lite

svt_axi_checker

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI4_STREAM,AXI5_STREAM

svt_axi_checker

None

svt_amba_system_checker

Group	Sub Group	Protocol Check Instance name	Reference	Description	Check Intent	Pass Condition	Fail Condition	Applicable Device Type	Additional Information	Error Category	Protocol Check Class
APB2	State Transition	initial_bus_state_after_reset	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	After reset the bus initially should be in either IDLE or SETUP State	Checks that after reset de-assertion, APB Bus is in either IDLE or SETUP state.	APB Bus is in either IDLE or SETUP state after reset de-assertion. For master, either PSEL is zero or PENABLE is 0, immediately after reset de-assertion For slave, either PSEL or PENABLE sampled as 0, immediately after reset de-assertion	APB Bus is in ACCESS state after reset de-assertion. For master, PSEL of the selected slave is 1 and PENABLE is 1, immediately after reset de-assertion For slave, PSEL and PENABLE both sampled as 1, immediately after reset de-assertion	Active & Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Slave Selection	multiple_select_signals_active_during_transfer	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.4.2 APB bridge description	Only one select signal can be active during a transfer	Checks if multiple select signals asserted during transfer	Only one select signal asserted during transfer	Multiple select signals asserted during transfer	Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_prdata_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PRDATA must be valid when PSEL, PENABLE and PREADY are asserted for read transfer	Checks that PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer	PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer	PRDATA is X or Z when PSEL, PENABLE and PREADY are asserted for read transfer	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 The macro SVT_APB_SLAVE_DRIVE_X_IF_MEMDATA_X is not defined	ERROR	svt_apb_checker
APB2	Unaligned Transfers	address_not_aligned_when_unaligned_address_support_not_enabled	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus	Unaligned address should not be driven on PADDR when unaligned_address_support is not enabled	Checks if unaligned address is driven on PADDR when unaligned_address_support is not enabled.	Aligned address is driven on PADDR	Unaligned address is driven on PADDR	Passive Master, Active & Passive Slave	Group: APB2 Default severity: WARNING If unaligned address driving and sampling is required and need to bypass this check, please enable unaligned address support setting svt_apb_configuration :: unaligned_address_support to 1	WARNING	svt_apb_checker
APB2	Signal Stability	pwdata_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers	PWDATA must be stable until the write transfer completes	Checks if PWDATA changed value during write transfer	PWDATA is stable during write transfer	PWDATA is changed during write transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 If svt_apb_configuration :: check_valid_data_bytes_only_enable and svt_apb_system_configuration :: apb4_enable are set to 1, then check will be performed only on active data byte lanes based on pstrb.	ERROR	svt_apb_checker
APB2	Signal Stability	pwrite_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PWRITE must be stable until the transfer completes	Checks if PWRITE changed value during transfer	PWRITE is stable during transfer	PWRITE is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Stability	paddr_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PADDR must be stable until the transfer completes	Checks if PADDR changed value during transfer	PADDR is stable during transfer	PADDR is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Stability	psel_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PSEL must be stable until the transfer completes	Checks if PSEL changed value during transfer	PSEL is stable during the transfer	PSEL is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_pwdata_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PWDATA must be valid when PSEL is asserted for write transfer	Checks that PWDATA is not X or Z when PSEL is asserted for write transfer	PWDATA is not X or Z when PSEL is asserted for write transfer	PWDATA is X or Z when PSEL is asserted for write transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 If svt_apb_configuration :: check_valid_data_bytes_only_enable and svt_apb_system_configuration :: apb4_enable are set to 1, then check will be performed only on active data byte lanes based on pstrb.	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_penable_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PENABLE must be valid when PSEL is asserted	Checks that PENABLE is not X or Z when PSEL is asserted	PENABLE is not X or Z when PSEL is asserted	PENABLE is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_pwrite_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PWRITE must be valid when PSEL is asserted	Checks that PWRITE is not X or Z when PSEL is asserted	PWRITE is not X or Z when PSEL is asserted	PWRITE is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_paddr_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PADDR must be valid when PSEL is asserted	Checks that PADDR is not X or Z when PSEL is asserted	PADDR is not X or Z when PSEL is asserted	PADDR is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_psel_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSEL must be always valid	Checks that PSEL is not X or Z	PSEL is not X or Z	PSEL is X or Z	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	State Transition	penable_after_psel	AMBA APB Protocol Specification ARM IHI 0011A: 5.2.1 State diagram	PENABLE should be asserted after one clock cycle of PSEL being asserted	Checks that PENABLE is asserted after one clock cycle of PSEL being asserted.	PENABLE is asserted after one clock cycle of PSEL being asserted	PSEL and PENABLE asserted simultaneously PENABLE is not asserted after one clock cycle of PSEL being asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Address Mapping	psel_match_with_address_map	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.5.2 APB slave description	Asserted PSEL should match with the address map	Checks that asserted PSEL matches with the address map. Refer to ARM IHI 0011A section 2.4, signal description of PSELx for the protocol info.	slave ID obtained by address decoding is equal to the slave ID that has PSEL asserted.	slave ID obtained by address decoding is not equal to the slave ID that has PSEL asserted.	Passive Master, Active & Passive Slave	In case of complex_memory_map enabled, pprot1 is also considered in address decoding.	ERROR	svt_apb_checker
APB2	State Transition	setup_to_setup	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	SETUP to SETUP is an illegal state transition	Checks that if illegal state transition occured from setup to setup	No state transition occured from setup to setup	Illegal state transition occured from setup to setup	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	APB2 State Transition	access_to_access	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	ACCESS to ACCESS is an illegal state transition in APB2	Checks that if illegal state transition occured from access to access in APB2. In APB3 state transition from access to access is valid transition.	No state transition occured from access to access in APB2	Illegal state transition occured from access to access in APB2	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	State Transition	setup_to_idle	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	SETUP to IDLE is an illegal state transition	Checks that if illegal state transition occured from setup to idle	No state transition occured from setup to idle	Illegal state transition occured from setup to idle	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	APB2 State Transition	bus_in_enable_state_for_one_clock	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.2.1 State diagram	ENABLE state lasts only for a single clock cycle in APB2	Checks that bus remains in ENABLE state for one clock cycle in APB2	Bus remains in ENABLE state for one clock cycle in APB2	Bus remains in ENABLE state for more than one clock cycle in APB2	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb3_enable and svt_apb_system_configuration :: apb4_enable are set to 0	ERROR	svt_apb_checker
APB3	Signal Validity	signal_valid_pslverr_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSLVERR must be valid when PSEL, PENABLE and PREADY are asserted	Checks that PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted	PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted	PSLVERR is X or Z when PSEL, PENABLE and PREADY are asserted	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB3	Signal Validity	signal_valid_pready_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PREADY must be valid when PSEL and PENABLE are asserted	Checks that PREADY is not X or Z when PSEL and PENABLE are asserted	PREADY is not X or Z when PSEL and PENABLE are asserted	PREADY is X or Z when PSEL and PENABLE are asserted	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB3	Transaction Timeout	pready_timeout_check	Synopsys Defined	PREADY should be asserted by the slave within the timeout period	Checks that PREADY signal is asserted by slave within timeout period slave_pready_timeout	PREADY signal is asserted by slave within timeout period slave_pready_timeout	PREADY signal is not asserted by slave within timeout period slave_pready_timeout	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1 svt_apb_system_configuration :: slave_pready_timeout is not equal to 0	ERROR	svt_apb_checker
APB3	Signal Stability	penable_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PENABLE must be stable until the transfer completes	Checks if PENABLE changed value during access phase of transfer	PENABLE high during access phase of transfer	PENABLE low during access phase of transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB3	State Transition	idle_to_access	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	IDLE to ACCESS is an illegal state transition	Checks that if illegal state transition occured from idle to access	No state transition occured from idle to access	Illegal state transition occured from idle to access	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB4 Protection Unit Support	Signal Stability	pprot_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PPROT must be stable until the transfer completes	Checks if PPROT changed value during transfer	PPROT is stable during transfer	PPROT is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Protection Unit Support	Signal Validity	signal_valid_pprot_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PPROT must be valid when PSEL is asserted	Checks that PPROT is not X or Z when PSEL is asserted	PPROT is not X or Z when PSEL is asserted	PPROT is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	Signal Stability	pstrb_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers	PSTRB must be stable until the transfer completes	Checks if PSTRB changed value during write transfer	PSTRB is stable during write transfer	PSTRB is changed during write transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	PSTRB Validity	pstrb_low_for_read	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.2 Write strobes	All bits of PSTRB must be LOW for read transfer	Checks that PSTRB is low for read transfer	All bits of PSTRB are low for read transfer	Any bit of PSTRB is high for read transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	Signal Validity	signal_valid_pstrb_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSTRB must be valid when PSEL is asserted	Checks that PSTRB is not X or Z when PSEL is asserted	PSTRB is not X or Z when PSEL is asserted	PSTRB is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	Unaligned Transfers	pstrb_asserted_for_invalid_byte_in_unaligned_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus & 3.2 Write strobes	PSTRB should be correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled	Checks if PSTRB is correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled.	PSTRB is correctly asserted based on the address alignment	PSTRB is not correctly asserted based on the address alignment	Passive Master, Active & Passive Slave	Group: APB4 Default severity: ERROR Applicable for APB4 systems when unaligned address support is enabled using svt_apb_configuration :: unaligned_address_support configuration.	ERROR	svt_apb_checker
AHB System	Manager Subordinate Transaction Association	master_slave_xact_resp_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Response signals should match between manager transaction and the corresponding subordinate transaction.	Checks that response signals match between manager transaction and the corresponding subordinate transaction.	All the all_beat_response array values match between manager and corresponding subordinate transaction.	Any of the all_beat_response array values does not match between manager and corresponding subordinate transaction.	System Monitor	Group: AHB Default severity: ERROR Limitations: Currently disabled for AHB Lite multilayer.	ERROR	svt_ahb_system_checker
AHB System	Manager Subordinate Transaction Association	master_slave_xact_data_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Data values should match between manager transaction and the corresponding subordinate transaction.	Checks that data values match between manager transaction and the corresponding subordinate transaction.	All the data array values match between manager and corresponding subordinate transaction.	Any of the data array values does not match between manager and corresponding subordinate transaction.	System Monitor	Group: AHB Default severity: ERROR Limitations: Currently disabled for AHB Lite multilayer.	ERROR	svt_ahb_system_checker
AHB System	Manager Subordinate Transaction Association	master_slave_xact_addr_ctrl_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Address and control signals should match between manager transaction and the corresponding subordinate transaction.	Checks that address and control signals match between manager transaction and the corresponding subordinate transaction. Following control signal attributes are compared. addr xact_type burst_type burst_size prot_type	All the compared signal attributes match between manager and corresponding subordinate transaction.	Any of the compared signal attributes does not match between manager and corresponding subordinate transaction.	System Monitor	Group: AHB Default severity: ERROR Limitations: Currently disabled for AHB Lite multilayer.	ERROR	svt_ahb_system_checker
AHB System	Dummy Manager	xact_not_idle_when_dummy_master_active	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus manager	Transfer type of the transaction is not IDLE when dummy manager is active.	Checks that IDLE transactions are driven when the dummy manager is active	IDLE transactions are driven when the dummy manager is active	IDLE transactions are not driven when the dummy manager is active	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	hmastlock_changed_during_incr	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked transfers	HMASTLOCK signal changed during INCR burst transfer.	Checks that the HMASTLOCK signal remains constant during an INCR burst	HMASTLOCK signal remains constant during an INCR burst	HMASTLOCK signal changes during an INCR burst	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	arbiter_asserted_hmastlock_without_hlock	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers	Arbiter asserted HMASTLOCK signal when the manager has not requested.	Checks that the arbiter does not assert HMASTLOCK when the manager has not requested	Arbiter does not assert HMASTLOCK when the manager has not requested	Arbiter does asserts HMASTLOCK when the manager has not requested	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	arbiter_lock_last_grant	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers	Arbiter did not keep manager granted for an additional transfer after a locked sequence.	Checks that the arbiter keeps the manager granted for an additional transfer after a locked sequence	Arbiter keeps the manager granted for an additional transfer after a locked sequence	Arbiter does not keeps the manager granted for an additional transfer after a locked sequence	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	arbiter_changed_hmaster_during_lock	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers	HMASTER signal changed during locked transfer.	Checks that the arbiter does not change HMASTER during a locked transfer	Arbiter does not change HMASTER during a locked transfer	Arbiter changes HMASTER during a locked transfer	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Split Transfer in Arbiter	mask_hgrant_until_hsplit_assert	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12.1 Split transfer sequence	Manager should not be regranted until the subordinate is ready to complete the transfer and asserts HSPLIT.	Checks that if the manager has got split, grant must be not given to that manager until subordinate asserts hsplitx	Grant not given to the manager until subordinate asserts hsplitx	Grant given to the manager when subordinate didn't asserted hsplitx	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Split Transfer in Arbiter	grant_to_default_master_during_allmaster_split	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus master	If all managers has received a SPLIT response then the default manager is granted the bus.	Checks that If all managers has received a SPLIT response then the default manager is granted the bus.	Default manager is granted the bus when all managers has received a SPLIT.	Default manager is not granted the bus when all managers has received a SPLIT.	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Arbiter	arbiter_changed_hmaster_during_wait	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.11.3 Granting bus access	HMASTER signal changed during waited state.	Checks that the arbiter does not change HMASTER during a waited transfer	Arbiter does not change HMASTER during a waited transfer	Arbiter changes HMASTER during a waited transfer.	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Arbiter	arbiter_asserted_hmaster_ne_granted_master	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access	HMASTER signal does not reflect the granted manager.	Checks that the arbiter assert HMASTER to reflect the Granted manager	HMASTER signal reflects the granted manager	HMASTER signal does not reflect the granted manager	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Arbiter	arbiter_asserted_multi_hgrant	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access	Arbiter asserted more than one HGRANT signal.	Checks that the arbiter does not assert more than one HGRANT signal	Arbiter not asserted more than one HGRANT signal	Arbiter asserted more than one HGRANT signal	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Subordinate Selection in Decoder	decoder_not_asserted_any_hsel	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals	Decoder not asserted any HSEL signal.	Checks that the decoder does assert atleast one HSEL signal	Decoder asserted atleast one HSEL signal	Decoder not asserted atleast one HSEL signal	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Subordinate Selection in Decoder	decoder_asserted_multi_hsel	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals	Decoder asserted more than one HSEL signal.	Checks that the decoder does not assert more than one HSEL signal	Decoder not asserted more than one HSEL signal	Decoder asserted more than one HSEL signal	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Data Integrity	data_integrity_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Transaction data inconsistent with subordinate memory.	Checks that data in transaction is consistent with data in memory when the transaction completes. This checks that a WRITE transaction issued by a manager is written to memory correctly. Similarly, it checks that a READ transaction fetches the correct data from memory. The check assumes that a transaction issued by a manager completes only after response is received from the subordinate to which that transaction was routed. It also assumes that there is no other transaction that accesses an overlapping address during the period that the response is issued by the subordinate and the transaction completes in the manager that issued the transaction. Note that this check is not performed on the transactions that are routed to the default subordinate.	Data in transaction is consistent with data in memory	Data in transaction is not consistent with data in memory	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB System	Routing	slave_transaction_routing_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.1 Interconnect	Transaction not routed to the correct subordinate based on system address map.	Checks that a transaction is routed correctly to a slave port based on address. This check is not performed on default_slave if the default slave is set to -1 through svt_ahb_system_configuration :: default_slave. If svt_ahb_system_configuration :: default_slave is set to a value in the range 0 to 15, then this check is performed on the default slave also. This check is preformed on all the slaves other than the default slave irrespective of the value of svt_ahb_system_configuration :: default_slave.	Transaction routed to the correct subordinate based on system address map	Transaction not routed to the correct subordinate based on system address map	System Monitor	Group: AHB Default severity: ERROR	ERROR	svt_ahb_system_checker
AHB_COMMON	Address Phase Timing	ahb_address_phase_extended	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 1.3 Operation	A Subordinate cannot request that the address phase is extended.	Checks that address phase is not extended by the Subordinate	Address phase is started by driving HREADY high when HTRANS is NSEQ	Address phase is extended by driving HREADY low when HTRANS is NSEQ, and no extended data phase pending from a previous transaction	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	During Reset	hready_out_from_bus_high_during_reset	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset	During reset, HREADY output from bus must be HIGH	Checks that HREADY output signal from bus is HIGH when reset is active	HREADY output signal from bus is HIGH when reset is active	HREADY output signal from bus is not HIGH when reset is active	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR This check is performed when svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1.	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_write_throughput	SYNOPSYS DEFINED	Checks that the throughput of write transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of write transactions in a given interval is not less that the configured min value	Throughput of write transactions in a given interval is not less that the configured min value	Throughput of write transactions in a given interval is less that the configured min value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_write_throughput	SYNOPSYS DEFINED	Checks that the throughput of write transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of write transactions in a given interval is not more that the configured max value	Throughput of write transactions in a given interval is not more that the configured max value	Throughput of write transactions in a given interval is more that the configured max value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_read_throughput	SYNOPSYS DEFINED	Checks that the throughput of read transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of read transactions in a given interval is not less that the configured min value	Throughput of read transactions in a given interval is not less that the configured min value	Throughput of read transactions in a given interval is less that the configured min value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_read_throughput	SYNOPSYS DEFINED	Checks that the throughput of read transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of read transactions in a given interval is not more that the configured max value	Throughput of read transactions in a given interval is not more that the configured max value	Throughput of read transactions in a given interval is more that the configured max value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_min_read_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of read transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of read transactions in a given interval is not less than the configured min value	Average latency of read transactions in a given interval is not less than the configured min value	Average latency of read transactions in a given interval is less than the configured min value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_max_read_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of read transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of read transactions in a given interval is not more than the configured max value	Average latency of read transactions in a given interval is not more than the configured max value	Average latency of read transactions in a given interval is more than the configured max value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_read_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a read transaction is more than or equal to the configured min value	Checks that the latency of a read transaction is not lesser than the configured min value	Latency of a read transaction is not lesser than the configured min value	Latency of a read transaction is lesser than the configured min value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_read_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a read transaction is less than or equal to the configured max value	Checks that the latency of a read transaction is not greater than the configured max value	Latency of a read transaction is not greater than the configured max value	Latency of a read transaction is greater than the configured max value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_min_write_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of write transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of write transactions in a given interval is not less than the configured min value	Average latency of write transactions in a given interval is not less than the configured min value	Average latency of write transactions in a given interval is less than the configured min value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_max_write_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of write transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of write transactions in a given interval is not more than the configured max value	Average latency of write transactions in a given interval is not more than the configured max value	Average latency of write transactions in a given interval is more than the configured max value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_write_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a write transaction is more than or equal to the configured min value	Checks that the latency of a write transaction is not lesser than the configured min value	Latency of a write transaction is not lesser than the configured min value	Latency of a write transaction is lesser than the configured min value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_write_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a write transaction is less than or equal to the configured max value	Checks that the latency of a write transaction is not greater than the configured max value	Latency of a write transaction is not greater than the configured max value	Latency of a write transaction is greater than the configured max value	Active/Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hrdata_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HRDATA must not be X/Z	Checks that HRDATA is not X or Z	HRDATA does not contain any X or Z bits	HRDATA contains X or Z bits	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR Note: This check is performed only for the transaction with OKAY response and ERROR response having svt_ahb_system_configuration :: error_response_policy as svt_ahb_system_configuration :: CONTINUE_ON_ERROR. It is recommended that HRDATA is driven to zero when an ERROR response is given to a read transfer. When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hwdata_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HWDATA must not be X/Z	Checks that HWDATA is not X or Z	HWDATA does not contain any X or Z bits	HWDATA contains X or Z bits	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR Note: This check is performed only for the transaction with OKAY response and ERROR response having svt_ahb_system_configuration :: error_response_policy as svt_ahb_system_configuration :: CONTINUE_ON_ERROR. When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_COMMON	Response Type	zero_wait_cycle_okay	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	IDLE and BUSY transfers must receive zero wait cycle OKAY response.	Checks that IDLE and BUSY transfers receive zero wait cycle OKAY response	IDLE and BUSY transfers receive zero wait cycle OKAY response	IDLE and BUSY transfers doesn't receive zero wait cycle OKAY response	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Two Cycle Response	two_cycle_error_resp	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response	ERROR response was not completed in two cycles.	Checks that ERROR response completes in two cycles	ERROR response completes in two cycles	ERROR response was not completed in two cycles	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Response Type	non_okay_response_in_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.2 Transfer pending	Response other than OKAY response was received during wait state.	Checks that only OKAY responses are received during wait state	OKAY responses are received during wait state	OKAY responses are not received during wait state	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hresp_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HRESP must not be X/Z	Checks that HRESP is not X or Z	HRESP is not X or Z	HRESP is X or Z	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hready_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HREADY must not be X/Z	Checks that HREADY is not X or Z	HREADY does not contain any X or Z bits	HREADY contains X or Z bits	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_COMMON	Burst Length	burst_length_exceeded	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Burst length exceeded for fixed length burst.	Checks number of beats in a fixed length burst	Burst length not exceeded fixed length burst	Burst length exceeded for fixed length burst	Passive Manager	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Locked Transfers	hlock_asserted_during_non_locked_xact	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.1 Signal description	Manager should not assert lock signal in the middle of a non-locked transaction.	Checks that manager shouldn't assert hlock in the middle of a non-locked transaction	Manager not asserted hlock in the middle of a non-locked transaction	Manager asserted hlock in the middle of a non-locked transaction	Passive Manager	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hlock_check	AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list	HLOCK must not be X/Z	Checks that HLOCK is not X or Z on manager interface	HLOCK does not contain any X or Z bits	HLOCK contains X or Z bits	Passive Manager	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_COMMON	Locked Transfers	different_subordinate_addr_region_during_locked_sequence	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked Transfers	It is required that all transfers in a locked sequence are to the same Subordinate address region.	It is required that all transfers in a locked sequence are to the same subordinate address region.	Manager performing a transfer to the same subordinate address region	Manager performing a transfer to a different subordinate address region	Passive Manager and Active/Passive Subordinate	Group: AHB5 Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	htrans_not_changed_to_idle_during_error	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response	HTRANS did not change to IDLE during ERROR response.	Checks that HTRANS changes to IDLE during second cycle of ERROR response	HTRANS changes to IDLE during ERROR response	HTRANS did not change to IDLE during ERROR response	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	During Reset	htrans_idle_during_reset	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset	During reset, HTRANS must be IDLE2'b00	Checks that HTRANS output signal from manager/bus is IDLE when reset is active	HTRANS output signal from manager/bus is IDLE when reset is active	HTRANS output signal from manager/bus is not IDLE when reset is active	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR This check is performed when svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1.	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	seq_or_busy_before_nseq_during_xfer	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Manager started burst with SEQ or BUSY instead of NSEQ.	Checks that a manager started burst with SEQ or BUSY instead of NSEQ	Manager started burst with NSEQ	Manager started burst with BUSY or SEQ	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	illegal_idle2seq	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Manager attempted SEQ transfer following IDLE.	Checks for IDLE changed to SEQ	SEQ is not followed by IDLE	SEQ is followed by IDLE	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	illegal_idle2busy	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Manager attempted BUSY transfer following IDLE.	Checks for IDLE changed to BUSY	BUSY is not followed by IDLE	BUSY is followed by IDLE	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	idle_changed_to_busy_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Manager cancelled IDLE transfer during wait state and changed it to BUSY transfer.	Checks for IDLE changed to BUSY during wait state	IDLE not changed to BUSY during wait state	IDLE changed to BUSY during wait state	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	idle_changed_to_seq_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Manager cancelled IDLE transfer during wait state and changed it to SEQ transfer.	Checks for IDLE changed to SEQ during wait state	IDLE not changed to SEQ during wait state	IDLE changed to SEQ during wait state	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	ctrl_or_addr_changed_during_busy	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Control signalsother than HTRANS or address changed during BUSY.	Checks whether control signals(other than HTRANS) or address changed during BUSY	Control signals and address not changed during busy transfer	Control signals or address changed during busy transfer	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	illegal_control_transition	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals	Control signals other than HTRANS changed during burst.	Checks whether control signals(other than HTRANS) changed during burst	Control signals not changed during burst	Control signals changed during burst	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	ahb_valid_beat_address_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	valid beat address check.	Checks for valid beat address of each beat in a transaction	Beat address is getting updated correctly	Beat address not updated correctly Beat address and haddr is not same	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	illegal_address_transition	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Illegal address transition during burst.	Checks for illegal address transition during burst	Address is getting updated correctly	Address not updated correctly	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	boundry_crossing_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Burst transfer crossed boundary	Checks that burst transfer does not cross configured boundary limit	Burst transfer does not cross configured boundary limit	Burst transfer crosses configured boundary limit	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	one_k_boundry_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Burst transfer crossed 1 KB boundary.	Checks that burst transfer does not cross 1 KB boundary	Burst transfer does not cross 1 KB boundary	Burst transfer crosses 1KB boundary	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Size	hsize_too_big_for_data_width	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.3.3 Implementing a Manager on a wide bus	Manager attempted transfer size greater than data bus width.	Checks that manager attempted transfer size greater than data bus width	Manager attempted transfer size is not greater than data bus width	Manager attempted transfer size greater than data bus width	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Early Burst Termination	burst_terminated_early_after_okay	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination	Manager terminated burst early after OKAY response.	Checks that burst transaction was not terminated early: AHB manager should never terminate a burst transfer when OKAY response is received. In case of Full-AHB mode, the manager should rebuild the burst transfer in case of EBT/SPLIT/RETRY before initiating new burst.	Manager not terminated burst early after OKAY response	Manager terminated burst early after OKAY response	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	hwdata_changed_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.1.1 HWDATA	HWDATA changed during wait state.	Checks that write data does not change during waited state	Write data does not change during waited state	Write data changed during waited state	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	ctrl_or_addr_changed_end_of_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Control or address changed at the end of wait state.	Checks that control and address does not change at the end of wait state	Control signals and address not changed at the end of wait state	Control signals or address changed at the end of wait state	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR Check is not performed during reset and other than OKAY response conditions	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	ctrl_or_addr_changed_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Control or address changed during wait state.	Checks that contol and address does not change during wait state except when htrans changes from IDLE to NSEQ	Control signals and address not changed during wait state	Control signals or address changed during wait state	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR Check is not performed when htrans changes from IDLE to NSEQ other than OKAY response conditions.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	htrans_changed_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	HTRANS changed during wait state.	Checks that htrans does not change during wait state except when htrans changes from IDLE to NSEQ during wait state for all burst types BUSY to SEQ during wait state for all burst types BUSY to NSEQ during wait state for unspecified length burst BUSY to IDLE during wait state for unspecified length burst	HTRANS not changed during wait state	HTRANS changed during wait state	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	seq_or_busy_during_active_xact	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	In active transaction, SEQ or BUSY transfer should only occur after NSEQ.	Checks that a SEQ or BUSY trans only occur during active transaction after nseq	SEQ or BUSY trans occurs during active transaction after nseq	SEQ or BUSY trans occurs not during active transaction	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	trans_during_single_is_nseq	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Transfer type of a SINGLE burst is not NSEQ	Checks that transfer type of a SINGLE burst is NSEQ	Transfer type of a SINGLE burst is NSEQ	Transfer type of a SINGLE burst is not NSEQ	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hprot_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HPROT must not be X/Z	Checks that HPROT is not X or Z	HPROT does not contain any X or Z bits	HPROT contains X or Z bits	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hburst_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HBURST must not be X/Z	Checks that HBURST is not X or Z	HBURST does not contain any X or Z bits	HBURST contains X or Z bits	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hsize_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HSIZE must not be X/Z	Checks that HSIZE is not X or Z	HSIZE does not contain any X or Z bits	HSIZE contains X or Z bits	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_htrans_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HTRANS must not be X/Z	Checks that HTRANS is not X or Z	HTRANS does not contain any X or Z bits	HTRANS contains X or Z bits	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hwrite_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HWRITE must not be X/Z	Checks that HWRITE is not X or Z	HWRITE is not X or Z	HWRITE is X or Z	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_haddr_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HADDR must not be X/Z	Checks that HADDR is not X or Z	HADDR does not contain any X or Z bits	HADDR contains X or Z bits	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: addr_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	hready_out_from_slave_not_X_or_Z_when_data_phase_not_pending	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.3 Subordinate signals	HREADY output from subordinate must be either HIGH or LOW when there is no pending data phase.	Checks that HREADY output from subordinate must be either HIGH or LOW when there is no data phase pending. That is, checks that the subordinate cannot request that the address phase is extended.	HREADY output from subordinate must be either HIGH or LOW	HREADY output from subordinate is either X or Z	Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	During Reset	hready_out_from_slave_not_X_or_Z_during_reset	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset	During reset, HREADY output from subordinate must be either HIGH or LOW	Checks that HREADY output signal from subordinate is either HIGH or LOW when reset is active	HREADY output signal from subordinate is either HIGH or LOW when reset is active	HREADY output signal from subordinate is X or Z when reset is active	Passive Subordinate	Group: AHB Default severity: ERROR This check is performed when svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1.	ERROR	svt_ahb_checker
AHB_COMMON	Response Type	illegal_default_slave_resp_to_nseq_seq	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.1 Default Subordinate	Default subordinate should provide ERROR response for NON_SEQ or SEQ transfer.	Checks that for non existent memory location default subordinate should provide ERROR response for NSEQ/SEQ transfers	Default subordinate giving error response for NSEQ/SEQ transfers when accessing nonexistent address location	Default subordinate not giving error response for NSEQ/SEQ transfers when accessing nonexistent address location	Active/Passive Manager	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Subordinate Selection	invalid_hsel_assert_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.2 Multiple Subordinate select	Invalid HSEL signal asserted for selected subordinate	Checks that if invalid HSEL is asserted for selected subordinate. This is applicable only in mutli_hsel_enable mode	HSEL is asserted for selected subordinate	Invalid HSEL is asserted for selected subordinate	Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hready_in_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HREADY_IN must not be X/Z	Checks that HREADY_IN is not X or Z	HREADY_IN does not contain any X or Z bits	HREADY_IN contains X or Z bits	Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hmastlock_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HMASTLOCK must not be X/Z	Checks that HMASTLOCK is not X or Z on subordinate interface	HMASTLOCK is not X or Z	HMASTLOCK is X or Z	Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hmaster_range_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals	HMASTER should not be beyond SVT_AHB_MAX_NUM_MASTERS	Checks that HMASTER value is in valid range based on SVT_AHB_MAX_NUM_MASTERS	HMASTER value is less than SVT_AHB_MAX_NUM_MASTERS	HMASTER value is more than SVT_AHB_MAX_NUM_MASTERS	Active/Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hsel_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HSEL must not be X/Z	Checks that HSEL is not X or Z	HSEL is not X or Z	HSEL is X or Z	Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: addr_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_FULL	Two Cycle Response	two_cycle_retry_resp	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	RETRY response was not completed in two cycles.	Checks that RETRY response completes in two cycles	RETRY response completes in two cycles	RETRY response was not completed in two cycles	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Two Cycle Response	two_cycle_split_resp	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	SPLIT response was not completed in two cycles.	Checks that SPLIT response completes in two cycles	SPLIT response completes in two cycles	SPLIT response was not completed in two cycles	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_idle_or_nseq_during_no_grant	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access	Manager should drive HTRANS to IDLE or NSEQ when it does not have access to the bus.	Checks that manager drives HTRANS to IDLE or NSEQ when it does not have access to the bus	Manager drives HTRANS to IDLE or NSEQ when it does not have access to the bus	Manager not driving HTRANS to IDLE or NSEQ when it does not have access to the bus	Passive Manager	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_retry	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during RETRY response.	Checks that HTRANS changes to IDLE during second cycle of RETRY response	HTRANS changed to IDLE during RETRY response	HTRANS was not changed to IDLE during RETRY response	Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_split	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during SPLIT response.	Checks that HTRANS changes to IDLE during second cycle of SPLIT response	HTRANS changed to IDLE during SPLIT response	HTRANS was not changed to IDLE during SPLIT response	Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Signal Validity	signal_valid_hbusreq_check	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access	HBUSREQ must not be X/Z	Checks that HBUSREQ is not X or Z	HBUSREQ does not contain any X or Z bits	HBUSREQ contains X or Z bits	Passive Manager	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_FULL	Rebuild Transaction	rebuild_xact_with_valid_combination_of_bursts	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry	Manager should restart an interrupted burst with a valid combination of bursts.	Checks that the manager restarted an interrupted burst with a valid combination of bursts	Manager restarted an interrupted burst with a valid combination of bursts	Manager not restarted an interrupted burst with a valid combination of bursts	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.	ERROR	svt_ahb_checker
AHB_FULL	Rebuild Transaction	rebuild_xact_with_expected_addr	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry	Manager should restart an interrupted burst from the address of the aborted beat.	Checks that the manager restarted an interrupted burst from the address of the aborted beat	Manager restarted an interrupted burst from the address of the aborted beat	Manager not restarted an interrupted burst from the address of the aborted beat	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.	ERROR	svt_ahb_checker
AHB_FULL	Response Type	hsplit_asserted_for_non_split_master	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers	Subordinate should not assert HSPLIT corresponding to a manager it has not split earlier.	Checks that HSPLIT is not asserted for a manager that has not SPLIT earlier.	HSPLIT is not asserted for a manager that has not SPLIT earlier.	HSPLIT is asserted for a manager that has not SPLIT earlier.	Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Response Type	hsplit_asserted_for_one_cycle	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers	Subordinate should assert a bit of HSPLIT only for one clock cycle	Checks that HSPLIT is asserted for only one clock cycle	HSPLIT is asserted for only one clock cycle	HSPLIT is not asserted for only one clock cycle	Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_retry	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during RETRY response.	Checks that HTRANS changes to IDLE during second cycle of RETRY response	HTRANS changed to IDLE during RETRY response	HTRANS was not changed to IDLE during RETRY response	Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_split	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during SPLIT response.	Checks that HTRANS changes to IDLE during second cycle of SPLIT response	HTRANS changed to IDLE during SPLIT response	HTRANS was not changed to IDLE during SPLIT response	Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_FULL	Bus Grant	illegal_hgrant_on_split_resp	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers	Manager should lose the bus once it gets the split response from the subordinate.	Checks that manager loses the bus once it gets the split response from the subordinate.	Manager loses the bus once it gets the split response from the subordinate	Manager didn't lose the bus during the split response from the subordinate	Active/Passive Manager	Group: AHB Default severity: ERROR Check is constructed only when num_masters > 1	ERROR	svt_ahb_checker
AHB_FULL	Signal Validity	signal_valid_hgrant_check	AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list	HGRANT must not be X/Z	Checks that HGRANT is not X or Z	HGRANT does not contain any X or Z bits	HGRANT contains X or Z bits	Active/Passive Manager	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB_FULL	Signal Validity	signal_valid_hmaster_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HMASTER must not be X/Z	Checks that HMASTER is not X or Z	HMASTER is not X or Z	HMASTER is X or Z	Active/Passive Subordinate	Group: AHB Default severity: ERROR This is performed in full-AHB mode. When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_Lite	Response Type	ahb_lite_split_response	AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses	SPLIT response was received when configured as AHB Lite system.	Checks that SPLIT responses are not received when configured for AHB Lite	SPLIT responses are not received when configured for AHB Lite	SPLIT responses are received when configured for AHB Lite	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
AHB_Lite	Response Type	ahb_lite_retry_response	AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses	RETRY response was received when configured as AHB Lite system.	Checks that RETRY responses are not received when configured for AHB Lite	RETRY responses are not received when configured for AHB Lite	RETRY responses are received when configured for AHB Lite	Active/Passive Manager and Passive Subordinate	Group: AHB Default severity: ERROR	ERROR	svt_ahb_checker
ARM11/AHB_V6 Exclusive Accesses	Two Cycle Response	two_cycle_xfail_resp	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.3.1 Exclusive Access Protocol	XFAIL response was not completed in two cycles.	Checks that XFAIL response completes in two cycles	XFAIL response completes in two cycles	XFAIL response does not completed in two cycles	Active Manager	Group: AHB_V6 Default severity: ERROR Applicable for AHB_V6 extention AHB_LITE	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Valid Unaligned Transfer	valid_unaligned_transfer	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1.2 Burst, Unaligned accesses and Byte Lane Strobes	HUNALIGN should be asserted for an unaligned transfer	Checks that HUNALIGN signal is correctly set for unaligned transfers. Based on ARMv6 AMBA Extension Spec (Document No: PR022-GENC-001011) section 3.1.2, example 3.1.2.2 in the document and ARM discussions following items are mandatory. It would be mandatory for any initiator using the ARM11 extensions generating an unaligned AHB transfer to drive HUNALIGN=1 If HUNALIGN=0 it tells the target that HADDR will be fully AHB v2.0 compliant and HADDR will be aligned to HSIZE	HUNALIGN is 1 for the unaligned transfer	HUNALIGN is 0 for the unaligned transfer	Passive Manager and Active/Passive Subordinate	Group: AHB_V6 Default severity: ERROR Applicable for AHB_V6 extention AHB_LITE	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Signal Stability	hunalign_changed_during_transfer	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HUNALIGN should not change in middle of a transfer	Checks that HUNALIGN output signal from manager dosenot changes its value in middle of a transfer	HUNALIGN is stable in a transfer	HUNALIGN is not stable in a transfer	Passive Manager and Active/Passive Subordinate	Group: AHB_V6 Default severity: ERROR Applicable for AHB_V6 extention AHB_LITE	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Valid Byte Lane Strobes	valid_byte_lane_for_hbstrb	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HRDATA/HWDATA byte lanes corresponding to HBSTRB should be selected	Checks that HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB signal which have value 1	HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB	Invalid HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB	Passive Manager and Active/Passive Subordinate	Group: AHB_V6 Default severity: ERROR Applicable for AHB_V6 extention AHB_LITE	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Signal Validity	signal_valid_hunalign_check	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HUNALIGN must not be X/Z	Checks that HUNALIGN is not X or Z	HUNALIGN is not X or Z	HUNALIGN is X or Z	Passive Manager and Active/Passive Subordinate	Group: AHB_V6 Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. Applicable for AHB_V6 extention AHB_LITE During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Signal Validity	signal_valid_hbstrb_check	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HBSTRB must not be X/Z	Checks that HBSTRB is not X or Z	HBSTRB does not contain any X or Z bits	HBSTRB contains X or Z bits	Passive Manager and Active/Passive Subordinate	Group: AHB_V6 Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. Applicable for AHB_V6 extention AHB_LITE During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB5 Extended Memory Types	Signal Validity	signal_valid_hprot_ex_range_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.9 Memory types	HPROT signal is not having the valid value	Checks that Extended_Memory_Type supporting HPROT[6:2] is having valid values	HPROT[6:2] value is in valid range	HPROT[6:2] value is not in valid range	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.	ERROR	svt_ahb_checker
AHB5 Secure Transfers	Signal Validity	signal_valid_hnonsec_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HNONSEC must not be X/Z	Checks that HNONSEC is not X or Z	HNONSEC is not X or Z	HNONSEC is X or Z	Passive Manager and Active/Passive Subordinate	Group: AHB5 Default severity: ERROR When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset. During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.	ERROR	svt_ahb_checker
AHB_Lite_Multilayer	Rebuild Transaction	rebuild_xact_with_valid_combination_of_bursts	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination	Manager should restart an interrupted burst with a valid combination of bursts.	Checks that the manager restarted an interrupted burst with a valid combination of bursts	Manager restarted an interrupted burst with a valid combination of bursts	Manager not restarted an interrupted burst with a valid combination of bursts	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.	ERROR	svt_ahb_checker
AHB_Lite_Multilayer	Rebuild Transaction	rebuild_xact_with_expected_addr	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination	Manager should restart an interrupted burst from the address of the aborted beat.	Checks that the manager restarted an interrupted burst from the address of the aborted beat	Manager restarted an interrupted burst from the address of the aborted beat	Manager not restarted an interrupted burst from the address of the aborted beat	Passive Manager and Active/Passive Subordinate	Group: AHB Default severity: ERROR This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.	ERROR	svt_ahb_checker
SYSTEM: ACE	CMO	forward_cmos_to_slave_check	Synopsys Defined	Monitor check that cache maintenance transactions are forwarded to slaves if forward_cmos_to_slaves_check_enable is set in the slave configuration	Checks that cache maintenance transactions are forwarded to slaves If two or more slaves are in the same address space of the memory map, this check is performed on each of the slave ports with overlapping address.	When cache maintenance transactions are forwarded to slaves if forward_cmos_to_slaves_check_enable is set in the slave configuration	When cache maintenance transactions are not forwarded to slaves if forward_cmos_to_slaves_check_enable is set in the slave configuration		The check is performed only if forward_cmos_to_slaves_check_enable is set in the port configuration of the slave	ERROR	svt_axi_system_checker
SYSTEM: ACE	Exclusive Access	exclusive_snoop_propagation_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.3.1 Minimum PoS Exclusive Monitor	Monitor Checks that if interconnect stopped snoop propagation for exclusive transaction that was not successful	Checks if interconnect stopped snoop propagation for exclusive transaction that was not successful	When interconnect stopped snoop propagation for exclusive transaction that was not successful	When interconnect still send snoop propagation for exclusive transaction			ERROR	svt_axi_system_checker
SYSTEM: ACE	Exclusive Access	exclusive_store_from_valid_state_sys_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store	Monitor Checks that if cacheline is in invalid state then exclusive store transaction is not issued	Checks that if cacheline is in invalid state then exclusive store transaction is not issued	When cacheline is in invalid state then exclusive store transaction is not issued	When cacheline is in valid state then exclusive store transaction is not issued			ERROR	svt_axi_system_checker
SYSTEM: ACE	Exclusive Access	exclusive_load_from_valid_state_sys_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load	Monitor Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED	Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED	When cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED	When cacheline is in valid state then exclusive load transaction is issued only as READCLEAN or READSHARED			ERROR	svt_axi_system_checker
SYSTEM: ACE	Exclusive Access	restart_exclusive_seq_post_cache_line_invalidation_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store	Monitor Check that an exclusive sequence is reset after a cacheline is invalidated by a snoop. After a snoop invalidates a cacheline, an exclusive load must always be sent prior to sending the exclusive store	Checks that an exclusive sequence is reset after a cacheline is invalidated by a snoop. This checks that after a snoop invalidates a cacheline, an exclusive load is always sent prior to sending the exclusive store.	When an exclusive sequence is reset after a cacheline is invalidated by a snoop. After a snoop invalidates a cacheline, an exclusive load must always be sent prior to sending the exclusive store	When an exclusive sequence is not reset after a cacheline is invalidated by a snoop			ERROR	svt_axi_system_checker
SYSTEM: ACE	Barrier	outstanding_master_barrier_transaction_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements	Monitor Check that an ACE master interface must not issue more than 256 outstanding barrier transactions	System monitor should ensure that an ACE master interface must not issue more than 256 outstanding barrier transactions	When ACE master interface must not issue more than 256 outstanding barrier transactions	When ACE master interface issue more than 256 outstanding barrier transactions			ERROR	svt_axi_system_checker
SYSTEM: ACE	Routing	no_slave_respond_with_decerr_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A3.4.5 Read and write response structure	Monitor Check that each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it	System monitor should ensure that each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it	When each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it	When no slave responds with DECERR if any transaction is routed to it with an address range			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	master_dvm_no_data_transfer_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.1.1 Transaction groups	Monitor Check that no data is transferred for a DVM transaction	Checks that no data is transferred for a DVM transaction	When no data is transferred for a DVM transaction	When a snoop data transfer is observed for associated DVM Snoop transaction			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	interconnect_dvm_response_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses	Monitor Check that the interconnect sets RRESP value of a DVM transaction correctly	Checks that the interconnect sets RRESP value of a DVM transaction correctly based on the following: The interconnect component gathers all response values and responds to the originator as follows: if CRRESP is 0b00000 for all responses, the interconnect component sets RRESP to 0b0000. If CRRESP is 0b00010 for any responses, the interconnect component sets RRESP to 0b0010.	When the interconnect sets RRESP value of a DVM transaction correctly	When the interconnect not sets RRESP value of a DVM transaction correctly			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	interconnect_dvm_complete_issue_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions	Monitor Check that the interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master	Checks that the interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master.	When interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master	When DVM Complete snoop transaction is received, but a DVM Complete on the read channel is not observed for port			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	master_dvm_complete_issue_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions	Monitor Check that a DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master.	Checks that a DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master	When DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master	When DVM Complete is issued on read channel before handshake on snoop address channel of associated DVM Sync			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	interconnect_dvm_response_timing_check	Synopsys Defined	Monitor Check that the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync after all snoop responses are received.	Checks that the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync. This check ensures that this acknowledgement is sent only after all snoop responses are received.	When the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync after all snoop responses are received	When response is observed to DVM transaction, but response of associated snoop was not yet received			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	interconnect_dvm_sync_snoop_transaction_association_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions	Monitor Check that interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component.	Checks that interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component	When interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component	When DVM Sync snoop transaction was not sent on port for corresponding DVM Sync %0s sent on read channel			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	interconnect_dvm_operation_snoop_transaction_association_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.1 DVM message transactions	Monitor Check that interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component.	Checks that interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component.	When interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component	When DVM Operation snoop transaction was not sent on port for corresponding DVM Operation sent on read channel			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	interconnect_dvm_complete_dvm_sync_association_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions	Monitor Check that a DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel	Checks that a DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel	When DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel	When Received DVM Complete transaction on snoop channel, but no outstanding DVM Sync found on this port			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	master_outstanding_snoop_dvm_sync_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.4 DVM Complete	Monitor checks that maximum number of outstanding DVM Sync messages that a master must be able to accept is 256. The number of outstanding DVM Sync messages accepted by master exceeds 256.	Checks that maximum number of outstanding DVM Sync messages that a master must be able to accept is 256. This check fires an error if the number of outstanding DVM Sync messages exceeds 256.	When maximum number of outstanding DVM Sync messages that a master must be able to accept is 256	When maximum number of outstanding DVM Sync messages that a master must be able to accept is exceeds 256			ERROR	svt_axi_system_checker
SYSTEM: ACE	DVM	master_outstanding_dvm_sync_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions	Monitor Check that a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction	Checks that a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction	When a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction	When a component not have only one outstanding DVM Sync transaction			ERROR	svt_axi_system_checker
SYSTEM: ACE	Data Integrity	data_integrity_with_outstanding_coherent_write_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.5.1 Interconnect read from main memory or peripheral device	Monitor Check that data returned in a coherent read transaction matches that of a WRITEBACK/WRITECLEAN transaction that was in progress when the read was initiated	Checks that the read data returned for a coherent read is the same as that of a WRITEBACK or WRITECLEAN transaction which was in progress when the read was initiated. This is to check that an interconnect that does speculative reads re-fetches the data in a scenario where the preceding WRITEBACK/WRITECLEAN did not complete and none of the snoops returned data. For example, consider that a WRITEBACK was in progress while a read is initiated by the master. If the interconnect does speculative reads, the speculative read may return stale data since the WRITEBACK is not complete. If none of the snoops return data as well, the interconnect should re-fetch data after the completion of the WRITEBACK.	When data returned in a coherent read transaction matches that of a WRITEBACK/WRITECLEAN transaction that was in progress when the read was initiated	When data returned in a coherent read transaction is not matches that of a WRITEBACK/WRITECLEAN transaction that was in progress when the read was initiated		This check is applicable only when: svt_axi_system_configuration :: posted_write_xacts_enable is not set.	ERROR	svt_axi_system_checker
SYSTEM: ACE	Routing	slave_read_xact_timing_relative_to_last_posted_write_xact_check	Synopsys Defined	Monitor Check that a read transaction is routed to the slave only after the last posted write transaction with overlapping address from the same port has completed at the slave	Checks that a READ transaction is routed to a slave only after a previous WRITE transaction from the same port and with an overlapping address completes at the slave. This is required in posted writes to ensure that a READ transaction retreives the same data as the previous WRITE transaction.	When read transaction is routed to the slave only after the last posted write transaction with overlapping address from the same port has completed at the slave	When read transaction is not routed to the slave only after the last posted write transaction with overlapping address from the same port has completed at the slave		This check is applicable only when: svt_axi_system_configuration :: posted_write_xacts_enable is set.	ERROR	svt_axi_system_checker
SYSTEM: ACE	Cache Coherency	cacheline_and_memory_coherency_check_per_xact	Synopsys Defined	Monitor Check that if cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory. This check may not pass if a transaction to the slave is in the interconnect's buffer by the time a coherent transaction completes.	Checks that if all cachelines are clean, the data in cacheline is consistent with data in memory. This check is done on a per transaction basis at the end of each coherent transaction. Note that in some implementations a transaction to the memory could still be in the interconnect's buffer in which case this check would fail. Hence this check is issued as a warning, rather than an error.	When cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory	This check may not pass if a transaction to the slave is in the interconnect's buffer by the time a coherent transaction completes		This check is not performed if the agents connected to the interfaces are configured to work in passive mode. .	WARNING	svt_axi_system_checker
SYSTEM: ACE	Cache Coherency	interconnect_generated_write_xact_to_update_main_memory_check	Synopsys Defined	Monitor Check that if a snoop response has the PassDirty response asserted, and the interconnect does not assert the PassDirty transaction response for the initiating master, the interconnect must generate a write transaction to update main memory.		Checks that the interconnect generated slave write transaction to update main memory when: 1) A snoop response has the PassDirty response asserted, and the interconnect does not assert the PassDirty transaction response for the initiating master 2) The interconnect has provided a read response to an initiating master before it has received all the snoop responses and a later snoop response has PassDirty asserted This check passes when the system monitor associates interconnect generated slave write transaction to the corresponding snoop transaction that returned dirty data.	This check reports an ERROR at the end of simulation, if the interconnect fails to generate slave write transaction under the above described situations.		The master_slave_xact_data_integrity_check must be enabled for this check to function correctly. svt_axi_system_configuration :: interconnect_generated_write_xact_to_update_main_memory_check_enable must to set to 1 to enable this check.	ERROR	svt_axi_system_checker
SYSTEM: ACE	Cache Coherency	cacheline_and_memory_coherency_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model	Monitor Check that if cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory	Checks that if all cachelines are clean, the data in cacheline is consistent with data in memory	When all cachelines are clean, the data in cacheline is consistent with data in memory	When all cachelines are clean, the data in cacheline is not consistent with data in memory		This check is not performed if the agents connected to the interfaces are configured to work in passive mode.	ERROR	svt_axi_system_checker
SYSTEM: ACE	Cache Coherency	no_two_cachelines_in_dirty_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model	Monitor Check that no two masters have the same cacheline in the dirty state	Checks that no two masters have the same cacheline in dirty state	When no two masters have the same cacheline in dirty state	When two masters have the same cacheline in dirty state		This check is not performed if the agents connected to the interfaces are configured to work in passive mode.	ERROR	svt_axi_system_checker
SYSTEM: ACE	Cache Coherency	no_two_cachelines_in_unique_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model	Monitor Check that no two masters have the same cacheline in the unique state	Checks that no two masters have the same cacheline in unique state	When no two masters have the same cacheline in the unique state	When two masters have the same cacheline in the unique state		This check is not performed if the agents connected to the interfaces are configured to work in passive mode.	ERROR	svt_axi_system_checker
SYSTEM: ACE	Cache Coherency	overlapping_addr_sequencing_check	Synopsys Defined	Monitor Check that if two masters access the same cache line, one master is sequenced after the other	Checks that if two masters access the same cache line, one master is sequenced after the other	When two masters access the same cache line, one master is sequenced after the other	When two masters does not access the same cache line			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent And Snoop	coherent_and_snoop_data_match_check	Synopsys Defined	Monitor Check that data returned to initiating master matches the data received from snoop transaction	Checks that data returned to initiating master matches the data received from snoop transaction	When data returned to initiating master matches the data received from snoop transaction	When data returned to initiating master does not matches the data received from snoop transaction			ERROR	svt_axi_system_checker
SYSTEM: ACE	Snoop Response	snoop_data_consistency_check	Synopsys Defined	Monitor Check that data returned from all snoop transactions are consistent	Checks that data returned from all snoop transactions are consistent	When data returned from all snoop transactions are consistent	When data returned from all snoop transactions are inconsistent			ERROR	svt_axi_system_checker
SYSTEM: ACE	Snoop Response	snoop_resp_passdirty_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor Check that no two responses to a snoop transaction have the PassDirtyCRRESP[2] bit asserted	Checks that no two responses to a snoop transaction have the PassDirty(CRRESP[2]) bit asserted	When no two responses to a snoop transaction have the PassDirty(CRRESP[2]) bit asserted	When two responses to a snoop transaction have the PassDirty(CRRESP[2]) bit asserted			ERROR	svt_axi_system_checker
SYSTEM: ACE	Snoop Response	snoop_resp_wasunique_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor Check that no two responses to a snoop transaction have the WasUniqueCRRESP[4] bit asserted	Checks that no two responses to a snoop transaction have the WasUnique(CRRESP[4]) bit asserted	When no two responses to a snoop transaction have the WasUnique(CRRESP[4]) bit asserted	When two responses to a snoop transaction have the WasUnique(CRRESP[4]) bit asserted			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent Response	coherent_resp_passdirty_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.4 Transaction responses from the interconnect	Monitor Check that the PassDirty response to initiating master is correct	Checks that the PassDirty response to initiating master is correct	When the PassDirty response to initiating master is correct	When the PassDirty response to initiating master is not correct			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent Response	coherent_resp_isshared_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.4 Transaction responses from the interconnect	Monitor Check that the IsShared response to initiating master is correct	Checks that the IsShared response to initiating master is correct	When the IsShared response to initiating master is correct	When the IsShared response to initiating master is not correct			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent Response	coherent_resp_start_conditions_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor Check that the response to a coherent transaction is not started before sufficient information from snooped masters are obtained	Checks that the response to a coherent transaction is not started before sufficient information from snooped masters are obtained	When the response to a coherent transaction is not started before sufficient information from snooped masters are obtained	When the response to a coherent transaction is started before sufficient information from snooped masters are obtained			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent And Snoop	coherent_xact_with_no_snoop_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.3 Issuing snoop transactions	Monitor Check that READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters	Checks that READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters	When READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters	When READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT cause a snoop of cached masters			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent And Snoop	snoop_not_sent_to_initiating_master_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.3 Issuing snoop transactions	Monitor Check that a snoop is not sent to the initiating master	Checks that a snoop is not sent to the initiating master	When snoop is not sent to the initiating master	When snoop is sent to the initiating master			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent And Snoop	coherent_snoop_prot_type_match_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling	Monitor Check that the security level determined by signal ACPROT[1] of the snoop transaction matches the security level of corresponding coherent transaction determined by signal AxPROT[1]	Monitor Check that the security level (determined by signal ACPROT[1]) of the snoop transaction matches the security level of corresponding coherent transaction (determined by signal AxPROT[1])	When the security level (determined by signal ACPROT[1]) of the snoop transaction matches the security level of corresponding coherent transaction (determined by signal AxPROT[1])	When the security level (determined by signal ACPROT[1]) of the snoop transaction does not matches the security level of corresponding coherent transaction (determined by signal AxPROT[1])			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent And Snoop	coherent_snoop_domain_match_check	Synopsys Defined	Monitor Check that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master	Checks that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master	When the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master	When the port on which snoop transaction is not received corresponds to the domain indicated in coherent transaction of initiating master			ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent And Snoop	coherent_snoop_type_match_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.1 Mapping coherency operations to snoop operations	Monitor Check that the snoop transaction type corresponds to the coherent transaction type of initiating master	Checks that the snoop transaction type corresponds to the coherent transaction type of initiating master	When Snoop corresponding to the coherent transaction must be one according to the coherent to snoop transaction mapping	When Snoop corresponding to the coherent transaction is not according to the coherent to snoop transaction mapping		This check is applicable only when: When is_coherent_to_snoop_type_match bit is set to 1 than check will pass.	ERROR	svt_axi_system_checker
SYSTEM: ACE	Coherent And Snoop	snoop_addr_matches_coherent_addr_check	Synopsys Defined	Monitor Check that the address of a snoop transaction must match one of the outstanding coherent transactions	Checks that the address of a snoop transaction matches address of one of the outstanding coherent transactions.	When address of a snoop transaction matches address of one of the outstanding coherent transactions	When address of a snoop transaction does not matches address of one of the outstanding coherent transactions		The VIP requires that svt_axi_port_configuration :: cache_line_size of ACE_LITE port type matches that of AXI_ACE port types. If cache line size of ACE_LITE and AXI_ACE ports does not match, this check would misfire.	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Data Integrity	write_byte_count_match_across_interconnect	Synopsys Defined	Monitor check that the effective number of bytes bytes for which strobe is asserted of write transactions sent by masters match the effective number of bytes for write transactions sent by interconnect to slave	Checks that the effective number of bytes for write transactions sent by master components match that which are sent by the interconnect to the slaves. This basically checks for spurious writes from the interconnect. The effective write byte count is the number of bytes for which write strobe is asserted. If there are writes generated by the interconnect because dirty data returned by a snoop could not be passed back to a master, the effective write byte count includes the number of bytes in a snoop also.					ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	M2S Correlation	eos_unmapped_master_xact	Synopsys Defined	Monitor check that all master transactions are correlated to corresponding slave transactions	At the end of the simulation if there are master transactions that could not be associated to corresponding slave transactions, this error is issued.	When all master transactions are correlated to corresponding slave transactions	When Found no slave transaction corresponding to master transaction, Unmapped master xact		This check is applicable only when: svt_axi_system_configuration :: posted_write_xacts_enable is set.	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Memory Type	eos_unmapped_non_modifiable_xact	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.4.1 Memory type requirements	Monitor check that all non-modifiable transactions are made visible to the final destination in a timely manner	At the end of simulation there should be no non-modifiable transaction that hasn't been mapped to a slave transaction. If such a transaction exists it shows that a non-modifiable transaction hasn't been made visible at the slave, which is not allowed	When all non-modifiable transactions are made visible to the final destination in a timely manner When non-modifiable upstream address is routed to register space of DUT, and no downstream traffic expected	When no downstream transaction found corresponding to non-modifiable upstream transaction. When non-modifiable upstream address is not routed to register space of DUT, and no downstream traffic observed For coherent transactions, whenever a downstream traffic is exepected but not observed		This check is applicable only when either: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set to 1 in system configuration or svt_axi_system_configuration :: posted_write_xacts_enable is set to 1 in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Memory Type	device_non_bufferable_response_match_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.4.1 Memory type requirements	Monitor check that for device non-bufferable transactions, responses are obtained from the final destination	For device non-bufferable transactions, responses must be obtained from the final destination. Checks that the timing of the response of the master transaction is after that of the corresponding slave transaction and that the responses match.	When for device non-bufferable transactions, responses are obtained from the final destination	When for device non-bufferable transactions, responses are not obtained from the final destination		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Ordering	ordering_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, transactions with the same ID to the same slave must be ordered	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, transactions in the same direction to the same slave with the same ID, must be ordered irrespective of the address	When for non-modifiable transactions, transactions with the same ID to the same slave must be ordered	When for non-modifiable transactions, transactions with the same ID to the same slave is not in ordered		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Attributes Propagation	cache_type_match_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, cache_type matches between master transaction and corresponding slave transaction for all bits except the bufferable bit cache_type[0]	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the cache_type should match between master transaction and corresponding slave transaction, except for ARCACHE[0]/AWCACHE[0].	When for non-modifiable transactions, cache_type matches between master transaction and corresponding slave transaction for all bits except the bufferable bit (cache_type[0])	When for non-modifiable transactions, cache_type is not matches between master transaction and corresponding slave transaction for all bits except the bufferable bit (cache_type[0])		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Attributes Propagation	burst_size_match_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, burst_size matches between master transaction and corresponding slave transaction	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_size should match between master transaction and corresponding slave transaction	When for non-modifiable transactions, burst_size matches between master transaction and corresponding slave transaction	When for non-modifiable transactions, burst_size is not matches between master transaction and corresponding slave transaction		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Attributes Propagation	burst_type_match_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, burst_type matches between master transaction and corresponding slave transaction	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_type should match between master transaction and corresponding slave transaction	When for non-modifiable transactions, burst_type matches between master transaction and corresponding slave transaction	When for non-modifiable transactions, burst_type is not matches between master transaction and corresponding slave transaction		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Attributes Propagation	burst_length_match_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, burst_length matches between master transaction and corresponding slave transaction	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_length should match between master transaction and corresponding slave transaction if burst_length <= 16. For larger burst lengths a transaction could get split if getting routed to an AXI interface that doesn't support burst length > 16. This check is not done when burst_length > 16.	When for non-modifiable transactions, burst_length matches between master transaction and corresponding slave transaction	When for non-modifiable transactions, burst_length is not matches between master transaction and corresponding slave transaction		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Attributes Propagation	region_match_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, region matches between master transaction and corresponding slave transaction	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the region should match between master transaction and corresponding slave transaction	When for non-modifiable transactions, region matches between master transaction and corresponding slave transaction	When for non-modifiable transactions, region is not matches between master transaction and corresponding slave transaction		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Attributes Propagation	prot_type_match_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, prot_type matches between master transaction and corresponding slave transaction	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the prot_type should match between master transaction and corresponding slave transaction	When for non-modifiable transactions, prot_type matches between master transaction and corresponding slave transaction	When for non-modifiable transactions, prot_type is not matches between master transaction and corresponding slave transaction		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Attributes Propagation	atomic_type_match_for_non_modifiable_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable	Monitor check that for non-modifiable transactions, atomic_type matches between master transaction and corresponding slave transaction	For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the atomic_type should match between master transaction and corresponding slave transaction	When for non-modifiable transactions, atomic_type matches between master transaction and corresponding slave transaction	When for non-modifiable transactions, atomic_type is not matches between master transaction and corresponding slave transaction		This check is applicable only when: svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Data Integrity	master_slave_xact_data_integrity_check	Synopsys Defined	Monitor Check that data in slave transaction matches that in the master transaction	Checks that the data in a slave transaction is the same as that of the corresponding master transaction. In order to perform this check, slave transactions are correlated to corresponding master transactions. When only the former is set, this check is done only on non-modifiable transactions.	When data in slave transaction matches that in the master transaction	When data in slave transaction is not matches that in the master transaction		This check is done only when either of svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable, svt_axi_system_configuration :: posted_write_xacts_enable or svt_axi_system_configuration :: master_slave_xact_data_integrity_check_enable is set.	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Data Integrity	data_integrity_check	Synopsys Defined	Monitor Check that data is fetched and routed correctly by the interconnect	Checks that data in transaction is consistent with data in memory when the transaction completes. This checks that a WRITE transaction issued by a master is written to memory correctly. Similarly, it checks that a READ transaction fetches the correct data from memory. The check assumes that a transaction issued by a master completes only after response is received from the slave to which that transaction was routed. It also assums that there is no other transaction that accesses an overlapping address during the period that the response is issed by the slave and the transaction completes in the master that issued the transaction. In ACE, this check is issued only when the snoop has not returned any data and data is fetched from memory or when data is written to memory.	When data is fetched and routed correctly by the interconnect	When data is not fetched and routed correctly by the interconnect		This check is applicable only when: svt_axi_system_configuration :: posted_write_xacts_enable is not set.	ERROR	svt_axi_system_checker
SYSTEM: AXI3 Onwards	Routing	slave_transaction_routing_check	Synopsys Defined	Monitor Check that transaction is routed to the correct slave based on address	Checks that a transaction is routed correctly to a slave port based on address	When transaction is routed correctly to a slave port based on address	When transaction is not routed correctly to a slave port based on address			ERROR	svt_axi_system_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_ctrl_csysreq_stable_till_csysack_check	AXI low-power interface	while exiting from low power state, csysreq has gone low before the cactive, csysack have gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_ctrl_csysack_timeout_after_cactive_check	AXI low-power interface	after cactive, csysreq have gone high, timedout waiting for csysack to go high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_ctrl_cactive_stable_till_csysreq_csysack_check	AXI low-power interface	while exiting from low power state, cactive has gone low before the csysack has gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_ctrl_csysack_before_cactive_check	AXI low-power interface	while exiting from low power state, csysack has gone high before the cactive has gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_ctrl_cactive_timeout_after_csysreq_check	AXI low-power interface	after csysreq has gone high, timedout waiting for cactive to go high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_ctrl_csysreq_stable_till_cactive_check	AXI low-power interface	while exiting from low power state, csysreq has gone low before the cactive has gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_prp_csysreq_stable_till_csysack_check	AXI low-power interface	while exiting from low power state, csysreq has gone low before the csysack has gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_prp_csysack_timeout_after_csysreq_check	AXI low-power interface	after cactive, csysreq have gone high, timedout waiting for csysack to go high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_prp_cactive_stable_till_csysreq_csysack_check	AXI low-power interface	while exiting from low power state, cactive has gone low before the csysreq, csysack have gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_prp_csysack_before_csysreq_check	AXI low-power interface	while exiting from low power state, csysack has gone high before the csysreq has gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_prp_csysreq_timeout_after_cactive_check	AXI low-power interface	after cactive has gone high, timedout waiting for csysreq to go high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_prp_cactive_stable_till_csysreq_check	AXI low-power interface	while exiting from low power state, cactive has gone low before the csysreq has gone high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Exit From LP	exit_from_lp_csysack_before_cactive_csysreq_check	AXI low-power interface	while exiting from low power state, csysack has gone high before cactive/csysreq going high						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_csysreq_stable_till_csysack_check	AXI low-power interface	csysreq has gone high without waiting for csysack to go low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_csysack_timeout_after_csysreq_check	AXI low-power interface	after csysreq has gone low, timedout waiting for csysack to go low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_cactive_stable_till_csysreq_csysack_check	AXI low-power interface	while entering into low power state, cactive has gone high without waiting for csysreq and csysack to go low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_csysack_before_csysreq_check	AXI low-power interface	after cactive has gone low, csysack has gone low before csysreq going low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_csysreq_timeout_after_cactive_check	AXI low-power interface	after cactive has gone low, timedout waiting for csysreq to go low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_cactive_stable_till_csysreq_check	AXI low-power interface	while entering into low power state, cactive has gone high without waiting for csysreq to go low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_csysack_before_cactive_check	AXI low-power interface	while entering into low power state, csysack has gone low before cactive going low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Entry To LP	entry_to_lp_csysreq_before_cactive_check	AXI low-power interface	while entering into low power state, csysreq has gone low before cactive going low						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Signal Validity	signal_valid_csysack_check	AXI low-power interface	X/Z on the csysack signal						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Signal Validity	signal_valid_csysreq_check	AXI low-power interface	X/Z on the csysreq signal						ERROR	svt_axi_lp_checker
PORT: AXI_LP	Signal Validity	signal_valid_cactive_check	AXI low-power interface	X/Z on the cactive signal						ERROR	svt_axi_lp_checker
ACE	Outstanding	no_outstanding_write_transaction_with_same_awid	Synopsys Defined	Monitor checks that master must not drive same AWID transaction when there is a write request or ongoing write outstanding transaction with same AWID	Checks that there is no outstanding transaction with same awid	When there is no outstanding transaction with same awid	When there is outstanding transaction with same awid		This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE	Outstanding	no_outstanding_read_transaction_with_same_arid	Synopsys Defined	Monitor checks that master must not drive same ARID transaction when there is a read request or ongoing read outstanding transaction with same ARID	Checks that there is no outstanding transaction with same arid	When there is no outstanding transaction with same arid	When there is outstanding transaction with same arid		This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_min_write_bandwidth_check	Synopsys Defined	Monitor Check that the bandwidth of write transactions in a given interval is more than or equal to the configured min value	Checks that the bandwidth of write transactions in a given interval is not less that the configured min value	When the bandwidth of write transactions in a given interval is not less that the configured min value	When the bandwidth of write transactions in a given interval is less that the configured min value		This check is applicable only when: perf_min_write_bandwidth is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_max_write_bandwidth_check	Synopsys Defined	Monitor Check that the bandwidth of write transactions in a given interval is less than or equal to the configured max value	Checks that the bandwidth of write transactions in a given interval is not more that the configured max value	When the bandwidth of write transactions in a given interval is not more that the configured max value	When the bandwidth of write transactions in a given interval is more that the configured max value		This check is applicable only when: perf_max_write_bandwidth is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_min_read_bandwidth_check	Synopsys Defined	Monitor Check that the bandwidth of read transactions in a given interval is more than or equal to the configured min value	Checks that the bandwidth of read transactions in a given interval is not less that the configured min value	When the bandwidth of read transactions in a given interval is not less that the configured min value	When the bandwidth of read transactions in a given interval is less that the configured min value		This check is applicable only when: perf_min_read_bandwidth is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_max_read_bandwidth_check	Synopsys Defined	Monitor Check that the bandwidth of read transactions in a given interval is less than or equal to the configured max value	Checks that the bandwidth of read transactions in a given interval is not more that the configured max value	When the bandwidth of read transactions in a given interval is not more that the configured max value	When the bandwidth of read transactions in a given interval is more that the configured max value		This check is applicable only when: perf_max_read_bandwidth is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_min_write_throughput_check	Synopsys Defined	Monitor Check that the throughput of write transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of write transactions in a given interval is not less that the configured min value	When the throughput of write transactions in a given interval is not less that the configured min value	When the throughput of write transactions in a given interval is less that the configured min value		This check is applicable only when: perf_min_write_throughput is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_max_write_throughput_check	Synopsys Defined	Monitor Check that the throughput of write transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of write transactions in a given interval is not more that the configured max value	When the throughput of write transactions in a given interval is not more that the configured max value	When the throughput of write transactions in a given interval is more that the configured max value		This check is applicable only when: perf_max_write_throughput is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_min_read_throughput_check	Synopsys Defined	Monitor Check that the throughput of read transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of read transactions in a given interval is not less that the configured min value	When the throughput of read transactions in a given interval is not less that the configured min value	When the throughput of read transactions in a given interval is less that the configured min value		This check is applicable only when: perf_min_read_throughput is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_max_read_throughput_check	Synopsys Defined	Monitor Check that the throughput of read transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of read transactions in a given interval is not more that the configured max value	When the throughput of read transactions in a given interval is not more that the configured max value	When the throughput of read transactions in a given interval is more that the configured max value		This check is applicable only when: perf_max_read_throughput is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_avg_min_read_xact_latency_check	Synopsys Defined	Monitor Check that the average latency of read transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of read transactions in a given interval is not less than the configured min value	When the average latency of read transactions in a given interval is not less than the configured min value	When the average latency of read transactions in a given interval is less than the configured min value		This check is applicable only when: perf_avg_min_read_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_avg_max_read_xact_latency_check	Synopsys Defined	Monitor Check that the average latency of read transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of read transactions in a given interval is not more than the configured max value	When the average latency of read transactions in a given interval is not more than the configured max value	When the average latency of read transactions in a given interval is more than the configured max value		This check is applicable only when: perf_avg_max_read_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_min_read_xact_latency_check	Synopsys Defined	Monitor Check that the latency of a read transaction is more than or equal to the configured min value	Checks that the latency of a read transaction is not lesser than the configured min value	When the latency of a read transaction is not lesser than the configured min value	When lthe latency of a read transaction is lesser than the configured min value		This check is applicable only when: perf_min_read_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_max_read_xact_latency_check	Synopsys Defined	Monitor Check that the latency of a read transaction is less than or equal to the configured max value	Checks that the latency of a read transaction is not greater than the configured max value	When the latency of a read transaction is not greater than the configured max value	When the latency of a read transaction is greater than the configured max value		This check is applicable only when: perf_max_read_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_avg_min_write_xact_latency_check	Synopsys Defined	Monitor Check that the average latency of write transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of write transactions in a given interval is not less than the configured min value	When the average latency of write transactions in a given interval is not less than the configured min value	When the average latency of write transactions in a given interval is less than the configured min value		This check is applicable only when: perf_avg_min_write_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_avg_max_write_xact_latency_check	Synopsys Defined	Monitor Check that the average latency of write transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of write transactions in a given interval is not more than the configured max value	When the average latency of write transactions in a given interval is not more than the configured max value	When the average latency of write transactions in a given interval is more than the configured max value		This check is applicable only when: perf_avg_max_write_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_min_write_xact_latency_check	Synopsys Defined	Monitor Check that the latency of a write transaction is more than or equal to the configured min value	Checks that the latency of a write transaction is not lesser than the configured min value	When latency of a write transaction is not lesser than the configured min value	When latency of a write transaction is lesser than the configured min value		This check is applicable only when: perf_min_write_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Performance Metrics	perf_max_write_xact_latency_check	Synopsys Defined	Monitor Check that the latency of a write transaction is less than or equal to the configured max value	Checks that the latency of a write transaction is not greater than the configured max value	When latency of a write transaction is not greater than the configured max value	When latency of a write transaction is greater than the configured max value		This check is applicable only when: perf_max_write_xact_latency is not set to -1	ERROR	svt_axi_checker
ACE	Non DVM Non Device	write_non_dvm_non_device_xact_id_overlap_check	Synopsys Defined	Monitor Check for the AWID overlap of Non-DVM or Non-device transactions with another active transaction	Checks the overlapping AWID of Non-DVM or Non-Device transactions with any active transactions	When AWID of Non-DVM or Non-Device transactions overlap with any active transactions	When AWID of Non-DVM or Non-Device transactions not overlap with any active transactions	Passive Slave, Active/Passive Master		ERROR	svt_axi_checker
ACE	Non DVM Non Device	read_non_dvm_non_device_xact_id_overlap_check	Synopsys Defined	Monitor Check for the ARID overlap of Non-DVM or Non-device transactions with another active transaction	Checks the overlapping ARID of Non-DVM or Non-Device transactions with any active transactions	When ARID of Non-DVM or Non-Device transactions overlap with any active transactions	When ARID of Non-DVM or Non-Device transactions not overlap with any active transactions	Passive Slave, Active/Passive Master		ERROR	svt_axi_checker
AXI3	Port Interleaving	port_interleaving_check	Synopsys Defined	Monitor checks that if interleaved port is expected port for the given transaction	Checks if address does fall to correct interleaved port. Valid when port cfg port_interleaving_enable = 1.	address does fall to correct interleaved port.	address does not fall to correct interleaved port.	Active/Passive Slave, Active/Passive Master		ERROR	svt_axi_checker
AXI3	Locked Accesses	locked_sequence_to_same_slave_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses	Monitor Check that only locked slave is used for all the transactions in the locked sequence	Checks that when a master does a lock transaction, it does not target subsequent transactions in the lock sequence to any slave other than the locked slave	When the the slave port id for the new sequence is match the slave port id for the previous transaction in the locked sequence	When the the slave port id for the new sequence does not match the slave port id for the previous transaction in the locked sequence	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: locked_access_enable is set to 1	WARNING	svt_axi_checker
AXI3	Locked Accesses	locked_sequence_length_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses	Monitor Check that a locked sequence does not have more than two consecutive locked transactions at the same time	Check that the master follows as per the recommendation from spec to limit 2 transaction for the lock access	When the Sequence detected with less than two locked transactions	When the Sequence detected with more than two locked transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: locked_access_enable is set to 1	WARNING	svt_axi_checker
AXI3	Locked Accesses	no_pending_locked_xacts_before_normal_xacts_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses	Monitor Check that there are no pending transactions of a locked sequence when a normal transaction is received	Checks that there are no pending transactions of a locked sequeunce when a normal transaction is received	When the normal transaction detected when a locked sequeunce is complete	When the normal transaction detected when a locked sequeunce is not complete	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: locked_access_enable is set to 1	ERROR	svt_axi_checker
AXI3	Locked Accesses	locked_sequeunce_id_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses	Monitor Check that all transactions of a locked sequence have the same id	Checks that all transactions of locked sequence have the same id	When the transaction id is same as locked transaction id	When the transaction id is not same as locked transaction id	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: locked_access_enable is set to 1	ERROR	svt_axi_checker
AXI3	Locked Accesses	no_pending_xacts_during_locked_xact_sequeunce_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses	Monitor Check that there are no pending transactions before a locked sequence starts	Checks that there are no pending transactions before a locked sequence starts	When the locked sequence is detected and active transaction found	When the locked sequence is detected and no active transaction found	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: locked_access_enable is set to 1	ERROR	svt_axi_checker
AXI3	Write Data Ordering	write_data_interleave_order_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A5.2.2 Write data ordering	Monitor check that the order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions for Write Data Interleaving	Checks that the order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions for Write Data Interleaving transactions	When the Address order and data order is same for the write data interleaving transaction	When the Address order and data order is not same for the write data interleaving transaction	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.	ERROR	svt_axi_checker
AXI3	Write Data Ordering	write_data_interleave_depth_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A5.2.2 Write data ordering	Monitor check that received write data is not interleaved beyond write_data_interleave_depth value. An error is issued if write data is interleaved beyond this value for Write data interleaving	Checks that received write data is not interleaved beyond write_data_interleave_depth value	When the first active write xact index is not greater to the write_data_interleave_depth	When the first active write xact index is greater to the write_data_interleave_depth if write data is interleaved beyond this value for Write data interleaving	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.	ERROR	svt_axi_checker
AXI3	Signal Stability	signal_stable_wid_when_wvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel	Monitor check for signal stability when corresponding valid signal is high	Checks that WID is stable when WVALID is high	WID is stable when WVALID is high	WID is not stable when WVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.	ERROR	svt_axi_checker
AXI3	Signal Validity	signal_valid_wid_when_wvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that WID is not X or Z when WVALID is high	WID is not X or Z when WVALID is high	WID is X or Z when WVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3. svt_axi_port_configuration :: protocol_checks_enable is set to 1. svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1. wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	writebarrier_norm_xact_id_overlap_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements	Monitor Check for the AWID overlap of Write transactions with other active WriteBarrier transactions	Checks the overlapping AWID of Non-Barrier Non-DVM transactions with any active Barrier/DVM transactions	When AWID of Non-Barrier Non-DVM transactions overlap with any active Barrier/DVM transactions	When AWID of Non-Barrier Non-DVM transactions is not overlap with any active Barrier/DVM transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: barrier_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	readbarrier_dvm_norm_xact_id_overlap_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements	Monitor Check for the ARID overlap of Read transactions with other active ReadBarrier/DVM transactions	Checks the overlapping ARID of Non-Barrier Non-DVM transactions with any active Barrier/DVM transactions	When RID of Non-Barrier Non-DVM transactions overlap with any active Barrier/DVM transactions	When RID of Non-Barrier Non-DVM transactions is not overlap with any active Barrier/DVM transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: dvm_enable or barrier_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	readbarrier_xact_id_overlap_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements	Monitor Check for the ARID overlap of ReadBarrier transactions with other active Non-Barrier transactions	Checks the overlapping ARID of Read Barrier transactions with any active Read transactions	When ARID of Read Barrier transactions overlap with other active Non-Barrier transactions	When ARID Read Barrier transactions is not overlap with other active Non-Barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: barrier_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	writebarrier_xact_id_overlap_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements	Monitor Check for the AWID overlap of WriteBarrier transactions with other active Non-Barrier transactions	Checks the overlapping AWID of Write Barrier transactions with any active Write transactions	When AWID of WriteBarrier transactions overlap with other active Non-Barrier transactions	When AWID of WriteBarrier transactions is not overlap with other active Non-Barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: barrier_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite	DVM	dvm_message_arbar_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes	Monitor Check that for DVM transactions ARBAR[0] is 'b0 Normal Access!	Checks for DVM ARBAR[0] is 1'b0	When DVM ARBAR must be zero means must having normal access	When DVM ARBAR is not zero means not having normal access	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	barrier_pair_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.1 About barrier transactions	Monitor Check that Barrier pairs must be issued in the same sequence on the read address and write address channels	Checks that barrier pairs must be issued in the same sequence on the read address and write address channels	When Barrier pairs must be issued in the same sequence on the read address and write address channels	When Barrier pairs not issued in the same sequence on the read address and write address channels	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	barrier_pair_cntrl_signals_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements	Monitor Check that Both transactions in a barrier pair must have the same AxID, AxBAR, AxDOMAIN, and AxPROT values.	Checks that both transactions in a barrier pair must have the same AxID, AxBAR, AxDOMAIN, and AxPROT values	When ReadBarrier and write barrier transactions with AxID, AxBAR, AxDOMAIN, AxPROT not matching the last WriteBarrier/ReadBarrier with AxID	When ReadBarrier and write barrier transactions with AxID, AxBAR, AxDOMAIN, AxPROT is matching the last WriteBarrier/ReadBarrier with AxID	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	barrier_write_response_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling	Monitor Check that for barrier write transaction only BRESP = '00 response is permitted!	Checks the Write Barrier valid response	When BRESP must be all zeros for write barrier transactions	When BRESP is not zeros for write barrier transactions	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	barrier_read_response_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling	Monitor Check that for barrier read transaction only RRESP ='00 response is permitted!	Checks the Read Barrier valid response	When RRESP must be all zeros for read barrier transactions	When RRESP is not zeros for read barrier transactions	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	barrier_id_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling	Monitor Check that the range of ID for barrier transactions should be inside svt_axi_transaction::barrier_id_min and svt_axi_transaction::barrier_id_max!	Checks the Barrier Id valid and unreserved	When range of ID values which can be used for Barrier transactions are specified using members barrier_id_min and barrier_id_max	When range of ID values which can be used for Barrier transactions are not specified using members barrier_id_min and barrier_id_max	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	read_barrier_arlock_type_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier read transaction ARLOCK is Normal Access 'b0!	Checks the combinations of ARLOCK and ARBAR are valid and unreserved	When ARLOCK must have normal access for read barrier transactions	When ARLOCK is not having normal access for read barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	read_barrier_arsnoop_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier read transaction ARSNOOP is all zeros !	Checks the combinations of ARSNOOP and ARBAR are valid and unreserved	When ARSNOOP must be all zeros for read barrier transactions	When ARSNOOP is not zero for read barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	read_barrier_arcache_type_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier read transaction ARCACHE is Normal non-cacheable'b0010 !	Checks the combinations of ARCACHE and ARBAR are valid and unreserved	When ARCACHE must be Normal, Non-cacheable for read barrier transactions	When ARCACHE is not of Normal, Non-cacheable for read barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	read_barrier_arsize_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier read transaction ARSIZE matches the data bus width!	Checks the combinations of ARSIZE and ARBAR are valid and unreserved	When ARSIZE must be equal to the data bus width for read barrier transactions	When ARSIZE is not equal to the data bus width for read barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	read_barrier_arlen_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that a barrier read transaction should be of length 1!	Checks the combinations of ARLEN and ARBAR are valid and unreserved	When ARLEN must be all zeros for read barrier transactions	When ARLEN is not zero for read barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	read_barrier_arburst_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier read transaction the burst_type is INCR !	Checks the combinations ARBURST and ARBAR are valid and unreserved	When ARBURST must be INCR type for read barrier transactions	When ARBURST is not INCR type for read barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	read_barrier_araddr_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier read transaction the ARADDR should be all zeros!	Checks the ARADDR is valid for ARBAR	When ARADDR must be all zeros for read barrier transactions	When ARADDR is not zero for read barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	barrier_transaction_user_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling	Monitor Checks that for a barrier transaction AxUSER has valid value 0x00	Checks the valid value of AxUSER for write barrier transactions	When a barrier transaction AxUSER has valid value 0x00	When a barrier transaction AxUSER not have valid value	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1 svt_axi_port_configuration :: awuser_enable or aruser_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	write_barrier_awlock_type_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier write transaction AWLOCK is Normal Access 'b0!	Checks the combinations of AWLOCK and AWBAR are valid and unreserved	When AWLOCK must be normal access for write barrier transactions	When AWLOCK is not having normal access for write barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	write_barrier_awsnoop_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier write transaction AWSNOOP is all zeros!	Checks the combinations of AWSNOOP and AWBAR are valid and unreserved	When AWSNOOP must be all zeros for write barrier transactions	When AWSNOOP is not zero for write barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	write_barrier_awcache_type_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier write transaction AWCACHE is Normal non-cacheable 'b0010!	Checks the combinations of AWCACHE and AWBAR are valid and unreserved	When AWCACHE must be Normal, non-cacheable for write barrier transactions	When AWCACHE is not of Normal, non-cacheable for write barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	write_barrier_awsize_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier write transaction the AWSIZE matches the data bus width!	Checks the combinations of AWSIZE and AWBAR are valid and unreserved	When AWSIZE must be equal to the data bus width for write barrier transactions	When AWSIZE is not equal to the data bus width for write barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions Constraints	write_barrier_awlen_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that a barrier write transaction should be of length 1!	Checks the combinations of AWLEN and AWBAR are valid and unreserved	When AWLEN must be all zeros for write barrier transactions	When AWLEN is not zero for write barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	write_barrier_awburst_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier write transaction the burst_type is INCR!	Checks the combinations AWBURST and AWBAR are valid and unreserved	When AWBURST must be INCR type for write barrier transactions	When AWBURST is not INCR type for write barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions	write_barrier_awaddr_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a barrier write transaction the AWADDR should be all zeros!	Checks the AWADDR is valid for AWBAR	When AWADDR must be all zeros for write barrier transactions	When AWADDR is not zero for write barrier transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: barrier_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Cache Line Size Transactions Constraints	cache_line_axbar_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that AxBAR is valid for Cache Line Size Transactions!	Checks if the AxBAR is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AxBAR	When All cache line size transactions not have have valid AxBAR	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite	Cache Line Size Transactions Constraints	full_cache_line_size_check	Synopsys Defined	Monitor Check that all transactions other than ReadNoSnoop, ReadOnce, WriteNoSnoop, WriteUnique, WriteBack, WriteClean,DVM Message and Barrier are required to be a full cache line size!	Checks if all transactions (other than ReadNoSnoop, ReadOnce, WriteNoSnoop, WriteUnique, WriteBack, WriteClean,DVM Message and Barrier) are required to be a full cache line size	When all these transaction are full cache line size	When all these are not required to be a full cache line size	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite	Signal Stability	signal_stable_awbar_when_awvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions	Monitor check for signal stability when corresponding valid signal is high	Checks that AWBAR is stable when AWVALID is high	AWBAR is stable when AWVALID is high	AWBAR is not stable when AWVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions: Signal Validity	signal_valid_awbar_when_awvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that AWBAR is not X or Z when AWVALID is high	AWBAR is not X or Z when AWVALID is high	AWBAR is X or Z when AWVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: ace_version is not set to svt_axi_port_configuration :: ACE_VERSION_2_0. svt_axi_port_configuration :: protocol_checks_enable is set to 1. svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1. awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.	ERROR	svt_axi_checker
ACE,ACE_Lite	Signal Stability	signal_stable_arbar_when_arvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions	Monitor check for signal stability when corresponding valid signal is high	Checks that ARBAR is stable when ARVALID is high	ARBAR is stable when ARVALID is high	ARBAR is not stable when ARVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.	ERROR	svt_axi_checker
ACE,ACE_Lite	Barrier Transactions: Signal Validity	signal_valid_arbar_when_arvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ARBAR is not X or Z when ARVALID is high	ARBAR is not X or Z when ARVALID is high	ARBAR is X or Z when ARVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: ace_version is not set to svt_axi_port_configuration :: ACE_VERSION_2_0. svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1. arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Mulipart	multipart_dvm_snoop_successive_transaction_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.1 DVM message transactions	Monitor Checks that there are no unrelated snoop channel transfer in between two multi-part DVM operations which relate to the same DVM transaction	Checks that all snoop transactions of multi-part DVM operation are sent in successive manner and no unrelated snoop transaction sent during multi-part DVM opearion over AC channel	When there are no unrelated snoop channel transfer in between two multi-part DVM operations which relate to the same DVM transaction	When there are unrelated snoop channel transfer in between two multi-part DVM operations which is not relate to the same DVM transaction	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Mulipart	multipart_dvm_coherent_successive_transaction_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.1 DVM message transactions	Monitor Checks that there are no unrelated read-address channel transfer in between two multi-part DVM operations which relate to the same DVM transaction	Checks that all coherent transactions of multi-part DVM operation are sent in successive manner and no unrelated coherent transaction sent during multi-part DVM opearion over AR channel	When there are no unrelated read-address channel transfer in between two multi-part DVM operations which relate to the same DVM transaction	When there are unrelated read-address channel transfer in between two multi-part DVM operations which is not relate to the same DVM transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Mulipart	multipart_dvm_snoop_same_response_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses	Monitor Checks that each snoop transaction related to a multi-part DVM Operation must send same snoop response	Checks that all transactions of multi-part DVM operation have same snoop response	When snoop response which should be same as first-part of the multi-part DVM transaction	When snoop response is not same as first-part of the multi-part DVM transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Mulipart	multipart_dvm_coherent_same_response_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses	Monitor Checks that each transaction of a multi-part DVM Message must send same coherent response	Checks that all transactions of multi-part DVM operation have same coherent response	When all transactions of multi-part DVM operation have same coherent response	When all transactions of multi-part DVM operation not have same coherent response	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Mulipart	multipart_dvm_coherent_same_id_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.4 DVM ID values	Monitor Checks that each transaction of a multi-part DVM Message must use the same AXI ID	Checks that all transactions of multi-part DVM operation have same ID	When all transactions of multi-part DVM operation have same ID as normal transaction id	When all transactions of multi-part DVM operation not have same ID as normal transaction id	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvm_xact_id_overlap_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.4 DVM ID values	Monitor Check for the ARID overlap of DVM transactions with other active Non-DVM transactions	Checks the overlapping ARID of DVM transactions with any active Read transactions	When ARID of DVM transactions overlap with any active Read transactions	When ARID of DVM transactions is not overlap with any active Read transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvmmessage_snoop_araddr_reserve_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.3 DVM messages	Monitor Check that for DVM Message the value of reserve address bits must be zero!	Checks FOR DVM Message the value of reserve address bit should be zero	When for DVM Message the value of reserve address bit is zero	When for DVM Message the value of reserve address bit is not zero	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_snoop_transaction :: snoop_xact_type is set to svt_axi_snoop_transaction :: DVMMESSAGE svt_axi_system_configuration :: dvm_version is set to svt_axi_system_configuration :: DVMV8 or Later.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_virtual_inst_cache_addr_specified_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[0] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ARADDR[0] of DVM message type Virtual Instruction Cache Invalidate	When ARADDR[0] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b00 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0 When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b1 than ARADDR[0] is 1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b1 than ARADDR[0] is 1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b1 than ARADDR[0] is 1'b1 When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b1	When ARADDR[0] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_virtual_inst_cache_asid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[5] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ARADDR[5] of DVM message type Virtual Instruction Cache Invalidate	When ARADDR[5] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b00 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b0 When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 than ARADDR[5] is 1'b0,1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 than ARADDR[5] is 1'b0,1'b1 When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY ARADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_4 ARADDR[5] is 1'b0 for other versions	When ARADDR[5] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_virtual_inst_cache_vmid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[6] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ARADDR[6] of DVM message type Virtual Instruction Cache Invalidate	When ARADDR[6] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b00 than ARADDR[6] is 1'b0 When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b11 than ARADDR[6] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 than ARADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4 ARADDR[6] is 1'b0 for other dvm version When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 than ARADDR[6] is 1'b1 When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 than ARADDR[6] is 1'b0	When ARADDR[6] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_virtual_inst_cache_secure_nonsecure_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[9:8] for DVM Message type Virtual Instruction Cache Invalidate!	Checks the valid values of ARADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate	When ARADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate have the following valid values: When ARADDR[11:10] is 2'b00 than ARADDR[9:8] is 2'b00,2'b11 When ARADDR[11:10] is 2'b10 than ARADDR[9:8] is 2'b10,2'b11 When ARADDR[11:10] is 2'b11 than ARADDR[9:8] is 2'b11	When ARADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate not have the valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_virtual_inst_cache_invalidate_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[11:10] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ARADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate	When ARADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate have values {2'b00,2'b10,2'b11}	When ARADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate not have values {2'b00,2'b10,2'b11}	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_physical_inst_cache_addr_specified_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[0] for DVM Message type Physical Instruction Cache Invalidate !	Checks the valid values of ARADDR[0] of DVM message type Physical Instruction Cache Invalidate	When ARADDR[0] of DVM message type Physical Instruction Cache Invalidate have following valid values: When ARADDR[9:8] is 2'b10 & ARADDR[6:5] is 2'b00 than ARADDR[0] is 1'b0,1'b1 When ACADDR[9:8] is 2'b10 & ARADDR[6:5] is 2'b11 than ARADDR[0] is 1'b1 When ACADDR[9:8] is 2'b11 & ARADDR[6:5] is 2'b00 than ARADDR[0] is 1'b0,1'b1 When ARADDR[9:8] is 2'b11 & ARADDR[6:5] is 2'b11 than ARADDR[0] is 1'b1	When ARADDR[0] of DVM message type Physical Instruction Cache Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_physical_inst_cache_vid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[6:5] for DVM Message type Physical Instruction Cache Invalidate !	Checks the valid values of ARADDR[6:5] of DVM message type Physical Instruction Cache Invalidate	When ARADDR[6:5] of DVM message type Physical Instruction Cache Invalidate have following valid values: When ARADDR[9:8] is 2'b10 than ARADDR[6:5] is 2'b00,2'b11 When ARADDR[9:8] is 2'b11 than ARADDR[6:5] is 2'b00,2'b11	When ARADDR[6:5] of DVM message type Physical Instruction Cache Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_physical_inst_cache_secure_nonsecure_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations	Monitor Check for the supported values of ARADDR[9:8] for DVM Message type Physical Instruction Cache Invalidate !	Checks the valid values of ARADDR[9:8] of DVM message type Physical Instruction Cache Invalidate	When ARADDR[9:8] is have valid values (2'b10, 2'b11) of DVM message type Physical Instruction Cache Invalidate	When ARADDR[9:8] is not have valid values (2'b10, 2'b11) of DVM message type Physical Instruction Cache Invalidate	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Branch Predictor	dvmmessage_branch_predictor_invalidate_supported_message_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate	Monitor Check for the supported values of ARADDR[0] for DVM Message type Branch Predictor Invalidate!	Checks the valid values of ARADDR[0] of DVM message type Branch Predictor Invalidate	When ARADDR[0] must have valid value 1'b0,1'b1 for DVM message Branch Predictor Invalidate	When ARADDR[0] is not have values 1'b0,1'b1 for DVM message Branch Predictor Invalidate	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: TLBI	dvmmessage_tlb_addr_specified_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ARADDR[0] for DVM Message type TLB Invalidate !	Checks the valid values of ARADDR[0] of DVM message type TLB Invalidate	When ARADDR[0] of DVM message type TLB Invalidate have following valid values: When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0,1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b1 than ARADDR[0] is 1'b0,1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0,1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b1 than ARADDR[0] is 1'b0,1'b1 When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b0,1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b01 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than ARADDR[0] is 1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 than ARADDR[0] is 1'b0,1'b1 When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than ARADDR[0] is 1'b0,1'b1	When ARADDR[0] of DVM message type TLB Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: TLBI	dvmmessage_tlb_asid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ARADDR[5] for DVM Message type TLB Invalidate !	Checks the valid values of ARADDR[5] of DVM message type TLB Invalidate	When ARADDR[5] of DVM message type TLB Invalidate must have following valid values: When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b0,1'b1 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 than ARADDR[5] is 1'b0,1'b1 When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY ARADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_4 or DVMV9_2 ARADDR[5] is 1'b0 for other versions When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b01 & ARADDR[6] is 1'b1 than ARADDR[5] is 1'b0 When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 than ARADDR[5] is 1'b0,1'b1 When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than ARADDR[5] is 1'b0,1'b1	When ARADDR[5] of DVM message type TLB Invalidate not takes valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: TLBI	dvmmessage_tlb_vmid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ARADDR[6] for DVM Message type TLB Invalidate !	Checks the valid values of ARADDR[6] of DVM message type TLB Invalidate	When ARADDR[6] of DVM message type TLB Invalidate have the following valid values: When ARADDR[11:10] is 2'b10 and ARADDR[9:8] is 2'b10 than ARADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4 or DVMV9_2 ARADDR[6] is 2'b0 for other versions When ARADDR[11:10] is 2'b10 and ARADDR[9:8] is 2'b11 than ARADDR[6] is 1'b0,1'b1 When ARADDR[11:10] is 2'b11 and ARADDR[9:8] is 2'b11 than ARADDR[6] is 1'b0 When ARADDR[11:10] is 2'b11 and ARADDR[9:8] is 2'b10 than ARADDR[6] is 1'b0 When ARADDR[11:10] is 2'b10 and ARADDR[9:8] is 2'b01 than ARADDR[6] is 1'b1	When ARADDR[6] of DVM message type TLBI not takes valid value according to dvm versions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: TLBI	dvmmessage_tlb_secure_nonsecure_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check the for supported values of ARADDR[9:8] for DVM Message type TLB Invalidate !	Checks the valid values of ARADDR[9:8] of DVM message type TLB Invalidate	When ARADDR[9:8] of DVM message type TLBI must have following valid values: When ARADDR [11:10] is 2'b10 than ARADDR[9:8] have value 2'b00,2'b01,2'b10,2'b11 for dvm_version DVMV9_2 ARADDR[9:8] have value 2'b01,2'b10,2'b11 for dvm_version DVMV8_4 ARADDR[9:8] have value 2'b10,2'b11 for other versions When ACADDR [11:10] is 2'b11 than ARADDR[9:8] have value 2'b00,2'b10,2'b11 for dvm_version DVMV9_2 ARADDR[9:8] have value 2'b10,2'b11 for dvm_version DVMV8_4 ARADDR[9:8] have value 2'b11 for other version	When ARADDR[9:8] of DVM message type TLBI not takes valid values for all the versions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: TLBI	dvmmessage_tlb_hypervisor_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ARADDR[11:10] for DVM Message type TLB Invalidate !	Checks the valid values of ARADDR[11:10] of DVM message type TLB Invalidate	When ARADDR[11:10] of DVM message type TLBI have following valid value: For dvm_version DVMV9_2 when ARADDR[11:10] is 2'b00,2'b01,2'b10,2'b11 For other version ARADDR[11:10] is 2'b01,2'b10,2'b11	When ARADDR[11:10] of DVM message type TLB Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvmmessage_araddr_reserve_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.3.5 DVM message encoding, first part	Monitor Check that for DVM Message the value of reserve address bits must be zero!	Checks FOR DVM Message the value of reserve address bit should be zero			Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvmcomplete_araddr_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes	Monitor Check that for a DVM Complete message, ARADDR is defined to be all zeros!	Checks For a DVM Complete message, ARADDR is defined to be all zeros	When ARADDR must be zero for DVM Complete	When ARADDR is not zero for DVM Complete	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Hint	dvm_operation_dvm_hint_araddr_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.12 Hint	Monitor Checks that for DVM HINT Message ARADDR bit[15] == 1	Checks for DVMHINT, DVM Operation the valid value of ARADDR[15]			Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM Operation	dvm_operation_dvm_sync_araddr_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.11 Synchronization	Monitor Checks that for DVM SYNC Message ARADDR bits [n-1:32] and [11:0] are all set to 0 and bit[15] == 1	Checks for DVMSYNC, DVM Operation the valid value of ARADDR[(n-1):32],[15],[11:0] bits			Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM Operation	dvm_operation_dvm_sync_arsnoop_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes	Monitor Check that ARSNOOP is 'b1111 for DVM Operation and DVM Sync!	Checks for DVMSYNC, DVM Operation the valid value of ARSNOOP	When ARSNOOP for DVM Message must be 0b1111	When ARSNOOP for DVM Message is not of 0b1111	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvm_message_ardomain_type_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes	Monitor Check that for DVM transactions ARDOMAIN is Inner shareable or Outer shareable!	Checks for DVM ARDOMAIN is Inner shareable or Outer shareable	When DVM ARDOMAIN must be Inner shareable or Outer shareable	When DVM ARDOMAIN is not of the Inner shareable or Outer shareable	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvm_message_arlock_type_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes	Monitor Check that for DVM transactions ARLOCK is 'b0 Normal Access!	Checks for DVM ARLOCK 'b0 Normal Access	When DVM ARLOCK must be zero or having normal access	When DVM ARLOCK is not having normal acsess	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvm_message_arcache_type_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes	Monitor Check that for DVM transactions ARCACHE is 'b0010 Normal non-cacheable!	Checks for DVM ARCACHE 'b0010 Normal non-cacheable	When DVM ARCACHE must be 0b0010, which means must be modifiable and non-cacheable	When DVM ARCACHE is not 0b0010	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvm_message_arsize_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes	Monitor Check that for DVM transactions the ARSIZE Matches the data bus width !	Checks for DVM ARSIZE Matches the data bus width	When burst length must be 1, which means ARLEN[7:0] must be 0x00.	When burst length is not equal to 1	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvm_message_arlen_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes	Monitor Check that DVM transactions are of length 1!	Checks For DVM ARLEN All zero	When burst length must be 1, which means ARLEN[7:0] must be 0x00.	When burst length is not equal to 1	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM	dvm_message_arburst_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes	Monitor Check that for DVM transactions burst_type is INCR !	Checks For DVM ARBURST 'b01 Burst Type INCR	When ARBURST for dvm must be INCR type	When ARBURST for dvm is not of INCR type	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Domain Types	awsnoop_awdomain_awbar_reserve_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.3 Read and write Shareable transaction types	Monitor Check that the combinations of AWDOMAIN,AWSNOOP and AWBAR are Valid and are un-reserved!	Checks the combinations of AWDOMAIN,AWSNOOP and AWBAR are valid and unreserved	When the combinations of AWDOMAIN, AWSNOOP and AWBAR takes valid and unreserved values	When the combinations of AWDOMAIN, AWSNOOP and AWBAR are not takes valid and unreserved values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE The barrier transactions are not supported starting from AMBA5 interfaces (i.e. AXI5/ACE5_Lite). So, the AxBAR signal is tied-off to default value of (00) indicating a normal transaction.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Domain Types	arsnoop_ardomain_arbar_reserve_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.3 Read and write Shareable transaction types	Monitor Check that the combinations of ARDOMAIN,ARSNOOP and ARBAR are Valid and are un-reserved!	Checks the combinations of ARDOMAIN,ARSNOOP and ARBAR are valid and unreserved	When the combinations of ARDOMAIN, ARSNOOP and ARBAR takes valid and unreserved values	When the combinations of ARDOMAIN, ARSNOOP and ARBAR are not takes valid and unreserved values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE. The barrier transactions are not supported starting from AMBA5 interfaces (i.e. AXI5/ACE5_Lite). So, the AxBAR signal is tied-off to default value of (00) indicating a normal transaction.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Burst Type	fixed_burst_type_valid	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute	Monitor Check that the FIXED burst type is only permitted for ReadNoSnoop and WriteNoSnoop transactions!	Checks that the FIXED burst type is not supported for shareable transactions	When FIXED burst type for coherent transaction type is inside ReadNoSnoop and WriteNoSnoop transactions	When FIXED burst type for coherent transaction type is not inside ReadNoSnoop and WriteNoSnoop transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Maintenance	valid_snoop_response_during_cache_maintenance_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.4.4 Cache maintenance transactions	Monitor checks that when master initiates a CleanShared cache maintenance transaction, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty snoop response. It also checks that when master initiates CleanInvalid or MakeInvalid cache maintenance transactions, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty, IsShared and DataTransfer snoop responses	Monitor checks that when master initiates a CleanShared cache maintenance transaction, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty snoop response. It also checks that when master initiates CleanInvalid or MakeInvalid cache maintenance transactions, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty, IsShared and DataTransfer snoop responses	When cleanshared or cleansharedpersist transactions is outstanding then cacheline should be in invalid or clean state and hence snoop response must not assert pass_dirty bit	When valid snoop response is not asserted	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Maintenance	no_memory_update_or_shareable_txn_during_cache_maintenance_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.9 ACE Managers and CMOs	Monitor checks that WriteBack, WriteClean or any shareable transactions which permits the line to be allocated are not issued while cache maintenance transaction is in progress	Checks that WriteBack, WriteClean or any shareable transactions that permits the line to be allocated are not issued while cache maintenance transaction is in progress.	check will pass if WriteBack, WriteClean or any shareable transactions that permits the line to be allocated are not issued while cache maintenance transaction is in progress.	check will fail if WriteBack, WriteClean or any shareable transactions that permits the line to be allocated are issued while cache maintenance transaction is in progress.	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Maintenance	cache_maintenance_outstanding_transaction_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D12.1 About the interface control signals	Monitor checks that CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding. Checks that CleanShared cache maintenance transactions are not initiated while any memory update or any shareable transactions that can make the cacheline dirty, are outstanding	Checks that CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding. It also checks that CleanShared cache maintenance transactions are not initiated while any memory update or any shareable transactions that can make the cacheline dirty, are outstanding	When CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding	When CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are not outstanding	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_dvmcomplete_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for DVMComplete Transaction are IsShared=0;PassDirty=0 !	Checks the valid response of DVM Complete Transactions	When the valid response for DVMComplete Transaction are IsShared=0;PassDirty=0	When the valid response for DVMComplete Transaction are not of IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_dvmmessage_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for DVMMessage Transaction are IsShared=0;PassDirty=0 !	Checks the valid response of DVM Message Transactions	When the valid response for DVMMessage Transaction are IsShared=0;PassDirty=0	When the valid response for DVMMessage Transaction are not IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_readbarrier_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for ReadBarrier Transaction are IsShared=0;PassDirty=0 !	Checks the valid response of readbarrier Transactions	When the valid response for ReadBarrier Transaction are IsShared=0;PassDirty=0	When the valid response for ReadBarrier Transaction are not of IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Data Transfer Check	coherent_single_read_data_transfer_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED,CLEANSHAREDPERSIST, CLEANINVALID, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer	Checks the CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED, CLEANINVALID,CLEANSHAREDPERSIST, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer	When CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED,CLEANSHAREDPERSIST, CLEANINVALID, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer	When CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED,CLEANSHAREDPERSIST, CLEANINVALID, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions not have single read data channel transfer	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_readnosnoop_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for ReadNoSnoop Transaction are IsShared=0;PassDirty=0!	Checks the valid response of readnosnoop Transactions	When the valid response for ReadNoSnoop Transaction are IsShared=0;PassDirty=0	When the valid response for ReadNoSnoop Transaction are not of IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_readonce_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for ReadOnce Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!	Checks the valid response of readonce Transactions	When the valid response for ReadOnce Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	When the valid response for ReadOnce Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_cleaninvalid_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for CleanInvalid Transaction are IsShared=0;PassDirty=0!	Checks the valid response of cleaninvalid Transactions	When the valid response for CleanInvalid Transaction are IsShared=0;PassDirty=0	When the valid response for CleanInvalid Transaction are not of IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_makeinvalid_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for MakeInvalid Transaction are IsShared=0;PassDirty=0!	Checks the valid response of makeinvalid Transactions	When the valid response for MakeInvalid Transaction are IsShared=0;PassDirty=0	When the valid response for MakeInvalid Transaction are not of IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Maintenance	read_data_chan_cleansharedpersist_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.7.4 PCMOs on read channels	Monitor Check that the valid response for CleanSharedPersist Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!	Checks the valid response of cleansharedPersist Transactions	When the valid response for CleanSharedPersist Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	When the valid response for CleanSharedPersist Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Read response signaling	read_data_chan_cleanshared_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for CleanShared Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!	Checks the valid response of cleanshared Transactions	When the valid response for CleanShared Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	When the valid response for CleanShared Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Data Transfer Check	perform_no_datatransfer_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that no data transfer occurs for a CleanShared,CleansharedPersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions !	Checks for no data transfer occurs for a CleanShared,Cleansharedpersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions	When no data transfer occurs for a CleanShared,Cleansharedpersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions	When data transfer occurs for a CleanShared,Cleansharedpersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	writelineunique_wstrb_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that WriteLineUnique transactions are required to have every write data strobe bits asserted, that is, sparse write data strobes are not permitted	Monitor check that all write strobes bits are asserted for a WRITELINEUNIQUE transaction	When all write strobes bits are asserted for a WRITELINEUNIQUE transaction	When all write strobes bits are not asserted for a WRITELINEUNIQUE transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	readonce_arlock_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Checks that ARLOCK is valid for ReadOnce Transactions!	Checks if the ARLOCK is valid for ReadOnce Transactions	When ARLOCK is valid for ReadOnce Transactions	When ARLOCK is not valid for ReadOnce Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	writeunique_awlock_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWLOCK is valid for WriteUnique Transactions!	Checks if the AWLOCK is valid for WriteUnique Transactions	When AWLOCK is valid for WriteUnique Transactions	When AWLOCK is not valid for WriteUnique Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	readonce_arcache_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that ARCACHE is valid for ReadOnce Transactions!	Checks if the ARCACHE is valid for ReadOnce Transactions	When ARCACHE is valid for ReadOnce Transactions	When ARCACHE is not valid for ReadOnce Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	writeunique_awcache_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWCACHE is valid for WriteUnique Transactions!	Checks if the AWCACHE is valid for WriteUnique Transactions	When AWCACHE is valid for WriteUnique Transactions	When AWCACHE is not valid for WriteUnique Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	readonce_arburst_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that ARBURST is valid for ReadOnce Transactions!	Checks if the ARBURST is valid for ReadOnce Transactions	When ARBURST is valid for ReadOnce Transactions	When ARBURST is not valid for ReadOnce Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	writeunique_awburst_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWBURST is valid for WriteUnique Transactions!	Checks if the AWBURST is valid for WriteUnique Transactions	When AWBURST is valid for WriteUnique Transactions	When AWBURST is not valid for WriteUnique Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	readonce_ardomain_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that ARDOMAIN is valid for ReadOnce Transactions!	Checks if the ARDOMAIN is valid for ReadOnce Transactions	When ARDOMAIN is valid for ReadOnce Transactions	When ARDOMAIN is not valid for ReadOnce Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	ReadOnce and WriteUnique Transactions Constraints	writeunique_awdomain_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWDOMAIN is valid for WriteUnique Transactions!	Checks if the AWDOMAIN is valid for ReadOnce & WriteUnique Transactions	When AWDOMAIN is valid for ReadOnce & WriteUnique Transactions	When AWDOMAIN is not valid for ReadOnce & WriteUnique Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_sz_eq_alen_asize_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that AxLEN is correctly indicated according to Cache Line Size configured!	Checks if the AxLEN is correctly indicated as per the Cache Line Size configured	When Coherent transaction type of CLEANUNIQUE, EVICT, CLEANSHARED, CLEANINVALID, MAKEINVALID, MAKEUNIQUE, CLEANSHAREDPERSIST must have indicated correct AxLEN as per cache-line size	When Coherent transaction type of CLEANUNIQUE, EVICT, CLEANSHARED, CLEANINVALID, MAKEINVALID, MAKEUNIQUE, CLEANSHAREDPERSIST is not indicated correct AxLEN as per cache-line size	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arlock_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that ARLOCK is valid for Cache Line Size Transactions!	Checks if the ARLOCK is valid for Cache Line Size Transactions	When All cache line size transactions must have valid ARLOCK	When All cache line size transactions not have have valid ARLOCK	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awlock_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that AWLOCK is valid for Cache Line Size Transactions!	Checks if the AWLOCK is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AWLOCK	When All cache line size transactions not have have valid AWLOCK	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arcache_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that ARCACHE is valid for Cache Line Size Transactions!	Checks if the ARCACHE is valid for Cache Line Size Transactions	When All cache line size transactions must have valid ARCACHE	When All cache line size transactions not have have valid ARCACHE	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awcache_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that AWCACHE is valid for Cache Line Size Transactions!	Checks if the AWCACHE is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AWCACHE	When All cache line size transactions not have have valid AWCACHE	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_ardomain_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that ARDOMAIN is valid for Cache Line Size Transactions!	Checks if the ARDOMAIN is valid for Cache Line Size Transactions	When All cache line size transactions must have valid ARDOMAIN	When All cache line size transactions not have have valid ARDOMAIN	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awdomain_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that AWDOMAIN is valid for Cache Line Size Transactions!	Checks if the AWDOMAIN is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AWDOMAIN	When All cache line size transactions not have have valid AWDOMAIN	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arburst_incr_addr_aligned_valid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the address is aligned to cache line size for INCR burst in a Cache Line Size Transaction!	Checks if the address is aligned for ARBURST in Cache Line Size Transactions	When address is aligned to burst_size for INCR burst in a Cache Line Size Transaction	When address is not aligned to burst_size for INCR burst in a Cache Line Size Transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awburst_incr_addr_aligned_valid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the address is aligned to cache line size for INCR burst in a Cache Line Size Transaction!	Checks if the address is aligned for AWBURST in Cache Line Size Transactions	When address is aligned to burst_size for INCR burst in a Cache Line Size Transaction	When address is not aligned to burst_size for INCR burst in a Cache Line Size Transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arburst_wrap_addr_aligned_valid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction!	Checks if the address is aligned for ARBURST in Cache Line Size Transactions	When address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction	When address is not aligned to burst_size for WRAP burst in a Cache Line Size Transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awburst_wrap_addr_aligned_valid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction!	Checks if the address is aligned for AWBURST in Cache Line Size Transactions	When address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction	When address is not aligned to burst_size for WRAP burst in a Cache Line Size Transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to either svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arsize_valid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the total number of bytes transferred in the transaction is equal to the cache_line_size!	Checks if the ARSIZE is valid for Cache Line Size Transactions	When All cache line size transactions must have valid ARSIZE	When All cache line size transactions not have have valid ARSIZE	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to either svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arburst_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that If DataTransfer de-asserted then no data transfer will occur on the snoop data channel for this transaction DataTransfer, CRRESP[0]!	Checks if the ARBURST is valid for Cache Line Size Transactions	When All cache line size transactions must have valid ARBURST	When All cache line size transactions not have have valid ARBURST	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awsize_valid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the total number of bytes transferred in the transaction is equal to the cache_line_size!	Checks if the AWSIZE is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AWSIZE	When All cache line size transactions not have have valid AWSIZE	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awburst_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that awburst is valid for Cache Line Size Transactions!	Checks if the AWBURST is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AWBURST	When All cache line size transactions not have valid AWBURST	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Domain Types	axcache_axdomain_invalid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.6 Domains and memory types AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types	Monitor Check that the combination of AxDOMAIN and AxCACHE are valid !	Checks if the AXCACHE and AXDOMAIN value are valid	When the combination of AXCACHE and AXDOMAIN value are valid	When the combination of AXCACHE and AXDOMAIN value are not valid	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Domain Types	axcache_axdomain_restriction_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.6 Domains and memory types AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types	Monitor Check that Device transactions, as indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 System Shareable !	Checks if the Device transactions, as indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 Checks if the Cacheable transactions, as indicated by AxCACHE[3:2] != 00, must not use AxDOMAIN = 11	When device transaction indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 When cacheable transaction indicated by AxCACHE[3:2] != 00, must not use AxDOMAIN = 11	When device transaction indicated by AxCACHE[1] = 0, not use AxDOMAIN = 11 When cacheable transaction indicated by AxCACHE[3:2] != 00, use AxDOMAIN = 11	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses: ACE Master	exclusive_ace_transaction_type_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.1 About Exclusive accesses from ACE Managers	Monitor check that exclusive transaction sent on AXI_ACE interface are only of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type	Checks that exclusive transaction sent on AXI_ACE interface are only of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type	When exclusive transaction type coherent and coherent transaction type is WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type	When exclusive transaction type coherent and coherent transaction type is not of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE OR ACE_LITE. svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exclusive_read_write_id_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.1 Exclusive access process	Monitor check that the bits of the AXI ID signal that are used to identify the Exclusive-capable thread must be the same for all Exclusive transactions from the same Exclusive-capable thread. In other words, monitor checks that same ID is used for exclusive access READ and WRITE transactions	Checks that id is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.	When the exclusive transaction partial exclusive id is equal to the normal transaction partial exclusive id	NA	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE OR ACE_LITE. svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_transaction :: atomic_type is set to svt_axi_transaction :: EXCLUSIVE.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses: ACE Master	exclusive_store_response_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store	Monitor check that response generated for exclusive store accesss is correct	Checks that response generated for exclusive store accesss is correct	When exclusive read response is match exclusive store response	When exclusive read response does not match exclusive store response	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE OR ACE_LITE. svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses: ACE Master	exclusive_load_response_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load	Monitor check that response generated for exclusive load accesss is correct	Checks that response generated for exclusive load accesss is correct	When exclusive read response match with expected exclusive response	When exclusive read response does not match with expected exclusive response	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE. svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Snoop Data: Signal Stability	signal_stable_awsnoop_when_awvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A8.1 Opcode signaling AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.3 Read and write Shareable transaction types	Monitor check for signal stability when corresponding valid signal is high	Checks that AWSNOOP is stable when AWVALID is high	AWSNOOP is stable when AWVALID is high	AWSNOOP is not stable when AWVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Domain Types: Signal Stability	signal_stable_awdomain_when_awvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types	Monitor check for signal stability when corresponding valid signal is high	Checks that AWDOMAIN is stable when AWVALID is high	AWDOMAIN is stable when AWVALID is high	AWDOMAIN is not stable when AWVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Snoop Data: Signal Stability	signal_stable_arsnoop_when_arvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A8.1 Opcode signaling AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.3 Read and write Shareable transaction types	Monitor check for signal stability when corresponding valid signal is high	Checks that ARSNOOP is stable when ARVALID is high	ARSNOOP is stable when ARVALID is high	ARSNOOP is not stable when ARVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Domain Types: Signal Stability	signal_stable_ardomain_when_arvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types	Monitor check for signal stability when corresponding valid signal is high	Checks that ARDOMAIN is stable when ARVALID is high	ARDOMAIN is stable when ARVALID is high	ARDOMAIN is not stable when ARVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	DVM: Mulipart	signal_araddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.2 Addresses in DVM messages	Monitor check for dvm multipart xact ADDR[2:0] should be SBZ	Checks that ARADDR[2:0] for multipart dvm xact is not other than SBZ	When ARADDR[2:0] for multipart dvm xact is not other than SBZ	When ARADDR[2:0] for multipart dvm xact is other than SBZ	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE. svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Snoop Address: Signal Validity	signal_valid_arsnoop_when_arvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A8.1 Opcode signaling AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.3 Read and write Shareable transaction types	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ARSNOOP is not X or Z when ARVALID is high	ARSNOOP is not X or Z when ARVALID is high	ARSNOOP is X or Z when ARVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1. arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.	ERROR	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	Domain Types: Signal Validity	signal_valid_ardomain_when_arvalid_high_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ARDOMAIN is not X or Z when ARVALID is high	ARDOMAIN is not X or Z when ARVALID is high	ARDOMAIN is X or Z when ARVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1. arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.	ERROR	svt_axi_checker
ACE,ACE5	Interconnect Requirements	snoop_to_same_cache_line_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.2 Sequencing transactions	The interconnect must ensure that, if the interconnect sends a snoop transaction to a master, it must not provide the same master with a response to a transaction to the same cache line, until it has received a snoop response on CRRESP to the snoop transaction	Checks that if received a snoop transaction, response to a transaction to the same cache line is not received , until snoop response is sent	When snoop transaction is received than response to a transaction to the same cache line is not received , until snoop response is sent	When snoop transaction is not received	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Interconnect Requirements	resp_to_same_cache_line_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.2 Sequencing transactions	The interconnect must ensure that, if the interconnect provides a master with a response to a transaction, it must not send the same master a snoop transaction to the same cache line until it has received an acknowledgment of the transaction response on either RACK or WACK	Checks that Master does not receive a snoop transaction until any preceding transaction to the same cache line has completed	When Master does not receive a snoop transaction until any preceding transaction to the same cache line has completed	When Master receive a snoop transaction until any preceding transaction to the same cache line has completed	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	WACK Signaling	wack_status_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling	Monitor Check that WACK is asserted in response to BVALID/BREADY handshakes!	Checks the WACK for valid response	When WACK is asserted in response to BVALID/BREADY handshakes	When WACK is not asserted in response to BVALID/BREADY handshakes	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	RACK Signaling	rack_status_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling	Monitor Check that RACK is asserted in response to all RLAST/RVALID/RREADY handshakes!	Checks the RACK for valid response	When RACK is asserted in response to all RLAST/RVALID/RREADY handshakes	When RACK is not asserted in response to all RLAST/RVALID/RREADY handshakes	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Snoop Transactions	snoop_addr_snoop_data_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor Check that the master must wait for both ACVALID and ACREADY to be asserted before asserting CDVALID!	Checks that ACVALID and ACREADY to be asserted before asserting CDVALID	When the master must wait for both ACVALID and ACREADY to be asserted before asserting CDVALID	When the master is not wait for both ACVALID and ACREADY to be asserted before asserting CDVALID	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Snoop Data	cdlast_asserted_for_last_snoopread_data_beat	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor Check that the CDLAST signal is asserted during the final data transfer associated with a snoop transaction!	Checks that CDLAST signal is asserted during the final data transfer	When CDLAST signal is asserted during the final data transfer	When CDLAST signal is not asserted during the final data transfer	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Snoop Response	snoop_response_channel_isshared_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor Check that for ReadUnique, CleanInvalid and MakeInvalid transaction, snoop_resp_isshared cannot be asserted!	Checks for readunique cleaninvalid makeinvalid illegal response	When IsShared = 0 for a ReadUnique, CleanInvalid, MakeInvalid transaction is illegal snoop response	When IsShared = 1 for a ReadUnique, CleanInvalid, MakeInvalid transaction is illegal snoop response	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Snoop Data	full_cache_line_datatransfer_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor Check that if DataTransfer is asserted, a full cache line of data must be provided on the snoop data channel!	If DataTransfer is asserted, a full cache line of data must be provided on the snoop data channel	When DataTransfer = 1 is asserted, a full cache line of data must be provided on the snoop data channel	When DataTransfer = 1 is asserted, a full cache line of data is not provided on the snoop data channel	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Snoop Response	snoop_resp_passdirty_datatransfer_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor Check that snoop_resp_datatransfer is asserted if snoop_resp_passdirty is asserted!	Checks that for MakeInvalid transactions a data transfer is never required	When DataTransfer = 0 and PassDirty = 1 for any transaction is not have valid snoop response	When DataTransfer = 0 and PassDirty = 1 for any transaction is have illegal snoop response	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	complete_outstanding_writeunique_writelineunique_before_memory_write_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.7 Restrictions on WriteUnique and WriteLineUnique usage	Monitor checks that no additional WriteBack, WriteClean, or WriteEvict transactions are issued until all outstanding WriteUnique or WriteLineUnique transactions are completed	Checks that a cached master does not issue WriteBack, WriteClean or WriteEvict transaction while any WriteUnique or WriteLineUnique coherent write transaction is in progress. It automatically checks second rule which says, Complete any incoming snoop transactions without the use of WriteBack, WriteClean, or WriteEvict transactions while a WriteUnique or WriteLineUnique transaction is in progress	When no additional WriteBack, WriteClean, or WriteEvict transactions are issued until all outstanding WriteUnique or WriteLineUnique transactions are completed	When additional WriteBack, WriteClean, or WriteEvict transactions are issued until all outstanding WriteUnique or WriteLineUnique transactions are completed	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	complete_outstanding_memory_write_before_writeunique_writelineunique_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.7 Restrictions on WriteUnique and WriteLineUnique usage	Monitor checks that a cached master completes any outstanding WriteBack, WriteClean, or WriteEvict transactions before issuing a WriteUnique or WriteLineUnique transaction	Checks that a cached master does not initiate WriteUnique or WriteLineUnique coherent write transaction while any WriteBack, WriteClean or WriteEvict transaction is outstanding	When a cached master completes any outstanding WriteBack, WriteClean, or WriteEvict transactions before issuing a WriteUnique or WriteLineUnique transaction	When a cached master not completes any outstanding WriteBack, WriteClean, or WriteEvict transactions before issuing a WriteUnique or WriteLineUnique transaction	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Snoop Address	acaddr_aligned_to_cddata_width_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling	Monitor Check that ACADDR must be aligned to the data transfer size, which is determined by the width of the snoop data bus in bytes	Checks if snoop address is aligned with snoop data width	When ACADDR must be aligned to the data transfer size, which is determined by the width of the snoop data bus in bytes	When ACADDR is not aligned to the data transfer size, which is determined by the width of the snoop data bus in bytes	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Snoop Transactions	snoop_transaction_burst_length_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor Check that snoop transaction burst length must be 1, 2, 4, 8, or 16	Checks if number of databeat transferred over snoop data channel is valid	When number of databeat transferred over snoop data channel is of valid value 1,2,4,8,16	When number of databeat transferred over snoop data channel is of not have valid value 1,2,4,8,16	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Read response signaling	read_data_chan_readclean_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for ReadClean Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!	Checks the valid response of readclean Transactions	When the valid response for ReadClean Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	When the valid response for ReadClean Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Read response signaling	read_data_chan_readnotshareddirty_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for ReadNotSharedDirty Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1 & IsShared=1;PassDirty=0!	Checks the valid response of readnotshareddirty Transactions	When the valid response for ReadNotSharedDirty Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1 & IsShared=1;PassDirty=0	When the valid response for ReadNotSharedDirty Transaction are not of IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1 & IsShared=1;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Read response signaling	read_data_chan_readunique_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for ReadUnique Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1!	Checks the valid response of readunique Transactions	When the valid response for ReadUnique Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1	When the valid response for ReadUnique Transaction are not of IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Read response signaling	read_data_chan_cleanunique_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for CleanUnique Transaction are IsShared=0;PassDirty=0!	Checks the valid response of cleanunique Transactions	When the valid response for CleanUnique Transaction are IsShared=0;PassDirty=0	When the valid response for CleanUnique Transaction are not of IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Read response signaling	read_data_chan_makeunique_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling	Monitor Check that the valid response for MakeUnique Transaction are IsShared=0;PassDirty=0!	Checks the valid response of makeunique Transactions	When the valid response for MakeUnique Transaction are IsShared=0;PassDirty=0	When the valid response for MakeUnique Transaction are not of IsShared=0;PassDirty=0	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE	ERROR	svt_axi_checker
ACE,ACE5	Exclusive Accesses: ACE Master	exclusive_transaction_from_shared_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store	Monitor Checks that if cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED	Checks that if cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED	When cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED	When cacheline is in shared state then exclusive transaction is issued other than CLEANUNIQUE, READCLEAN or READSHARED		This check is applicable only when: svt_axi_port_configuration :: exclusive_access_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: snoop_filter_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Exclusive Accesses: ACE Master	exclusive_store_from_valid_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store	Monitor Checks that if cacheline is in invalid state then exclusive store transaction is not issued	Checks that if cacheline is in invalid state then exclusive store transaction is not issued	When cacheline is in invalid state then exclusive store transaction is not issued	When cacheline is not in invalid state then exclusive store transaction is issued		This check is applicable only when: svt_axi_port_configuration :: exclusive_access_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: snoop_filter_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Exclusive Accesses: ACE Master	exclusive_load_from_valid_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load	Monitor Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED	Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED	When cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED	When cacheline is not in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED		This check is applicable only when: svt_axi_port_configuration :: exclusive_access_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: snoop_filter_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	writeevict_wstrb_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict	Monitor Check that all write strobes bits are asserted for a WRITEEVICT transaction	Monitor check that all write strobes bits are asserted for a WRITEEVICT transaction	When all write strobes bits are asserted for a WRITEEVICT transaction	When all write strobes bits are not asserted for a WRITEEVICT transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: writeevict_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Cache Line Size Transactions Constraints	writeevict_awunique_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWUNIQUE is asserted for a WRITEEVICT transaction	AWUNIQUE must be asserted for WRITEEVICT transactions	When AWUNIQUE must be asserted for WRITEEVICT transactions	When AWUNIQUE is not asserted for WRITEEVICT transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: writeevict_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeclean_awunique_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWUNIQUE is deasserted for a WRITECLEAN transaction	AWUNIQUE must be deasserted for WRITECLEAN transactions	When AWUNIQUE must be deasserted for WRITECLEAN transactions	When AWUNIQUE is not deasserted for WRITECLEAN transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: awunique_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Awnique Signal	snoop_response_to_same_cacheline_during_xact_with_awunique_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal	Monitor check that while a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line	While a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line	When a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line	When a transaction is in progress which has the AWUNIQUE signal asserted, the master give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: writeevict_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	snoop_response_to_same_cacheline_during_writeevict_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict	Monitor check that if a snooped master receives a snoop transaction when it has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time	If a snooped master receives a snoop transaction when it is has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time. The snooped master achieves this by delaying the snoop response until the snooped master has completed the WriteEvict transaction	When a snooped master receives a snoop transaction when it has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time	When a snooped master receives a snoop transaction when it has an outstanding WriteEvict transaction and any master can update the same area of main memory at the same time	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: writeevict_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awlock_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a WRAP burst for WriteBack and WriteClean transactions, AWSIZE x AWLEN must not exceed the cache line size!	Checks if the AWLOCK is 0 for WriteBack and WriteClean Transactions	When WRITEBACK and WRITECLEAN transactions must have atomic_type as NORMAL	When WRITEBACK and WRITECLEAN transactions not have atomic_type as NORMAL	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awburst_wrap_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for a WRAP burst for WriteBack and WriteClean transactions, AWSIZE x AWLEN must not exceed the cache line size!	Checks if the AWSIZE x AWLEN not exceed the cache line size WriteBack and WriteClean Transactions	When for WRAP burst, AWSIZE x AWLEN must not exceed the cache line size	When for WRAP burst, AWSIZE x AWLEN is exceed the cache line size	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awburst_incr_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that for an INCR burst for WriteBack and WriteClean transactions, the last byte in the burst added to the AWSIZE aligned start address, must be within the same cache line as the first byte in the burst!	Checks if the Address aligned for INCR is valid for WriteBack and WriteClean Transactions	When Address aligned for INCR is valid for WriteBack and WriteClean Transactions	When Address aligned for INCR is not valid for WriteBack and WriteClean Transactions	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awcache_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWCACHE is valid for WriteBack and WriteClean Transactions!	Checks if the AWCACHE is valid for WriteBack and WriteClean Transactions	When WRITEBACK and WRITECLEAN transactions cache_type[1] should be 1'b1 (modifiable)	When WRITEBACK and WRITECLEAN transactions cache_type[1] is not 1'b1 (modifiable)	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awdomain_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWDOMAIN is valid for WriteBack and WriteClean Transactions!	Checks if the AWDOMAIN is valid for WriteBack and WriteClean Transactions	When WRITEBACK and WRITECLEAN transactions domain_type should be INNERSHAREABLE, OUTERSHAREABLE or NONSHAREABLE.	When WRITEBACK and WRITECLEAN transactions domain_type is not of INNERSHAREABLE, OUTERSHAREABLE or NONSHAREABLE.	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awburst_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWBURST is valid for WriteBack and WriteClean Transactions!	Checks if the AWBURST is valid for WriteBack and WriteClean Transactions	When WRITEBACK and WRITECLEAN transactions burst_type should be INCR or WRAP	When WRITEBACK and WRITECLEAN transactions burst_type is not of INCR or WRAP	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awburst_awlen_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWLEN and AWBURST are valid for WriteBack and WriteClean Transactions!	Checks if the AWLEN for INCR is valid for WriteBack and WriteClean Transactions	When WRITEBACK and WRITECLEAN transactions burst_length should be inside {1:16} for INCR bursts and inside {2,4,8,16} for WRAP bursts	When WRITEBACK and WRITECLEAN transactions burst_length is not inside {1:16} for INCR bursts and not inside {2,4,8,16} for WRAP bursts	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awlen_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWLEN is valid for WriteBack and WriteClean Transactions!	Checks if the AWLEN is valid for WriteBack and WriteClean Transactions	When WRITEBACK and WRITECLEAN transactions the burst_length should be less than or equal to 16	When WRITEBACK and WRITECLEAN transactions the burst_length is not less than or equal to 16	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	WriteBack and WriteClean Transactions Constraints	writeback_writeclean_awsize_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints	Monitor Check that AWSIZE is valid for WriteBack and WriteClean Transactions!	Checks if the AWSIZE is valid for WriteBack and WriteClean Transactions	When WRITEBACK and WRITECLEAN transactions burst_size should be less than or equal to the data width	When WRITEBACK and WRITECLEAN transactions burst_size is not less than or equal to the data width	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Snoop Transactions	dirty_state_data_transfer_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.2.2 Snoop data transfers	Monitor checks that, if cacheline is in Dirty state UD or SD then dataTransfer bit must be set when master sends snoop response	Checks if snoop response has data transfer bit set for cacheline in dirty state	When cacheline is in Dirty state (UD or SD) then dataTransfer bit must be set when master sends snoop response	When cacheline is not in Dirty state (UD or SD) then dataTransfer bit is not set when master sends snoop response	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	evict_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.9.1 Evict	Monitor checks that, EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state	Checks if EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state	When EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state	When EVICT transaction not starts from UNIQUECLEAN or SHAREDCLEAN state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	writeevict_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict	Monitor checks that, WRITEEVICT transaction starts only from UNIQUECLEAN state	Checks if WRITEEVICT transaction starts only from UNIQUECLEAN state	When WRITEEVICT transaction starts only from UNIQUECLEAN state	When WRITEEVICT transaction not starts from UNIQUECLEAN state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	writeclean_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.5 WriteClean	Monitor checks that, WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state	Checks if WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state	When WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state	When WRITECLEAN transaction not starts from UNIQUEDIRTY or SHAREDDIRTY state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	writeback_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.4 WriteBack	Monitor checks that, WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state	Checks if WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state	When WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state	When WRITEBACK transaction not starts from UNIQUEDIRTY or SHAREDDIRTY state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	writelineunique_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.3 WriteLineUnique	Monitor checks that, WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Checks if WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When WRITELINEUNIQUE transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	writeunique_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.2 WriteUnique	Monitor checks that, WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Checks if WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When WRITEUNIQUE transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	makeinvalid_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.7.2 MakeInvalid	Monitor checks that, MAKEINVALID transaction starts only from INVALID state	Checks if MAKEINVALID transaction starts only from INVALID state	When MAKEINVALID transaction starts only from INVALID state	When MAKEINVALID transaction not starts from INVALID state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	cleaninvalid_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.6.3 CleanInvalid	Monitor checks that, CLEANINVALID transaction starts only from INVALID state	Checks if CLEANINVALID transaction starts only from INVALID state	When CLEANINVALID transaction starts only from INVALID state	When CLEANINVALID transaction not starts from INVALID state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Cache Maintenance	cleansharedpersist_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.7 Cache maintenance for Persistence	Monitor checks that, CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Checks if CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When CLEANSHAREDPERSIST transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Passive Slave, Active/Passive Master	This check is applicable only when: - svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE - cfg.sys_cfg.passive_cache_monitor_enable is set to 1 .	ERROR	svt_axi_checker
ACE,ACE5	Coherency Transactions	cleanshared_correct_start_state_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.6.2 CleanShared	Monitor checks that, CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Checks if CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state	When CLEANSHARED transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cfg.sys_cfg.passive_cache_monitor_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Snoop Transactions	cdvalid_high_no_data_transfer_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.2.1 Channel activity	Monitor Check that arburst is valid for Cache Line Size Transactions!	Checks that the if DataTransfer de-asserted then no data transfer will occur on the snoop data channel for this transaction DataTransfer, CRRESP[0]	When DataTransfer is de-asserted and cdvalid is high then no data transfer should occur on the snoop data channel	When DataTransfer is de-asserted and cdvalid is high, if data transfer occur on the snoop data channel	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Reset	cdvalid_low_when_reset_is_active_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D2.3.3 Reset requirements	Monitor Check for CDVALID low when reset is active!	Checks if cdvalid is low when reset is active	When reset is high than cdvalid must not be asserted	When reset is high and cdvalid is asserted	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.	ERROR	svt_axi_checker
ACE,ACE5	Signal Stability	cdvalid_interrupted_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor Check for CDVALID held steady until CDREADY is asserted!	Checks if cdvalid was interrupted before cdrready got asserted	When cdready is received and cdvalid to cdready delay is zero	When cdready is received and cdvalid to cdready delay is not zero	Passive Master, Active/Passive Slave	This check is applicable When: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5	Snoop Data: Signal Validity	signal_valid_cdvalid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor Check for X or Z on CDVALID!	Checks that CDVALID is not X or Z	When CDVALID is not X or Z	When CDVALID is X or Z	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.	ERROR	svt_axi_checker
ACE,ACE5	WACK Signaling	signal_wack_after_handshake_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling	Monitor Checks that WACK signal must be asserted the cycle after the associated handshake or later!	Checks that WACK signal must be asserted the cycle after the associated handshake or later	When WACK signal must be asserted the cycle after the associated handshake or later	When WACK signal is asserted the cycle before the associated handshake or later	Passive Master, Active/Passive Slave	This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.	ERROR	svt_axi_checker
ACE,ACE5	WACK Signaling	signal_wack_single_cycle_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling	Monitor Checks that WACK is asserted for a single cycle!	Checks that WACK is asserted for a single cycle	When WACK is asserted for a single cycle	When WACK is seen, but found no associated transaction whose data is complete WACK should be asserted for a single cycle	Passive Master, Active/Passive Slave	This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.	ERROR	svt_axi_checker
ACE,ACE5	RACK Signaling	signal_rack_after_handshake_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling	Monitor Checks that RACK signal must be asserted the cycle after the associated handshake or later!	Checks that RACK signal must be asserted the cycle after the associated handshake or later	When RACK signal must be asserted the cycle after the associated handshake or later	When RACK signal is asserted the cycle before the associated handshake or later	Passive Master, Active/Passive Slave	This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.	ERROR	svt_axi_checker
ACE,ACE5	RACK Signaling	signal_rack_single_cycle_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling	Monitor Checks that RACK is asserted for a single cycle!	Checks that RACK is asserted for a single cycle	When RACK is not asserted for a single cycle	When RACK is seen, but found no associated transaction whose data is complete RACK should be asserted for a single cycle	Passive Master, Active/Passive Slave	This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.	ERROR	svt_axi_checker
ACE,ACE5	Exclusive Accesses: ACE Master	exokay_not_sent_until_successful_exclusive_store_rack_observed_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.3.1 Minimum PoS Exclusive Monitor	Monitor checks that, once a master receives successful exclusive store response EXOKAY from interconnect, then no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK	Checks that, once a master receives successful exclusive store response EXOKAY from interconnect, then no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK	When no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK	When any master provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE. svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5	Exclusive Accesses: ACE Master	exclusive_store_overlap_with_another_exclusive_sequence_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store	Monitor check that a master must not permit an Exclusive Store transaction to be in progress at the same time as any transaction that registers that it is performing an Exclusive sequence	Checks that master does not permit an Exclusive Store transaction to be in progress at the same time as any transaction that registers that it is performing an Exclusive sequence	When any transaction is performing exclusive sequence than master does not permit an exclusive store transaction to be in progress at same time.	When any transaction is performing exclusive sequence and if master permit an exclusive store transaction to be in progress at same time.	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE. svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5	Trace Signals: Signal Stability	signal_stable_cdtrace_when_cdvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.4 Trace signals	Monitor check for signal stability when corresponding valid signal is high	Checks that CDTRACE is stable when CDVALID is high.	CDTRACE is stable when CDVALID is high.	CDTRACE is not stable when CDVALID is high.	Passive Master, Active/Passive Slave	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: trace_tag_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5	Signal Stability	signal_stable_cdlast_when_cdvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor check for signal stability when corresponding valid signal is high	Checks that cdlast is stable when cdvalid is high	cdlast is stable when cdvalid is high	cdlast is not stable when cdvalid is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Signal Stability	signal_stable_cddata_when_cdvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor check for signal stability when corresponding valid signal is high	Checks that CDDATA is stable when CDVALID is high	CDDATA is stable when CDVALID is high	CDDATA is not stable when CDVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5	Trace Signals: Signal Validity	signal_valid_cdtrace_when_cdvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.4 Trace signals	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that CDTRACE is not X or Z when CDVALID is high.	CDTRACE is not X or Z when CDVALID is high.	CDTRACE is X or Z when CDVALID is high.	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: trace_tag_enable is set to 1 svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cdvalid_cdready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5	Snoop Data: Signal Validity	signal_valid_cdlast_when_cdvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that cdlast is not X or Z when cdvalid is high	cdlast is not X or Z when cdvalid is high	cdlast is X or Z when cdvalid is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: poison_enable is set to 1 svt_axi_port_configuration :: protocol_checks_enable is set to 1 cdvalid_cdready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5	Snoop Data: Signal Validity	signal_valid_cddata_when_cdvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that CDDATA is not X or Z when CDVALID is high	CDDATA is not X or Z when CDVALID is high	CDDATA is X or Z when CDVALID is high	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE cdvalid_cdready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5	Snoop Data: Signal Validity	signal_valid_cdready_when_cdvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that CDREADY is not X or Z when CDVALID is high	CDREADY is not X or Z when CDVALID is high	CDREADY is X or Z when CDVALID is high	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5	Signal Stability	signal_stable_awunique_when_awvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal	Monitor check for signal stability when corresponding valid signal is high	Checks that AWUNIQUE is stable when AWVALID is high	AWUNIQUE is stable when AWVALID is high	AWUNIQUE is not stable when AWVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE. svt_axi_port_configuration :: awunique_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5	Awnique Signal	signal_valid_awunique_when_awvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that AWUNIQUE is not X or Z when AWVALID is high	AWUNIQUE is not X or Z when AWVALID is high	AWUNIQUE is X or Z when AWVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE. svt_axi_port_configuration :: awunique_enable is set to 1. svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1. awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_virtual_inst_cache_snoop_addr_specified_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ACADDR[0] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ACADDR[0] of DVM message type Virtual Instruction Cache Invalidate	When ACADDR[0] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b00 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0 When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b1 then ACADDR[0] is 1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b1 then ACADDR[0] is 1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b1 then ACADDR[0] is 1'b1 When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b1	When ACADDR[0] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	snoop_dvmmessage_virtual_inst_cache_asid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ACADDR[5] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ACADDR[5] of DVM message type Virtual Instruction Cache Invalidate	When ACADDR[5] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b00 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b0 When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b0 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 then ACADDR[5] is 1'b0,1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 then ACADDR[5] is 1'b0,1'b1 When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY ACADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_4 ACADDR[5] is 1'b0 for other versions	When ACADDR[5] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	snoop_dvmmessage_virtual_inst_cache_vmid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ACADDR[6] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ACADDR[6] of DVM message type Virtual Instruction Cache Invalidate	When ACADDR[6] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b00 then ACADDR[6] is 1'b0 When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b11 then ACADDR[6] is 1'b0 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 then ACADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4 ACADDR[6] is 1'b0 for other dvm version When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 then ACADDR[6] is 1'b1 When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 then ACADDR[6] is 1'b0	When ACADDR[6] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	snoop_dvmmessage_virtual_inst_cache_secure_nonsecure_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ACADDR[9:8] for DVM Message type Virtual Instruction Cache Invalidate!	Checks the valid values of ACADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate	When ACADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ACADDR[11:10] is 2'b00 then ACADDR[9:8] is 2'b00,2'b11 When ACADDR[11:10] is 2'b10 then ACADDR[9:8] is 2'b10,2'b11 When ACADDR[11:10] is 2'b11 then ACADDR[9:8] is 2'b11	When ACADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	snoop_dvmmessage_virtual_inst_cache_invalidate_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations	Monitor Check for the supported values of ACADDR[11:10] for DVM Message type Virtual Instruction Cache Invalidate !	Checks the valid values of ACADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate	When ACADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate have following valid values: When ACADDR[14:12] is 3'b011 then ACADDR[11:10] is 2'b00,2'b10,2'b11	When ACADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	dvmmessage_physical_inst_cache_snoop_addr_specified_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations	Monitor Check for the supported values of ACADDR[0] for DVM Message type Physical Instruction Cache Invalidate !	Checks the valid values of ACADDR[0] of DVM message type Physical Instruction Cache Invalidate	When ACADDR[0] of DVM message type Physical Instruction Cache Invalidate have following valid values: When ACADDR[9:8] is 2'b10 & ACADDR[6:5] is 2'b00 then ACADDR[0] is 1'b0,1'b1 When ACADDR[9:8] is 2'b10 & ACADDR[6:5] is 2'b11 then ACADDR[0] is 1'b1 When ACADDR[9:8] is 2'b11 & ACADDR[6:5] is 2'b00 then ACADDR[0] is 1'b0,1'b1 When ACADDR[9:8] is 2'b11 & ACADDR[6:5] is 2'b11 then ACADDR[0] is 1'b1	When ACADDR[0] of DVM message type Physical Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	snoop_dvmmessage_physical_inst_cache_vid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations	Monitor Check for the supported values of ACADDR[6:5] for DVM Message type Physical Instruction Cache Invalidate !	Checks the valid values of ACADDR[6:5] of DVM message type Physical Instruction Cache Invalidate	When ACADDR[6:5] of DVM message type Physical Instruction Cache Invalidate have following valid values: When ACADDR[9:8] is 2'b10 then ACADDR[6:5] is 2'b00,2'b11 When ACADDR[9:8] is 2'b11 then ACADDR[6:5] is 2'b00,2'b11	When ACADDR[6:5] of DVM message type Physical Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Instruction Cache invalidations	snoop_dvmmessage_physical_inst_cache_secure_nonsecure_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate	Monitor Check for the supported values of ACADDR[9:8] for DVM Message type Physical Instruction Cache Invalidate !	Checks the valid values of ACADDR[9:8] of DVM message type Physical Instruction Cache Invalidate	When ACADDR[9:8] of DVM message type Physical Instruction Cache Invalidate have following valid values: When ACADDR[14:12] is 3'b010 then ACADDR[9:8] is 2'b10,2'b11	When ACADDR[9:8] of DVM message type Physical Instruction Cache Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: Branch Predictor	snoop_dvmmessage_branch_predictor_invalidate_supported_message_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate	Monitor Check for the supported values of ACADDR[0] for DVM Message type Branch Predictor Invalidate!	Checks the valid values of ACADDR[0] of DVM message type Branch Predictor Invalidate	When ACADDR[0] of DVM message type Branch Predictor Invalidate have following valid values: When ACADDR[14:12] is 3'b001 then ACADDR[0] is 1'b0,1'b1	When ACADDR[0] of DVM message type Branch Predictor Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: TLBI	dvmmessage_tlb_snoop_addr_specified_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ACADDR[0] for DVM Message type TLB Invalidate !	Checks the valid values of ACADDR[0] of DVM message type TLB Invalidate	When ACADDR[0] of DVM message type TLB Invalidate have following valid values: When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0,1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b1 then ACADDR[0] is 1'b0,1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0,1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b1 then ACADDR[0] is 1'b0,1'b1 When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b0,1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b01 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then ACADDR[0] is 1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 then ACADDR[0] is 1'b0,1'b1 When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then ACADDR[0] is 1'b0,1'b1	When ACADDR[0] of DVM message type TLB Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: TLBI	snoop_dvmmessage_tlb_asid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ACADDR[5] for DVM Message type TLB Invalidate !	Checks the valid values of ACADDR[5] of DVM message type TLB Invalidate	When ACADDR[5] of DVM message type TLB Invalidate have following valid values: When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b0,1'b1 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b0 When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 then ACADDR[5] is 1'b0,1'b1 When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY ACADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_1 or DVMV8_4 or DVMV9_2 ACADDR[5] is 1'b0 for other versions When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b01 & ACADDR[6] is 1'b1 then ACADDR[5] is 1'b0,1'b1 When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then ACADDR[5] is 1'b0,1'b1	ACADDR[5] of DVM message type TLB Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: TLBI	snoop_dvmmessage_tlb_vmid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ACADDR[6] for DVM Message type TLB Invalidate !	Checks the valid values of ACADDR[6] of DVM message type TLB Invalidate	When ACADDR[6] of DVM message type TLB Invalidate have the following valid values: When ACADDR[11:10] is 2'b10 and ACADDR[9:8] is 2'b10 then ACADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4 or DVMV9_2 ACADDR[6] is 2'b0 for other versions When ACADDR[11:10] is 2'b10 and ACADDR[9:8] is 2'b11 then ACADDR[6] is 1'b0,1'b1 When ACADDR[11:10] is 2'b11 and ACADDR[9:8] is 2'b11 then ACADDR[6] is 1'b0 When ACADDR[11:10] is 2'b11 and ACADDR[9:8] is 2'b10 then ACADDR[6] is 1'b0 When ACADDR[11:10] is 2'b10 and ACADDR[9:8] is 2'b01 then ACADDR[6] is 1'b1	When ACADDR[6] of DVM message type TLB Invalidate not have the valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: TLBI	snoop_dvmmessage_tlb_secure_nonsecure_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ACADDR[9:8] for DVM Message type TLB Invalidate !	Checks the valid values of ACADDR[9:8] of DVM message type TLB Invalidate	When ACADDR[9:8] of DVM message type TLB Invalidate have following valid values: When ACADDR [11:10] is 2'b10 than ACADDR[9:8] have value 2'b00,2'b01,2'b10,2'b11 for dvm_version DVMV9_2 ACADDR[9:8] have value 2'b01,2'b10,2'b11 for dvm_version DVMV8_4 When ACADDR [11:10] is 2'b11 than ACADDR[9:8] have value 2'b00,2'b10,2'b11 for dvm_version DVMV9_2 ACADDR[9:8] have value 2'b10,2'b11 for dvm_version DVMV8_4 ACADDR[9:8] have value 2'b11 for other version	When ACADDR[9:8] of DVM message type TLB Invalidate not have valid values	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: TLBI	snoop_dvmmessage_tlb_hypervisor_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages	Monitor Check for the supported values of ACADDR[11:10] for DVM Message type TLB Invalidate !	Checks the valid values of ACADDR[11:10] of DVM message type TLB Invalidate	When ACADDR[11:10] of DVM message type TLBI have following valid value: For dvm_version DVMV9_2 when ACADDR[11:10] is 2'b00,2'b01,2'b10,2'b11 For other version ACADDR[11:10] is 2'b01,2'b10,2'b11	When ACADDR[11:10] of DVM message type TLB Invalidate not have valid values	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM	dvmcomplete_acaddr_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes	Monitor Check that for a DVM Complete, ACADDR is defined to be all zeros!	Checks For a DVM Complete, ACADDR is defined to be all zeros	When ACADDR must be zero for DVM Complete	When ACADDR is not zero for DVM Complete	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM Operation	dvm_operation_dvm_sync_acsnoop_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes	Monitor Check that ACSNOOP is 'b1111 for DVM Operation and DVM Sync!	Checks the value of ACSNOOP for the DVM SYNC	When the ACSNOOP value for DVM message must be 0b1111	When ACSNOOP value for DVM message is not 0b1111	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM	dvm_complete_acsnoop_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes	Monitor Check that ACSNOOP is 'b1110 for DVM Complete !	Checks the value of ACSNOOP for the DVM complete	When ACSNOOP for DVM complete must be 0b1110	When ACSNOOP for DVM complete is not 0b1110	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM	dvm_complete_arsnoop_valid_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes	Monitor Check that ARSNOOP is 'b1110 for DVM Complete!	Checks for DVMCOMPLETE the valid value of ARSNOOP	When ARSNOOP for DVMCOMPLETE must be 0b1110	When ARSNOOP for DVMCOMPLETE not of 0b1110	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Transactions	snoop_transaction_order_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor Check that all snoop transactions are ordered. The response, as given on the snoop response channel, must be in the same order that the transactions are presented on the snoop address channel!	Checks all snoop transactions are ordered	When the response, as given on the snoop response channel, must be in the same order that the transactions are presented on the snoop address channel	When the response, as given on the snoop response channel, is not in the same order that the transactions are presented on the snoop address channel	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Transactions	snoop_addr_snoop_resp_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor Check that the master must wait for both ACVALID and ACREADY to be asserted before asserting CRVALID!	Checks that ACVALID and ACREADY to be asserted before asserting CRVALID	When the master must wait for both ACVALID and ACREADY to be asserted before asserting CRVALID	When the master is not wait for both ACVALID and ACREADY to be asserted before asserting CRVALID	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Address	acsnoop_reserved_value_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling	Monitor Check that ACSNOOP does not have a reserved value!	Checks that ACSNOOP does not have reserved values	When ACSNOOP value is inside {0, 1, 2, 3, 7, 8, 9, 13, 14, 15}	When ACSNOOP value is not inside {0, 1, 2, 3, 7, 8, 9, 13, 14, 15}	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM	snoop_chan_dvmcomplete_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses	Monitor Check that a snoop responseCRRESP of 5'b00010 is not given for DVMComplete Transaction !	Checks the valid snoop response of DVM Complete Transactions	When a snoop response(CRRESP) of 5'b00010 is not given for DVM Complete Transaction	When a snoop response(CRRESP) of 5'b00010 is given for DVM Complete Transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM	snoop_chan_dvmsync_resp_valid_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses	Monitor Check that a snoop responseCRRESP of 5'b00010 is not given for DVMSync Transaction !	Checks the valid snoop response of DVM Message Transactions	When a snoop response(CRRESP) of 5'b00010 is not given for DVMSync Transaction	When a snoop response(CRRESP) of 5'b00010 is given for DVMSync Transaction	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arlen_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the arlen is valid for Cache Line Size Transactions!	Checks if the ARLEN is valid for Cache Line Size Transactions	When All cache line size transactions must have valid ARLEN	When All cache line size transactions not have have valid ARLEN	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awlen_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the awlen is valid for Cache Line Size Transactions!	Checks if the AWLEN is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AWLEN	When All cache line size transactions not have have valid AWLEN	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_arsize_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the arsize is valid for Cache Line Size Transactions!	Checks if the ARSIZE is valid for Cache Line Size Transactions	When All cache line size transactions must have valid ARSIZE	When All cache line size transactions not have have valid ARSIZE	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Cache Line Size Transactions Constraints	cache_line_awsize_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints	Monitor Check that the awsize is valid for Cache Line Size Transactions!	Checks if the AWSIZE is valid for Cache Line Size Transactions	When All cache line size transactions must have valid AWSIZE	When All cache line size transactions not have have valid AWSIZE	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Reset	acvalid_low_when_reset_is_active_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.1 Snoop request channel AC AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D2.3.3 Reset requirements	Monitor Check for ACVALID low when reset is active!	Checks if acvalid is low when reset is active	When reset is high than acvalid must not be asserted	When reset is high and acvalid is asserted	Passive Slave, Active/Passive Master	This check is applicable When: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: dvm_enable is set 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Reset	crvalid_low_when_reset_is_active_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D2.3.3 Reset requirements	Monitor Check for CRVALID low when reset is active!	Checks if crvalid is low when reset is active	When reset is high than crvalid must not be asserted	When reset is high and crvalid is asserted	Passive Master, Active/Passive Slave	This check is applicable When: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: dvm_enable is set 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Signal Stability	crvalid_interrupted_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.9 Snoop channel dependencies	Monitor Check for CRVALID held steady until CRREADY is asserted!	Checks if crvalid was interrupted before crready got asserted	When crready is received and crvalid to crready delay is zero	When crready is received and crvalid to crready delay is not zero	Passive Master, Active/Passive Slave	This check is applicable When: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: dvm_enable is set 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Signal Stability	acvalid_interrupted_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.1 Snoop request channel AC AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.6.2 Snoop address channel signaling	Monitor Check for ACVALID held steady until ACREADY is asserted!	Checks if acvalid was interrupted before acready got asserted	When acvalid is asserted and arvalid to acready delay is zero	When acvalid is not observed and acvalid to acready delay is not equal to zero	Passive Slave, Active/Passive Master	This check is applicable When: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE. svt_axi_port_configuration :: dvm_enable is set 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Response: Signal Validity	signal_valid_crvalid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.7 Snoop response channel signaling	Monitor Check for X or Z on CRVALID!	Checks that CRVALID is not X or Z	When CRVALID is not X or Z	When CRVALID is X or Z	Passive Master, Active/Passive Slave	This check is applicable When: svt_axi_port_configuration :: protocol_checks_enable is set to 1. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE and dvm_enable is set 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Address: Signal Validity	signal_valid_acvalid_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.1 Snoop request channel AC AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.6.2 Snoop address channel signaling	Monitor Check for X or Z on ACVALID!	Checks that ACVALID is not X or Z	When ACVALID is not X or Z	When ACVALID is X or Z	Passive Slave, Active/Passive Master	This check is applicable When: svt_axi_port_configuration :: protocol_checks_enable is set to 1. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE and dvm_enable is set 1.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Signal Stability	signal_stable_crtrace_when_crvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor check for signal stability when corresponding valid signal is high	Checks that CRTRACE is stable when CRVALID is high	CRTRACE is stable when CRVALID is high	CRTRACE is not stable when CRVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_port_configuration :: trace_tag_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Signal Stability	signal_stable_crresp_when_crvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor check for signal stability when corresponding valid signal is high	Checks that CRRESP is stable when CRVALID is high	CRRESP is stable when CRVALID is high	CRRESP is not stable when CRVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Signal Stability	signal_stable_acprot_when_acvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor check for signal stability when corresponding valid signal is high	Checks that ACPROT is stable when ARVALID is high	ACPROT is stable when ARVALID is high	ACPROT is not stable when ARVALID is high	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Signal Stability	signal_stable_acsnoop_when_acvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor check for signal stability when corresponding valid signal is high	Checks that ACSNOOP is stable when ARVALID is high	ACSNOOP is stable when ARVALID is high	ACSNOOP is not stable when ARVALID is high	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Signal Stability	signal_stable_acaddr_when_acvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies	Monitor check for signal stability when corresponding valid signal is high	Checks that ACADDR is stable when ARVALID is high	ACADDR is stable when ARVALID is high	ACADDR is not stable when ARVALID is high	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Response: Signal Validity	signal_valid_crtrace_when_crvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that CRTRACE is not X or Z when CRVALID is high	CRTRACE is not X or Z when CRVALID is high	CRTRACE is X or Z when CRVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_port_configuration :: trace_tag_enable is set to 1 svt_axi_port_configuration :: protocol_checks_enable is set to 1 crvalid_crready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Response: Signal Validity	signal_valid_crresp_when_crvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that CRRESP is not X or Z when CRVALID is high	CRRESP is not X or Z when CRVALID is high	CRRESP is X or Z when CRVALID is high	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_port_configuration :: protocol_checks_enable is set to 1 crvalid_crready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Response: Signal Validity	signal_valid_crready_when_crvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that CRREADY is not X or Z when CRVALID is high	CRREADY is not X or Z when CRVALID is high	CRREADY is X or Z when CRVALID is high	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1 svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Address: Signal Validity	signal_valid_acprot_when_acvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ACPROT is not X or Z when ARVALID is high	ACPROT is not X or Z when ARVALID is high	ACPROT is X or Z when ARVALID is high	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1 acvalid_to_acready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Address: Signal Validity	signal_valid_acsnoop_when_acvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ACSNOOP is not X or Z when ARVALID is high	ACSNOOP is not X or Z when ARVALID is high	ACSNOOP is X or Z when ARVALID is high	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1 acvalid_to_acready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Address: Signal Validity	signal_valid_acaddr_when_acvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ACADDR is not X or Z when ARVALID is high	ACADDR is not X or Z when ARVALID is high	ACADDR is X or Z when ARVALID is high	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1 acvalid_to_acready_delay is set to 0.	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	Snoop Address: Signal Validity	signal_valid_acready_when_arvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ACREADY is not X or Z when ARVALID is high	ACREADY is not X or Z when ARVALID is high	ACREADY is X or Z when ARVALID is high	Passive Slave, Active/Passive Master	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE svt_axi_port_configuration :: dvm_enable is set to 1	ERROR	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	DVM: VMID	signal_valid_arvmidext_when_arvalid_high_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.4 Support for 16-bit VMID	Monitor check for X or Z on signal when corresponding valid signal is high	Checks that ARVMIDEXT is not X or Z when ARVALID is high	ARVMIDEXT is not X or Z when ARVALID is high	ARVMIDEXT is X or Z when ARVALID is high	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: protocol_checks_enable is set to 1. svt_axi_system_configuration :: dvm_version is set to greater than equal to DVMV8_1 arvmidext_enable is set to 1. svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1. arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	signal_acaddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that observed_araddr[2:0] must be zero for multipart DVM transactions for dvm version less than DVMv8_4	Checks that observed_acaddr[2:0] must be zero for dvm_version less than DVM_v8.4 for multipart DVM transactions.	observed_acaddr[2:0] is zero for multipart DVM transactions.	observed_acaddr[2:0] is non zero for multipart DVM transactions.	Passive Slave, Active/Passive Master	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to less than DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_num_acaddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[5:4] and observed_araddr[2:0] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[5:4] and observed_acaddr[2:0] (NUM bits) must be zero for multipart DVM transactions.	observed_acaddr[5:4] and observed_acaddr[2:0] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_acaddr[5:4] and observed_acaddr[2:0] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Slave, Active/Passive Master	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_scale_acaddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[7:6] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[7:6] (SCALE) must be zero for multipart DVM transactions.	observed_acaddr[7:6] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_acaddr[7:6] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Slave, Active/Passive Master	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_ttl_acaddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[9:8] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[9:8] (TTL) must be zero for multipart DVM transactions.	observed_acaddr[9:8] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_acaddr[9:8] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Slave, Active/Passive Master	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_tg_acaddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[11:10] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[11:10] (TG) must be zero for multipart DVM transactions.	observed_acaddr[11:10] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_acaddr[11:10] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Slave, Active/Passive Master	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_num_araddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[5:4] and observed_araddr[2:0] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[5:4] and observed_araddr[2:0] (NUM bits) must be zero for multipart DVM transactions.	observed_araddr[5:4] and observed_araddr[2:0] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_araddr[5:4] and observed_araddr[2:0] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Master, Active/Passive Slave	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_scale_araddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[7:6] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[7:6] (SCALE) must be zero for multipart DVM transactions.	observed_araddr[7:6] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_araddr[7:6] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Master, Active/Passive Slave	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_ttl_araddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[9:8] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[9:8] (TTL) must be zero for multipart DVM transactions.	observed_araddr[9:8] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_araddr[9:8] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Master, Active/Passive Slave	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
ACE5_LiteDVM	DVM v8.4	valid_tg_araddr_multipart_dvm_xact_check	AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4	Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[11:10] must be zero for multipart DVM transactions	Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[11:10] (TG) must be zero for multipart DVM transactions.	observed_araddr[11:10] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	observed_araddr[11:10] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.	Passive Master, Active/Passive Slave	This check is applicable only when: The macro SVT_ACE5_ENABLE is defined svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4 svt_axi_port_configuration :: dvm_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1	ERROR	svt_axi_checker
AXI4,AXI5	Atomic Accesses	align_addr_atomicity_size_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A7.1 Single-copy atomicity size	Monitor Check that a transaction never has an atomicity guarantee greater than the alignment of its start address on ARADDR/AWADDR.	Checks that ARADDR/AWADDR should always be aligned to Atomicity Size	When transaction never has an atomicity size greater than the alignment of its start address on ARADDR/AWADDR	When transaction has an atomicity size greater than the alignment of its start address on ARADDR/AWADDR	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: atomicity_size is set to greater than -1	ERROR	svt_axi_checker
AXI4,AXI5	Interface Requirements	excl_access_on_write_only_interface_check	Synopsys Defined	Monitor Check that write only interface does not support exclusive access!	Checks that WRITE_ONLY_INTERFACE does not support exclusive access	When write only interface support does not exclusive access	When write only interface support exclusive access	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4. svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_WRITE_ONLY and curr_write_addr_xact.atomic_type is set to svt_axi_transaction :: EXCLUSIVE.	ERROR	svt_axi_checker
AXI4,AXI5	Interface Requirements	excl_access_on_read_only_interface_check	Synopsys Defined	Monitor Check that read only interface does not support exclusive access!	Checks that READ_ONLY_INTERFACE does not support exclusive access	When write only interface support does not exclusive access	When write only interface support exclusive access	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4. svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_ONLY and curr_read_addr_xact.atomic_type is set to svt_axi_transaction :: EXCLUSIVE.	ERROR	svt_axi_checker
AXI4,AXI5	Interface Requirements	write_xact_on_write_only_interface_check	Synopsys Defined	Monitor Check that write only interface supports only write Transactions!	Checks that WRITE_ONLY_INTERFACE supports only write transactions	When read transaction is not detected on WRITE ONLY interface	When read transaction detected on WRITE ONLY interface	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4. svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_WRITE_ONLY.	ERROR	svt_axi_checker
AXI4,AXI5	Interface Requirements	read_xact_on_read_only_interface_check	Synopsys Defined	Monitor Check that read only interface supports only read Transactions!	Checks that READ_ONLY_INTERFACE supports only read transactions	When write transaction is not detected on READ ONLY interface	When write transaction detected on READ ONLY interface	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4. svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_ONLY.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exokay_resp_observed_only_for_exclusive_transactions_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2 Exclusive accesses	Monitor checks that the EXOKAY response is observed only for permitted exclusive access transactions.For AXI3/AXI4 interfaces these are transactions with atomic_type is equal to EXCLUSIVE,For ACE_LITE interface these are READNOSNOOP, WRITENOSNOOP transaction or READONCE, WRITEUNIQUE if shareable_exclusive_access_from_acelite_ports_enable is set to '1'. For ACE interface these are READSHARED, READCLEAN and CLEANUNIQUE transaction !	checks that the EXOKAY response is observed only for permitted exclusive access transactions	When EXOKAY response is observed only for permitted exclusive access transactions	When EXOKAY response is not observed only for permitted exclusive access transactions	Passive Slave, Active/Passive Master	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 svt_axi_port_configuration :: exclusive_access_enable is set to 1 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3 svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Interface Requirements	awburst_awlen_valid_value_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute	Monitor Check that AWLEN and AWBURST are valid for AXI Transactions!	Checks if the AWLEN for INCR is valid for AXI Transactions	When the AWLEN can be any value from 1-16 for an INCR burst and AWLEN must be 2,4,8 or 16 for a WRAP burst	When the AWLEN does not take value from 1-16 for an INCR burst and AWLEN must be 2,4,8 or 16 for a WRAP burst	Passive Master, Active/Passive Slave	This check is applicable only when: svt_axi_port_configuration :: protocol_checks_enable is set to 1 transmitted_channel is set to svt_axi_transaction :: WRITE	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Interface Requirements	rlast_asserted_for_last_read_data_beat	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels	Monitor Check that RLAST is HIGH only for the last beat of READ burst !	Monitor Check that RLAST is HIGH only for the last beat of READ burst	When the last beat of read data is transfer than RLAST must be asserted	When the last beat of read data is transfer and RLAST is not asserted	Passive Slave, Active/Passive Master	This check is applicable when svt_axi_port_configuration :: rlast_enable is set to 1	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Interface Requirements	wlast_asserted_for_last_write_data_beat	AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.3.2 Write data channel W	Monitor Check that WLAST is asserted for last beat of write data!	Checks that WLAST is asserted for the last beat of write data Can be done reliably only if data_before_addr is not set, since if data_before_addr, observed_wlast could come at any point before the address comes	When the last beat of write data is transfered than wlast must be asserted	When the last beat of write data is transfered and wlast not asserted	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_transaction :: data_before_addr is not set and cfg.wlast_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exclusive_read_write_prot_type_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that protection type is generated same for exclusive accesss READ and WRITE transactions	Checks that protection type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.	When the exclusive access transaction protection type is same as normal transaction protection type	NA	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exclusive_read_write_cache_type_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that cache type is generated same for exclusive accesss READ and WRITE transactions	Checks that cache type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.	When the exclusive access transaction cache type is same as normal transaction cache type	NA	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exclusive_read_write_burst_type_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that burst type is generated same for exclusive accesss READ and WRITE transactions	Checks that burst type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.	When the exclusive access transaction burst type is same as normal transaction burst type	NA	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exclusive_read_write_burst_size_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that burst size is generated same for exclusive accesss READ and WRITE transactions	Checks that burst size is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.	When the exclusive access transaction burst size is same as normal transaction burst size	NA	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exclusive_read_write_burst_length_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that burst length is generated same for exclusive accesss READ and WRITE transactions	Checks that burst length is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.	When the exclusive access transaction burst length is same as normal transaction burst length	NA	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	exclusive_read_write_addr_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that address is generated same for exclusive accesss READ and WRITE transactions	Checks that address is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.	When the exclusive access transaction address is same as normal transaction	NA	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	signal_valid_exclusive_write_addr_aligned_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that exclusive access start address is aligned to the total number of bytes of the transaction	Checks that address is aligned for exclusive write transaction	When the start address is aligned to the total number of bytes in the exclusive write transaction	When the start address is not aligned to the total number of bytes in the transaction which is not valid for exclusive write transactions	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	signal_valid_exclusive_awcache_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that exclusive access being monitored by a slave must not have an ARCACHE[3:0] or AWCACHE[3:0] value that indicates that the transaction is cacheable	Checks that AWCACHE is valid for exclusive read transaction	When AWCACHE[3:0] indicates that the transaction is cacheable for exclusive read transactions	When AWCACHE[3:0] indicates that the transaction is not cacheable for exclusive read transactions	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	signal_valid_exclusive_awlen_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	The burst length for an exclusive access must not exceed 16 transfers.	Checks that AWLEN is valid for exclusive store transaction	The burst length for an exclusive store transaction does not exceed 16 transfers.	The burst length for an exclusive store transaction exceeds 16 transfers.	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	signal_valid_exclusive_awlen_awsize_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that burst size and burst_length combination is valid for Exclusive access. The number of bytes that can be transferred in an exclusive access burst must be power of 2	Checks that AWLEN and AWSIZE are valid for exclusive store transaction	When the number of bytes that can be transferred in an exclusive access burst must be power of 2 That is 1,2,4,8,16,32,64,128 bytes	When the number of bytes that can be transferred in an exclusive access burst is not power of 2	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	signal_valid_exclusive_read_addr_aligned_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that exclusive access start address is aligned to the total number of bytes of the transaction	Checks that address is aligned for exclusive read transaction	When the start address is aligned to the total number of bytes in the exclusive read transaction	When the start address is not aligned to the total number of bytes in the transaction which is not valid for exclusive read transactions	Passive Master, Active/Passive Slave	This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	signal_valid_exclusive_arcache_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	Monitor check that exclusive access being monitored by a slave must not have an ARCACHE[3:0] or AWCACHE[3:0] value that indicates that the transaction is cacheable	Checks that ARCACHE is valid for exclusive read transaction	When ARCACHE[3:0] indicates that the transaction is cacheable for exclusive read transactions	When ARCACHE[3:0] indicates that the transaction is not cacheable for exclusive read transactions	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.	ERROR	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	Exclusive Accesses	signal_valid_exclusive_arlen_check	AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions	The burst length for an exclusive access must not exceed 16 transfers.	Checks that ARLEN is valid for exclusive read transaction	The burst length for an exclusive read transaction does not exceed 16 transfers	The burst length for an exclusive read transaction exceeds 16 transfers	Passive Master, Active/Passive Slave	This check is applicable when: svt_axi_port_configuration :: exclusive_access_enable is set to 1. svt_axi_port_configuration :: protocol_checks_enable is set to 1.	ERROR	svt_axi_checker

Group

Sub Group

Protocol Check Instance name

Reference

Description

Check Intent

Pass Condition

Fail Condition

Applicable Device Type

Additional Information

Error Category

Protocol Check Class

APB2

State Transition

initial_bus_state_after_reset

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

After reset the bus initially should be in either IDLE or SETUP State

Checks that after reset de-assertion, APB Bus is in either IDLE or SETUP state.

APB Bus is in either IDLE or SETUP state after reset de-assertion.

For master, either PSEL is zero or PENABLE is 0, immediately after reset de-assertion
For slave, either PSEL or PENABLE sampled as 0, immediately after reset de-assertion

APB Bus is in ACCESS state after reset de-assertion.

For master, PSEL of the selected slave is 1 and PENABLE is 1, immediately after reset de-assertion
For slave, PSEL and PENABLE both sampled as 1, immediately after reset de-assertion

Active & Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Slave Selection

multiple_select_signals_active_during_transfer

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.4.2 APB bridge description

Only one select signal can be active during a transfer

Checks if multiple select signals asserted during transfer

Only one select signal asserted during transfer

Multiple select signals asserted during transfer

Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_prdata_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PRDATA must be valid when PSEL, PENABLE and PREADY are asserted for read transfer

Checks that PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer

PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer

PRDATA is X or Z when PSEL, PENABLE and PREADY are asserted for read transfer

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
The macro SVT_APB_SLAVE_DRIVE_X_IF_MEMDATA_X is not defined

ERROR

APB2

Unaligned Transfers

address_not_aligned_when_unaligned_address_support_not_enabled

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus

Unaligned address should not be driven on PADDR when unaligned_address_support is not enabled

Checks if unaligned address is driven on PADDR when unaligned_address_support is not enabled.

Aligned address is driven on PADDR

Unaligned address is driven on PADDR

Passive Master, Active & Passive Slave

Group: APB2
Default severity: WARNING
If unaligned address driving and sampling is required and need to bypass this check, please enable unaligned address support setting svt_apb_configuration :: unaligned_address_support to 1

WARNING

APB2

Signal Stability

pwdata_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers

PWDATA must be stable until the write transfer completes

Checks if PWDATA changed value during write transfer

PWDATA is stable during write transfer

PWDATA is changed during write transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

If svt_apb_configuration :: check_valid_data_bytes_only_enable and svt_apb_system_configuration :: apb4_enable are set to 1, then check will be performed only on active data byte lanes based on pstrb.

ERROR

APB2

Signal Stability

pwrite_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PWRITE must be stable until the transfer completes

Checks if PWRITE changed value during transfer

PWRITE is stable during transfer

PWRITE is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Stability

paddr_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PADDR must be stable until the transfer completes

Checks if PADDR changed value during transfer

PADDR is stable during transfer

PADDR is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Stability

psel_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PSEL must be stable until the transfer completes

Checks if PSEL changed value during transfer

PSEL is stable during the transfer

PSEL is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_pwdata_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PWDATA must be valid when PSEL is asserted for write transfer

Checks that PWDATA is not X or Z when PSEL is asserted for write transfer

PWDATA is not X or Z when PSEL is asserted for write transfer

PWDATA is X or Z when PSEL is asserted for write transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_penable_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PENABLE must be valid when PSEL is asserted

Checks that PENABLE is not X or Z when PSEL is asserted

PENABLE is not X or Z when PSEL is asserted

PENABLE is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_pwrite_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PWRITE must be valid when PSEL is asserted

Checks that PWRITE is not X or Z when PSEL is asserted

PWRITE is not X or Z when PSEL is asserted

PWRITE is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_paddr_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PADDR must be valid when PSEL is asserted

Checks that PADDR is not X or Z when PSEL is asserted

PADDR is not X or Z when PSEL is asserted

PADDR is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_psel_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSEL must be always valid

Checks that PSEL is not X or Z

PSEL is not X or Z

PSEL is X or Z

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

State Transition

penable_after_psel

AMBA APB Protocol Specification ARM IHI 0011A: 5.2.1 State diagram

PENABLE should be asserted after one clock cycle of PSEL being asserted

Checks that PENABLE is asserted after one clock cycle of PSEL being asserted.

PENABLE is asserted after one clock cycle of PSEL being asserted

PSEL and PENABLE asserted simultaneously
PENABLE is not asserted after one clock cycle of PSEL being asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Address Mapping

psel_match_with_address_map

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.5.2 APB slave description

Asserted PSEL should match with the address map

Checks that asserted PSEL matches with the address map. Refer to ARM IHI 0011A section 2.4, signal description of PSELx for the protocol info.

slave ID obtained by address decoding is equal to the slave ID that has PSEL asserted.

slave ID obtained by address decoding is not equal to the slave ID that has PSEL asserted.

Passive Master, Active & Passive Slave

In case of complex_memory_map enabled, pprot1 is also considered in address decoding.

ERROR

APB2

State Transition

setup_to_setup

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

SETUP to SETUP is an illegal state transition

Checks that if illegal state transition occured from setup to setup

No state transition occured from setup to setup

Illegal state transition occured from setup to setup

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

APB2 State Transition

access_to_access

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

ACCESS to ACCESS is an illegal state transition in APB2

Checks that if illegal state transition occured from access to access in APB2. In APB3 state transition from access to access is valid transition.

No state transition occured from access to access in APB2

Illegal state transition occured from access to access in APB2

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

State Transition

setup_to_idle

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

SETUP to IDLE is an illegal state transition

Checks that if illegal state transition occured from setup to idle

No state transition occured from setup to idle

Illegal state transition occured from setup to idle

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

APB2 State Transition

bus_in_enable_state_for_one_clock

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.2.1 State diagram

ENABLE state lasts only for a single clock cycle in APB2

Checks that bus remains in ENABLE state for one clock cycle in APB2

Bus remains in ENABLE state for one clock cycle in APB2

Bus remains in ENABLE state for more than one clock cycle in APB2

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb3_enable and svt_apb_system_configuration :: apb4_enable are set to 0

ERROR

APB3

Signal Validity

signal_valid_pslverr_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSLVERR must be valid when PSEL, PENABLE and PREADY are asserted

Checks that PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted

PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted

PSLVERR is X or Z when PSEL, PENABLE and PREADY are asserted

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB3

Signal Validity

signal_valid_pready_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PREADY must be valid when PSEL and PENABLE are asserted

Checks that PREADY is not X or Z when PSEL and PENABLE are asserted

PREADY is not X or Z when PSEL and PENABLE are asserted

PREADY is X or Z when PSEL and PENABLE are asserted

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB3

Transaction Timeout

pready_timeout_check

Synopsys Defined

PREADY should be asserted by the slave within the timeout period

Checks that PREADY signal is asserted by slave within timeout period slave_pready_timeout

PREADY signal is asserted by slave within timeout period slave_pready_timeout

PREADY signal is not asserted by slave within timeout period slave_pready_timeout

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1
svt_apb_system_configuration :: slave_pready_timeout is not equal to 0

ERROR

APB3

Signal Stability

penable_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PENABLE must be stable until the transfer completes

Checks if PENABLE changed value during access phase of transfer

PENABLE high during access phase of transfer

PENABLE low during access phase of transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB3

State Transition

idle_to_access

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

IDLE to ACCESS is an illegal state transition

Checks that if illegal state transition occured from idle to access

No state transition occured from idle to access

Illegal state transition occured from idle to access

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB4 Protection Unit Support

Signal Stability

pprot_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PPROT must be stable until the transfer completes

Checks if PPROT changed value during transfer

PPROT is stable during transfer

PPROT is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Protection Unit Support

Signal Validity

signal_valid_pprot_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PPROT must be valid when PSEL is asserted

Checks that PPROT is not X or Z when PSEL is asserted

PPROT is not X or Z when PSEL is asserted

PPROT is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

Signal Stability

pstrb_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers

PSTRB must be stable until the transfer completes

Checks if PSTRB changed value during write transfer

PSTRB is stable during write transfer

PSTRB is changed during write transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

PSTRB Validity

pstrb_low_for_read

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.2 Write strobes

All bits of PSTRB must be LOW for read transfer

Checks that PSTRB is low for read transfer

All bits of PSTRB are low for read transfer

Any bit of PSTRB is high for read transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

Signal Validity

signal_valid_pstrb_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSTRB must be valid when PSEL is asserted

Checks that PSTRB is not X or Z when PSEL is asserted

PSTRB is not X or Z when PSEL is asserted

PSTRB is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

Unaligned Transfers

pstrb_asserted_for_invalid_byte_in_unaligned_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus & 3.2 Write strobes

PSTRB should be correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled

Checks if PSTRB is correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled.

PSTRB is correctly asserted based on the address alignment

PSTRB is not correctly asserted based on the address alignment

Passive Master, Active & Passive Slave

Group: APB4
Default severity: ERROR
Applicable for APB4 systems when unaligned address support is enabled using svt_apb_configuration :: unaligned_address_support configuration.

ERROR

AHB System

Manager Subordinate Transaction Association

master_slave_xact_resp_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Response signals should match between manager transaction and the corresponding subordinate transaction.

Checks that response signals match between manager transaction and the corresponding subordinate transaction.

All the all_beat_response array values match between manager and corresponding subordinate transaction.

Any of the all_beat_response array values does not match between manager and corresponding subordinate transaction.

System Monitor

Group: AHB
Default severity: ERROR
Limitations: Currently disabled for AHB Lite multilayer.

ERROR

AHB System

Manager Subordinate Transaction Association

master_slave_xact_data_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Data values should match between manager transaction and the corresponding subordinate transaction.

Checks that data values match between manager transaction and the corresponding subordinate transaction.

All the data array values match between manager and corresponding subordinate transaction.

Any of the data array values does not match between manager and corresponding subordinate transaction.

System Monitor

Group: AHB
Default severity: ERROR
Limitations: Currently disabled for AHB Lite multilayer.

ERROR

AHB System

Manager Subordinate Transaction Association

master_slave_xact_addr_ctrl_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Address and control signals should match between manager transaction and the corresponding subordinate transaction.

Checks that address and control signals match between manager transaction and the corresponding subordinate transaction.
Following control signal attributes are compared.

addr
xact_type
burst_type
burst_size
prot_type

All the compared signal attributes match between manager and corresponding subordinate transaction.

Any of the compared signal attributes does not match between manager and corresponding subordinate transaction.

System Monitor

Group: AHB
Default severity: ERROR
Limitations: Currently disabled for AHB Lite multilayer.

ERROR

AHB System

Dummy Manager

xact_not_idle_when_dummy_master_active

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus manager

Transfer type of the transaction is not IDLE when dummy manager is active.

Checks that IDLE transactions are driven when the dummy manager is active

IDLE transactions are driven when the dummy manager is active

IDLE transactions are not driven when the dummy manager is active

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Locked Transfers in Arbiter

hmastlock_changed_during_incr

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked transfers

HMASTLOCK signal changed during INCR burst transfer.

Checks that the HMASTLOCK signal remains constant during an INCR burst

HMASTLOCK signal remains constant during an INCR burst

HMASTLOCK signal changes during an INCR burst

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Locked Transfers in Arbiter

arbiter_asserted_hmastlock_without_hlock

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers

Arbiter asserted HMASTLOCK signal when the manager has not requested.

Checks that the arbiter does not assert HMASTLOCK when the manager has not requested

Arbiter does not assert HMASTLOCK when the manager has not requested

Arbiter does asserts HMASTLOCK when the manager has not requested

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Locked Transfers in Arbiter

arbiter_lock_last_grant

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers

Arbiter did not keep manager granted for an additional transfer after a locked sequence.

Checks that the arbiter keeps the manager granted for an additional transfer after a locked sequence

Arbiter keeps the manager granted for an additional transfer after a locked sequence

Arbiter does not keeps the manager granted for an additional transfer after a locked sequence

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Locked Transfers in Arbiter

arbiter_changed_hmaster_during_lock

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers

HMASTER signal changed during locked transfer.

Checks that the arbiter does not change HMASTER during a locked transfer

Arbiter does not change HMASTER during a locked transfer

Arbiter changes HMASTER during a locked transfer

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Granted Manager in Split Transfer in Arbiter

mask_hgrant_until_hsplit_assert

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12.1 Split transfer sequence

Manager should not be regranted until the subordinate is ready to complete the transfer and asserts HSPLIT.

Checks that if the manager has got split, grant must be not given to that manager until subordinate asserts hsplitx

Grant not given to the manager until subordinate asserts hsplitx

Grant given to the manager when subordinate didn't asserted hsplitx

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Granted Manager in Split Transfer in Arbiter

grant_to_default_master_during_allmaster_split

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus master

If all managers has received a SPLIT response then the default manager is granted the bus.

Checks that If all managers has received a SPLIT response then the default manager is granted the bus.

Default manager is granted the bus when all managers has received a SPLIT.

Default manager is not granted the bus when all managers has received a SPLIT.

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Granted Manager in Arbiter

arbiter_changed_hmaster_during_wait

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.11.3 Granting bus access

HMASTER signal changed during waited state.

Checks that the arbiter does not change HMASTER during a waited transfer

Arbiter does not change HMASTER during a waited transfer

Arbiter changes HMASTER during a waited transfer.

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Granted Manager in Arbiter

arbiter_asserted_hmaster_ne_granted_master

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access

HMASTER signal does not reflect the granted manager.

Checks that the arbiter assert HMASTER to reflect the Granted manager

HMASTER signal reflects the granted manager

HMASTER signal does not reflect the granted manager

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Granted Manager in Arbiter

arbiter_asserted_multi_hgrant

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access

Arbiter asserted more than one HGRANT signal.

Checks that the arbiter does not assert more than one HGRANT signal

Arbiter not asserted more than one HGRANT signal

Arbiter asserted more than one HGRANT signal

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Subordinate Selection in Decoder

decoder_not_asserted_any_hsel

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals

Decoder not asserted any HSEL signal.

Checks that the decoder does assert atleast one HSEL signal

Decoder asserted atleast one HSEL signal

Decoder not asserted atleast one HSEL signal

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Subordinate Selection in Decoder

decoder_asserted_multi_hsel

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals

Decoder asserted more than one HSEL signal.

Checks that the decoder does not assert more than one HSEL signal

Decoder not asserted more than one HSEL signal

Decoder asserted more than one HSEL signal

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Data Integrity

data_integrity_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Transaction data inconsistent with subordinate memory.

Checks that data in transaction is consistent with data in memory when the transaction completes. This checks that a WRITE transaction issued by a manager is written to memory correctly. Similarly, it checks that a READ transaction fetches the correct data from memory. The check assumes that a transaction issued by a manager completes only after response is received from the subordinate to which that transaction was routed. It also assumes that there is no other transaction that accesses an overlapping address during the period that the response is issued by the subordinate and the transaction completes in the manager that issued the transaction.
Note that this check is not performed on the transactions that are routed to the default subordinate.

Data in transaction is consistent with data in memory

Data in transaction is not consistent with data in memory

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB System

Routing

slave_transaction_routing_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.1 Interconnect

Transaction not routed to the correct subordinate based on system address map.

Checks that a transaction is routed correctly to a slave port based on address.

This check is not performed on default_slave if the default slave is set to -1 through svt_ahb_system_configuration :: default_slave.
If svt_ahb_system_configuration :: default_slave is set to a value in the range 0 to 15, then this check is performed on the default slave also.
This check is preformed on all the slaves other than the default slave irrespective of the value of svt_ahb_system_configuration :: default_slave.

Transaction routed to the correct subordinate based on system address map

Transaction not routed to the correct subordinate based on system address map

System Monitor

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Address Phase Timing

ahb_address_phase_extended

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 1.3 Operation

A Subordinate cannot request that the address phase is extended.

Checks that address phase is not extended by the Subordinate

Address phase is started by driving HREADY high when HTRANS is NSEQ

Address phase is extended by driving HREADY low when HTRANS is NSEQ, and no extended data phase pending from a previous transaction

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

During Reset

hready_out_from_bus_high_during_reset

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset

During reset, HREADY output from bus must be HIGH

Checks that HREADY output signal from bus is HIGH when reset is active

HREADY output signal from bus is HIGH when reset is active

HREADY output signal from bus is not HIGH when reset is active

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
This check is performed when svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1.

ERROR

AHB_COMMON

Performance Metrics

perf_min_write_throughput

SYNOPSYS DEFINED

Checks that the throughput of write transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of write transactions in a given interval is not less that the configured min value

Throughput of write transactions in a given interval is not less that the configured min value

Throughput of write transactions in a given interval is less that the configured min value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_max_write_throughput

SYNOPSYS DEFINED

Checks that the throughput of write transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of write transactions in a given interval is not more that the configured max value

Throughput of write transactions in a given interval is not more that the configured max value

Throughput of write transactions in a given interval is more that the configured max value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_min_read_throughput

SYNOPSYS DEFINED

Checks that the throughput of read transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of read transactions in a given interval is not less that the configured min value

Throughput of read transactions in a given interval is not less that the configured min value

Throughput of read transactions in a given interval is less that the configured min value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_max_read_throughput

SYNOPSYS DEFINED

Checks that the throughput of read transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of read transactions in a given interval is not more that the configured max value

Throughput of read transactions in a given interval is not more that the configured max value

Throughput of read transactions in a given interval is more that the configured max value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_avg_min_read_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of read transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of read transactions in a given interval is not less than the configured min value

Average latency of read transactions in a given interval is not less than the configured min value

Average latency of read transactions in a given interval is less than the configured min value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_avg_max_read_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of read transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of read transactions in a given interval is not more than the configured max value

Average latency of read transactions in a given interval is not more than the configured max value

Average latency of read transactions in a given interval is more than the configured max value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_min_read_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a read transaction is more than or equal to the configured min value

Checks that the latency of a read transaction is not lesser than the configured min value

Latency of a read transaction is not lesser than the configured min value

Latency of a read transaction is lesser than the configured min value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_max_read_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a read transaction is less than or equal to the configured max value

Checks that the latency of a read transaction is not greater than the configured max value

Latency of a read transaction is not greater than the configured max value

Latency of a read transaction is greater than the configured max value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_avg_min_write_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of write transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of write transactions in a given interval is not less than the configured min value

Average latency of write transactions in a given interval is not less than the configured min value

Average latency of write transactions in a given interval is less than the configured min value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_avg_max_write_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of write transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of write transactions in a given interval is not more than the configured max value

Average latency of write transactions in a given interval is not more than the configured max value

Average latency of write transactions in a given interval is more than the configured max value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_min_write_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a write transaction is more than or equal to the configured min value

Checks that the latency of a write transaction is not lesser than the configured min value

Latency of a write transaction is not lesser than the configured min value

Latency of a write transaction is lesser than the configured min value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Performance Metrics

perf_max_write_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a write transaction is less than or equal to the configured max value

Checks that the latency of a write transaction is not greater than the configured max value

Latency of a write transaction is not greater than the configured max value

Latency of a write transaction is greater than the configured max value

Active/Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Validity

signal_valid_hrdata_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HRDATA must not be X/Z

Checks that HRDATA is not X or Z

HRDATA does not contain any X or Z bits

HRDATA contains X or Z bits

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR
Note: This check is performed only for the transaction with OKAY response and ERROR response having svt_ahb_system_configuration :: error_response_policy as svt_ahb_system_configuration :: CONTINUE_ON_ERROR.
It is recommended that HRDATA is driven to zero when an ERROR response is given to a read transfer.
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_COMMON

Signal Validity

signal_valid_hwdata_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HWDATA must not be X/Z

Checks that HWDATA is not X or Z

HWDATA does not contain any X or Z bits

HWDATA contains X or Z bits

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
Note: This check is performed only for the transaction with OKAY response and ERROR response having svt_ahb_system_configuration :: error_response_policy as svt_ahb_system_configuration :: CONTINUE_ON_ERROR.
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_COMMON

Response Type

zero_wait_cycle_okay

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

IDLE and BUSY transfers must receive zero wait cycle OKAY response.

Checks that IDLE and BUSY transfers receive zero wait cycle OKAY response

IDLE and BUSY transfers receive zero wait cycle OKAY response

IDLE and BUSY transfers doesn't receive zero wait cycle OKAY response

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Two Cycle Response

two_cycle_error_resp

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response

ERROR response was not completed in two cycles.

Checks that ERROR response completes in two cycles

ERROR response completes in two cycles

ERROR response was not completed in two cycles

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Response Type

non_okay_response_in_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.2 Transfer pending

Response other than OKAY response was received during wait state.

Checks that only OKAY responses are received during wait state

OKAY responses are received during wait state

OKAY responses are not received during wait state

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Validity

signal_valid_hresp_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HRESP must not be X/Z

Checks that HRESP is not X or Z

HRESP is not X or Z

HRESP is X or Z

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_COMMON

Signal Validity

signal_valid_hready_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HREADY must not be X/Z

Checks that HREADY is not X or Z

HREADY does not contain any X or Z bits

HREADY contains X or Z bits

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_COMMON

Burst Length

burst_length_exceeded

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Burst length exceeded for fixed length burst.

Checks number of beats in a fixed length burst

Burst length not exceeded fixed length burst

Burst length exceeded for fixed length burst

Passive Manager

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Locked Transfers

hlock_asserted_during_non_locked_xact

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.1 Signal description

Manager should not assert lock signal in the middle of a non-locked transaction.

Checks that manager shouldn't assert hlock in the middle of a non-locked transaction

Manager not asserted hlock in the middle of a non-locked transaction

Manager asserted hlock in the middle of a non-locked transaction

Passive Manager

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Validity

signal_valid_hlock_check

AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list

HLOCK must not be X/Z

Checks that HLOCK is not X or Z on manager interface

HLOCK does not contain any X or Z bits

HLOCK contains X or Z bits

Passive Manager

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_COMMON

Locked Transfers

different_subordinate_addr_region_during_locked_sequence

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked Transfers

It is required that all transfers in a locked sequence are to the same Subordinate address region.

It is required that all transfers in a locked sequence are to the same subordinate address region.

Manager performing a transfer to the same subordinate address region

Manager performing a transfer to a different subordinate address region

Passive Manager and Active/Passive Subordinate

Group: AHB5
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Type

htrans_not_changed_to_idle_during_error

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response

HTRANS did not change to IDLE during ERROR response.

Checks that HTRANS changes to IDLE during second cycle of ERROR response

HTRANS changes to IDLE during ERROR response

HTRANS did not change to IDLE during ERROR response

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

During Reset

htrans_idle_during_reset

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset

During reset, HTRANS must be IDLE2'b00

Checks that HTRANS output signal from manager/bus is IDLE when reset is active

HTRANS output signal from manager/bus is IDLE when reset is active

HTRANS output signal from manager/bus is not IDLE when reset is active

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
This check is performed when svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1.

ERROR

AHB_COMMON

Transfer Type

seq_or_busy_before_nseq_during_xfer

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Manager started burst with SEQ or BUSY instead of NSEQ.

Checks that a manager started burst with SEQ or BUSY instead of NSEQ

Manager started burst with NSEQ

Manager started burst with BUSY or SEQ

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Type

illegal_idle2seq

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Manager attempted SEQ transfer following IDLE.

Checks for IDLE changed to SEQ

SEQ is not followed by IDLE

SEQ is followed by IDLE

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Type

illegal_idle2busy

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Manager attempted BUSY transfer following IDLE.

Checks for IDLE changed to BUSY

BUSY is not followed by IDLE

BUSY is followed by IDLE

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Type

idle_changed_to_busy_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Manager cancelled IDLE transfer during wait state and changed it to BUSY transfer.

Checks for IDLE changed to BUSY during wait state

IDLE not changed to BUSY during wait state

IDLE changed to BUSY during wait state

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Type

idle_changed_to_seq_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Manager cancelled IDLE transfer during wait state and changed it to SEQ transfer.

Checks for IDLE changed to SEQ during wait state

IDLE not changed to SEQ during wait state

IDLE changed to SEQ during wait state

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Stability

ctrl_or_addr_changed_during_busy

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Control signalsother than HTRANS or address changed during BUSY.

Checks whether control signals(other than HTRANS) or address changed during BUSY

Control signals and address not changed during busy transfer

Control signals or address changed during busy transfer

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Stability

illegal_control_transition

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals

Control signals other than HTRANS changed during burst.

Checks whether control signals(other than HTRANS) changed during burst

Control signals not changed during burst

Control signals changed during burst

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Burst Address

ahb_valid_beat_address_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

valid beat address check.

Checks for valid beat address of each beat in a transaction

Beat address is getting updated correctly

Beat address not updated correctly Beat address and haddr is not same

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Burst Address

illegal_address_transition

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Illegal address transition during burst.

Checks for illegal address transition during burst

Address is getting updated correctly

Address not updated correctly

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Burst Address

boundry_crossing_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Burst transfer crossed boundary

Checks that burst transfer does not cross configured boundary limit

Burst transfer does not cross configured boundary limit

Burst transfer crosses configured boundary limit

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Burst Address

one_k_boundry_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Burst transfer crossed 1 KB boundary.

Checks that burst transfer does not cross 1 KB boundary

Burst transfer does not cross 1 KB boundary

Burst transfer crosses 1KB boundary

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Size

hsize_too_big_for_data_width

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.3.3 Implementing a Manager on a wide bus

Manager attempted transfer size greater than data bus width.

Checks that manager attempted transfer size greater than data bus width

Manager attempted transfer size is not greater than data bus width

Manager attempted transfer size greater than data bus width

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Early Burst Termination

burst_terminated_early_after_okay

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination

Manager terminated burst early after OKAY response.

Checks that burst transaction was not terminated early:

AHB manager should never terminate a burst transfer when OKAY response is received.
In case of Full-AHB mode, the manager should rebuild the burst transfer in case of EBT/SPLIT/RETRY before initiating new burst.

Manager not terminated burst early after OKAY response

Manager terminated burst early after OKAY response

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Stability

hwdata_changed_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.1.1 HWDATA

HWDATA changed during wait state.

Checks that write data does not change during waited state

Write data does not change during waited state

Write data changed during waited state

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Stability

ctrl_or_addr_changed_end_of_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Control or address changed at the end of wait state.

Checks that control and address does not change at the end of wait state

Control signals and address not changed at the end of wait state

Control signals or address changed at the end of wait state

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
Check is not performed during reset and other than OKAY response conditions

ERROR

AHB_COMMON

Signal Stability

ctrl_or_addr_changed_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Control or address changed during wait state.

Checks that contol and address does not change during wait state except when htrans changes from IDLE to NSEQ

Control signals and address not changed during wait state

Control signals or address changed during wait state

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
Check is not performed when htrans changes from IDLE to NSEQ other than OKAY response conditions.

ERROR

AHB_COMMON

Signal Stability

htrans_changed_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

HTRANS changed during wait state.

Checks that htrans does not change during wait state except when htrans changes from

IDLE to NSEQ during wait state for all burst types
BUSY to SEQ during wait state for all burst types
BUSY to NSEQ during wait state for unspecified length burst
BUSY to IDLE during wait state for unspecified length burst

HTRANS not changed during wait state

HTRANS changed during wait state

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Type

seq_or_busy_during_active_xact

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

In active transaction, SEQ or BUSY transfer should only occur after NSEQ.

Checks that a SEQ or BUSY trans only occur during active transaction after nseq

SEQ or BUSY trans occurs during active transaction after nseq

SEQ or BUSY trans occurs not during active transaction

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Transfer Type

trans_during_single_is_nseq

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Transfer type of a SINGLE burst is not NSEQ

Checks that transfer type of a SINGLE burst is NSEQ

Transfer type of a SINGLE burst is NSEQ

Transfer type of a SINGLE burst is not NSEQ

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Validity

signal_valid_hprot_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HPROT must not be X/Z

Checks that HPROT is not X or Z

HPROT does not contain any X or Z bits

HPROT contains X or Z bits

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_COMMON

Signal Validity

signal_valid_hburst_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HBURST must not be X/Z

Checks that HBURST is not X or Z

HBURST does not contain any X or Z bits

HBURST contains X or Z bits

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_COMMON

Signal Validity

signal_valid_hsize_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HSIZE must not be X/Z

Checks that HSIZE is not X or Z

HSIZE does not contain any X or Z bits

HSIZE contains X or Z bits

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_COMMON

Signal Validity

signal_valid_htrans_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HTRANS must not be X/Z

Checks that HTRANS is not X or Z

HTRANS does not contain any X or Z bits

HTRANS contains X or Z bits

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_COMMON

Signal Validity

signal_valid_hwrite_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HWRITE must not be X/Z

Checks that HWRITE is not X or Z

HWRITE is not X or Z

HWRITE is X or Z

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_COMMON

Signal Validity

signal_valid_haddr_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HADDR must not be X/Z

Checks that HADDR is not X or Z

HADDR does not contain any X or Z bits

HADDR contains X or Z bits

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: addr_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_COMMON

Signal Validity

hready_out_from_slave_not_X_or_Z_when_data_phase_not_pending

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.3 Subordinate signals

HREADY output from subordinate must be either HIGH or LOW when there is no pending data phase.

Checks that HREADY output from subordinate must be either HIGH or LOW when there is no data phase pending. That is, checks that the subordinate cannot request that the address phase is extended.

HREADY output from subordinate must be either HIGH or LOW

HREADY output from subordinate is either X or Z

Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

During Reset

hready_out_from_slave_not_X_or_Z_during_reset

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset

During reset, HREADY output from subordinate must be either HIGH or LOW

Checks that HREADY output signal from subordinate is either HIGH or LOW when reset is active

HREADY output signal from subordinate is either HIGH or LOW when reset is active

HREADY output signal from subordinate is X or Z when reset is active

Passive Subordinate

Group: AHB
Default severity: ERROR
This check is performed when svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1.

ERROR

AHB_COMMON

Response Type

illegal_default_slave_resp_to_nseq_seq

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.1 Default Subordinate

Default subordinate should provide ERROR response for NON_SEQ or SEQ transfer.

Checks that for non existent memory location default subordinate should provide ERROR response for NSEQ/SEQ transfers

Default subordinate giving error response for NSEQ/SEQ transfers when accessing nonexistent address location

Default subordinate not giving error response for NSEQ/SEQ transfers when accessing nonexistent address location

Active/Passive Manager

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Subordinate Selection

invalid_hsel_assert_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.2 Multiple Subordinate select

Invalid HSEL signal asserted for selected subordinate

Checks that if invalid HSEL is asserted for selected subordinate. This is applicable only in mutli_hsel_enable mode

HSEL is asserted for selected subordinate

Invalid HSEL is asserted for selected subordinate

Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Validity

signal_valid_hready_in_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HREADY_IN must not be X/Z

Checks that HREADY_IN is not X or Z

HREADY_IN does not contain any X or Z bits

HREADY_IN contains X or Z bits

Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_COMMON

Signal Validity

signal_valid_hmastlock_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HMASTLOCK must not be X/Z

Checks that HMASTLOCK is not X or Z on subordinate interface

HMASTLOCK is not X or Z

HMASTLOCK is X or Z

Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_COMMON

Signal Validity

signal_valid_hmaster_range_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals

HMASTER should not be beyond SVT_AHB_MAX_NUM_MASTERS

Checks that HMASTER value is in valid range based on SVT_AHB_MAX_NUM_MASTERS

HMASTER value is less than SVT_AHB_MAX_NUM_MASTERS

HMASTER value is more than SVT_AHB_MAX_NUM_MASTERS

Active/Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_COMMON

Signal Validity

signal_valid_hsel_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HSEL must not be X/Z

Checks that HSEL is not X or Z

HSEL is not X or Z

HSEL is X or Z

Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: addr_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_FULL

Two Cycle Response

two_cycle_retry_resp

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

RETRY response was not completed in two cycles.

Checks that RETRY response completes in two cycles

RETRY response completes in two cycles

RETRY response was not completed in two cycles

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Two Cycle Response

two_cycle_split_resp

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

SPLIT response was not completed in two cycles.

Checks that SPLIT response completes in two cycles

SPLIT response completes in two cycles

SPLIT response was not completed in two cycles

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Transfer Type

htrans_not_idle_or_nseq_during_no_grant

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access

Manager should drive HTRANS to IDLE or NSEQ when it does not have access to the bus.

Checks that manager drives HTRANS to IDLE or NSEQ when it does not have access to the bus

Manager drives HTRANS to IDLE or NSEQ when it does not have access to the bus

Manager not driving HTRANS to IDLE or NSEQ when it does not have access to the bus

Passive Manager

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_retry

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during RETRY response.

Checks that HTRANS changes to IDLE during second cycle of RETRY response

HTRANS changed to IDLE during RETRY response

HTRANS was not changed to IDLE during RETRY response

Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_split

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during SPLIT response.

Checks that HTRANS changes to IDLE during second cycle of SPLIT response

HTRANS changed to IDLE during SPLIT response

HTRANS was not changed to IDLE during SPLIT response

Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Signal Validity

signal_valid_hbusreq_check

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access

HBUSREQ must not be X/Z

Checks that HBUSREQ is not X or Z

HBUSREQ does not contain any X or Z bits

HBUSREQ contains X or Z bits

Passive Manager

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_FULL

Rebuild Transaction

rebuild_xact_with_valid_combination_of_bursts

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry

Manager should restart an interrupted burst with a valid combination of bursts.

Checks that the manager restarted an interrupted burst with a valid combination of bursts

Manager restarted an interrupted burst with a valid combination of bursts

Manager not restarted an interrupted burst with a valid combination of bursts

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.

ERROR

AHB_FULL

Rebuild Transaction

rebuild_xact_with_expected_addr

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry

Manager should restart an interrupted burst from the address of the aborted beat.

Checks that the manager restarted an interrupted burst from the address of the aborted beat

Manager restarted an interrupted burst from the address of the aborted beat

Manager not restarted an interrupted burst from the address of the aborted beat

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.

ERROR

AHB_FULL

Response Type

hsplit_asserted_for_non_split_master

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers

Subordinate should not assert HSPLIT corresponding to a manager it has not split earlier.

Checks that HSPLIT is not asserted for a manager that has not SPLIT earlier.

HSPLIT is not asserted for a manager that has not SPLIT earlier.

HSPLIT is asserted for a manager that has not SPLIT earlier.

Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Response Type

hsplit_asserted_for_one_cycle

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers

Subordinate should assert a bit of HSPLIT only for one clock cycle

Checks that HSPLIT is asserted for only one clock cycle

HSPLIT is asserted for only one clock cycle

HSPLIT is not asserted for only one clock cycle

Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_retry

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during RETRY response.

Checks that HTRANS changes to IDLE during second cycle of RETRY response

HTRANS changed to IDLE during RETRY response

HTRANS was not changed to IDLE during RETRY response

Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_split

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during SPLIT response.

Checks that HTRANS changes to IDLE during second cycle of SPLIT response

HTRANS changed to IDLE during SPLIT response

HTRANS was not changed to IDLE during SPLIT response

Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_FULL

Bus Grant

illegal_hgrant_on_split_resp

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers

Manager should lose the bus once it gets the split response from the subordinate.

Checks that manager loses the bus once it gets the split response from the subordinate.

Manager loses the bus once it gets the split response from the subordinate

Manager didn't lose the bus during the split response from the subordinate

Active/Passive Manager

Group: AHB
Default severity: ERROR
Check is constructed only when num_masters > 1

ERROR

AHB_FULL

Signal Validity

signal_valid_hgrant_check

AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list

HGRANT must not be X/Z

Checks that HGRANT is not X or Z

HGRANT does not contain any X or Z bits

HGRANT contains X or Z bits

Active/Passive Manager

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB_FULL

Signal Validity

signal_valid_hmaster_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HMASTER must not be X/Z

Checks that HMASTER is not X or Z

HMASTER is not X or Z

HMASTER is X or Z

Active/Passive Subordinate

Group: AHB
Default severity: ERROR
This is performed in full-AHB mode.
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_Lite

Response Type

ahb_lite_split_response

AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses

SPLIT response was received when configured as AHB Lite system.

Checks that SPLIT responses are not received when configured for AHB Lite

SPLIT responses are not received when configured for AHB Lite

SPLIT responses are received when configured for AHB Lite

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

AHB_Lite

Response Type

ahb_lite_retry_response

AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses

RETRY response was received when configured as AHB Lite system.

Checks that RETRY responses are not received when configured for AHB Lite

RETRY responses are not received when configured for AHB Lite

RETRY responses are received when configured for AHB Lite

Active/Passive Manager and Passive Subordinate

Group: AHB
Default severity: ERROR

ERROR

ARM11/AHB_V6 Exclusive Accesses

Two Cycle Response

two_cycle_xfail_resp

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.3.1 Exclusive Access Protocol

XFAIL response was not completed in two cycles.

Checks that XFAIL response completes in two cycles

XFAIL response completes in two cycles

XFAIL response does not completed in two cycles

Active Manager

Group: AHB_V6
Default severity: ERROR
Applicable for AHB_V6 extention AHB_LITE

ERROR

ARM11/AHB_V6 Unaligned Transfers

Valid Unaligned Transfer

valid_unaligned_transfer

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1.2 Burst, Unaligned accesses and Byte Lane Strobes

HUNALIGN should be asserted for an unaligned transfer

Checks that HUNALIGN signal is correctly set for unaligned transfers. Based on ARMv6 AMBA Extension Spec (Document No: PR022-GENC-001011) section 3.1.2, example 3.1.2.2 in the document and ARM discussions following items are mandatory.

It would be mandatory for any initiator using the ARM11 extensions generating an unaligned AHB transfer to drive HUNALIGN=1
If HUNALIGN=0 it tells the target that HADDR will be fully AHB v2.0 compliant and HADDR will be aligned to HSIZE

HUNALIGN is 1 for the unaligned transfer

HUNALIGN is 0 for the unaligned transfer

Passive Manager and Active/Passive Subordinate

Group: AHB_V6
Default severity: ERROR
Applicable for AHB_V6 extention AHB_LITE

ERROR

ARM11/AHB_V6 Unaligned Transfers

Signal Stability

hunalign_changed_during_transfer

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HUNALIGN should not change in middle of a transfer

Checks that HUNALIGN output signal from manager dosenot changes its value in middle of a transfer

HUNALIGN is stable in a transfer

HUNALIGN is not stable in a transfer

Passive Manager and Active/Passive Subordinate

Group: AHB_V6
Default severity: ERROR
Applicable for AHB_V6 extention AHB_LITE

ERROR

ARM11/AHB_V6 Unaligned Transfers

Valid Byte Lane Strobes

valid_byte_lane_for_hbstrb

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HRDATA/HWDATA byte lanes corresponding to HBSTRB should be selected

Checks that HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB signal which have value 1

HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB

Invalid HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB

Passive Manager and Active/Passive Subordinate

Group: AHB_V6
Default severity: ERROR
Applicable for AHB_V6 extention AHB_LITE

ERROR

ARM11/AHB_V6 Unaligned Transfers

Signal Validity

signal_valid_hunalign_check

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HUNALIGN must not be X/Z

Checks that HUNALIGN is not X or Z

HUNALIGN is not X or Z

HUNALIGN is X or Z

Passive Manager and Active/Passive Subordinate

Group: AHB_V6
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
Applicable for AHB_V6 extention AHB_LITE
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

ARM11/AHB_V6 Unaligned Transfers

Signal Validity

signal_valid_hbstrb_check

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HBSTRB must not be X/Z

Checks that HBSTRB is not X or Z

HBSTRB does not contain any X or Z bits

HBSTRB contains X or Z bits

Passive Manager and Active/Passive Subordinate

Group: AHB_V6
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
Applicable for AHB_V6 extention AHB_LITE
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB5 Extended Memory Types

Signal Validity

signal_valid_hprot_ex_range_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.9 Memory types

HPROT signal is not having the valid value

Checks that Extended_Memory_Type supporting HPROT[6:2] is having valid values

HPROT[6:2] value is in valid range

HPROT[6:2] value is not in valid range

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.

ERROR

AHB5 Secure Transfers

Signal Validity

signal_valid_hnonsec_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HNONSEC must not be X/Z

Checks that HNONSEC is not X or Z

HNONSEC is not X or Z

HNONSEC is X or Z

Passive Manager and Active/Passive Subordinate

Group: AHB5
Default severity: ERROR
When svt_ahb_configuration :: signal_valid_during_reset_checks_enable is set to 1, this check is performed during reset.
During IDLE cycles, this check can be disabled by setting svt_ahb_configuration :: control_idle_value to INACTIVE_X_VAL or INACTIVE_Z_VAL.

ERROR

AHB_Lite_Multilayer

Rebuild Transaction

rebuild_xact_with_valid_combination_of_bursts

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination

Manager should restart an interrupted burst with a valid combination of bursts.

Checks that the manager restarted an interrupted burst with a valid combination of bursts

Manager restarted an interrupted burst with a valid combination of bursts

Manager not restarted an interrupted burst with a valid combination of bursts

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.

ERROR

AHB_Lite_Multilayer

Rebuild Transaction

rebuild_xact_with_expected_addr

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination

Manager should restart an interrupted burst from the address of the aborted beat.

Checks that the manager restarted an interrupted burst from the address of the aborted beat

Manager restarted an interrupted burst from the address of the aborted beat

Manager not restarted an interrupted burst from the address of the aborted beat

Passive Manager and Active/Passive Subordinate

Group: AHB
Default severity: ERROR
This check is performed when there is an active rebuilding transaction due to Early Burst Termination (EBT) occurred for AHB-Full system (svt_ahb_system_configuration :: ahb_lite = 0) or AHB Multilayer system (svt_ahb_system_configuration :: ahb_lite_multilayer = 1) with subordinate configuration svt_ahb_slave_configuration :: rebuild_after_multilayer_interconnect_termination is enabled.

ERROR

SYSTEM: ACE

CMO

forward_cmos_to_slave_check

Synopsys Defined

Monitor check that cache maintenance transactions are forwarded to slaves if forward_cmos_to_slaves_check_enable is set in the slave configuration

Checks that cache maintenance transactions are forwarded to slaves If two or more slaves are in the same address space of the memory map, this check is performed on each of the slave ports with overlapping address.

When cache maintenance transactions are forwarded to slaves if forward_cmos_to_slaves_check_enable is set in the slave configuration

When cache maintenance transactions are not forwarded to slaves if forward_cmos_to_slaves_check_enable is set in the slave configuration

The check is performed only if forward_cmos_to_slaves_check_enable is set in the port configuration of the slave

ERROR

SYSTEM: ACE

Exclusive Access

exclusive_snoop_propagation_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.3.1 Minimum PoS Exclusive Monitor

Monitor Checks that if interconnect stopped snoop propagation for exclusive transaction that was not successful

Checks if interconnect stopped snoop propagation for exclusive transaction that was not successful

When interconnect stopped snoop propagation for exclusive transaction that was not successful

When interconnect still send snoop propagation for exclusive transaction

ERROR

SYSTEM: ACE

Exclusive Access

exclusive_store_from_valid_state_sys_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Checks that if cacheline is in invalid state then exclusive store transaction is not issued

Checks that if cacheline is in invalid state then exclusive store transaction is not issued

When cacheline is in invalid state then exclusive store transaction is not issued

When cacheline is in valid state then exclusive store transaction is not issued

ERROR

SYSTEM: ACE

Exclusive Access

exclusive_load_from_valid_state_sys_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load

Monitor Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

When cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

When cacheline is in valid state then exclusive load transaction is issued only as READCLEAN or READSHARED

ERROR

SYSTEM: ACE

Exclusive Access

restart_exclusive_seq_post_cache_line_invalidation_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Check that an exclusive sequence is reset after a cacheline is invalidated by a snoop. After a snoop invalidates a cacheline, an exclusive load must always be sent prior to sending the exclusive store

Checks that an exclusive sequence is reset after a cacheline is invalidated by a snoop. This checks that after a snoop invalidates a cacheline, an exclusive load is always sent prior to sending the exclusive store.

When an exclusive sequence is reset after a cacheline is invalidated by a snoop. After a snoop invalidates a cacheline, an exclusive load must always be sent prior to sending the exclusive store

When an exclusive sequence is not reset after a cacheline is invalidated by a snoop

ERROR

SYSTEM: ACE

Barrier

outstanding_master_barrier_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check that an ACE master interface must not issue more than 256 outstanding barrier transactions

System monitor should ensure that an ACE master interface must not issue more than 256 outstanding barrier transactions

When ACE master interface must not issue more than 256 outstanding barrier transactions

When ACE master interface issue more than 256 outstanding barrier transactions

ERROR

SYSTEM: ACE

Routing

no_slave_respond_with_decerr_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A3.4.5 Read and write response structure

Monitor Check that each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it

System monitor should ensure that each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it

When each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it

When no slave responds with DECERR if any transaction is routed to it with an address range

ERROR

SYSTEM: ACE

DVM

master_dvm_no_data_transfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.1.1 Transaction groups

Monitor Check that no data is transferred for a DVM transaction

Checks that no data is transferred for a DVM transaction

When no data is transferred for a DVM transaction

When a snoop data transfer is observed for associated DVM Snoop transaction

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_response_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Check that the interconnect sets RRESP value of a DVM transaction correctly

Checks that the interconnect sets RRESP value of a DVM transaction correctly based on the following: The interconnect component gathers all response values and responds to the originator as follows: if CRRESP is 0b00000 for all responses, the interconnect component sets RRESP to 0b0000. If CRRESP is 0b00010 for any responses, the interconnect component sets RRESP to 0b0010.

When the interconnect sets RRESP value of a DVM transaction correctly

When the interconnect not sets RRESP value of a DVM transaction correctly

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_complete_issue_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that the interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master

Checks that the interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master.

When interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master

When DVM Complete snoop transaction is received, but a DVM Complete on the read channel is not observed for port

ERROR

SYSTEM: ACE

DVM

master_dvm_complete_issue_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that a DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master.

Checks that a DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master

When DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master

When DVM Complete is issued on read channel before handshake on snoop address channel of associated DVM Sync

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_response_timing_check

Synopsys Defined

Monitor Check that the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync after all snoop responses are received.

Checks that the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync. This check ensures that this acknowledgement is sent only after all snoop responses are received.

When the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync after all snoop responses are received

When response is observed to DVM transaction, but response of associated snoop was not yet received

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_sync_snoop_transaction_association_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component.

Checks that interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component

When interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component

When DVM Sync snoop transaction was not sent on port for corresponding DVM Sync %0s sent on read channel

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_operation_snoop_transaction_association_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.1 DVM message transactions

Monitor Check that interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component.

Checks that interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component.

When interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component

When DVM Operation snoop transaction was not sent on port for corresponding DVM Operation sent on read channel

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_complete_dvm_sync_association_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that a DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel

Checks that a DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel

When DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel

When Received DVM Complete transaction on snoop channel, but no outstanding DVM Sync found on this port

ERROR

SYSTEM: ACE

DVM

master_outstanding_snoop_dvm_sync_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.4 DVM Complete

Monitor checks that maximum number of outstanding DVM Sync messages that a master must be able to accept is 256. The number of outstanding DVM Sync messages accepted by master exceeds 256.

Checks that maximum number of outstanding DVM Sync messages that a master must be able to accept is 256. This check fires an error if the number of outstanding DVM Sync messages exceeds 256.

When maximum number of outstanding DVM Sync messages that a master must be able to accept is 256

When maximum number of outstanding DVM Sync messages that a master must be able to accept is exceeds 256

ERROR

SYSTEM: ACE

DVM

master_outstanding_dvm_sync_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction

Checks that a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction

When a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction

When a component not have only one outstanding DVM Sync transaction

ERROR

SYSTEM: ACE

Data Integrity

data_integrity_with_outstanding_coherent_write_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.5.1 Interconnect read from main memory or peripheral device

Monitor Check that data returned in a coherent read transaction matches that of a WRITEBACK/WRITECLEAN transaction that was in progress when the read was initiated

Checks that the read data returned for a coherent read is the same as that of a WRITEBACK or WRITECLEAN transaction which was in progress when the read was initiated. This is to check that an interconnect that does speculative reads re-fetches the data in a scenario where the preceding WRITEBACK/WRITECLEAN did not complete and none of the snoops returned data. For example, consider that a WRITEBACK was in progress while a read is initiated by the master. If the interconnect does speculative reads, the speculative read may return stale data since the WRITEBACK is not complete. If none of the snoops return data as well, the interconnect should re-fetch data after the completion of the WRITEBACK.

When data returned in a coherent read transaction matches that of a WRITEBACK/WRITECLEAN transaction that was in progress when the read was initiated

When data returned in a coherent read transaction is not matches that of a WRITEBACK/WRITECLEAN transaction that was in progress when the read was initiated

This check is applicable only when:

svt_axi_system_configuration :: posted_write_xacts_enable is not set.

ERROR

SYSTEM: ACE

Routing

slave_read_xact_timing_relative_to_last_posted_write_xact_check

Synopsys Defined

Monitor Check that a read transaction is routed to the slave only after the last posted write transaction with overlapping address from the same port has completed at the slave

Checks that a READ transaction is routed to a slave only after a previous WRITE transaction from the same port and with an overlapping address completes at the slave. This is required in posted writes to ensure that a READ transaction retreives the same data as the previous WRITE transaction.

When read transaction is routed to the slave only after the last posted write transaction with overlapping address from the same port has completed at the slave

When read transaction is not routed to the slave only after the last posted write transaction with overlapping address from the same port has completed at the slave

This check is applicable only when:

svt_axi_system_configuration :: posted_write_xacts_enable is set.

ERROR

SYSTEM: ACE

Cache Coherency

cacheline_and_memory_coherency_check_per_xact

Synopsys Defined

Monitor Check that if cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory. This check may not pass if a transaction to the slave is in the interconnect's buffer by the time a coherent transaction completes.

Checks that if all cachelines are clean, the data in cacheline is consistent with data in memory. This check is done on a per transaction basis at the end of each coherent transaction. Note that in some implementations a transaction to the memory could still be in the interconnect's buffer in which case this check would fail. Hence this check is issued as a warning, rather than an error.

When cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory

This check may not pass if a transaction to the slave is in the interconnect's buffer by the time a coherent transaction completes

This check is not performed if the agents connected to the interfaces are configured to work in passive mode. .

WARNING

SYSTEM: ACE

Cache Coherency

interconnect_generated_write_xact_to_update_main_memory_check

Synopsys Defined

Monitor Check that if a snoop response has the PassDirty response asserted, and the interconnect does not assert the PassDirty transaction response for the initiating master, the interconnect must generate a write transaction to update main memory.

Checks that the interconnect generated slave write transaction to update main memory when: 1) A snoop response has the PassDirty response asserted, and the interconnect does not assert the PassDirty transaction response for the initiating master 2) The interconnect has provided a read response to an initiating master before it has received all the snoop responses and a later snoop response has PassDirty asserted

This check passes when the system monitor associates interconnect generated slave write transaction to the corresponding snoop transaction that returned dirty data.

This check reports an ERROR at the end of simulation, if the interconnect fails to generate slave write transaction under the above described situations.

The master_slave_xact_data_integrity_check must be enabled for this check to function correctly.
svt_axi_system_configuration :: interconnect_generated_write_xact_to_update_main_memory_check_enable must to set to 1 to enable this check.

ERROR

SYSTEM: ACE

Cache Coherency

cacheline_and_memory_coherency_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model

Monitor Check that if cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory

Checks that if all cachelines are clean, the data in cacheline is consistent with data in memory

When all cachelines are clean, the data in cacheline is consistent with data in memory

When all cachelines are clean, the data in cacheline is not consistent with data in memory

This check is not performed if the agents connected to the interfaces are configured to work in passive mode.

ERROR

SYSTEM: ACE

Cache Coherency

no_two_cachelines_in_dirty_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model

Monitor Check that no two masters have the same cacheline in the dirty state

Checks that no two masters have the same cacheline in dirty state

When no two masters have the same cacheline in dirty state

When two masters have the same cacheline in dirty state

This check is not performed if the agents connected to the interfaces are configured to work in passive mode.

ERROR

SYSTEM: ACE

Cache Coherency

no_two_cachelines_in_unique_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model

Monitor Check that no two masters have the same cacheline in the unique state

Checks that no two masters have the same cacheline in unique state

When no two masters have the same cacheline in the unique state

When two masters have the same cacheline in the unique state

This check is not performed if the agents connected to the interfaces are configured to work in passive mode.

ERROR

SYSTEM: ACE

Cache Coherency

overlapping_addr_sequencing_check

Synopsys Defined

Monitor Check that if two masters access the same cache line, one master is sequenced after the other

Checks that if two masters access the same cache line, one master is sequenced after the other

When two masters access the same cache line, one master is sequenced after the other

When two masters does not access the same cache line

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_and_snoop_data_match_check

Synopsys Defined

Monitor Check that data returned to initiating master matches the data received from snoop transaction

Checks that data returned to initiating master matches the data received from snoop transaction

When data returned to initiating master matches the data received from snoop transaction

When data returned to initiating master does not matches the data received from snoop transaction

ERROR

SYSTEM: ACE

Snoop Response

snoop_data_consistency_check

Synopsys Defined

Monitor Check that data returned from all snoop transactions are consistent

Checks that data returned from all snoop transactions are consistent

When data returned from all snoop transactions are consistent

When data returned from all snoop transactions are inconsistent

ERROR

SYSTEM: ACE

Snoop Response

snoop_resp_passdirty_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that no two responses to a snoop transaction have the PassDirtyCRRESP[2] bit asserted

Checks that no two responses to a snoop transaction have the PassDirty(CRRESP[2]) bit asserted

When no two responses to a snoop transaction have the PassDirty(CRRESP[2]) bit asserted

When two responses to a snoop transaction have the PassDirty(CRRESP[2]) bit asserted

ERROR

SYSTEM: ACE

Snoop Response

snoop_resp_wasunique_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that no two responses to a snoop transaction have the WasUniqueCRRESP[4] bit asserted

Checks that no two responses to a snoop transaction have the WasUnique(CRRESP[4]) bit asserted

When no two responses to a snoop transaction have the WasUnique(CRRESP[4]) bit asserted

When two responses to a snoop transaction have the WasUnique(CRRESP[4]) bit asserted

ERROR

SYSTEM: ACE

Coherent Response

coherent_resp_passdirty_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.4 Transaction responses from the interconnect

Monitor Check that the PassDirty response to initiating master is correct

Checks that the PassDirty response to initiating master is correct

When the PassDirty response to initiating master is correct

When the PassDirty response to initiating master is not correct

ERROR

SYSTEM: ACE

Coherent Response

coherent_resp_isshared_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.4 Transaction responses from the interconnect

Monitor Check that the IsShared response to initiating master is correct

Checks that the IsShared response to initiating master is correct

When the IsShared response to initiating master is correct

When the IsShared response to initiating master is not correct

ERROR

SYSTEM: ACE

Coherent Response

coherent_resp_start_conditions_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that the response to a coherent transaction is not started before sufficient information from snooped masters are obtained

Checks that the response to a coherent transaction is not started before sufficient information from snooped masters are obtained

When the response to a coherent transaction is not started before sufficient information from snooped masters are obtained

When the response to a coherent transaction is started before sufficient information from snooped masters are obtained

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_xact_with_no_snoop_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.3 Issuing snoop transactions

Monitor Check that READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters

Checks that READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters

When READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters

When READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT cause a snoop of cached masters

ERROR

SYSTEM: ACE

Coherent And Snoop

snoop_not_sent_to_initiating_master_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.3 Issuing snoop transactions

Monitor Check that a snoop is not sent to the initiating master

Checks that a snoop is not sent to the initiating master

When snoop is not sent to the initiating master

When snoop is sent to the initiating master

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_snoop_prot_type_match_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor Check that the security level determined by signal ACPROT[1] of the snoop transaction matches the security level of corresponding coherent transaction determined by signal AxPROT[1]

Monitor Check that the security level (determined by signal ACPROT[1]) of the snoop transaction matches the security level of corresponding coherent transaction (determined by signal AxPROT[1])

When the security level (determined by signal ACPROT[1]) of the snoop transaction matches the security level of corresponding coherent transaction (determined by signal AxPROT[1])

When the security level (determined by signal ACPROT[1]) of the snoop transaction does not matches the security level of corresponding coherent transaction (determined by signal AxPROT[1])

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_snoop_domain_match_check

Synopsys Defined

Monitor Check that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master

Checks that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master

When the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master

When the port on which snoop transaction is not received corresponds to the domain indicated in coherent transaction of initiating master

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_snoop_type_match_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.1 Mapping coherency operations to snoop operations

Monitor Check that the snoop transaction type corresponds to the coherent transaction type of initiating master

Checks that the snoop transaction type corresponds to the coherent transaction type of initiating master

When Snoop corresponding to the coherent transaction must be one according to the coherent to snoop transaction mapping

When Snoop corresponding to the coherent transaction is not according to the coherent to snoop transaction mapping

This check is applicable only when:

When is_coherent_to_snoop_type_match bit is set to 1 than check will pass.

ERROR

SYSTEM: ACE

Coherent And Snoop

snoop_addr_matches_coherent_addr_check

Synopsys Defined

Monitor Check that the address of a snoop transaction must match one of the outstanding coherent transactions

Checks that the address of a snoop transaction matches address of one of the outstanding coherent transactions.

When address of a snoop transaction matches address of one of the outstanding coherent transactions

When address of a snoop transaction does not matches address of one of the outstanding coherent transactions

The VIP requires that svt_axi_port_configuration :: cache_line_size of ACE_LITE port type matches that of AXI_ACE port types.
If cache line size of ACE_LITE and AXI_ACE ports does not match, this check would misfire.

ERROR

SYSTEM: AXI3 Onwards

Data Integrity

write_byte_count_match_across_interconnect

Synopsys Defined

Monitor check that the effective number of bytes bytes for which strobe is asserted of write transactions sent by masters match the effective number of bytes for write transactions sent by interconnect to slave

Checks that the effective number of bytes for write transactions sent by master components match that which are sent by the interconnect to the slaves. This basically checks for spurious writes from the interconnect. The effective write byte count is the number of bytes for which write strobe is asserted. If there are writes generated by the interconnect because dirty data returned by a snoop could not be passed back to a master, the effective write byte count includes the number of bytes in a snoop also.

ERROR

SYSTEM: AXI3 Onwards

M2S Correlation

eos_unmapped_master_xact

Synopsys Defined

Monitor check that all master transactions are correlated to corresponding slave transactions

At the end of the simulation if there are master transactions that could not be associated to corresponding slave transactions, this error is issued.

When all master transactions are correlated to corresponding slave transactions

When Found no slave transaction corresponding to master transaction, Unmapped master xact

This check is applicable only when:

svt_axi_system_configuration :: posted_write_xacts_enable is set.

ERROR

SYSTEM: AXI3 Onwards

Memory Type

eos_unmapped_non_modifiable_xact

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.4.1 Memory type requirements

Monitor check that all non-modifiable transactions are made visible to the final destination in a timely manner

At the end of simulation there should be no non-modifiable transaction that hasn't been mapped to a slave transaction. If such a transaction exists it shows that a non-modifiable transaction hasn't been made visible at the slave, which is not allowed

When all non-modifiable transactions are made visible to the final destination in a timely manner When non-modifiable upstream address is routed to register space of DUT, and no downstream traffic expected

When no downstream transaction found corresponding to non-modifiable upstream transaction. When non-modifiable upstream address is not routed to register space of DUT, and no downstream traffic observed For coherent transactions, whenever a downstream traffic is exepected but not observed

This check is applicable only when either:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set to 1 in system configuration or
svt_axi_system_configuration :: posted_write_xacts_enable is set to 1 in system configuration

ERROR

SYSTEM: AXI3 Onwards

Memory Type

device_non_bufferable_response_match_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.4.1 Memory type requirements

Monitor check that for device non-bufferable transactions, responses are obtained from the final destination

For device non-bufferable transactions, responses must be obtained from the final destination. Checks that the timing of the response of the master transaction is after that of the corresponding slave transaction and that the responses match.

When for device non-bufferable transactions, responses are obtained from the final destination

When for device non-bufferable transactions, responses are not obtained from the final destination

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Ordering

ordering_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, transactions with the same ID to the same slave must be ordered

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, transactions in the same direction to the same slave with the same ID, must be ordered irrespective of the address

When for non-modifiable transactions, transactions with the same ID to the same slave must be ordered

When for non-modifiable transactions, transactions with the same ID to the same slave is not in ordered

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

cache_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, cache_type matches between master transaction and corresponding slave transaction for all bits except the bufferable bit cache_type[0]

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the cache_type should match between master transaction and corresponding slave transaction, except for ARCACHE[0]/AWCACHE[0].

When for non-modifiable transactions, cache_type matches between master transaction and corresponding slave transaction for all bits except the bufferable bit (cache_type[0])

When for non-modifiable transactions, cache_type is not matches between master transaction and corresponding slave transaction for all bits except the bufferable bit (cache_type[0])

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

burst_size_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, burst_size matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_size should match between master transaction and corresponding slave transaction

When for non-modifiable transactions, burst_size matches between master transaction and corresponding slave transaction

When for non-modifiable transactions, burst_size is not matches between master transaction and corresponding slave transaction

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

burst_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, burst_type matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_type should match between master transaction and corresponding slave transaction

When for non-modifiable transactions, burst_type matches between master transaction and corresponding slave transaction

When for non-modifiable transactions, burst_type is not matches between master transaction and corresponding slave transaction

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

burst_length_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, burst_length matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_length should match between master transaction and corresponding slave transaction if burst_length <= 16. For larger burst lengths a transaction could get split if getting routed to an AXI interface that doesn't support burst length > 16. This check is not done when burst_length > 16.

When for non-modifiable transactions, burst_length matches between master transaction and corresponding slave transaction

When for non-modifiable transactions, burst_length is not matches between master transaction and corresponding slave transaction

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

region_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, region matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the region should match between master transaction and corresponding slave transaction

When for non-modifiable transactions, region matches between master transaction and corresponding slave transaction

When for non-modifiable transactions, region is not matches between master transaction and corresponding slave transaction

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

prot_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, prot_type matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the prot_type should match between master transaction and corresponding slave transaction

When for non-modifiable transactions, prot_type matches between master transaction and corresponding slave transaction

When for non-modifiable transactions, prot_type is not matches between master transaction and corresponding slave transaction

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

atomic_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, atomic_type matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the atomic_type should match between master transaction and corresponding slave transaction

When for non-modifiable transactions, atomic_type matches between master transaction and corresponding slave transaction

When for non-modifiable transactions, atomic_type is not matches between master transaction and corresponding slave transaction

This check is applicable only when:

svt_axi_system_configuration :: master_slave_non_modifiable_xact_checks_enable is set in system configuration

ERROR

SYSTEM: AXI3 Onwards

Data Integrity

master_slave_xact_data_integrity_check

Synopsys Defined

Monitor Check that data in slave transaction matches that in the master transaction

Checks that the data in a slave transaction is the same as that of the corresponding master transaction. In order to perform this check, slave transactions are correlated to corresponding master transactions. When only the former is set, this check is done only on non-modifiable transactions.

When data in slave transaction matches that in the master transaction

When data in slave transaction is not matches that in the master transaction

This check is done only when either of

ERROR

SYSTEM: AXI3 Onwards

Data Integrity

data_integrity_check

Synopsys Defined

Monitor Check that data is fetched and routed correctly by the interconnect

Checks that data in transaction is consistent with data in memory when the transaction completes. This checks that a WRITE transaction issued by a master is written to memory correctly. Similarly, it checks that a READ transaction fetches the correct data from memory. The check assumes that a transaction issued by a master completes only after response is received from the slave to which that transaction was routed. It also assums that there is no other transaction that accesses an overlapping address during the period that the response is issed by the slave and the transaction completes in the master that issued the transaction. In ACE, this check is issued only when the snoop has not returned any data and data is fetched from memory or when data is written to memory.

When data is fetched and routed correctly by the interconnect

When data is not fetched and routed correctly by the interconnect

This check is applicable only when:

svt_axi_system_configuration :: posted_write_xacts_enable is not set.

ERROR

SYSTEM: AXI3 Onwards

Routing

slave_transaction_routing_check

Synopsys Defined

Monitor Check that transaction is routed to the correct slave based on address

Checks that a transaction is routed correctly to a slave port based on address

When transaction is routed correctly to a slave port based on address

When transaction is not routed correctly to a slave port based on address

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysreq_stable_till_csysack_check

AXI low-power interface

while exiting from low power state, csysreq has gone low before the cactive, csysack have gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysack_timeout_after_cactive_check

AXI low-power interface

after cactive, csysreq have gone high, timedout waiting for csysack to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_cactive_stable_till_csysreq_csysack_check

AXI low-power interface

while exiting from low power state, cactive has gone low before the csysack has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysack_before_cactive_check

AXI low-power interface

while exiting from low power state, csysack has gone high before the cactive has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_cactive_timeout_after_csysreq_check

AXI low-power interface

after csysreq has gone high, timedout waiting for cactive to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysreq_stable_till_cactive_check

AXI low-power interface

while exiting from low power state, csysreq has gone low before the cactive has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysreq_stable_till_csysack_check

AXI low-power interface

while exiting from low power state, csysreq has gone low before the csysack has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysack_timeout_after_csysreq_check

AXI low-power interface

after cactive, csysreq have gone high, timedout waiting for csysack to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_cactive_stable_till_csysreq_csysack_check

AXI low-power interface

while exiting from low power state, cactive has gone low before the csysreq, csysack have gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysack_before_csysreq_check

AXI low-power interface

while exiting from low power state, csysack has gone high before the csysreq has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysreq_timeout_after_cactive_check

AXI low-power interface

after cactive has gone high, timedout waiting for csysreq to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_cactive_stable_till_csysreq_check

AXI low-power interface

while exiting from low power state, cactive has gone low before the csysreq has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_csysack_before_cactive_csysreq_check

AXI low-power interface

while exiting from low power state, csysack has gone high before cactive/csysreq going high

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysreq_stable_till_csysack_check

AXI low-power interface

csysreq has gone high without waiting for csysack to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysack_timeout_after_csysreq_check

AXI low-power interface

after csysreq has gone low, timedout waiting for csysack to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_cactive_stable_till_csysreq_csysack_check

AXI low-power interface

while entering into low power state, cactive has gone high without waiting for csysreq and csysack to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysack_before_csysreq_check

AXI low-power interface

after cactive has gone low, csysack has gone low before csysreq going low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysreq_timeout_after_cactive_check

AXI low-power interface

after cactive has gone low, timedout waiting for csysreq to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_cactive_stable_till_csysreq_check

AXI low-power interface

while entering into low power state, cactive has gone high without waiting for csysreq to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysack_before_cactive_check

AXI low-power interface

while entering into low power state, csysack has gone low before cactive going low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysreq_before_cactive_check

AXI low-power interface

while entering into low power state, csysreq has gone low before cactive going low

ERROR

PORT: AXI_LP

Signal Validity

signal_valid_csysack_check

AXI low-power interface

X/Z on the csysack signal

ERROR

PORT: AXI_LP

Signal Validity

signal_valid_csysreq_check

AXI low-power interface

X/Z on the csysreq signal

ERROR

PORT: AXI_LP

Signal Validity

signal_valid_cactive_check

AXI low-power interface

X/Z on the cactive signal

ERROR

ACE

Outstanding

no_outstanding_write_transaction_with_same_awid

Synopsys Defined

Monitor checks that master must not drive same AWID transaction when there is a write request or ongoing write outstanding transaction with same AWID

Checks that there is no outstanding transaction with same awid

When there is no outstanding transaction with same awid

When there is outstanding transaction with same awid

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE

Outstanding

no_outstanding_read_transaction_with_same_arid

Synopsys Defined

Monitor checks that master must not drive same ARID transaction when there is a read request or ongoing read outstanding transaction with same ARID

Checks that there is no outstanding transaction with same arid

When there is no outstanding transaction with same arid

When there is outstanding transaction with same arid

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE

Performance Metrics

perf_min_write_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of write transactions in a given interval is more than or equal to the configured min value

Checks that the bandwidth of write transactions in a given interval is not less that the configured min value

When the bandwidth of write transactions in a given interval is not less that the configured min value

When the bandwidth of write transactions in a given interval is less that the configured min value

This check is applicable only when:

perf_min_write_bandwidth is not set to -1

ERROR

ACE

Performance Metrics

perf_max_write_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of write transactions in a given interval is less than or equal to the configured max value

Checks that the bandwidth of write transactions in a given interval is not more that the configured max value

When the bandwidth of write transactions in a given interval is not more that the configured max value

When the bandwidth of write transactions in a given interval is more that the configured max value

This check is applicable only when:

perf_max_write_bandwidth is not set to -1

ERROR

ACE

Performance Metrics

perf_min_read_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of read transactions in a given interval is more than or equal to the configured min value

Checks that the bandwidth of read transactions in a given interval is not less that the configured min value

When the bandwidth of read transactions in a given interval is not less that the configured min value

When the bandwidth of read transactions in a given interval is less that the configured min value

This check is applicable only when:

perf_min_read_bandwidth is not set to -1

ERROR

ACE

Performance Metrics

perf_max_read_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of read transactions in a given interval is less than or equal to the configured max value

Checks that the bandwidth of read transactions in a given interval is not more that the configured max value

When the bandwidth of read transactions in a given interval is not more that the configured max value

When the bandwidth of read transactions in a given interval is more that the configured max value

This check is applicable only when:

perf_max_read_bandwidth is not set to -1

ERROR

ACE

Performance Metrics

perf_min_write_throughput_check

Synopsys Defined

Monitor Check that the throughput of write transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of write transactions in a given interval is not less that the configured min value

When the throughput of write transactions in a given interval is not less that the configured min value

When the throughput of write transactions in a given interval is less that the configured min value

This check is applicable only when:

perf_min_write_throughput is not set to -1

ERROR

ACE

Performance Metrics

perf_max_write_throughput_check

Synopsys Defined

Monitor Check that the throughput of write transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of write transactions in a given interval is not more that the configured max value

When the throughput of write transactions in a given interval is not more that the configured max value

When the throughput of write transactions in a given interval is more that the configured max value

This check is applicable only when:

perf_max_write_throughput is not set to -1

ERROR

ACE

Performance Metrics

perf_min_read_throughput_check

Synopsys Defined

Monitor Check that the throughput of read transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of read transactions in a given interval is not less that the configured min value

When the throughput of read transactions in a given interval is not less that the configured min value

When the throughput of read transactions in a given interval is less that the configured min value

This check is applicable only when:

perf_min_read_throughput is not set to -1

ERROR

ACE

Performance Metrics

perf_max_read_throughput_check

Synopsys Defined

Monitor Check that the throughput of read transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of read transactions in a given interval is not more that the configured max value

When the throughput of read transactions in a given interval is not more that the configured max value

When the throughput of read transactions in a given interval is more that the configured max value

This check is applicable only when:

perf_max_read_throughput is not set to -1

ERROR

ACE

Performance Metrics

perf_avg_min_read_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of read transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of read transactions in a given interval is not less than the configured min value

When the average latency of read transactions in a given interval is not less than the configured min value

When the average latency of read transactions in a given interval is less than the configured min value

This check is applicable only when:

perf_avg_min_read_xact_latency is not set to -1

ERROR

ACE

Performance Metrics

perf_avg_max_read_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of read transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of read transactions in a given interval is not more than the configured max value

When the average latency of read transactions in a given interval is not more than the configured max value

When the average latency of read transactions in a given interval is more than the configured max value

This check is applicable only when:

perf_avg_max_read_xact_latency is not set to -1

ERROR

ACE

Performance Metrics

perf_min_read_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a read transaction is more than or equal to the configured min value

Checks that the latency of a read transaction is not lesser than the configured min value

When the latency of a read transaction is not lesser than the configured min value

When lthe latency of a read transaction is lesser than the configured min value

This check is applicable only when:

perf_min_read_xact_latency is not set to -1

ERROR

ACE

Performance Metrics

perf_max_read_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a read transaction is less than or equal to the configured max value

Checks that the latency of a read transaction is not greater than the configured max value

When the latency of a read transaction is not greater than the configured max value

When the latency of a read transaction is greater than the configured max value

This check is applicable only when:

perf_max_read_xact_latency is not set to -1

ERROR

ACE

Performance Metrics

perf_avg_min_write_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of write transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of write transactions in a given interval is not less than the configured min value

When the average latency of write transactions in a given interval is not less than the configured min value

When the average latency of write transactions in a given interval is less than the configured min value

This check is applicable only when:

perf_avg_min_write_xact_latency is not set to -1

ERROR

ACE

Performance Metrics

perf_avg_max_write_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of write transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of write transactions in a given interval is not more than the configured max value

When the average latency of write transactions in a given interval is not more than the configured max value

When the average latency of write transactions in a given interval is more than the configured max value

This check is applicable only when:

perf_avg_max_write_xact_latency is not set to -1

ERROR

ACE

Performance Metrics

perf_min_write_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a write transaction is more than or equal to the configured min value

Checks that the latency of a write transaction is not lesser than the configured min value

When latency of a write transaction is not lesser than the configured min value

When latency of a write transaction is lesser than the configured min value

This check is applicable only when:

perf_min_write_xact_latency is not set to -1

ERROR

ACE

Performance Metrics

perf_max_write_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a write transaction is less than or equal to the configured max value

Checks that the latency of a write transaction is not greater than the configured max value

When latency of a write transaction is not greater than the configured max value

When latency of a write transaction is greater than the configured max value

This check is applicable only when:

perf_max_write_xact_latency is not set to -1

ERROR

ACE

Non DVM Non Device

write_non_dvm_non_device_xact_id_overlap_check

Synopsys Defined

Monitor Check for the AWID overlap of Non-DVM or Non-device transactions with another active transaction

Checks the overlapping AWID of Non-DVM or Non-Device transactions with any active transactions

When AWID of Non-DVM or Non-Device transactions overlap with any active transactions

When AWID of Non-DVM or Non-Device transactions not overlap with any active transactions

Passive Slave, Active/Passive Master

ERROR

ACE

Non DVM Non Device

read_non_dvm_non_device_xact_id_overlap_check

Synopsys Defined

Monitor Check for the ARID overlap of Non-DVM or Non-device transactions with another active transaction

Checks the overlapping ARID of Non-DVM or Non-Device transactions with any active transactions

When ARID of Non-DVM or Non-Device transactions overlap with any active transactions

When ARID of Non-DVM or Non-Device transactions not overlap with any active transactions

Passive Slave, Active/Passive Master

ERROR

AXI3

Port Interleaving

port_interleaving_check

Synopsys Defined

Monitor checks that if interleaved port is expected port for the given transaction

Checks if address does fall to correct interleaved port.
Valid when port cfg port_interleaving_enable = 1.

address does fall to correct interleaved port.

address does not fall to correct interleaved port.

Active/Passive Slave, Active/Passive Master

ERROR

AXI3

Locked Accesses

locked_sequence_to_same_slave_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that only locked slave is used for all the transactions in the locked sequence

Checks that when a master does a lock transaction, it does not target subsequent transactions in the lock sequence to any slave other than the locked slave

When the the slave port id for the new sequence is match the slave port id for the previous transaction in the locked sequence

When the the slave port id for the new sequence does not match the slave port id for the previous transaction in the locked sequence

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: locked_access_enable is set to 1

WARNING

AXI3

Locked Accesses

locked_sequence_length_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that a locked sequence does not have more than two consecutive locked transactions at the same time

Check that the master follows as per the recommendation from spec to limit 2 transaction for the lock access

When the Sequence detected with less than two locked transactions

When the Sequence detected with more than two locked transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: locked_access_enable is set to 1

WARNING

AXI3

Locked Accesses

no_pending_locked_xacts_before_normal_xacts_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that there are no pending transactions of a locked sequence when a normal transaction is received

Checks that there are no pending transactions of a locked sequeunce when a normal transaction is received

When the normal transaction detected when a locked sequeunce is complete

When the normal transaction detected when a locked sequeunce is not complete

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: locked_access_enable is set to 1

ERROR

AXI3

Locked Accesses

locked_sequeunce_id_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that all transactions of a locked sequence have the same id

Checks that all transactions of locked sequence have the same id

When the transaction id is same as locked transaction id

When the transaction id is not same as locked transaction id

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: locked_access_enable is set to 1

ERROR

AXI3

Locked Accesses

no_pending_xacts_during_locked_xact_sequeunce_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that there are no pending transactions before a locked sequence starts

Checks that there are no pending transactions before a locked sequence starts

When the locked sequence is detected and active transaction found

When the locked sequence is detected and no active transaction found

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: locked_access_enable is set to 1

ERROR

AXI3

Write Data Ordering

write_data_interleave_order_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A5.2.2 Write data ordering

Monitor check that the order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions for Write Data Interleaving

Checks that the order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions for Write Data Interleaving transactions

When the Address order and data order is same for the write data interleaving transaction

When the Address order and data order is not same for the write data interleaving transaction

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.

ERROR

AXI3

Write Data Ordering

write_data_interleave_depth_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A5.2.2 Write data ordering

Monitor check that received write data is not interleaved beyond write_data_interleave_depth value. An error is issued if write data is interleaved beyond this value for Write data interleaving

Checks that received write data is not interleaved beyond write_data_interleave_depth value

When the first active write xact index is not greater to the write_data_interleave_depth

When the first active write xact index is greater to the write_data_interleave_depth if write data is interleaved beyond this value for Write data interleaving

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.

ERROR

AXI3

Signal Stability

signal_stable_wid_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that WID is stable when WVALID is high

WID is stable when WVALID is high

WID is not stable when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.

ERROR

AXI3

Signal Validity

signal_valid_wid_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WID is not X or Z when WVALID is high

WID is not X or Z when WVALID is high

WID is X or Z when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE,ACE_Lite

Barrier Transactions

writebarrier_norm_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the AWID overlap of Write transactions with other active WriteBarrier transactions

Checks the overlapping AWID of Non-Barrier Non-DVM transactions with any active Barrier/DVM transactions

When AWID of Non-Barrier Non-DVM transactions overlap with any active Barrier/DVM transactions

When AWID of Non-Barrier Non-DVM transactions is not overlap with any active Barrier/DVM transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: barrier_enable is set to 1.

ERROR

ACE,ACE_Lite

Barrier Transactions

readbarrier_dvm_norm_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the ARID overlap of Read transactions with other active ReadBarrier/DVM transactions

Checks the overlapping ARID of Non-Barrier Non-DVM transactions with any active Barrier/DVM transactions

When RID of Non-Barrier Non-DVM transactions overlap with any active Barrier/DVM transactions

When RID of Non-Barrier Non-DVM transactions is not overlap with any active Barrier/DVM transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: dvm_enable or barrier_enable is set to 1.

ERROR

ACE,ACE_Lite

Barrier Transactions

readbarrier_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the ARID overlap of ReadBarrier transactions with other active Non-Barrier transactions

Checks the overlapping ARID of Read Barrier transactions with any active Read transactions

When ARID of Read Barrier transactions overlap with other active Non-Barrier transactions

When ARID Read Barrier transactions is not overlap with other active Non-Barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: barrier_enable is set to 1.

ERROR

ACE,ACE_Lite

Barrier Transactions

writebarrier_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the AWID overlap of WriteBarrier transactions with other active Non-Barrier transactions

Checks the overlapping AWID of Write Barrier transactions with any active Write transactions

When AWID of WriteBarrier transactions overlap with other active Non-Barrier transactions

When AWID of WriteBarrier transactions is not overlap with other active Non-Barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: barrier_enable is set to 1.

ERROR

ACE,ACE_Lite

DVM

dvm_message_arbar_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARBAR[0] is 'b0 Normal Access!

Checks for DVM ARBAR[0] is 1'b0

When DVM ARBAR must be zero means must having normal access

When DVM ARBAR is not zero means not having normal access

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_pair_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.1 About barrier transactions

Monitor Check that Barrier pairs must be issued in the same sequence on the read address and write address channels

Checks that barrier pairs must be issued in the same sequence on the read address and write address channels

When Barrier pairs must be issued in the same sequence on the read address and write address channels

When Barrier pairs not issued in the same sequence on the read address and write address channels

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_pair_cntrl_signals_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check that Both transactions in a barrier pair must have the same AxID, AxBAR, AxDOMAIN, and AxPROT values.

Checks that both transactions in a barrier pair must have the same AxID, AxBAR, AxDOMAIN, and AxPROT values

When ReadBarrier and write barrier transactions with AxID, AxBAR, AxDOMAIN, AxPROT not matching the last WriteBarrier/ReadBarrier with AxID

When ReadBarrier and write barrier transactions with AxID, AxBAR, AxDOMAIN, AxPROT is matching the last WriteBarrier/ReadBarrier with AxID

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_write_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Check that for barrier write transaction only BRESP = '00 response is permitted!

Checks the Write Barrier valid response

When BRESP must be all zeros for write barrier transactions

When BRESP is not zeros for write barrier transactions

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_read_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Check that for barrier read transaction only RRESP ='00 response is permitted!

Checks the Read Barrier valid response

When RRESP must be all zeros for read barrier transactions

When RRESP is not zeros for read barrier transactions

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_id_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Check that the range of ID for barrier transactions should be inside svt_axi_transaction::barrier_id_min and svt_axi_transaction::barrier_id_max!

Checks the Barrier Id valid and unreserved

When range of ID values which can be used for Barrier transactions are specified using members barrier_id_min and barrier_id_max

When range of ID values which can be used for Barrier transactions are not specified using members barrier_id_min and barrier_id_max

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

read_barrier_arlock_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARLOCK is Normal Access 'b0!

Checks the combinations of ARLOCK and ARBAR are valid and unreserved

When ARLOCK must have normal access for read barrier transactions

When ARLOCK is not having normal access for read barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARSNOOP is all zeros !

Checks the combinations of ARSNOOP and ARBAR are valid and unreserved

When ARSNOOP must be all zeros for read barrier transactions

When ARSNOOP is not zero for read barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arcache_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARCACHE is Normal non-cacheable'b0010 !

Checks the combinations of ARCACHE and ARBAR are valid and unreserved

When ARCACHE must be Normal, Non-cacheable for read barrier transactions

When ARCACHE is not of Normal, Non-cacheable for read barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arsize_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARSIZE matches the data bus width!

Checks the combinations of ARSIZE and ARBAR are valid and unreserved

When ARSIZE must be equal to the data bus width for read barrier transactions

When ARSIZE is not equal to the data bus width for read barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that a barrier read transaction should be of length 1!

Checks the combinations of ARLEN and ARBAR are valid and unreserved

When ARLEN must be all zeros for read barrier transactions

When ARLEN is not zero for read barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction the burst_type is INCR !

Checks the combinations ARBURST and ARBAR are valid and unreserved

When ARBURST must be INCR type for read barrier transactions

When ARBURST is not INCR type for read barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

read_barrier_araddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction the ARADDR should be all zeros!

Checks the ARADDR is valid for ARBAR

When ARADDR must be all zeros for read barrier transactions

When ARADDR is not zero for read barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_transaction_user_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Checks that for a barrier transaction AxUSER has valid value 0x00

Checks the valid value of AxUSER for write barrier transactions

When a barrier transaction AxUSER has valid value 0x00

When a barrier transaction AxUSER not have valid value

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1
svt_axi_port_configuration :: awuser_enable or aruser_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awlock_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction AWLOCK is Normal Access 'b0!

Checks the combinations of AWLOCK and AWBAR are valid and unreserved

When AWLOCK must be normal access for write barrier transactions

When AWLOCK is not having normal access for write barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

write_barrier_awsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction AWSNOOP is all zeros!

Checks the combinations of AWSNOOP and AWBAR are valid and unreserved

When AWSNOOP must be all zeros for write barrier transactions

When AWSNOOP is not zero for write barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awcache_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction AWCACHE is Normal non-cacheable 'b0010!

Checks the combinations of AWCACHE and AWBAR are valid and unreserved

When AWCACHE must be Normal, non-cacheable for write barrier transactions

When AWCACHE is not of Normal, non-cacheable for write barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awsize_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction the AWSIZE matches the data bus width!

Checks the combinations of AWSIZE and AWBAR are valid and unreserved

When AWSIZE must be equal to the data bus width for write barrier transactions

When AWSIZE is not equal to the data bus width for write barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that a barrier write transaction should be of length 1!

Checks the combinations of AWLEN and AWBAR are valid and unreserved

When AWLEN must be all zeros for write barrier transactions

When AWLEN is not zero for write barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

write_barrier_awburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction the burst_type is INCR!

Checks the combinations AWBURST and AWBAR are valid and unreserved

When AWBURST must be INCR type for write barrier transactions

When AWBURST is not INCR type for write barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Barrier Transactions

write_barrier_awaddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction the AWADDR should be all zeros!

Checks the AWADDR is valid for AWBAR

When AWADDR must be all zeros for write barrier transactions

When AWADDR is not zero for write barrier transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: barrier_enable is set to 1

ERROR

ACE,ACE_Lite

Cache Line Size Transactions Constraints

cache_line_axbar_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AxBAR is valid for Cache Line Size Transactions!

Checks if the AxBAR is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AxBAR

When All cache line size transactions not have have valid AxBAR

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite

Cache Line Size Transactions Constraints

full_cache_line_size_check

Synopsys Defined

Monitor Check that all transactions other than ReadNoSnoop, ReadOnce, WriteNoSnoop, WriteUnique, WriteBack, WriteClean,DVM Message and Barrier are required to be a full cache line size!

Checks if all transactions (other than ReadNoSnoop, ReadOnce, WriteNoSnoop, WriteUnique, WriteBack, WriteClean,DVM Message and Barrier) are required to be a full cache line size

When all these transaction are full cache line size

When all these are not required to be a full cache line size

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE

ERROR

ACE,ACE_Lite

Signal Stability

signal_stable_awbar_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for signal stability when corresponding valid signal is high

Checks that AWBAR is stable when AWVALID is high

AWBAR is stable when AWVALID is high

AWBAR is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.

ERROR

ACE,ACE_Lite

Barrier Transactions: Signal Validity

signal_valid_awbar_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWBAR is not X or Z when AWVALID is high

AWBAR is not X or Z when AWVALID is high

AWBAR is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: ace_version is not set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE,ACE_Lite

Signal Stability

signal_stable_arbar_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for signal stability when corresponding valid signal is high

Checks that ARBAR is stable when ARVALID is high

ARBAR is stable when ARVALID is high

ARBAR is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.

ERROR

ACE,ACE_Lite

Barrier Transactions: Signal Validity

signal_valid_arbar_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARBAR is not X or Z when ARVALID is high

ARBAR is not X or Z when ARVALID is high

ARBAR is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: ace_version is not set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_snoop_successive_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.1 DVM message transactions

Monitor Checks that there are no unrelated snoop channel transfer in between two multi-part DVM operations which relate to the same DVM transaction

Checks that all snoop transactions of multi-part DVM operation are sent in successive manner and no unrelated snoop transaction sent during multi-part DVM opearion over AC channel

When there are no unrelated snoop channel transfer in between two multi-part DVM operations which relate to the same DVM transaction

When there are unrelated snoop channel transfer in between two multi-part DVM operations which is not relate to the same DVM transaction

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_coherent_successive_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.1 DVM message transactions

Monitor Checks that there are no unrelated read-address channel transfer in between two multi-part DVM operations which relate to the same DVM transaction

Checks that all coherent transactions of multi-part DVM operation are sent in successive manner and no unrelated coherent transaction sent during multi-part DVM opearion over AR channel

When there are no unrelated read-address channel transfer in between two multi-part DVM operations which relate to the same DVM transaction

When there are unrelated read-address channel transfer in between two multi-part DVM operations which is not relate to the same DVM transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_snoop_same_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Checks that each snoop transaction related to a multi-part DVM Operation must send same snoop response

Checks that all transactions of multi-part DVM operation have same snoop response

When snoop response which should be same as first-part of the multi-part DVM transaction

When snoop response is not same as first-part of the multi-part DVM transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_coherent_same_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Checks that each transaction of a multi-part DVM Message must send same coherent response

Checks that all transactions of multi-part DVM operation have same coherent response

When all transactions of multi-part DVM operation have same coherent response

When all transactions of multi-part DVM operation not have same coherent response

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_coherent_same_id_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.4 DVM ID values

Monitor Checks that each transaction of a multi-part DVM Message must use the same AXI ID

Checks that all transactions of multi-part DVM operation have same ID

When all transactions of multi-part DVM operation have same ID as normal transaction id

When all transactions of multi-part DVM operation not have same ID as normal transaction id

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.4 DVM ID values

Monitor Check for the ARID overlap of DVM transactions with other active Non-DVM transactions

Checks the overlapping ARID of DVM transactions with any active Read transactions

When ARID of DVM transactions overlap with any active Read transactions

When ARID of DVM transactions is not overlap with any active Read transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvmmessage_snoop_araddr_reserve_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.3 DVM messages

Monitor Check that for DVM Message the value of reserve address bits must be zero!

Checks FOR DVM Message the value of reserve address bit should be zero

When for DVM Message the value of reserve address bit is zero

When for DVM Message the value of reserve address bit is not zero

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_snoop_transaction :: snoop_xact_type is set to svt_axi_snoop_transaction :: DVMMESSAGE
svt_axi_system_configuration :: dvm_version is set to svt_axi_system_configuration :: DVMV8 or Later.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[0] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[0] of DVM message type Virtual Instruction Cache Invalidate

When ARADDR[0] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b00 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0

When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b1 than
ARADDR[0] is 1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b1 than
ARADDR[0] is 1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b1 than
ARADDR[0] is 1'b1

When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b1

When ARADDR[0] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[5] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[5] of DVM message type Virtual Instruction Cache Invalidate

When ARADDR[5] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b00 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b0

When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 than
ARADDR[5] is 1'b0,1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 than
ARADDR[5] is 1'b0,1'b1

When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY
ARADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_4
ARADDR[5] is 1'b0 for other versions

When ARADDR[5] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[6] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[6] of DVM message type Virtual Instruction Cache Invalidate

When ARADDR[6] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b00 than
ARADDR[6] is 1'b0

When ARADDR[11:10] is 2'b00 & ARADDR[9:8] is 2'b11 than
ARADDR[6] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 than
ARADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4
ARADDR[6] is 1'b0 for other dvm version

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 than
ARADDR[6] is 1'b1

When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 than
ARADDR[6] is 1'b0

When ARADDR[6] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[9:8] for DVM Message type Virtual Instruction Cache Invalidate!

Checks the valid values of ARADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate

When ARADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate have the following valid values:

When ARADDR[11:10] is 2'b00 than
ARADDR[9:8] is 2'b00,2'b11

When ARADDR[11:10] is 2'b10 than
ARADDR[9:8] is 2'b10,2'b11

When ARADDR[11:10] is 2'b11 than
ARADDR[9:8] is 2'b11

When ARADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate not have the valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_invalidate_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[11:10] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate

When ARADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate have values {2'b00,2'b10,2'b11}

When ARADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate not have values {2'b00,2'b10,2'b11}

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_addr_specified_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[0] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ARADDR[0] of DVM message type Physical Instruction Cache Invalidate

When ARADDR[0] of DVM message type Physical Instruction Cache Invalidate have following valid values:

When ARADDR[9:8] is 2'b10 & ARADDR[6:5] is 2'b00 than
ARADDR[0] is 1'b0,1'b1

When ACADDR[9:8] is 2'b10 & ARADDR[6:5] is 2'b11 than
ARADDR[0] is 1'b1

When ACADDR[9:8] is 2'b11 & ARADDR[6:5] is 2'b00 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[9:8] is 2'b11 & ARADDR[6:5] is 2'b11 than
ARADDR[0] is 1'b1

When ARADDR[0] of DVM message type Physical Instruction Cache Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_vid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[6:5] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ARADDR[6:5] of DVM message type Physical Instruction Cache Invalidate

When ARADDR[6:5] of DVM message type Physical Instruction Cache Invalidate have following valid values:

When ARADDR[9:8] is 2'b10 than
ARADDR[6:5] is 2'b00,2'b11

When ARADDR[9:8] is 2'b11 than
ARADDR[6:5] is 2'b00,2'b11

When ARADDR[6:5] of DVM message type Physical Instruction Cache Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_secure_nonsecure_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[9:8] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ARADDR[9:8] of DVM message type Physical Instruction Cache Invalidate

When ARADDR[9:8] is have valid values (2'b10, 2'b11) of DVM message type Physical Instruction Cache Invalidate

When ARADDR[9:8] is not have valid values (2'b10, 2'b11) of DVM message type Physical Instruction Cache Invalidate

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Branch Predictor

dvmmessage_branch_predictor_invalidate_supported_message_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate

Monitor Check for the supported values of ARADDR[0] for DVM Message type Branch Predictor Invalidate!

Checks the valid values of ARADDR[0] of DVM message type Branch Predictor Invalidate

When ARADDR[0] must have valid value 1'b0,1'b1 for DVM message Branch Predictor Invalidate

When ARADDR[0] is not have values 1'b0,1'b1 for DVM message Branch Predictor Invalidate

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[0] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[0] of DVM message type TLB Invalidate

When ARADDR[0] of DVM message type TLB Invalidate have following valid values:

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b1 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b1 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b01 & ARADDR[6] is 1'b1 & ARADDR[5] is 1'b0 than
ARADDR[0] is 1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than
ARADDR[0] is 1'b0,1'b1

When ARADDR[0] of DVM message type TLB Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[5] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[5] of DVM message type TLB Invalidate

When ARADDR[5] of DVM message type TLB Invalidate must have following valid values:

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b0,1'b1

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b1 than
ARADDR[5] is 1'b0,1'b1

When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b11 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY
ARADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_4 or DVMV9_2
ARADDR[5] is 1'b0 for other versions

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b01 & ARADDR[6] is 1'b1 than
ARADDR[5] is 1'b0

When ARADDR[11:10] is 2'b10 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b1 than
ARADDR[5] is 1'b0,1'b1

When ARADDR[11:10] is 2'b11 & ARADDR[9:8] is 2'b10 & ARADDR[6] is 1'b0 than
ARADDR[5] is 1'b0,1'b1

When ARADDR[5] of DVM message type TLB Invalidate not takes valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[6] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[6] of DVM message type TLB Invalidate

When ARADDR[6] of DVM message type TLB Invalidate have the following valid values:

When ARADDR[11:10] is 2'b10 and ARADDR[9:8] is 2'b10 than
ARADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4 or DVMV9_2
ARADDR[6] is 2'b0 for other versions

When ARADDR[11:10] is 2'b10 and ARADDR[9:8] is 2'b11 than
ARADDR[6] is 1'b0,1'b1

When ARADDR[11:10] is 2'b11 and ARADDR[9:8] is 2'b11 than
ARADDR[6] is 1'b0

When ARADDR[11:10] is 2'b11 and ARADDR[9:8] is 2'b10 than
ARADDR[6] is 1'b0

When ARADDR[11:10] is 2'b10 and ARADDR[9:8] is 2'b01 than
ARADDR[6] is 1'b1

When ARADDR[6] of DVM message type TLBI not takes valid value according to dvm versions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check the for supported values of ARADDR[9:8] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[9:8] of DVM message type TLB Invalidate

When ARADDR[9:8] of DVM message type TLBI must have following valid values:

When ARADDR [11:10] is 2'b10 than
ARADDR[9:8] have value 2'b00,2'b01,2'b10,2'b11 for dvm_version DVMV9_2
ARADDR[9:8] have value 2'b01,2'b10,2'b11 for dvm_version DVMV8_4
ARADDR[9:8] have value 2'b10,2'b11 for other versions

When ACADDR [11:10] is 2'b11 than
ARADDR[9:8] have value 2'b00,2'b10,2'b11 for dvm_version DVMV9_2
ARADDR[9:8] have value 2'b10,2'b11 for dvm_version DVMV8_4
ARADDR[9:8] have value 2'b11 for other version

When ARADDR[9:8] of DVM message type TLBI not takes valid values for all the versions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_hypervisor_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[11:10] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[11:10] of DVM message type TLB Invalidate

When ARADDR[11:10] of DVM message type TLBI have following valid value:

For dvm_version DVMV9_2 when ARADDR[11:10] is 2'b00,2'b01,2'b10,2'b11
For other version ARADDR[11:10] is 2'b01,2'b10,2'b11

When ARADDR[11:10] of DVM message type TLB Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvmmessage_araddr_reserve_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.3.5 DVM message encoding, first part

Monitor Check that for DVM Message the value of reserve address bits must be zero!

Checks FOR DVM Message the value of reserve address bit should be zero

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvmcomplete_araddr_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for a DVM Complete message, ARADDR is defined to be all zeros!

Checks For a DVM Complete message, ARADDR is defined to be all zeros

When ARADDR must be zero for DVM Complete

When ARADDR is not zero for DVM Complete

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Hint

dvm_operation_dvm_hint_araddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.12 Hint

Monitor Checks that for DVM HINT Message ARADDR bit[15] == 1

Checks for DVMHINT, DVM Operation the valid value of ARADDR[15]

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM Operation

dvm_operation_dvm_sync_araddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.11 Synchronization

Monitor Checks that for DVM SYNC Message ARADDR bits [n-1:32] and [11:0] are all set to 0 and bit[15] == 1

Checks for DVMSYNC, DVM Operation the valid value of ARADDR[(n-1):32],[15],[11:0] bits

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM Operation

dvm_operation_dvm_sync_arsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ARSNOOP is 'b1111 for DVM Operation and DVM Sync!

Checks for DVMSYNC, DVM Operation the valid value of ARSNOOP

When ARSNOOP for DVM Message must be 0b1111

When ARSNOOP for DVM Message is not of 0b1111

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_ardomain_type_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARDOMAIN is Inner shareable or Outer shareable!

Checks for DVM ARDOMAIN is Inner shareable or Outer shareable

When DVM ARDOMAIN must be Inner shareable or Outer shareable

When DVM ARDOMAIN is not of the Inner shareable or Outer shareable

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arlock_type_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARLOCK is 'b0 Normal Access!

Checks for DVM ARLOCK 'b0 Normal Access

When DVM ARLOCK must be zero or having normal access

When DVM ARLOCK is not having normal acsess

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arcache_type_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARCACHE is 'b0010 Normal non-cacheable!

Checks for DVM ARCACHE 'b0010 Normal non-cacheable

When DVM ARCACHE must be 0b0010, which means must be modifiable and non-cacheable

When DVM ARCACHE is not 0b0010

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arsize_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions the ARSIZE Matches the data bus width !

Checks for DVM ARSIZE Matches the data bus width

When burst length must be 1, which means ARLEN[7:0] must be 0x00.

When burst length is not equal to 1

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that DVM transactions are of length 1!

Checks For DVM ARLEN All zero

When burst length must be 1, which means ARLEN[7:0] must be 0x00.

When burst length is not equal to 1

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions burst_type is INCR !

Checks For DVM ARBURST 'b01 Burst Type INCR

When ARBURST for dvm must be INCR type

When ARBURST for dvm is not of INCR type

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

awsnoop_awdomain_awbar_reserve_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.3 Read and write Shareable transaction types

Monitor Check that the combinations of AWDOMAIN,AWSNOOP and AWBAR are Valid and are un-reserved!

Checks the combinations of AWDOMAIN,AWSNOOP and AWBAR are valid and unreserved

When the combinations of AWDOMAIN, AWSNOOP and AWBAR takes valid and unreserved values

When the combinations of AWDOMAIN, AWSNOOP and AWBAR are not takes valid and unreserved values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE
The barrier transactions are not supported starting from AMBA5 interfaces (i.e. AXI5/ACE5_Lite). So, the AxBAR signal is tied-off to default value of (00) indicating a normal transaction.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

arsnoop_ardomain_arbar_reserve_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.3 Read and write Shareable transaction types

Monitor Check that the combinations of ARDOMAIN,ARSNOOP and ARBAR are Valid and are un-reserved!

Checks the combinations of ARDOMAIN,ARSNOOP and ARBAR are valid and unreserved

When the combinations of ARDOMAIN, ARSNOOP and ARBAR takes valid and unreserved values

When the combinations of ARDOMAIN, ARSNOOP and ARBAR are not takes valid and unreserved values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.
The barrier transactions are not supported starting from AMBA5 interfaces (i.e. AXI5/ACE5_Lite). So, the AxBAR signal is tied-off to default value of (00) indicating a normal transaction.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Burst Type

fixed_burst_type_valid

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that the FIXED burst type is only permitted for ReadNoSnoop and WriteNoSnoop transactions!

Checks that the FIXED burst type is not supported for shareable transactions

When FIXED burst type for coherent transaction type is inside ReadNoSnoop and WriteNoSnoop transactions

When FIXED burst type for coherent transaction type is not inside ReadNoSnoop and WriteNoSnoop transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

valid_snoop_response_during_cache_maintenance_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.4.4 Cache maintenance transactions

Monitor checks that when master initiates a CleanShared cache maintenance transaction, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty snoop response. It also checks that when master initiates CleanInvalid or MakeInvalid cache maintenance transactions, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty, IsShared and DataTransfer snoop responses

When cleanshared or cleansharedpersist transactions is outstanding then cacheline should be in invalid or clean state and hence snoop response must not assert pass_dirty bit

When valid snoop response is not asserted

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

no_memory_update_or_shareable_txn_during_cache_maintenance_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.9 ACE Managers and CMOs

Monitor checks that WriteBack, WriteClean or any shareable transactions which permits the line to be allocated are not issued while cache maintenance transaction is in progress

Checks that WriteBack, WriteClean or any shareable transactions that permits the line to be allocated are not issued while cache maintenance transaction is in progress.

check will pass if WriteBack, WriteClean or any shareable transactions that permits the line to be allocated are not issued while cache maintenance transaction is in progress.

check will fail if WriteBack, WriteClean or any shareable transactions that permits the line to be allocated are issued while cache maintenance transaction is in progress.

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

cache_maintenance_outstanding_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D12.1 About the interface control signals

Monitor checks that CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding. Checks that CleanShared cache maintenance transactions are not initiated while any memory update or any shareable transactions that can make the cacheline dirty, are outstanding

Checks that CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding. It also checks that CleanShared cache maintenance transactions are not initiated while any memory update or any shareable transactions that can make the cacheline dirty, are outstanding

When CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding

When CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are not outstanding

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_dvmcomplete_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for DVMComplete Transaction are IsShared=0;PassDirty=0 !

Checks the valid response of DVM Complete Transactions

When the valid response for DVMComplete Transaction are IsShared=0;PassDirty=0

When the valid response for DVMComplete Transaction are not of IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_dvmmessage_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for DVMMessage Transaction are IsShared=0;PassDirty=0 !

Checks the valid response of DVM Message Transactions

When the valid response for DVMMessage Transaction are IsShared=0;PassDirty=0

When the valid response for DVMMessage Transaction are not IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_readbarrier_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadBarrier Transaction are IsShared=0;PassDirty=0 !

Checks the valid response of readbarrier Transactions

When the valid response for ReadBarrier Transaction are IsShared=0;PassDirty=0

When the valid response for ReadBarrier Transaction are not of IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Data Transfer Check

coherent_single_read_data_transfer_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED,CLEANSHAREDPERSIST, CLEANINVALID, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer

Checks the CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED, CLEANINVALID,CLEANSHAREDPERSIST, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer

When CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED,CLEANSHAREDPERSIST, CLEANINVALID, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer

When CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED,CLEANSHAREDPERSIST, CLEANINVALID, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions not have single read data channel transfer

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_readnosnoop_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadNoSnoop Transaction are IsShared=0;PassDirty=0!

Checks the valid response of readnosnoop Transactions

When the valid response for ReadNoSnoop Transaction are IsShared=0;PassDirty=0

When the valid response for ReadNoSnoop Transaction are not of IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_readonce_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadOnce Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of readonce Transactions

When the valid response for ReadOnce Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

When the valid response for ReadOnce Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_cleaninvalid_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for CleanInvalid Transaction are IsShared=0;PassDirty=0!

Checks the valid response of cleaninvalid Transactions

When the valid response for CleanInvalid Transaction are IsShared=0;PassDirty=0

When the valid response for CleanInvalid Transaction are not of IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_makeinvalid_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for MakeInvalid Transaction are IsShared=0;PassDirty=0!

Checks the valid response of makeinvalid Transactions

When the valid response for MakeInvalid Transaction are IsShared=0;PassDirty=0

When the valid response for MakeInvalid Transaction are not of IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

read_data_chan_cleansharedpersist_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.7.4 PCMOs on read channels

Monitor Check that the valid response for CleanSharedPersist Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of cleansharedPersist Transactions

When the valid response for CleanSharedPersist Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

When the valid response for CleanSharedPersist Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_cleanshared_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for CleanShared Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of cleanshared Transactions

When the valid response for CleanShared Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

When the valid response for CleanShared Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Data Transfer Check

perform_no_datatransfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that no data transfer occurs for a CleanShared,CleansharedPersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions !

Checks for no data transfer occurs for a CleanShared,Cleansharedpersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions

When no data transfer occurs for a CleanShared,Cleansharedpersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions

When data transfer occurs for a CleanShared,Cleansharedpersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

writelineunique_wstrb_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that WriteLineUnique transactions are required to have every write data strobe bits asserted, that is, sparse write data strobes are not permitted

Monitor check that all write strobes bits are asserted for a WRITELINEUNIQUE transaction

When all write strobes bits are asserted for a WRITELINEUNIQUE transaction

When all write strobes bits are not asserted for a WRITELINEUNIQUE transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_arlock_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Checks that ARLOCK is valid for ReadOnce Transactions!

Checks if the ARLOCK is valid for ReadOnce Transactions

When ARLOCK is valid for ReadOnce Transactions

When ARLOCK is not valid for ReadOnce Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awlock_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWLOCK is valid for WriteUnique Transactions!

Checks if the AWLOCK is valid for WriteUnique Transactions

When AWLOCK is valid for WriteUnique Transactions

When AWLOCK is not valid for WriteUnique Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_arcache_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that ARCACHE is valid for ReadOnce Transactions!

Checks if the ARCACHE is valid for ReadOnce Transactions

When ARCACHE is valid for ReadOnce Transactions

When ARCACHE is not valid for ReadOnce Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awcache_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWCACHE is valid for WriteUnique Transactions!

Checks if the AWCACHE is valid for WriteUnique Transactions

When AWCACHE is valid for WriteUnique Transactions

When AWCACHE is not valid for WriteUnique Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_arburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that ARBURST is valid for ReadOnce Transactions!

Checks if the ARBURST is valid for ReadOnce Transactions

When ARBURST is valid for ReadOnce Transactions

When ARBURST is not valid for ReadOnce Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWBURST is valid for WriteUnique Transactions!

Checks if the AWBURST is valid for WriteUnique Transactions

When AWBURST is valid for WriteUnique Transactions

When AWBURST is not valid for WriteUnique Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_ardomain_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that ARDOMAIN is valid for ReadOnce Transactions!

Checks if the ARDOMAIN is valid for ReadOnce Transactions

When ARDOMAIN is valid for ReadOnce Transactions

When ARDOMAIN is not valid for ReadOnce Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awdomain_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWDOMAIN is valid for WriteUnique Transactions!

Checks if the AWDOMAIN is valid for ReadOnce & WriteUnique Transactions

When AWDOMAIN is valid for ReadOnce & WriteUnique Transactions

When AWDOMAIN is not valid for ReadOnce & WriteUnique Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_sz_eq_alen_asize_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AxLEN is correctly indicated according to Cache Line Size configured!

Checks if the AxLEN is correctly indicated as per the Cache Line Size configured

When Coherent transaction type of CLEANUNIQUE, EVICT, CLEANSHARED, CLEANINVALID, MAKEINVALID, MAKEUNIQUE, CLEANSHAREDPERSIST must have indicated correct AxLEN as per cache-line size

When Coherent transaction type of CLEANUNIQUE, EVICT, CLEANSHARED, CLEANINVALID, MAKEINVALID, MAKEUNIQUE, CLEANSHAREDPERSIST is not indicated correct AxLEN as per cache-line size

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arlock_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that ARLOCK is valid for Cache Line Size Transactions!

Checks if the ARLOCK is valid for Cache Line Size Transactions

When All cache line size transactions must have valid ARLOCK

When All cache line size transactions not have have valid ARLOCK

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awlock_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AWLOCK is valid for Cache Line Size Transactions!

Checks if the AWLOCK is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AWLOCK

When All cache line size transactions not have have valid AWLOCK

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arcache_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that ARCACHE is valid for Cache Line Size Transactions!

Checks if the ARCACHE is valid for Cache Line Size Transactions

When All cache line size transactions must have valid ARCACHE

When All cache line size transactions not have have valid ARCACHE

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awcache_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AWCACHE is valid for Cache Line Size Transactions!

Checks if the AWCACHE is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AWCACHE

When All cache line size transactions not have have valid AWCACHE

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_ardomain_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that ARDOMAIN is valid for Cache Line Size Transactions!

Checks if the ARDOMAIN is valid for Cache Line Size Transactions

When All cache line size transactions must have valid ARDOMAIN

When All cache line size transactions not have have valid ARDOMAIN

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awdomain_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AWDOMAIN is valid for Cache Line Size Transactions!

Checks if the AWDOMAIN is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AWDOMAIN

When All cache line size transactions not have have valid AWDOMAIN

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arburst_incr_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to cache line size for INCR burst in a Cache Line Size Transaction!

Checks if the address is aligned for ARBURST in Cache Line Size Transactions

When address is aligned to burst_size for INCR burst in a Cache Line Size Transaction

When address is not aligned to burst_size for INCR burst in a Cache Line Size Transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awburst_incr_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to cache line size for INCR burst in a Cache Line Size Transaction!

Checks if the address is aligned for AWBURST in Cache Line Size Transactions

When address is aligned to burst_size for INCR burst in a Cache Line Size Transaction

When address is not aligned to burst_size for INCR burst in a Cache Line Size Transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arburst_wrap_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction!

Checks if the address is aligned for ARBURST in Cache Line Size Transactions

When address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction

When address is not aligned to burst_size for WRAP burst in a Cache Line Size Transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awburst_wrap_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction!

Checks if the address is aligned for AWBURST in Cache Line Size Transactions

When address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction

When address is not aligned to burst_size for WRAP burst in a Cache Line Size Transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to either svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arsize_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the total number of bytes transferred in the transaction is equal to the cache_line_size!

Checks if the ARSIZE is valid for Cache Line Size Transactions

When All cache line size transactions must have valid ARSIZE

When All cache line size transactions not have have valid ARSIZE

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to either svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that If DataTransfer de-asserted then no data transfer will occur on the snoop data channel for this transaction DataTransfer, CRRESP[0]!

Checks if the ARBURST is valid for Cache Line Size Transactions

When All cache line size transactions must have valid ARBURST

When All cache line size transactions not have have valid ARBURST

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awsize_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the total number of bytes transferred in the transaction is equal to the cache_line_size!

Checks if the AWSIZE is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AWSIZE

When All cache line size transactions not have have valid AWSIZE

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that awburst is valid for Cache Line Size Transactions!

Checks if the AWBURST is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AWBURST

When All cache line size transactions not have valid AWBURST

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

axcache_axdomain_invalid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.6 Domains and memory types
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor Check that the combination of AxDOMAIN and AxCACHE are valid !

Checks if the AXCACHE and AXDOMAIN value are valid

When the combination of AXCACHE and AXDOMAIN value are valid

When the combination of AXCACHE and AXDOMAIN value are not valid

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

axcache_axdomain_restriction_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.6 Domains and memory types
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor Check that Device transactions, as indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 System Shareable !

Checks if the Device transactions, as indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 Checks if the Cacheable transactions, as indicated by AxCACHE[3:2] != 00, must not use AxDOMAIN = 11

When device transaction indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 When cacheable transaction indicated by AxCACHE[3:2] != 00, must not use AxDOMAIN = 11

When device transaction indicated by AxCACHE[1] = 0, not use AxDOMAIN = 11 When cacheable transaction indicated by AxCACHE[3:2] != 00, use AxDOMAIN = 11

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses: ACE Master

exclusive_ace_transaction_type_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.1 About Exclusive accesses from ACE Managers

Monitor check that exclusive transaction sent on AXI_ACE interface are only of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type

Checks that exclusive transaction sent on AXI_ACE interface are only of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type

When exclusive transaction type coherent and coherent transaction type is WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type

When exclusive transaction type coherent and coherent transaction type is not of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE OR ACE_LITE.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_id_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.1 Exclusive access process

Monitor check that the bits of the AXI ID signal that are used to identify the Exclusive-capable thread must be the same for all Exclusive transactions from the same Exclusive-capable thread. In other words, monitor checks that same ID is used for exclusive access READ and WRITE transactions

Checks that id is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

When the exclusive transaction partial exclusive id is equal to the normal transaction partial exclusive id

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE OR ACE_LITE.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_transaction :: atomic_type is set to svt_axi_transaction :: EXCLUSIVE.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses: ACE Master

exclusive_store_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor check that response generated for exclusive store accesss is correct

Checks that response generated for exclusive store accesss is correct

When exclusive read response is match exclusive store response

When exclusive read response does not match exclusive store response

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE OR ACE_LITE.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses: ACE Master

exclusive_load_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load

Monitor check that response generated for exclusive load accesss is correct

Checks that response generated for exclusive load accesss is correct

When exclusive read response match with expected exclusive response

When exclusive read response does not match with expected exclusive response

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Data: Signal Stability

signal_stable_awsnoop_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A8.1 Opcode signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.3 Read and write Shareable transaction types

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSNOOP is stable when AWVALID is high

AWSNOOP is stable when AWVALID is high

AWSNOOP is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Stability

signal_stable_awdomain_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for signal stability when corresponding valid signal is high

Checks that AWDOMAIN is stable when AWVALID is high

AWDOMAIN is stable when AWVALID is high

AWDOMAIN is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Data: Signal Stability

signal_stable_arsnoop_when_arvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that ARSNOOP is stable when ARVALID is high

ARSNOOP is stable when ARVALID is high

ARSNOOP is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Stability

signal_stable_ardomain_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for signal stability when corresponding valid signal is high

Checks that ARDOMAIN is stable when ARVALID is high

ARDOMAIN is stable when ARVALID is high

ARDOMAIN is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

signal_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.2 Addresses in DVM messages

Monitor check for dvm multipart xact ADDR[2:0] should be SBZ

Checks that ARADDR[2:0] for multipart dvm xact is not other than SBZ

When ARADDR[2:0] for multipart dvm xact is not other than SBZ

When ARADDR[2:0] for multipart dvm xact is other than SBZ

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_arsnoop_when_arvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARSNOOP is not X or Z when ARVALID is high

ARSNOOP is not X or Z when ARVALID is high

ARSNOOP is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Validity

signal_valid_ardomain_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARDOMAIN is not X or Z when ARVALID is high

ARDOMAIN is not X or Z when ARVALID is high

ARDOMAIN is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE,ACE5

Interconnect Requirements

snoop_to_same_cache_line_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.2 Sequencing transactions

The interconnect must ensure that, if the interconnect sends a snoop transaction to a master, it must not provide the same master with a response to a transaction to the same cache line, until it has received a snoop response on CRRESP to the snoop transaction

Checks that if received a snoop transaction, response to a transaction to the same cache line is not received , until snoop response is sent

When snoop transaction is received than response to a transaction to the same cache line is not received , until snoop response is sent

When snoop transaction is not received

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Interconnect Requirements

resp_to_same_cache_line_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.2 Sequencing transactions

The interconnect must ensure that, if the interconnect provides a master with a response to a transaction, it must not send the same master a snoop transaction to the same cache line until it has received an acknowledgment of the transaction response on either RACK or WACK

Checks that Master does not receive a snoop transaction until any preceding transaction to the same cache line has completed

When Master does not receive a snoop transaction until any preceding transaction to the same cache line has completed

When Master receive a snoop transaction until any preceding transaction to the same cache line has completed

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

WACK Signaling

wack_status_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling

Monitor Check that WACK is asserted in response to BVALID/BREADY handshakes!

Checks the WACK for valid response

When WACK is asserted in response to BVALID/BREADY handshakes

When WACK is not asserted in response to BVALID/BREADY handshakes

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

RACK Signaling

rack_status_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling

Monitor Check that RACK is asserted in response to all RLAST/RVALID/RREADY handshakes!

Checks the RACK for valid response

When RACK is asserted in response to all RLAST/RVALID/RREADY handshakes

When RACK is not asserted in response to all RLAST/RVALID/RREADY handshakes

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Snoop Transactions

snoop_addr_snoop_data_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor Check that the master must wait for both ACVALID and ACREADY to be asserted before asserting CDVALID!

Checks that ACVALID and ACREADY to be asserted before asserting CDVALID

When the master must wait for both ACVALID and ACREADY to be asserted before asserting CDVALID

When the master is not wait for both ACVALID and ACREADY to be asserted before asserting CDVALID

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Snoop Data

cdlast_asserted_for_last_snoopread_data_beat

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check that the CDLAST signal is asserted during the final data transfer associated with a snoop transaction!

Checks that CDLAST signal is asserted during the final data transfer

When CDLAST signal is asserted during the final data transfer

When CDLAST signal is not asserted during the final data transfer

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Snoop Response

snoop_response_channel_isshared_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that for ReadUnique, CleanInvalid and MakeInvalid transaction, snoop_resp_isshared cannot be asserted!

Checks for readunique cleaninvalid makeinvalid illegal response

When IsShared = 0 for a ReadUnique, CleanInvalid, MakeInvalid transaction is illegal snoop response

When IsShared = 1 for a ReadUnique, CleanInvalid, MakeInvalid transaction is illegal snoop response

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Snoop Data

full_cache_line_datatransfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check that if DataTransfer is asserted, a full cache line of data must be provided on the snoop data channel!

If DataTransfer is asserted, a full cache line of data must be provided on the snoop data channel

When DataTransfer = 1 is asserted, a full cache line of data must be provided on the snoop data channel

When DataTransfer = 1 is asserted, a full cache line of data is not provided on the snoop data channel

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Snoop Response

snoop_resp_passdirty_datatransfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that snoop_resp_datatransfer is asserted if snoop_resp_passdirty is asserted!

Checks that for MakeInvalid transactions a data transfer is never required

When DataTransfer = 0 and PassDirty = 1 for any transaction is not have valid snoop response

When DataTransfer = 0 and PassDirty = 1 for any transaction is have illegal snoop response

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

complete_outstanding_writeunique_writelineunique_before_memory_write_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.7 Restrictions on WriteUnique and WriteLineUnique usage

Monitor checks that no additional WriteBack, WriteClean, or WriteEvict transactions are issued until all outstanding WriteUnique or WriteLineUnique transactions are completed

Checks that a cached master does not issue WriteBack, WriteClean or WriteEvict transaction while any WriteUnique or WriteLineUnique coherent write transaction is in progress. It automatically checks second rule which says, Complete any incoming snoop transactions without the use of WriteBack, WriteClean, or WriteEvict transactions while a WriteUnique or WriteLineUnique transaction is in progress

When no additional WriteBack, WriteClean, or WriteEvict transactions are issued until all outstanding WriteUnique or WriteLineUnique transactions are completed

When additional WriteBack, WriteClean, or WriteEvict transactions are issued until all outstanding WriteUnique or WriteLineUnique transactions are completed

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Coherency Transactions

complete_outstanding_memory_write_before_writeunique_writelineunique_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.7 Restrictions on WriteUnique and WriteLineUnique usage

Monitor checks that a cached master completes any outstanding WriteBack, WriteClean, or WriteEvict transactions before issuing a WriteUnique or WriteLineUnique transaction

Checks that a cached master does not initiate WriteUnique or WriteLineUnique coherent write transaction while any WriteBack, WriteClean or WriteEvict transaction is outstanding

When a cached master completes any outstanding WriteBack, WriteClean, or WriteEvict transactions before issuing a WriteUnique or WriteLineUnique transaction

When a cached master not completes any outstanding WriteBack, WriteClean, or WriteEvict transactions before issuing a WriteUnique or WriteLineUnique transaction

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Snoop Address

acaddr_aligned_to_cddata_width_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor Check that ACADDR must be aligned to the data transfer size, which is determined by the width of the snoop data bus in bytes

Checks if snoop address is aligned with snoop data width

When ACADDR must be aligned to the data transfer size, which is determined by the width of the snoop data bus in bytes

When ACADDR is not aligned to the data transfer size, which is determined by the width of the snoop data bus in bytes

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Snoop Transactions

snoop_transaction_burst_length_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check that snoop transaction burst length must be 1, 2, 4, 8, or 16

Checks if number of databeat transferred over snoop data channel is valid

When number of databeat transferred over snoop data channel is of valid value 1,2,4,8,16

When number of databeat transferred over snoop data channel is of not have valid value 1,2,4,8,16

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Read response signaling

read_data_chan_readclean_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadClean Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of readclean Transactions

When the valid response for ReadClean Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

When the valid response for ReadClean Transaction are not of IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Read response signaling

read_data_chan_readnotshareddirty_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadNotSharedDirty Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1 & IsShared=1;PassDirty=0!

Checks the valid response of readnotshareddirty Transactions

When the valid response for ReadNotSharedDirty Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1 & IsShared=1;PassDirty=0

When the valid response for ReadNotSharedDirty Transaction are not of IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1 & IsShared=1;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Read response signaling

read_data_chan_readunique_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadUnique Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1!

Checks the valid response of readunique Transactions

When the valid response for ReadUnique Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1

When the valid response for ReadUnique Transaction are not of IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Read response signaling

read_data_chan_cleanunique_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for CleanUnique Transaction are IsShared=0;PassDirty=0!

Checks the valid response of cleanunique Transactions

When the valid response for CleanUnique Transaction are IsShared=0;PassDirty=0

When the valid response for CleanUnique Transaction are not of IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Read response signaling

read_data_chan_makeunique_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for MakeUnique Transaction are IsShared=0;PassDirty=0!

Checks the valid response of makeunique Transactions

When the valid response for MakeUnique Transaction are IsShared=0;PassDirty=0

When the valid response for MakeUnique Transaction are not of IsShared=0;PassDirty=0

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_transaction_from_shared_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Checks that if cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED

Checks that if cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED

When cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED

When cacheline is in shared state then exclusive transaction is issued other than CLEANUNIQUE, READCLEAN or READSHARED

This check is applicable only when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: snoop_filter_enable is set to 1

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_store_from_valid_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Checks that if cacheline is in invalid state then exclusive store transaction is not issued

Checks that if cacheline is in invalid state then exclusive store transaction is not issued

When cacheline is in invalid state then exclusive store transaction is not issued

When cacheline is not in invalid state then exclusive store transaction is issued

This check is applicable only when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: snoop_filter_enable is set to 1

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_load_from_valid_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load

Monitor Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

When cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

When cacheline is not in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

This check is applicable only when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: snoop_filter_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

writeevict_wstrb_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict

Monitor Check that all write strobes bits are asserted for a WRITEEVICT transaction

Monitor check that all write strobes bits are asserted for a WRITEEVICT transaction

When all write strobes bits are asserted for a WRITEEVICT transaction

When all write strobes bits are not asserted for a WRITEEVICT transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: writeevict_enable is set to 1

ERROR

ACE,ACE5

Cache Line Size Transactions Constraints

writeevict_awunique_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWUNIQUE is asserted for a WRITEEVICT transaction

AWUNIQUE must be asserted for WRITEEVICT transactions

When AWUNIQUE must be asserted for WRITEEVICT transactions

When AWUNIQUE is not asserted for WRITEEVICT transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: writeevict_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeclean_awunique_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWUNIQUE is deasserted for a WRITECLEAN transaction

AWUNIQUE must be deasserted for WRITECLEAN transactions

When AWUNIQUE must be deasserted for WRITECLEAN transactions

When AWUNIQUE is not deasserted for WRITECLEAN transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: awunique_enable is set to 1

ERROR

ACE,ACE5

Awnique Signal

snoop_response_to_same_cacheline_during_xact_with_awunique_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal

Monitor check that while a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line

While a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line

When a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line

When a transaction is in progress which has the AWUNIQUE signal asserted, the master give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: writeevict_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

snoop_response_to_same_cacheline_during_writeevict_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict

Monitor check that if a snooped master receives a snoop transaction when it has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time

If a snooped master receives a snoop transaction when it is has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time. The snooped master achieves this by delaying the snoop response until the snooped master has completed the WriteEvict transaction

When a snooped master receives a snoop transaction when it has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time

When a snooped master receives a snoop transaction when it has an outstanding WriteEvict transaction and any master can update the same area of main memory at the same time

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: writeevict_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awlock_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a WRAP burst for WriteBack and WriteClean transactions, AWSIZE x AWLEN must not exceed the cache line size!

Checks if the AWLOCK is 0 for WriteBack and WriteClean Transactions

When WRITEBACK and WRITECLEAN transactions must have atomic_type as NORMAL

When WRITEBACK and WRITECLEAN transactions not have atomic_type as NORMAL

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_wrap_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a WRAP burst for WriteBack and WriteClean transactions, AWSIZE x AWLEN must not exceed the cache line size!

Checks if the AWSIZE x AWLEN not exceed the cache line size WriteBack and WriteClean Transactions

When for WRAP burst, AWSIZE x AWLEN must not exceed the cache line size

When for WRAP burst, AWSIZE x AWLEN is exceed the cache line size

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_incr_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for an INCR burst for WriteBack and WriteClean transactions, the last byte in the burst added to the AWSIZE aligned start address, must be within the same cache line as the first byte in the burst!

Checks if the Address aligned for INCR is valid for WriteBack and WriteClean Transactions

When Address aligned for INCR is valid for WriteBack and WriteClean Transactions

When Address aligned for INCR is not valid for WriteBack and WriteClean Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awcache_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWCACHE is valid for WriteBack and WriteClean Transactions!

Checks if the AWCACHE is valid for WriteBack and WriteClean Transactions

When WRITEBACK and WRITECLEAN transactions cache_type[1] should be 1'b1 (modifiable)

When WRITEBACK and WRITECLEAN transactions cache_type[1] is not 1'b1 (modifiable)

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awdomain_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWDOMAIN is valid for WriteBack and WriteClean Transactions!

Checks if the AWDOMAIN is valid for WriteBack and WriteClean Transactions

When WRITEBACK and WRITECLEAN transactions domain_type should be INNERSHAREABLE, OUTERSHAREABLE or NONSHAREABLE.

When WRITEBACK and WRITECLEAN transactions domain_type is not of INNERSHAREABLE, OUTERSHAREABLE or NONSHAREABLE.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWBURST is valid for WriteBack and WriteClean Transactions!

Checks if the AWBURST is valid for WriteBack and WriteClean Transactions

When WRITEBACK and WRITECLEAN transactions burst_type should be INCR or WRAP

When WRITEBACK and WRITECLEAN transactions burst_type is not of INCR or WRAP

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_awlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWLEN and AWBURST are valid for WriteBack and WriteClean Transactions!

Checks if the AWLEN for INCR is valid for WriteBack and WriteClean Transactions

When WRITEBACK and WRITECLEAN transactions burst_length should be inside {1:16} for INCR bursts and inside {2,4,8,16} for WRAP bursts

When WRITEBACK and WRITECLEAN transactions burst_length is not inside {1:16} for INCR bursts and not inside {2,4,8,16} for WRAP bursts

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWLEN is valid for WriteBack and WriteClean Transactions!

Checks if the AWLEN is valid for WriteBack and WriteClean Transactions

When WRITEBACK and WRITECLEAN transactions the burst_length should be less than or equal to 16

When WRITEBACK and WRITECLEAN transactions the burst_length is not less than or equal to 16

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awsize_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWSIZE is valid for WriteBack and WriteClean Transactions!

Checks if the AWSIZE is valid for WriteBack and WriteClean Transactions

When WRITEBACK and WRITECLEAN transactions burst_size should be less than or equal to the data width

When WRITEBACK and WRITECLEAN transactions burst_size is not less than or equal to the data width

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Snoop Transactions

dirty_state_data_transfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.2.2 Snoop data transfers

Monitor checks that, if cacheline is in Dirty state UD or SD then dataTransfer bit must be set when master sends snoop response

Checks if snoop response has data transfer bit set for cacheline in dirty state

When cacheline is in Dirty state (UD or SD) then dataTransfer bit must be set when master sends snoop response

When cacheline is not in Dirty state (UD or SD) then dataTransfer bit is not set when master sends snoop response

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

evict_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.9.1 Evict

Monitor checks that, EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state

Checks if EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state

When EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state

When EVICT transaction not starts from UNIQUECLEAN or SHAREDCLEAN state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

writeevict_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict

Monitor checks that, WRITEEVICT transaction starts only from UNIQUECLEAN state

Checks if WRITEEVICT transaction starts only from UNIQUECLEAN state

When WRITEEVICT transaction starts only from UNIQUECLEAN state

When WRITEEVICT transaction not starts from UNIQUECLEAN state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

writeclean_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.5 WriteClean

Monitor checks that, WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

Checks if WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

When WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

When WRITECLEAN transaction not starts from UNIQUEDIRTY or SHAREDDIRTY state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

writeback_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.4 WriteBack

Monitor checks that, WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

Checks if WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

When WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

When WRITEBACK transaction not starts from UNIQUEDIRTY or SHAREDDIRTY state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

writelineunique_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.3 WriteLineUnique

Monitor checks that, WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When WRITELINEUNIQUE transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

writeunique_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.2 WriteUnique

Monitor checks that, WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When WRITEUNIQUE transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

makeinvalid_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.7.2 MakeInvalid

Monitor checks that, MAKEINVALID transaction starts only from INVALID state

Checks if MAKEINVALID transaction starts only from INVALID state

When MAKEINVALID transaction starts only from INVALID state

When MAKEINVALID transaction not starts from INVALID state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Coherency Transactions

cleaninvalid_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.6.3 CleanInvalid

Monitor checks that, CLEANINVALID transaction starts only from INVALID state

Checks if CLEANINVALID transaction starts only from INVALID state

When CLEANINVALID transaction starts only from INVALID state

When CLEANINVALID transaction not starts from INVALID state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Cache Maintenance

cleansharedpersist_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.7 Cache maintenance for Persistence

Monitor checks that, CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When CLEANSHAREDPERSIST transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Passive Slave, Active/Passive Master

This check is applicable only when: - svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE - cfg.sys_cfg.passive_cache_monitor_enable is set to 1 .

ERROR

ACE,ACE5

Coherency Transactions

cleanshared_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.6.2 CleanShared

Monitor checks that, CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

When CLEANSHARED transaction not starts from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cfg.sys_cfg.passive_cache_monitor_enable is set to 1

ERROR

ACE,ACE5

Snoop Transactions

cdvalid_high_no_data_transfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.2.1 Channel activity

Monitor Check that arburst is valid for Cache Line Size Transactions!

Checks that the if DataTransfer de-asserted then no data transfer will occur on the snoop data channel for this transaction DataTransfer, CRRESP[0]

When DataTransfer is de-asserted and cdvalid is high then no data transfer should occur on the snoop data channel

When DataTransfer is de-asserted and cdvalid is high, if data transfer occur on the snoop data channel

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Reset

cdvalid_low_when_reset_is_active_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D2.3.3 Reset requirements

Monitor Check for CDVALID low when reset is active!

Checks if cdvalid is low when reset is active

When reset is high than cdvalid must not be asserted

When reset is high and cdvalid is asserted

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.

ERROR

ACE,ACE5

Signal Stability

cdvalid_interrupted_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check for CDVALID held steady until CDREADY is asserted!

Checks if cdvalid was interrupted before cdrready got asserted

When cdready is received and cdvalid to cdready delay is zero

When cdready is received and cdvalid to cdready delay is not zero

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cdvalid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check for X or Z on CDVALID!

Checks that CDVALID is not X or Z

When CDVALID is not X or Z

When CDVALID is X or Z

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.

ERROR

ACE,ACE5

WACK Signaling

signal_wack_after_handshake_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling

Monitor Checks that WACK signal must be asserted the cycle after the associated handshake or later!

Checks that WACK signal must be asserted the cycle after the associated handshake or later

When WACK signal must be asserted the cycle after the associated handshake or later

When WACK signal is asserted the cycle before the associated handshake or later

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.

ERROR

ACE,ACE5

WACK Signaling

signal_wack_single_cycle_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling

Monitor Checks that WACK is asserted for a single cycle!

Checks that WACK is asserted for a single cycle

When WACK is asserted for a single cycle

When WACK is seen, but found no associated transaction whose data is complete WACK should be asserted for a single cycle

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.

ERROR

ACE,ACE5

RACK Signaling

signal_rack_after_handshake_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling

Monitor Checks that RACK signal must be asserted the cycle after the associated handshake or later!

Checks that RACK signal must be asserted the cycle after the associated handshake or later

When RACK signal must be asserted the cycle after the associated handshake or later

When RACK signal is asserted the cycle before the associated handshake or later

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.

ERROR

ACE,ACE5

RACK Signaling

signal_rack_single_cycle_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling

Monitor Checks that RACK is asserted for a single cycle!

Checks that RACK is asserted for a single cycle

When RACK is not asserted for a single cycle

When RACK is seen, but found no associated transaction whose data is complete RACK should be asserted for a single cycle

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exokay_not_sent_until_successful_exclusive_store_rack_observed_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.3.1 Minimum PoS Exclusive Monitor

Monitor checks that, once a master receives successful exclusive store response EXOKAY from interconnect, then no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK

Checks that, once a master receives successful exclusive store response EXOKAY from interconnect, then no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK

When no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK

When any master provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_store_overlap_with_another_exclusive_sequence_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor check that a master must not permit an Exclusive Store transaction to be in progress at the same time as any transaction that registers that it is performing an Exclusive sequence

Checks that master does not permit an Exclusive Store transaction to be in progress at the same time as any transaction that registers that it is performing an Exclusive sequence

When any transaction is performing exclusive sequence than master does not permit an exclusive store transaction to be in progress at same time.

When any transaction is performing exclusive sequence and if master permit an exclusive store transaction to be in progress at same time.

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

ACE,ACE5

Trace Signals: Signal Stability

signal_stable_cdtrace_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CDTRACE is stable when CDVALID is high.

CDTRACE is stable when CDVALID is high.

CDTRACE is not stable when CDVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: trace_tag_enable is set to 1.

ERROR

ACE,ACE5

Signal Stability

signal_stable_cdlast_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that cdlast is stable when cdvalid is high

cdlast is stable when cdvalid is high

cdlast is not stable when cdvalid is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Signal Stability

signal_stable_cddata_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that CDDATA is stable when CDVALID is high

CDDATA is stable when CDVALID is high

CDDATA is not stable when CDVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5

Trace Signals: Signal Validity

signal_valid_cdtrace_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDTRACE is not X or Z when CDVALID is high.

CDTRACE is not X or Z when CDVALID is high.

CDTRACE is X or Z when CDVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: trace_tag_enable is set to 1
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cdvalid_cdready_delay is set to 0.

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cdlast_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that cdlast is not X or Z when cdvalid is high

cdlast is not X or Z when cdvalid is high

cdlast is X or Z when cdvalid is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: poison_enable is set to 1
svt_axi_port_configuration :: protocol_checks_enable is set to 1
cdvalid_cdready_delay is set to 0.

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cddata_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDDATA is not X or Z when CDVALID is high

CDDATA is not X or Z when CDVALID is high

CDDATA is X or Z when CDVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cdvalid_cdready_delay is set to 0.

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cdready_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDREADY is not X or Z when CDVALID is high

CDREADY is not X or Z when CDVALID is high

CDREADY is X or Z when CDVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5

Signal Stability

signal_stable_awunique_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal

Monitor check for signal stability when corresponding valid signal is high

Checks that AWUNIQUE is stable when AWVALID is high

AWUNIQUE is stable when AWVALID is high

AWUNIQUE is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.
svt_axi_port_configuration :: awunique_enable is set to 1.

ERROR

ACE,ACE5

Awnique Signal

signal_valid_awunique_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWUNIQUE is not X or Z when AWVALID is high

AWUNIQUE is not X or Z when AWVALID is high

AWUNIQUE is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.
svt_axi_port_configuration :: awunique_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_snoop_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[0] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[0] of DVM message type Virtual Instruction Cache Invalidate

When ACADDR[0] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b00 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0

When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b1 then
ACADDR[0] is 1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b1 then
ACADDR[0] is 1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b1 then
ACADDR[0] is 1'b1

When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b1

When ACADDR[0] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[5] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[5] of DVM message type Virtual Instruction Cache Invalidate

When ACADDR[5] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b00 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b0

When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b0

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 then
ACADDR[5] is 1'b0,1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 then
ACADDR[5] is 1'b0,1'b1

When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY
ACADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_4
ACADDR[5] is 1'b0 for other versions

When ACADDR[5] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[6] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[6] of DVM message type Virtual Instruction Cache Invalidate

When ACADDR[6] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b00 then
ACADDR[6] is 1'b0

When ACADDR[11:10] is 2'b00 & ACADDR[9:8] is 2'b11 then
ACADDR[6] is 1'b0

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 then
ACADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4
ACADDR[6] is 1'b0 for other dvm version

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 then
ACADDR[6] is 1'b1

When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 then
ACADDR[6] is 1'b0

When ACADDR[6] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[9:8] for DVM Message type Virtual Instruction Cache Invalidate!

Checks the valid values of ACADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate

When ACADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ACADDR[11:10] is 2'b00 then
ACADDR[9:8] is 2'b00,2'b11

When ACADDR[11:10] is 2'b10 then
ACADDR[9:8] is 2'b10,2'b11

When ACADDR[11:10] is 2'b11 then
ACADDR[9:8] is 2'b11

When ACADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_invalidate_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[11:10] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate

When ACADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate have following valid values:

When ACADDR[14:12] is 3'b011 then
ACADDR[11:10] is 2'b00,2'b10,2'b11

When ACADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_snoop_addr_specified_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[0] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ACADDR[0] of DVM message type Physical Instruction Cache Invalidate

When ACADDR[0] of DVM message type Physical Instruction Cache Invalidate have following valid values:

When ACADDR[9:8] is 2'b10 & ACADDR[6:5] is 2'b00 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[9:8] is 2'b10 & ACADDR[6:5] is 2'b11 then
ACADDR[0] is 1'b1

When ACADDR[9:8] is 2'b11 & ACADDR[6:5] is 2'b00 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[9:8] is 2'b11 & ACADDR[6:5] is 2'b11 then
ACADDR[0] is 1'b1

When ACADDR[0] of DVM message type Physical Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_physical_inst_cache_vid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[6:5] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ACADDR[6:5] of DVM message type Physical Instruction Cache Invalidate

When ACADDR[6:5] of DVM message type Physical Instruction Cache Invalidate have following valid values:

When ACADDR[9:8] is 2'b10 then
ACADDR[6:5] is 2'b00,2'b11

When ACADDR[9:8] is 2'b11 then
ACADDR[6:5] is 2'b00,2'b11

When ACADDR[6:5] of DVM message type Physical Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_physical_inst_cache_secure_nonsecure_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate

Monitor Check for the supported values of ACADDR[9:8] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ACADDR[9:8] of DVM message type Physical Instruction Cache Invalidate

When ACADDR[9:8] of DVM message type Physical Instruction Cache Invalidate have following valid values:

When ACADDR[14:12] is 3'b010 then
ACADDR[9:8] is 2'b10,2'b11

When ACADDR[9:8] of DVM message type Physical Instruction Cache Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Branch Predictor

snoop_dvmmessage_branch_predictor_invalidate_supported_message_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate

Monitor Check for the supported values of ACADDR[0] for DVM Message type Branch Predictor Invalidate!

Checks the valid values of ACADDR[0] of DVM message type Branch Predictor Invalidate

When ACADDR[0] of DVM message type Branch Predictor Invalidate have following valid values:

When ACADDR[14:12] is 3'b001 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[0] of DVM message type Branch Predictor Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_snoop_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[0] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[0] of DVM message type TLB Invalidate

When ACADDR[0] of DVM message type TLB Invalidate have following valid values:

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b1 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b1 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b01 & ACADDR[6] is 1'b1 & ACADDR[5] is 1'b0 then
ACADDR[0] is 1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b1 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then
ACADDR[0] is 1'b0,1'b1

When ACADDR[0] of DVM message type TLB Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[5] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[5] of DVM message type TLB Invalidate

When ACADDR[5] of DVM message type TLB Invalidate have following valid values:

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b0,1'b1

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b0

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b1 then
ACADDR[5] is 1'b0,1'b1

When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b11 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b1 for dvm version DVMV8_1_ONLY
ACADDR[5] is 1'b0,1'b1 for dvm version DVMV8_1 or DVMV8_1 or DVMV8_4 or DVMV9_2
ACADDR[5] is 1'b0 for other versions

When ACADDR[11:10] is 2'b10 & ACADDR[9:8] is 2'b01 & ACADDR[6] is 1'b1 then
ACADDR[5] is 1'b0,1'b1

When ACADDR[11:10] is 2'b11 & ACADDR[9:8] is 2'b10 & ACADDR[6] is 1'b0 then
ACADDR[5] is 1'b0,1'b1

ACADDR[5] of DVM message type TLB Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[6] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[6] of DVM message type TLB Invalidate

When ACADDR[6] of DVM message type TLB Invalidate have the following valid values:

When ACADDR[11:10] is 2'b10 and ACADDR[9:8] is 2'b10 then
ACADDR[6] is 1'b0,1'b1 for dvm version DVMV8_4 or DVMV9_2
ACADDR[6] is 2'b0 for other versions

When ACADDR[11:10] is 2'b10 and ACADDR[9:8] is 2'b11 then
ACADDR[6] is 1'b0,1'b1

When ACADDR[11:10] is 2'b11 and ACADDR[9:8] is 2'b11 then
ACADDR[6] is 1'b0

When ACADDR[11:10] is 2'b11 and ACADDR[9:8] is 2'b10 then
ACADDR[6] is 1'b0

When ACADDR[11:10] is 2'b10 and ACADDR[9:8] is 2'b01 then
ACADDR[6] is 1'b1

When ACADDR[6] of DVM message type TLB Invalidate not have the valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[9:8] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[9:8] of DVM message type TLB Invalidate

When ACADDR[9:8] of DVM message type TLB Invalidate have following valid values:

When ACADDR [11:10] is 2'b10 than
ACADDR[9:8] have value 2'b00,2'b01,2'b10,2'b11 for dvm_version DVMV9_2
ACADDR[9:8] have value 2'b01,2'b10,2'b11 for dvm_version DVMV8_4

When ACADDR [11:10] is 2'b11 than
ACADDR[9:8] have value 2'b00,2'b10,2'b11 for dvm_version DVMV9_2
ACADDR[9:8] have value 2'b10,2'b11 for dvm_version DVMV8_4
ACADDR[9:8] have value 2'b11 for other version

When ACADDR[9:8] of DVM message type TLB Invalidate not have valid values

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_hypervisor_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[11:10] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[11:10] of DVM message type TLB Invalidate

When ACADDR[11:10] of DVM message type TLBI have following valid value:

For dvm_version DVMV9_2 when ACADDR[11:10] is 2'b00,2'b01,2'b10,2'b11
For other version ACADDR[11:10] is 2'b01,2'b10,2'b11

When ACADDR[11:10] of DVM message type TLB Invalidate not have valid values

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_transaction :: coherent_xact_type is set to svt_axi_transaction :: DVMMESSAGE

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

dvmcomplete_acaddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that for a DVM Complete, ACADDR is defined to be all zeros!

Checks For a DVM Complete, ACADDR is defined to be all zeros

When ACADDR must be zero for DVM Complete

When ACADDR is not zero for DVM Complete

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM Operation

dvm_operation_dvm_sync_acsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ACSNOOP is 'b1111 for DVM Operation and DVM Sync!

Checks the value of ACSNOOP for the DVM SYNC

When the ACSNOOP value for DVM message must be 0b1111

When ACSNOOP value for DVM message is not 0b1111

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

dvm_complete_acsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ACSNOOP is 'b1110 for DVM Complete !

Checks the value of ACSNOOP for the DVM complete

When ACSNOOP for DVM complete must be 0b1110

When ACSNOOP for DVM complete is not 0b1110

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

dvm_complete_arsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ARSNOOP is 'b1110 for DVM Complete!

Checks for DVMCOMPLETE the valid value of ARSNOOP

When ARSNOOP for DVMCOMPLETE must be 0b1110

When ARSNOOP for DVMCOMPLETE not of 0b1110

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Transactions

snoop_transaction_order_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that all snoop transactions are ordered. The response, as given on the snoop response channel, must be in the same order that the transactions are presented on the snoop address channel!

Checks all snoop transactions are ordered

When the response, as given on the snoop response channel, must be in the same order that the transactions are presented on the snoop address channel

When the response, as given on the snoop response channel, is not in the same order that the transactions are presented on the snoop address channel

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Transactions

snoop_addr_snoop_resp_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor Check that the master must wait for both ACVALID and ACREADY to be asserted before asserting CRVALID!

Checks that ACVALID and ACREADY to be asserted before asserting CRVALID

When the master must wait for both ACVALID and ACREADY to be asserted before asserting CRVALID

When the master is not wait for both ACVALID and ACREADY to be asserted before asserting CRVALID

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address

acsnoop_reserved_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor Check that ACSNOOP does not have a reserved value!

Checks that ACSNOOP does not have reserved values

When ACSNOOP value is inside {0, 1, 2, 3, 7, 8, 9, 13, 14, 15}

When ACSNOOP value is not inside {0, 1, 2, 3, 7, 8, 9, 13, 14, 15}

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

snoop_chan_dvmcomplete_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Check that a snoop responseCRRESP of 5'b00010 is not given for DVMComplete Transaction !

Checks the valid snoop response of DVM Complete Transactions

When a snoop response(CRRESP) of 5'b00010 is not given for DVM Complete Transaction

When a snoop response(CRRESP) of 5'b00010 is given for DVM Complete Transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

snoop_chan_dvmsync_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Check that a snoop responseCRRESP of 5'b00010 is not given for DVMSync Transaction !

Checks the valid snoop response of DVM Message Transactions

When a snoop response(CRRESP) of 5'b00010 is not given for DVMSync Transaction

When a snoop response(CRRESP) of 5'b00010 is given for DVMSync Transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the arlen is valid for Cache Line Size Transactions!

Checks if the ARLEN is valid for Cache Line Size Transactions

When All cache line size transactions must have valid ARLEN

When All cache line size transactions not have have valid ARLEN

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the awlen is valid for Cache Line Size Transactions!

Checks if the AWLEN is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AWLEN

When All cache line size transactions not have have valid AWLEN

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arsize_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the arsize is valid for Cache Line Size Transactions!

Checks if the ARSIZE is valid for Cache Line Size Transactions

When All cache line size transactions must have valid ARSIZE

When All cache line size transactions not have have valid ARSIZE

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awsize_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the awsize is valid for Cache Line Size Transactions!

Checks if the AWSIZE is valid for Cache Line Size Transactions

When All cache line size transactions must have valid AWSIZE

When All cache line size transactions not have have valid AWSIZE

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Reset

acvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.1 Snoop request channel AC
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D2.3.3 Reset requirements

Monitor Check for ACVALID low when reset is active!

Checks if acvalid is low when reset is active

When reset is high than acvalid must not be asserted

When reset is high and acvalid is asserted

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: dvm_enable is set 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

Reset

crvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D2.3.3 Reset requirements

Monitor Check for CRVALID low when reset is active!

Checks if crvalid is low when reset is active

When reset is high than crvalid must not be asserted

When reset is high and crvalid is asserted

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: dvm_enable is set 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

crvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.9 Snoop channel dependencies

Monitor Check for CRVALID held steady until CRREADY is asserted!

Checks if crvalid was interrupted before crready got asserted

When crready is received and crvalid to crready delay is zero

When crready is received and crvalid to crready delay is not zero

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: dvm_enable is set 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

acvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.1 Snoop request channel AC
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.6.2 Snoop address channel signaling

Monitor Check for ACVALID held steady until ACREADY is asserted!

Checks if acvalid was interrupted before acready got asserted

When acvalid is asserted and arvalid to acready delay is zero

When acvalid is not observed and acvalid to acready delay is not equal to zero

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: dvm_enable is set 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.7 Snoop response channel signaling

Monitor Check for X or Z on CRVALID!

Checks that CRVALID is not X or Z

When CRVALID is not X or Z

When CRVALID is X or Z

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE and dvm_enable is set 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acvalid_check

Monitor Check for X or Z on ACVALID!

Checks that ACVALID is not X or Z

When ACVALID is not X or Z

When ACVALID is X or Z

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE and dvm_enable is set 1.

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_crtrace_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that CRTRACE is stable when CRVALID is high

CRTRACE is stable when CRVALID is high

CRTRACE is not stable when CRVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_port_configuration :: trace_tag_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_crresp_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that CRRESP is stable when CRVALID is high

CRRESP is stable when CRVALID is high

CRRESP is not stable when CRVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_acprot_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that ACPROT is stable when ARVALID is high

ACPROT is stable when ARVALID is high

ACPROT is not stable when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_acsnoop_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that ACSNOOP is stable when ARVALID is high

ACSNOOP is stable when ARVALID is high

ACSNOOP is not stable when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_acaddr_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that ACADDR is stable when ARVALID is high

ACADDR is stable when ARVALID is high

ACADDR is not stable when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crtrace_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRTRACE is not X or Z when CRVALID is high

CRTRACE is not X or Z when CRVALID is high

CRTRACE is X or Z when CRVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_port_configuration :: trace_tag_enable is set to 1
svt_axi_port_configuration :: protocol_checks_enable is set to 1
crvalid_crready_delay is set to 0.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crresp_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRRESP is not X or Z when CRVALID is high

CRRESP is not X or Z when CRVALID is high

CRRESP is X or Z when CRVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_port_configuration :: protocol_checks_enable is set to 1
crvalid_crready_delay is set to 0.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crready_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRREADY is not X or Z when CRVALID is high

CRREADY is not X or Z when CRVALID is high

CRREADY is X or Z when CRVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE or ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acprot_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACPROT is not X or Z when ARVALID is high

ACPROT is not X or Z when ARVALID is high

ACPROT is X or Z when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1
acvalid_to_acready_delay is set to 0.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acsnoop_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACSNOOP is not X or Z when ARVALID is high

ACSNOOP is not X or Z when ARVALID is high

ACSNOOP is X or Z when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1
acvalid_to_acready_delay is set to 0.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acaddr_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACADDR is not X or Z when ARVALID is high

ACADDR is not X or Z when ARVALID is high

ACADDR is X or Z when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1
acvalid_to_acready_delay is set to 0.

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acready_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACREADY is not X or Z when ARVALID is high

ACREADY is not X or Z when ARVALID is high

ACREADY is X or Z when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE and ACE_LITE
svt_axi_port_configuration :: dvm_enable is set to 1

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: VMID

signal_valid_arvmidext_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.4 Support for 16-bit VMID

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARVMIDEXT is not X or Z when ARVALID is high

ARVMIDEXT is not X or Z when ARVALID is high

ARVMIDEXT is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_system_configuration :: dvm_version is set to greater than equal to DVMV8_1
arvmidext_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE5_LiteDVM

DVM v8.4

signal_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that observed_araddr[2:0] must be zero for multipart DVM transactions for dvm version less than DVMv8_4

Checks that observed_acaddr[2:0] must be zero for dvm_version less than DVM_v8.4 for multipart DVM transactions.

observed_acaddr[2:0] is zero for multipart DVM transactions.

observed_acaddr[2:0] is non zero for multipart DVM transactions.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to less than DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_num_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[5:4] and observed_araddr[2:0] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[5:4] and observed_acaddr[2:0] (NUM bits) must be zero for multipart DVM transactions.

observed_acaddr[5:4] and observed_acaddr[2:0] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_acaddr[5:4] and observed_acaddr[2:0] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_scale_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[7:6] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[7:6] (SCALE) must be zero for multipart DVM transactions.

observed_acaddr[7:6] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_acaddr[7:6] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_ttl_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[9:8] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[9:8] (TTL) must be zero for multipart DVM transactions.

observed_acaddr[9:8] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_acaddr[9:8] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_tg_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[11:10] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[11:10] (TG) must be zero for multipart DVM transactions.

observed_acaddr[11:10] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_acaddr[11:10] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_num_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[5:4] and observed_araddr[2:0] (NUM bits) must be zero for multipart DVM transactions.

observed_araddr[5:4] and observed_araddr[2:0] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_araddr[5:4] and observed_araddr[2:0] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_scale_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[7:6] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[7:6] (SCALE) must be zero for multipart DVM transactions.

observed_araddr[7:6] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_araddr[7:6] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_ttl_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[9:8] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[9:8] (TTL) must be zero for multipart DVM transactions.

observed_araddr[9:8] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_araddr[9:8] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

ACE5_LiteDVM

DVM v8.4

valid_tg_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[11:10] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[11:10] (TG) must be zero for multipart DVM transactions.

observed_araddr[11:10] is zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

observed_araddr[11:10] is non zero for multipart Non TLB Invalidate by IPA or VA DVM transactions.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_system_configuration :: dvm_version_enum is set to greater than or equal to DVMv8_4
svt_axi_port_configuration :: dvm_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

AXI4,AXI5

Atomic Accesses

align_addr_atomicity_size_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A7.1 Single-copy atomicity size

Monitor Check that a transaction never has an atomicity guarantee greater than the alignment of its start address on ARADDR/AWADDR.

Checks that ARADDR/AWADDR should always be aligned to Atomicity Size

When transaction never has an atomicity size greater than the alignment of its start address on ARADDR/AWADDR

When transaction has an atomicity size greater than the alignment of its start address on ARADDR/AWADDR

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: atomicity_size is set to greater than -1

ERROR

AXI4,AXI5

Interface Requirements

excl_access_on_write_only_interface_check

Synopsys Defined

Monitor Check that write only interface does not support exclusive access!

Checks that WRITE_ONLY_INTERFACE does not support exclusive access

When write only interface support does not exclusive access

When write only interface support exclusive access

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_WRITE_ONLY and curr_write_addr_xact.atomic_type is set to svt_axi_transaction :: EXCLUSIVE.

ERROR

AXI4,AXI5

Interface Requirements

excl_access_on_read_only_interface_check

Synopsys Defined

Monitor Check that read only interface does not support exclusive access!

Checks that READ_ONLY_INTERFACE does not support exclusive access

When write only interface support does not exclusive access

When write only interface support exclusive access

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4.
svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_ONLY and curr_read_addr_xact.atomic_type is set to svt_axi_transaction :: EXCLUSIVE.

ERROR

AXI4,AXI5

Interface Requirements

write_xact_on_write_only_interface_check

Synopsys Defined

Monitor Check that write only interface supports only write Transactions!

Checks that WRITE_ONLY_INTERFACE supports only write transactions

When read transaction is not detected on WRITE ONLY interface

When read transaction detected on WRITE ONLY interface

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4.
svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_WRITE_ONLY.

ERROR

AXI4,AXI5

Interface Requirements

read_xact_on_read_only_interface_check

Synopsys Defined

Monitor Check that read only interface supports only read Transactions!

Checks that READ_ONLY_INTERFACE supports only read transactions

When write transaction is not detected on READ ONLY interface

When write transaction detected on READ ONLY interface

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4.
svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_ONLY.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exokay_resp_observed_only_for_exclusive_transactions_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2 Exclusive accesses

Monitor checks that the EXOKAY response is observed only for permitted exclusive access transactions.For AXI3/AXI4 interfaces these are transactions with atomic_type is equal to EXCLUSIVE,For ACE_LITE interface these are READNOSNOOP, WRITENOSNOOP transaction or READONCE, WRITEUNIQUE if shareable_exclusive_access_from_acelite_ports_enable is set to '1'. For ACE interface these are READSHARED, READCLEAN and CLEANUNIQUE transaction !

checks that the EXOKAY response is observed only for permitted exclusive access transactions

When EXOKAY response is observed only for permitted exclusive access transactions

When EXOKAY response is not observed only for permitted exclusive access transactions

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: exclusive_access_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Interface Requirements

awburst_awlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that AWLEN and AWBURST are valid for AXI Transactions!

Checks if the AWLEN for INCR is valid for AXI Transactions

When the AWLEN can be any value from 1-16 for an INCR burst and AWLEN must be 2,4,8 or 16 for a WRAP burst

When the AWLEN does not take value from 1-16 for an INCR burst and AWLEN must be 2,4,8 or 16 for a WRAP burst

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
transmitted_channel is set to svt_axi_transaction :: WRITE

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Interface Requirements

rlast_asserted_for_last_read_data_beat

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that RLAST is HIGH only for the last beat of READ burst !

Monitor Check that RLAST is HIGH only for the last beat of READ burst

When the last beat of read data is transfer than RLAST must be asserted

When the last beat of read data is transfer and RLAST is not asserted

Passive Slave, Active/Passive Master

This check is applicable when svt_axi_port_configuration :: rlast_enable is set to 1

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Interface Requirements

wlast_asserted_for_last_write_data_beat

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.3.2 Write data channel W

Monitor Check that WLAST is asserted for last beat of write data!

Checks that WLAST is asserted for the last beat of write data
Can be done reliably only if data_before_addr is not set, since if data_before_addr, observed_wlast could come at any point before the address comes

When the last beat of write data is transfered than wlast must be asserted

When the last beat of write data is transfered and wlast not asserted

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_transaction :: data_before_addr is not set and cfg.wlast_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_prot_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that protection type is generated same for exclusive accesss READ and WRITE transactions

Checks that protection type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

When the exclusive access transaction protection type is same as normal transaction protection type

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_cache_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that cache type is generated same for exclusive accesss READ and WRITE transactions

Checks that cache type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

When the exclusive access transaction cache type is same as normal transaction cache type

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_burst_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst type is generated same for exclusive accesss READ and WRITE transactions

Checks that burst type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

When the exclusive access transaction burst type is same as normal transaction burst type

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_burst_size_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst size is generated same for exclusive accesss READ and WRITE transactions

Checks that burst size is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

When the exclusive access transaction burst size is same as normal transaction burst size

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_burst_length_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst length is generated same for exclusive accesss READ and WRITE transactions

Checks that burst length is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

When the exclusive access transaction burst length is same as normal transaction burst length

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_addr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that address is generated same for exclusive accesss READ and WRITE transactions

Checks that address is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

When the exclusive access transaction address is same as normal transaction

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_write_addr_aligned_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access start address is aligned to the total number of bytes of the transaction

Checks that address is aligned for exclusive write transaction

When the start address is aligned to the total number of bytes in the exclusive write transaction

When the start address is not aligned to the total number of bytes in the transaction which is not valid for exclusive write transactions

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_awcache_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access being monitored by a slave must not have an ARCACHE[3:0] or AWCACHE[3:0] value that indicates that the transaction is cacheable

Checks that AWCACHE is valid for exclusive read transaction

When AWCACHE[3:0] indicates that the transaction is cacheable for exclusive read transactions

When AWCACHE[3:0] indicates that the transaction is not cacheable for exclusive read transactions

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_awlen_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

The burst length for an exclusive access must not exceed 16 transfers.

Checks that AWLEN is valid for exclusive store transaction

The burst length for an exclusive store transaction does not exceed 16 transfers.

The burst length for an exclusive store transaction exceeds 16 transfers.

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_awlen_awsize_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst size and burst_length combination is valid for Exclusive access. The number of bytes that can be transferred in an exclusive access burst must be power of 2

Checks that AWLEN and AWSIZE are valid for exclusive store transaction

When the number of bytes that can be transferred in an exclusive access burst must be power of 2
That is 1,2,4,8,16,32,64,128 bytes

When the number of bytes that can be transferred in an exclusive access burst is not power of 2

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_read_addr_aligned_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access start address is aligned to the total number of bytes of the transaction

Checks that address is aligned for exclusive read transaction

When the start address is aligned to the total number of bytes in the exclusive read transaction

When the start address is not aligned to the total number of bytes in the transaction which is not valid for exclusive read transactions

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: exclusive_access_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_arcache_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access being monitored by a slave must not have an ARCACHE[3:0] or AWCACHE[3:0] value that indicates that the transaction is cacheable

Checks that ARCACHE is valid for exclusive read transaction

When ARCACHE[3:0] indicates that the transaction is cacheable for exclusive read transactions

When ARCACHE[3:0] indicates that the transaction is not cacheable for exclusive read transactions

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_arlen_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

The burst length for an exclusive access must not exceed 16 transfers.

Checks that ARLEN is valid for exclusive read transaction

The burst length for an exclusive read transaction does not exceed 16 transfers

The burst length for an exclusive read transaction exceeds 16 transfers

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_arlen_arsize_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst size and burst_length combination is valid for Exclusive access. The number of bytes that can be transferred in an exclusive access burst must be power of 2

Checks that ARLEN and ARSIZE are valid for exclusive read transaction

When the number of bytes that can be transferred in an exclusive access burst must be power of 2
That is 1,2,4,8,16,32,64,128 bytes

When the number of bytes that can be transferred in an exclusive access burst is not power of 2

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: exclusive_access_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_wlast_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that WLAST is stable when WVALID is high

WLAST is stable when WVALID is high

WLAST is not stable when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.
svt_axi_port_configuration :: wlast_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_wlast_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WLAST is not X or Z when WVALID is high

WLAST is not X or Z when WVALID is high

WLAST is X or Z when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: wlast_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awcache_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCACHE is stable when AWVALID is high

AWCACHE is stable when AWVALID is high

AWCACHE is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awlock_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWLOCK is stable when AWVALID is high

AWLOCK is stable when AWVALID is high

AWLOCK is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awburst_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWBURST is stable when AWVALID is high

AWBURST is stable when AWVALID is high

AWBURST is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awlen_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWLEN is stable when AWVALID is high

AWLEN is stable when AWVALID is high

AWLEN is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awcache_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWCACHE is not X or Z when AWVALID is high

AWCACHE is not X or Z when AWVALID is high

AWCACHE is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(awcache_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awlock_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWLOCK is not X or Z when AWVALID is high

AWLOCK is not X or Z when AWVALID is high

AWLOCK is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(awlock_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awburst_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWBURST is not X or Z when AWVALID is high

AWBURST is not X or Z when AWVALID is high

AWBURST is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(awburst_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awlen_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWLEN is not X or Z when AWVALID is high

AWLEN is not X or Z when AWVALID is high

AWLEN is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(awlen_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_rlast_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RLAST is stable when RVALID is high

RLAST is stable when RVALID is high

RLAST is not stable when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_rlast_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RLAST is not X or Z when RVALID is high

RLAST is not X or Z when RVALID is high

RLAST is X or Z when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: rlast_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
rvalid_rready_delay(Delay from RVALID assertion to RREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arcache_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARCACHE is stable when ARVALID is high

ARCACHE is stable when ARVALID is high

ARCACHE is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arlock_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARLOCK is stable when ARVALID is high

ARLOCK is stable when ARVALID is high

ARLOCK is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arburst_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARBURST is stable when ARVALID is high

ARBURST is stable when ARVALID is high

ARBURST is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arlen_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARLEN is stable when ARVALID is high

ARLEN is stable when ARVALID is high

ARLEN is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arcache_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARCACHE is not X or Z when ARVALID is high

ARCACHE is not X or Z when ARVALID is high

ARCACHE is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The marco `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(arcache_enable) is defined.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arlock_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARLOCK is not X or Z when ARVALID is high

ARLOCK is not X or Z when ARVALID is high

ARLOCK is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The marco `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(arlock_enable) is defined.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arburst_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARBURST is not X or Z when ARVALID is high

ARBURST is not X or Z when ARVALID is high

ARBURST is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The marco `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(arburst_enable) is defined.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arlen_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARLEN is not X or Z when ARVALID is high

ARLEN is not X or Z when ARVALID is high

ARLEN is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
The marco `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(arlen_enable) is defined.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals

trace_tag_validity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor Check that if valid loopback trace_tag is generated for data and response channel when

Trace tag value on data channel or resposne channel should be valid as per the trace tag value on the address channel.

when trace_tag in address channel is asserted, it is also asserted in the associated response/data channel.

when trace_tag in address channel is asserted, but not asserted in the associated response/data channel.

Active/Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: trace_tag_enable is set to 1 and svt_axi_port_configuration :: loopback_trace_tag_enable are set to 0.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals

loopback_trace_tag_validity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor Check that if trace_tag value on data channel or resposne channel directly mapped to the associated request when svt_axi_port_configuration::loopback_trace_tag_enable is enabled

Trace_tag value on data channel or resposne channel should be directly mapped to the associated request.

when trace_tag value on data channel or resposne channel is matching with the trace tag value in the address channel.

when trace_tag value on data channel or resposne channel is not matching with the trace tag value in the address channel.

Active/Passive Slave, Active/Passive Master

This check is applicable only when both svt_axi_port_configuration :: trace_tag_enable and svt_axi_port_configuration :: loopback_trace_tag_enable are set to 1 .
This check is not supported on snoop channels.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_btrace_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that BTRACE is stable when BVALID is high.

BTRACE is stable when BVALID is high.

BTRACE is not stable when BVALID is high.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_btrace_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BTRACE is not X or Z when BVALID is high.

BTRACE is not X or Z when BVALID is high.

BTRACE is X or Z when BVALID is high.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
bvalid_bready_delay(Delay from BVALID assertion to BREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Stability

signal_stable_wpoison_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for signal stability when corresponding valid signal is high

Checks that WPOISON is stable when WVALID is high.

WPOISON is stable when WVALID is high.

WPOISON is not stable when WVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: poison_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_Lite or AXI_ACE or ACE_Lite.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_wtrace_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WTRACE is stable when WVALID is high.

WTRACE is stable when WVALID is high.

WTRACE is not stable when WVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_wtrace_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WTRACE is not X or Z when WVALID is high.

WTRACE is not X or Z when WVALID is high.

WTRACE is X or Z when WVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Validity

signal_valid_wpoison_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WPOISON is not X or Z when WVALID is high.

WPOISON is not X or Z when WVALID is high.

WPOISON is X or Z when WVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: poison_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_Lite or AXI_ACE or ACE_Lite.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_awtrace_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWTRACE is stable when AWVALID is high.

AWTRACE is stable when AWVALID is high.

AWTRACE is not stable when AWVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_awtrace_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWTRACE is not X or Z when AWVALID is high.

AWTRACE is not X or Z when AWVALID is high.

AWTRACE is X or Z when AWVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Stability

signal_stable_rpoison_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for signal stability when corresponding valid signal is high

Checks that RPOISON is stable when RVALID is high.

RPOISON is stable when RVALID is high.

RPOISON is not stable when RVALID is high.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: poison_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_Lite or AXI_ACE or ACE_Lite.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_rtrace_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RTRACE is stable when RVALID is high.

RTRACE is stable when RVALID is high.

RTRACE is not stable when RVALID is high.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_rtrace_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RTRACE is not X or Z when RVALID is high.

RTRACE is not X or Z when RVALID is high.

RTRACE is X or Z when RVALID is high.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
rvalid_rready_delay(Delay from RVALID assertion to RREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Validity

signal_valid_rpoison_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RPOISON is not X or Z when RVALID is high.

RPOISON is not X or Z when RVALID is high.

RPOISON is X or Z when RVALID is high.

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: poison_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_Lite or AXI_ACE or ACE_Lite.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
rvalid_rready_delay(Delay from RVALID assertion to RREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_artrace_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARTRACE is stable when ARVALID is high.

ARTRACE is stable when ARVALID is high.

ARTRACE is not stable when ARVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_artrace_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARTRACE is not X or Z when ARVALID is high.

ARTRACE is not X or Z when ARVALID is high.

ARTRACE is X or Z when ARVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined.
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0.
svt_axi_port_configuration :: trace_tag_enable is set to 1.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI4_LITE or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

writeuniquefullstash_wstrb_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that writeuniquefullstash transactions are required to have every write data strobe asserted, that is, sparse write data strobes are not permitted

Monitor check that all byte strobes are asserted for a writeuniquefullstash transaction

When all byte strobes are asserted for a writeuniquefullstash transaction

When all byte strobes are not asserted for a writeuniquefullstash transaction

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awlock_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section E9.7.2 Stash transaction signaling

Monitor Check that AWLOCK is valid for writeuniqueptlstash Transactions!

Checks if the AWLOCK is valid for writeuniqueptlstash Transactions

When AWLOCK is valid for writeuniqueptlstash Transactions

When AWLOCK is not valid for writeuniqueptlstash Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awcache_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that AWCACHE is valid for writeuniqueptlstash Transactions!

Checks if the AWCACHE is valid for writeuniqueptlstash Transactions

When AWCACHE is valid for writeuniqueptlstash Transactions

When AWCACHE is not valid for writeuniqueptlstash Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that AWBURST is valid for writeuniqueptlstash Transactions!

Checks if the AWBURST is valid for writeuniqueptlstash Transactions

When writeuniqueptlstash transactions must have valid burst_type

When writeuniqueptlstash transactions not have valid burst_type

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awdomain_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that AWDOMAIN is valid for WriteUniqueptlstash Transactions!

Checks if the AWDOMAIN is valid for WriteUniquePtlstash Transactions

When AWDOMAIN is valid for WriteUniquePtlstash Transactions

When AWDOMAIN is not valid for WriteUniquePtlstash Transactions

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE

ERROR

ACE5

Poison: Signal Stability

signal_stable_cdpoison_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.1 Poison

Monitor check for signal stability when corresponding valid signal is high

Checks that CDPOISON is stable when CDVALID is high.

CDPOISON is stable when CDVALID is high.

CDPOISON is not stable when CDVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

The macro SVT_ACE5_ENABLE is defined
svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: poison_enable is set to 1
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE

ERROR

ACE5

Poison: Signal Validity

signal_valid_cdpoison_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.1 Poison

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDPOISON is not X or Z when CDVALID is high.

CDPOISON is not X or Z when CDVALID is high.

CDPOISON is X or Z when CDVALID is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: ace_version is set to svt_axi_port_configuration :: ACE_VERSION_2_0
svt_axi_port_configuration :: poison_enable is set to 1
svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_type is set svt_axi_port_configuration :: AXI_ACE
cdvalid_cdready_delay is set to 0.

ERROR

ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_awsnoop_when_awvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWSNOOP is not X or Z when AWVALID is high

AWSNOOP is not X or Z when AWVALID is high

AWSNOOP is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE or AXI5.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Validity

signal_valid_awdomain_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWDOMAIN is not X or Z when AWVALID is high

AWDOMAIN is not X or Z when AWVALID is high

AWDOMAIN is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE or AXI5.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_wuser_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that WUSER is stable when WVALID is high

WUSER is stable when WVALID is high

WUSER is not stable when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: wuser_enable is set to 1.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_wuser_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WUSER is not X or Z when WVALID is high

WUSER is not X or Z when WVALID is high

WUSER is X or Z when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: wuser_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_awuser_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWUSER is stable when AWVALID is high

AWUSER is stable when AWVALID is high

AWUSER is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: awuser_enable is set to 1.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_buser_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that BUSER is stable when BVALID is high

BUSER is stable when BVALID is high

BUSER is not stable when BVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: buser_enable is set to 1.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_buser_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BUSER is not X or Z when BVALID is high

BUSER is not X or Z when BVALID is high

BUSER is X or Z when BVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: buser_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
bvalid_bready_delay(Delay from BVALID assertion to BREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_awuser_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWUSER is not X or Z when AWVALID is high

AWUSER is not X or Z when AWVALID is high

AWUSER is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: awuser_enable is set to 1.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_ruser_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that RUSER is stable when RVALID is high

RUSER is stable when RVALID is high

RUSER is not stable when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: ruser_enable is set to 1.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_ruser_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RUSER is not X or Z when RVALID is high

RUSER is not X or Z when RVALID is high

RUSER is X or Z when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: ruser_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
rvalid_rready_delay(Delay from RVALID assertion to RREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_aruser_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARUSER is stable when ARVALID is high

ARUSER is stable when ARVALID is high

ARUSER is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: aruser_enable is set to 1.

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_aruser_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARUSER is not X or Z when ARVALID is high

ARUSER is not X or Z when ARVALID is high

ARUSER is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: aruser_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Stability

signal_stable_awregion_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWREGION is stable when AWVALID is high

AWREGION is stable when AWVALID is high

AWREGION is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4.
svt_axi_port_configuration :: awregion_enable is set to 1.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Stability

signal_stable_awqos_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWQOS is stable when AWVALID is high

AWQOS is stable when AWVALID is high

AWQOS is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4.
svt_axi_port_configuration :: awqos_enable is set to 1.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Validity

signal_valid_awregion_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWREGION is not X or Z when AWVALID is high

AWREGION is not X or Z when AWVALID is high

AWREGION is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: awregion_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Validity

signal_valid_awqos_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWQOS is not X or Z when AWVALID is high

AWQOS is not X or Z when AWVALID is high

AWQOS is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or AXI_ACE or ACE_LITE.
svt_axi_port_configuration :: awqos_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Stability

signal_stable_arregion_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARREGION is stable when ARVALID is high

ARREGION is stable when ARVALID is high

ARREGION is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE or AXI4.
svt_axi_port_configuration :: arregion_enable is set to 1.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Stability

signal_stable_arqos_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARQOS is stable when ARVALID is high

ARQOS is stable when ARVALID is high

ARQOS is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI_ACE or ACE_LITE or AXI4.
svt_axi_port_configuration :: arqos_enable is set to 1.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Validity

signal_valid_arregion_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARREGION is not X or Z when ARVALID is high

ARREGION is not X or Z when ARVALID is high

ARREGION is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: arregion_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Validity

signal_valid_arqos_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARQOS is not X or Z when ARVALID is high

ARQOS is not X or Z when ARVALID is high

ARQOS is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4 or svt_axi_port_configuration :: AXI_ACE or svt_axi_port_configuration :: ACE_LITE.
svt_axi_port_configuration :: arqos_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Interface Requirements

write_resp_follows_last_write_xfer_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that write response must always follow last write data transfer!

When a write response is sampled, checks that there is a transaction with corresponding ID whose data phase is complete

When write transfer must follow the last write transfer in a write transaction

When write transfer not follow the last write transfer in a write transaction

Passive Slave, Active/Passive Master

This check is applicable only svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

AXI3 Onwards

Interface Requirements

read_data_follows_addr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that read data must always follow address to which the data relates!

Checks that sample read data has associated address

When the read data must follow the read address of the data

When the read data not follow the read address of the data

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1 and dynamic_reset_flag is set to 0.

ERROR

AXI3 Onwards

Interface Requirements

write_resp_after_write_addr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that a slave must not transmit the write response before the corresponding address is accepted!

Checks if A slave must not give a write response before the write address

When bresp is asserted after the awaddr is being asserted

When bresp is asserted before the awaddr is asserted

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_transaction :: addr_status is set to svt_sequence_item :: ACCEPT

ERROR

AXI3 Onwards

Interface Requirements

write_resp_after_last_wdata_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that a slave must only give a write response after the last write data item is transferred !

Checks if the slave must only give a write response after the last write data item is transferred

When wlast asserted at last write data transfer than only the bresp is assert

When wlast asserted at last write data transfer and the bresp is not asserted

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_transaction.data_status is set to svt_sequence_item :: ACCEPT

ERROR

AXI3 Onwards

Interface Requirements

wdata_awlen_match_for_corresponding_awaddr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that the number of write data items matches AWLEN for the corresponding address!

Checks if the number of write data items matches AWLEN for the corresponding address

When the number of write data beats genearted matches the corrsponding AWLEN

When the number of write data beats genearted is not matches the corrsponding AWLEN

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_transaction :: data_before_addr and xact.data_status is set to svt_sequence_item :: ACCEPT

ERROR

AXI3 Onwards

Transaction Attributes

arvalid_arcache_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.2 Memory Attributes

Monitor Check that ARCACHE[3:2] is 2'b00 when ARVALID is HIGH and ARCACHE[1] is LOW !

Checks if the value of arcache[3:2]=2'b00 when arvalid is high and arcache[1] is also low

When the arvalid is asserted and arcache[1] is low than the value of arcache[3:2] is equal to 2'b00

When the arvalid is asserted and arcache[1] is not low than the value of arcache[3:2] is not equal to 2'b00

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

AXI3 Onwards

Interface Requirements

arburst_reserved_val_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that a value of 2'b11 on ARBURST is not permitted when ARVALID is HIGH !

Checks if the value of arburst=2'b11 when arvalid is high

When the arvalid is asserted and the arburst should not take reserved value 2'b11

When the arvalid is asserted and the arburst is taking reserved value 2'b11

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

AXI3 Onwards

Interface Requirements

arsize_data_width_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that a Read transfer does not exceed the width of the data interface!

Checks if size of read transfer exceeds the width of the data bus

When the burst size is not greater than the size of data width

When the burst size is greater than the size of data width

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
transmitted_channel is set to svt_axi_transaction :: READ

ERROR

AXI3 Onwards

Interface Requirements

arlen_wrap_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Read Transaction with burst type WRAP has a valid burst length!

Checks if read burst of WRAP type has a valid length

When burst length for read burst of WRAP type must be inside of 2,4,8,16

When burst length for read burst of WRAP type is not inside of 2,4,8,16

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
transmitted_channel is set to svt_axi_transaction :: READ

ERROR

AXI3 Onwards

Interface Requirements

araddr_wrap_aligned_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Read Transaction with burst type WRAP has an aligned address!

Checks if read burst of WRAP type has an aligned address

When start address is aligned for read burst of WRAP type

When start address is not aligned for read burst of WRAP type

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
transmitted_channel is set to svt_axi_transaction :: READ

ERROR

AXI3 Onwards

Interface Requirements

araddr_4k_boundary_cross_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.2 Length attribute

Monitor Check that a Read burst cannot cross a 4K boundary!

Checks if read burst cross a 4KB boundary

When read burst must not cross the 4KB boundary

When read burst is cross the 4KB boundary

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
transmitted_channel is set to svt_axi_transaction :: READ

ERROR

AXI3 Onwards

Transaction Attributes

awvalid_awcache_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.2 Memory Attributes

Monitor Check that AWCACHE[3:2] is 2'b00 when AWVALID is HIGH and AWCACHE[1] is LOW !

Checks if the value of awcache[3:2]=2'b00 when awvalid is high and awcache[1] is also low

When the awvalid is asserted and awcache[1] is low than the value of awcache[3:2] is equal to 2'b00

When the awvalid is asserted and awcache[1] is not low than the value of awcache[3:2] is not equal to 2'b00

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Interface Requirements

awburst_reserved_val_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that a value of 2'b11 on AWBURST is not permitted when AWVALID is HIGH !

Checks if the value of awburst=2'b11 when awvalid is high

When the awvalid is asserted and the awburst should not take reserved value 2'b11

When the awvalid is asserted and the awburst is taking reserved value 2'b11

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Interface Requirements

awsize_data_width_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that size of a transfer does not exceed the width of the data interface!

Checks if size of write transfer exceeds the width of the data bus

When the burst size is not greater than the size of data width

When the burst size is greater than the size of data width

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
transmitted_channel is set to svt_axi_transaction :: WRITE.

ERROR

AXI3 Onwards

Interface Requirements

valid_write_strobe_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.2.1 Write strobes

Monitor Check that valid Write Strobes are driven for each data beat!

WSTRB must not be asserted for invalid byte lanes

WSTRB is de-asserted for invalid byte lanes

WSTRB is asserted for invalid byte lanes

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: wysiwyg_enable is set to 0.
svt_axi_port_configuration :: wysiwyg_enable is set to 1 along with.
svt_axi_port_configuration :: ignore_wstrb_check_for_wysiwyg_format is set to 0.

ERROR

AXI3 Onwards

Interface Requirements

awlen_wrap_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Write Transaction with burst type WRAP has a valid burst length!

Checks if write burst of WRAP type has a valid length

When burst length for write burst of WRAP type must be inside of 2,4,8,16

When burst length for write burst of WRAP type is not inside of 2,4,8,16

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
transmitted_channel is set to svt_axi_transaction :: WRITE.

ERROR

AXI3 Onwards

Interface Requirements

awaddr_wrap_aligned_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Write Transaction with burst type WRAP has an aligned address!

Checks if write burst of WRAP type has an aligned address

When start address is aligned for write burst of WRAP type

When start address is not aligned for write burst of WRAP type

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
transmitted_channel is set to svt_axi_transaction :: WRITE.

ERROR

AXI3 Onwards

Interface Requirements

awaddr_4k_boundary_cross_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.2 Length attribute

Monitor Check that a write burst cannot cross a 4K boundary!

Checks if write burst cross a 4KB boundary

When write burst must not cross the 4KB boundary

When write burst cross 4KB boundary

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
transmitted_channel is set to svt_axi_transaction :: WRITE.

ERROR

AXI3 Onwards

Reset

bvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for BVALID low when reset is active!

Checks if bvalid is low when reset is active

When reset is high than bvalid must not be asserted

When reset is high and bvalid is asserted

Passive Slave, Active/Passive Master

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

wvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for WVALID low when reset is active!

Checks if wvalid is low when reset is active

When reset is high than wvalid must not be asserted

When reset is high and wvalid is asserted

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

awvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for AWVALID low when reset is active!

Checks if awvalid is low when reset is active

When reset is high than awvalid must not be asserted

When reset is high and awvalid is asserted

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

rvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for RVALID low when reset is active!

Checks if rvalid is low when reset is active

When reset is high than rvalid must not be asserted

When reset is high and rvalid is asserted

Passive Slave, Active/Passive Master

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

arvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for ARVALID low when reset is active!

Checks if arvalid is low when reset is active

When reset is high than arvalid must not be asserted

When reset is high and arvalid is asserted

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Outstanding

max_num_outstanding_xacts_check

Synopsys Defined

Checks that AXI master and AXI slave are not exceeding the user configured maximum number of outstanding transactions

Checks that AXI master and AXI slave are not exceeding the user configured maximum number of outstanding transactions (num_outstanding_xact) If num_outstanding_xact = -1 then num_outstanding_xact will not be considered, instead num_read_outstanding_xact and num_write_outstanding_xact will be considered for read and write transactions respectively. .

When the total number of outstanding transactions is not greater than the user configured num_oustanding_xact

When the total number of outstanding transactions is greater than the user configured num_oustanding_xact

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: max_num_outstanding_xacts_check_enable is set to 1

ERROR

AXI3 Onwards

Signal Stability

bvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for BVALID held steady until BREADY is asserted!

Checks if bvalid was interrupted before bready got asserted

When bready is asserted and bvalid to bready delay is zero

When bvalid is not observed and bvalid to bready delay is not equal to zero

Passive Slave, Active/Passive Master

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

wvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for WVALID held steady until WREADY is asserted!

Checks if wvalid was interrupted before wready got asserted

When wready is asserted and wvalid to wready delay is zero

When wvalid is not observed and wvalid to wready delay is not equal to zero

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

awvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for AWVALID held steady until AWREADY is asserted!

Checks if awvalid was interrupted before awready got asserted

When awready is asserted and awvalid to awready delay is zero

When awvalid is not observed and awvalid to awready delay is not equal to zero

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

rvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for RVALID held steady until RREADY is asserted!

Checks if rvalid was interrupted before rready got asserted

When rready is asserted and rvalid to rready delay is zero

When rvalid is not observed and rvalid to rready delay is not equal to zero

Passive Slave, Active/Passive Master

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

arvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for ARVALID held steady until ARREADY is asserted!

Checks if arvalid was interrupted before arready got asserted

When arready is asserted and arvalid to arready delay is zero

When arvalid is not observed and arvalid to arready delay is not equal to zero

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_bready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on BREADY During Reset!

Checks that BREADY is not X or Z During Reset

BREADY is not X or Z During Reset

BREADY is X or Z During Reset

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_READ_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_wready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on WREADY During Reset!

Checks that WREADY is not X or Z During Reset

WREADY is not X or Z During Reset

WREADY is X or Z During Reset

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_READ_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_awready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on AWREADY During Reset!

Checks that AWREADY is not X or Z During Reset

AWREADY is not X or Z During Reset

AWREADY is X or Z During Reset

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_READ_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_rready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on RREADY During Reset!

Checks that RREADY is not X or Z During Reset

RREADY is not X or Z During Reset

RREADY is X or Z During Reset

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_WRITE_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_arready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on ARREADY During Reset!

Checks that ARREADY is not X or Z During Reset

ARREADY is not X or Z During Reset

ARREADY is X or Z During Reset

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_WRITE_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor Check for X or Z on BREADY!

BREADY should not be X/Z.

When BREADY is non X/Z.

When BREADY is X/Z.

Passive Master, Active/Passive Slave

This check is applicable only When:

svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_WRITE or AXI_WRITE_ONLY.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor Check for X or Z on WREADY!

WREADY should not be X/Z.

When WREADY is non X/Z.

When WREADY is X/Z.

Passive Slave, Active/Passive Master

This check is applicable only When:

svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_WRITE or AXI_WRITE_ONLY.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor Check for X or Z on AWREADY!

AWREADY should not be X/Z.

When AWREADY is non X/Z.

When AWREADY is X/Z.

Passive Slave, Active/Passive Master

This check is applicable only When:

svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_WRITE or AXI_WRITE_ONLY.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor Check for X or Z on RREADY!

RREADY should not be X/Z.

When RREADY is non X/Z.

When RREADY is X/Z.

Passive Master, Active/Passive Slave

This check is applicable only When:

svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_WRITE or AXI_READ_ONLY.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor Check for X or Z on ARREADY!

ARREADY should not be X/Z.

When ARREADY is non X/Z.

When ARREADY is X/Z.

Passive Slave, Active/Passive Master

This check is applicable only When:

svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_WRITE or AXI_READ_ONLY.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_ready_signal_X_Z_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_aresetn_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on ARESETn!

ARESETn should not be X/Z.

When ARESETn is non X/Z.

When ARESETn is X/Z.

Active/Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: per_clock_cycle_aresetn_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_bvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on BVALID During Reset!

Checks that BVALID is not X or Z During Reset

BVALID is not X or Z During Reset

BVALID is X or Z During Reset

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_READ_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_wvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on WVALID During Reset!

Checks that WVALID is not X or Z During Reset

WVALID is not X or Z During Reset

WVALID is X or Z During Reset

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_READ_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_awvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on AWVALID During Reset!

Checks that AWVALID is not X or Z During Reset

AWVALID is not X or Z During Reset

AWVALID is X or Z During Reset

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_READ_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_rvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on RVALID During Reset!

Checks that RVALID is not X or Z During Reset

RVALID is not X or Z During Reset

RVALID is X or Z During Reset

Passive Slave, Active/Passive Master

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_WRITE_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Reset

signal_valid_arvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on ARVALID During Reset!

Checks that ARVALID is not X or Z During Reset

ARVALID is not X or Z During Reset

ARVALID is X or Z During Reset

Passive Master, Active/Passive Slave

This check is applicable When:

svt_axi_port_configuration :: axi_interface_category is not set to svt_axi_port_configuration :: AXI_WRITE_ONLY.
svt_axi_port_configuration :: signal_valid_during_reset_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor Check for X or Z on BVALID!

BVALID should not be X/Z.

When BVALID is non X/Z.

When BVALID is X/Z.

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1
svt_axi_port_configuration :: axi_interface_category is set to svt_axi_port_configuration :: AXI_READ_WRITE or AXI_WRITE_ONLY.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor Check for X or Z on WVALID!

WVALID should not be X/Z.

When WVALID is non X/Z.

When WVALID is X/Z.

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor Check for X or Z on AWVALID!

AWVALID should not be X/Z.

When AWVALID is non X/Z.

When AWVALID is X/Z.

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor Check for X or Z on RVALID!

RVALID should not be X/Z.

When RVALID is non X/Z.

When RVALID is X/Z.

Passive Slave, Active/Passive Master

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor Check for X or Z on ARVALID!

ARVALID should not be X/Z.

When ARVALID is non X/Z.

When ARVALID is X/Z.

Passive Master, Active/Passive Slave

This check is applicable when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_bresp_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for signal stability when corresponding valid signal is high

Checks that BRESP is stable when BVALID is high

BRESP is stable when BVALID is high

BRESP is not stable when BVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_bid_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for signal stability when corresponding valid signal is high

Checks that BID is stable when BVALID is high

BID is stable when BVALID is high

BID is not stable when BVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bready_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BREADY is not X or Z when BVALID is high

BREADY is not X or Z when BVALID is high

BREADY is X or Z when BVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bresp_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BRESP is not X or Z when BVALID is high

BRESP is not X or Z when BVALID is high

BRESP is X or Z when BVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(bresp_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
bvalid_bready_delay(Delay from BVALID assertion to BREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bid_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BID is not X or Z when BVALID is high

BID is not X or Z when BVALID is high

BID is X or Z when BVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(bid_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
bvalid_bready_delay(Delay from BVALID assertion to BREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_stable_wstrb_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WSTRB is stable when WVALID is high

WSTRB is stable when WVALID is high

WSTRB is not stable when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_wdata_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that WDATA is stable when WVALID is high

WDATA is stable when WVALID is high

WDATA is not stable when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI3.
When svt_axi_port_configuration :: check_valid_data_bytes_only_enable=1, it considers only valid byte lanes of wdata based on wstrb .
When svt_axi_port_configuration :: check_valid_data_bytes_only_enable=0, whole wdata as seen on the bus will be considered.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wready_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WREADY is not X or Z when WVALID is high

WREADY is not X or Z when WVALID is high

WREADY is X or Z when WVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wstrb_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WSTRB is not X or Z when WVALID is high

WSTRB is not X or Z when WVALID is high

WSTRB is X or Z when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

is_4state is not set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wdata_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WDATA is not X or Z when WVALID is high

WDATA is not X or Z when WVALID is high

WDATA is X or Z when WVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

is_4state is not set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
wvalid_wready_delay(Delay from WVALID assertion to WREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_awprot_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWPROT is stable when AWVALID is high

AWPROT is stable when AWVALID is high

AWPROT is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_awaddr_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWADDR is stable when AWVALID is high

AWADDR is stable when AWVALID is high

AWADDR is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_awid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWID is stable when AWVALID is high

AWID is stable when AWVALID is high

AWID is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awready_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWREADY is not X or Z when AWVALID is high

AWREADY is not X or Z when AWVALID is high

AWREADY is X or Z when AWVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awprot_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWPROT is not X or Z when AWVALID is high

AWPROT is not X or Z when AWVALID is high

AWPROT is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(awprot_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awaddr_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWADDR is not X or Z when AWVALID is high

AWADDR is not X or Z when AWVALID is high

AWADDR is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWID is not X or Z when AWVALID is high

AWID is not X or Z when AWVALID is high

AWID is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(awid_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_rresp_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RRESP is stable when RVALID is high

RRESP is stable when RVALID is high

RRESP is not stable when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_rdata_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RDATA is stable when RVALID is high

RDATA is stable when RVALID is high

RDATA is not stable when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_rid_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RID is stable when RVALID is high

RID is stable when RVALID is high

RID is not stable when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rready_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RREADY is not X or Z when RVALID is high

RREADY is not X or Z when RVALID is high

RREADY is X or Z when RVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rresp_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RRESP is not X or Z when RVALID is high

RRESP is not X or Z when RVALID is high

RRESP is X or Z when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(rresp_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
rvalid_rready_delay(Delay from RVALID assertion to RREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rdata_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RDATA is not X or Z when RVALID is high

RDATA is not X or Z when RVALID is high

RDATA is X or Z when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable when:

is_4state is not 1'b1.
This check execute when resp_type is not of svt_axi_transaction :: SLVERR or DECERR.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rid_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RID is not X or Z when RVALID is high

RID is not X or Z when RVALID is high

RID is X or Z when RVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

The macro `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(rid_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
rvalid_rready_delay(Delay from RVALID assertion to RREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_arprot_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARPROT is stable when ARVALID is high

ARPROT is stable when ARVALID is high

ARPROT is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_araddr_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARADDR is stable when ARVALID is high

ARADDR is stable when ARVALID is high

ARADDR is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_arid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARID is stable when ARVALID is high

ARID is stable when ARVALID is high

ARID is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arready_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARREADY is not X or Z when ARVALID is high

ARREADY is not X or Z when ARVALID is high

ARREADY is X or Z when ARVALID is high

Passive Slave, Active/Passive Master

This check is applicable only when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arprot_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARPROT is not X or Z when ARVALID is high

ARPROT is not X or Z when ARVALID is high

ARPROT is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The marco `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(arprot_enable) is defined.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_araddr_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARADDR is not X or Z when ARVALID is high

ARADDR is not X or Z when ARVALID is high

ARADDR is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARID is not X or Z when ARVALID is high

ARID is not X or Z when ARVALID is high

ARID is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
The marco `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(arid_enable) is defined.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,AXI5,ACE5_Lite

Read interleaving property

read_data_interleave_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.1 Read data interleaving

Monitor check that Master VIP has recieved interleaved read data though the svt_axi_port_configuration::read_interleaving_disabled is set to 1

Checks that Master reports an error when it recieves interleaved read data.

There is no check pass condition.

Check will fail if Master recieves read data in interleaved fashion and svt_axi_port_configuration :: read_interleaving_disabled is set to 1.

Active/Passive Master

This check is applicable when svt_axi_port_configuration :: read_interleaving_disabled is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awsize_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSIZE is stable when AWVALID is high

AWSIZE is stable when AWVALID is high

AWSIZE is not stable when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awsize_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWSIZE is not X or Z when AWVALID is high

AWSIZE is not X or Z when AWVALID is high

AWSIZE is X or Z when AWVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

The `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(awsize_enable) is defined.
svt_axi_port_configuration :: protocol_checks_enable is set to 1.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
awvalid_awready_delay(Delay from AWVALID assertion to AWREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arsize_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARSIZE is stable when ARVALID is high

ARSIZE is stable when ARVALID is high

ARSIZE is not stable when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable only when svt_axi_port_configuration :: protocol_checks_enable is set to 1.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arsize_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARSIZE is not X or Z when ARVALID is high

ARSIZE is not X or Z when ARVALID is high

ARSIZE is X or Z when ARVALID is high

Passive Master, Active/Passive Slave

This check is applicable when:

svt_axi_port_configuration :: protocol_checks_enable is set to 1.
The marco `SVT_AXI_CHECKER_IS_SIGNAL_ENABLED(arsize_enable) is defined.
svt_axi_port_configuration :: per_clock_cycle_signal_checks_enable is set to 1.
arvalid_arready_delay(Delay from ARVALID assertion to ARREADY assertion) is set to 0, this check will perform at first clock cycle after valid/ready handshake occurs.

ERROR

AXI4_STREAM,AXI5_STREAM

Packet Checks

max_stream_burst_length_exceeded_check

Synopsys Defined

The burst length of received data stream should not exceed the maximum value allowed for stream_burst_length

Checks that the burst length of received data stream is not exceeding the maximum value allowed for stream_burst_length defined by 256

When burst length of received data stream is not exceeding the maximum value allowed for stream_burst_length

When burst length of received data stream is exceeded the maximum value allowed for stream_burst_length

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM

ERROR

AXI4_STREAM,AXI5_STREAM

Packet Checks

tid_or_tdest_change_before_tlast_assertion

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.6 Packet boundaries

The TID or TDEST must not change before the packet end, that is before TLAST assertion as all bytes within a packet are from the same source and for the same destination and have the same TID and TDEST values

Checks if TID or TDEST changed before the packet end (TLAST assertion).

TID and TDEST do not change within the packet (before TLAST assertion).

TID or TDEST change within the packet (before TLAST assertion).

Passive Master, Active/Passive Slave

This check is not applicable when svt_axi_port_configuration :: stream_interleave_depth is set to a value greater than 1 for the data stream transaction.

ERROR

AXI4_STREAM,AXI5_STREAM

Interleaving Checks

stream_interleave_depth_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 4.1 Transfer interleaving

If a Receiver has a limited interleaving capability then the received data stream must not get interleaved beyond stream_interleave_depth value

Checks that received data stream is not interleaved beyond stream_interleave_depth value.
An error is issued if data stream is interleaved beyond this value

When received data stream is not interleaved beyond stream_interleave_depth value

When received data stream is interleaved beyond stream_interleave_depth value

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
svt_axi_port_configuration :: stream_interleave_depth is set greater than 1

ERROR

AXI4_STREAM,AXI5_STREAM

Byte Checks

tstrb_low_when_tkeep_low_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.5.3 TKEEP and TSTRB combinations

TSTRB must be low when corresponding TKEEP is low

Checks that TSTRB is low if TKEEP is low

When TSTRB is low when corresponding TKEEP is low

When TSTRB is not low when corresponding TKEEP is low

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
tready_enable is set to 1
tkeep_enable is set to 1

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

tvalid_interrupted_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2 Handshake signaling

Once TVALID is asserted, it must remain asserted until the handshake occurs

Checks if tvalid was interrupted before tready got asserted

When TVALID is held steady until TREADY is asserted

When TVALID is not steady until TREADY is asserted

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
tready_enable is set to 1

ERROR

AXI4_STREAM,AXI5_STREAM

Reset Checks

tvalid_low_when_reset_is_active_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.8.2 Reset

During reset, TVALID must be driven LOW

Checks that TVALID is low when reset is active

When reset is active TVALID must be low

When reset is active TVALID is not low

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
svt_axi_port_configuration :: protocol_checks_enable is set to 1

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tdest_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TDEST is stable when TVALID is high.

tdest is stable when tvalid is high.

tdest changes when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
This check will be executed only when tvalid_tready_delay is a non-zero value.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tuser_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TUSER is stable when TVALID is high.

tuser is stable when tvalid is high.

tuser changes when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
This check will be executed only when tvalid_tready_delay is a non-zero value.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tid_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TID is stable when TVALID is high.

tid is stable when tvalid is high.

tid changes when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
This check will be executed only when tvalid_tready_delay is a non-zero value.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tlast_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TLAST is stable when TVALID is high.

tlast is stable when tvalid is high.

tlast changes when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
This check will be executed only when tvalid_tready_delay is a non-zero value.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tkeep_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TKEEP is stable when TVALID is high.

tkeep is stable when tvalid is high.

tkeep changes when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
This check will be executed only when tvalid_tready_delay is a non-zero value.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tstrb_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TSTRB is stable when TVALID is high.

tstrb is stable when tvalid is high.

tstrb changes when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
This check will be executed only when tvalid_tready_delay is a non-zero value.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tdata_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TDATA is stable when TVALID is high.

tdata is stable when tvalid is high.

tdata changes when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM
This check will be executed only when tvalid_tready_delay is a non-zero value.
When svt_axi_port_configuration :: check_valid_data_bytes_only_enable=1 , it considers only valid byte lanes of tdata based on tstrb. When svt_axi_port_configuration :: check_valid_data_bytes_only_enable=0 , whole tdata as seen on the bus will be considered.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tdest_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tdest is enabled, checks that tdest is not X or Z when TVALID is high.

tdest is valid when tvalid is high.

tdest takes X or Z value when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tuser_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tuser is enabled, checks that tuser is not X or Z when TVALID is high.

tuser is valid when tvalid is high.

tuser takes X or Z value when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tid_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tid is enabled, checks that tid is not X or Z when TVALID is high.

tid is valid when tvalid is high.

tid takes X or Z value when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tlast_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tlast is enabled, checks that tlastchk is not X or Z when TVALID is high.

tlast is valid when tvalid is high.

tlast takes X or Z value when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tkeep_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tkeep is enabled, checks that tkeep is not X or Z when TVALID is high.

tkeep is valid when tvalid is high.

tkeep takes X or Z value when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tstrb_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tstrb is enabled, checks that tstrb is not X or Z when TVALID is high.

tstrb is valid when tvalid is high.

tstrb takes X or Z value when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when:

svt_axi_port_configuration :: axi_interface_type is set to svt_axi_port_configuration :: AXI4_STREAM

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tdata_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tdata is enabled, checks that tdata is not X or Z when TVALID is high.If svt_axi_port_configuration :: check_valid_data_bytes_only_enable is set to 1,this check is performed on masked_tdata(bytes of tdata having tstrb bit set to 1).

tdata is valid when tvalid is high.

tdata takes X or Z value when tvalid is high.

Passive Master, Active/Passive Slave

This check is applicable only when: