VIP Smartsearch

VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.
How to download VIP smartsearch?
1. Get VIP Smartsearch (Available as a seperate run file).
2. Set environment variable
```
DESIGNWARE_HOME
```
  to required designware home location where VIP Smartsearch should be downloaded.
3. Run
```
vip_smartsearch_<version>.run
```
  file.
  VIP Smartsearch will be downloaded to the location
```
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
```

How to install VIP Smartsearch?

Please refer to the file

VIP_Smartsearch_installation_and_usage_guide.pdf

$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

for installation steps.

Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.
Mention your queries along with below details and send email to above email id.
Product: Verification IP
Sub Product: <vip_title>
Tool: VIP Smartsearch

APB SVT OVM Documentation - Interfaces Reference

Product	Interface Group	Interfaces	Sub-interfaces
amba_svt	Default Group	svt_apb_slave_if
svt_apb_if	svt_apb_slave_if

interface svt_apb_if () APB VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_apb_if is defined. The top level interface contains the system level pins and an array of slave interfaces. By default, 16 slave interfaces are defined in the top level interface. Currently, the maximum number of slave interfaces supported is 128. The number of slave interfaces in top level interface can be controlled using macro SVT_APB_MAX_NUM_SLAVES_{0..128}. For example, if you want to use 20 slave interfaces, you can define following macro when compiling the VIP: SVT_APB_MAX_NUM_SLAVES_20 Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces
svt_apb_slave_if	slave_if

Ports
bit	is_active
bit	disable_x_check_of_presetn
bit	disable_x_check_of_pclk
logic	pclk
logic	presetn
logic [(SVT_APB_MAX_NUM_SLAVES-1):0]	psel
logic	penable
logic	pwrite
logic [(SVT_APB_MAX_ADDR_WIDTH-1):0]	paddr
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	pwdata
logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0]	pstrb
logic [2:0]	pprot
logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0]	control_puser
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	prdata
logic	pready
logic	pslverr
logic [31:0]	xact_id
logic [31:0]	mon_xact_id
string	full_name

Modports
modport svt_apb_master_modport ( input presetn, clocking apb_master_cb ) Modport used to connect the VIP Master to APB interface signals.

modport svt_apb_monitor_modport ( input presetn, clocking apb_monitor_cb ) Modport used to connect the VIP Monitor to APB interface signals.

modport svt_apb_debug_modport ( output xact_id, output mon_xact_id ) Modport used to connect the VIP Debug Port.

modport svt_apb_master_async_modport ( input presetn, output psel, output penable, output pwrite, output paddr, output pwdata, output pstrb, output pprot, output control_puser, input prdata, input pready, input pslverr ) Asynchronous modport suitable for SV Master Bind interface

Clocking blocks
clocking apb_master_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, output psel, output penable, output pwrite, output paddr, output pwdata, output pstrb, output pprot, output control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB Master Interface signal synchronization and directionality.

clocking apb_monitor_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB System Monitor Interface signal synchronization and directionality.

Functions
virtual APB_SLAVE_IF function	get_slave_if (int idx)
void function	set_enable_signal_log ()
string function	get_full_name ()

function void
svt_apb_slave_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_apb_slave_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

bit attribute
svt_apb_slave_if::is_active = 1

logic attribute
svt_apb_slave_if::pclk

logic attribute
svt_apb_slave_if::presetn

logic attribute
svt_apb_slave_if::psel

logic attribute
svt_apb_slave_if::penable

logic attribute
svt_apb_slave_if::pwrite

logic [(SVT_APB_MAX_ADDR_WIDTH-1):0] attribute
svt_apb_slave_if::paddr

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_slave_if::pwdata

logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0] attribute
svt_apb_slave_if::pstrb

logic [2:0] attribute
svt_apb_slave_if::pprot

logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0] attribute
svt_apb_slave_if::control_puser

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_slave_if::prdata

logic attribute
svt_apb_slave_if::pready

logic attribute
svt_apb_slave_if::pslverr

logic [31:0] attribute
svt_apb_slave_if::xact_id

Debug Signals for master driver

logic [31:0] attribute
svt_apb_slave_if::mon_xact_id

Debug Signals for master monitor

string attribute
svt_apb_slave_if::full_name

Full path to this interface or module instance

function virtual APB_SLAVE_IF
svt_apb_if::get_slave_if

( int idx )

function void
svt_apb_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_apb_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

svt_apb_slave_if attribute
svt_apb_if::slave_if

bit attribute
svt_apb_if::is_active = 1

bit attribute
svt_apb_if::disable_x_check_of_presetn = 0

bit attribute
svt_apb_if::disable_x_check_of_pclk = 0

logic attribute
svt_apb_if::pclk

logic attribute
svt_apb_if::presetn

logic [(SVT_APB_MAX_NUM_SLAVES-1):0] attribute
svt_apb_if::psel

logic attribute
svt_apb_if::penable

logic attribute
svt_apb_if::pwrite

logic [(SVT_APB_MAX_ADDR_WIDTH-1):0] attribute
svt_apb_if::paddr

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_if::pwdata

logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0] attribute
svt_apb_if::pstrb

logic [2:0] attribute
svt_apb_if::pprot

logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0] attribute
svt_apb_if::control_puser

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_if::prdata[SVT_APB_MAX_NUM_SLAVES-1:0]

logic attribute
svt_apb_if::pready[SVT_APB_MAX_NUM_SLAVES-1:0]

logic attribute
svt_apb_if::pslverr[SVT_APB_MAX_NUM_SLAVES-1:0]

logic [31:0] attribute
svt_apb_if::xact_id

Debug Signals for master driver

logic [31:0] attribute
svt_apb_if::mon_xact_id

Debug Signals for master monitor

string attribute
svt_apb_if::full_name

Full path to this interface or module instance

interface svt_apb_slave_if () APB Slave Interface provides the SystemVerilog interface which can be used to connect the Slave VIP to a DUT. A top level interface svt_apb_if is defined. The top level interface contains the system level pins and an array of slave interfaces.

Ports
bit	is_active
logic	pclk
logic	presetn
logic	psel
logic	penable
logic	pwrite
logic [(SVT_APB_MAX_ADDR_WIDTH-1):0]	paddr
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	pwdata
logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0]	pstrb
logic [2:0]	pprot
logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0]	control_puser
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	prdata
logic	pready
logic	pslverr
logic [31:0]	xact_id
logic [31:0]	mon_xact_id
string	full_name

Modports
modport svt_apb_slave_modport ( clocking apb_slave_cb ) Modport used to connect the VIP Slave to APB interface signals.

modport svt_apb_monitor_modport ( input presetn, clocking apb_monitor_cb ) Modport used to connect the VIP Monitor to APB interface signals.

modport svt_apb_debug_modport ( output xact_id, output mon_xact_id ) Modport used to connect the VIP Debug Port.

modport svt_apb_slave_async_modport ( input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, output prdata, output pready, output pslverr ) Asynchronous modport suitable for SV Slave Bind interface

Clocking blocks
clocking apb_slave_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pstrb, input pprot, input control_puser, output prdata, output pready, output pslverr Clocking block that defines VIP APB Slave Interface signal synchronization and directionality.

clocking apb_monitor_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB System Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

VIP Smartsearch

APB SVT OVM Documentation - Interfaces Reference

Interface Definition Documentation