VIP Smartsearch

X
  • VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.

  • How to download VIP smartsearch?

    1. Get VIP Smartsearch (Available as a seperate run file).
    2. Set environment variable 
      DESIGNWARE_HOME
      to required designware home location where VIP Smartsearch should be downloaded.
    3. Run 
      vip_smartsearch_<version>.run
      file.
      VIP Smartsearch will be downloaded to the location 
      $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

  • How to install VIP Smartsearch?

    Please refer to the file 
    VIP_Smartsearch_installation_and_usage_guide.pdf
    in 
    $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
    for installation steps.

  • Customer Support

    For more details about VIP smartsearch tool, contact support_center@synopsys.com.
    Mention your queries along with below details and send email to above email id.
    Product: Verification IP
    Sub Product: <vip_title>
    Tool: VIP Smartsearch
13 August 2024, Copyright © 2024 Synopsys, Inc.

APB SVT OVM Documentation - CoverGroup Reference

Functional Covergroups for Product: amba_svt

Covergroup Coverpoints Bins Description
trans_apb_state_after_reset_deasserted
  • apb_state:IDLE_STATE, SETUP_STATE
Covergroup trans_apb_state_after_reset_deasserted to check IDLE and SETUP state during reset deassertion (just after reset is de_asserted)
trans_apb_state_after_reset_deasserted
  • apb_state:idle_state, setup_state
Covergroup trans_apb_state_after_reset_deasserted to check IDLE and SETUP state during reset deassertion(just after reset is de-asserted)
trans_apb_states_covered
  • apb_state:IDLE_STATE, SETUP_STATE, ACCESS_STATE
Covergroup trans_apb_states_covered to check IDLE, SETUP and ACESS state during the transaction
trans_apb_states_covered
  • apb_state:IDLE_STATE, SETUP_STATE, ACCESS_STATE
Covergroup trans_apb_states_covered to check IDLE, SETUP and ACESS state during the transaction
trans_cross_master_to_slave_path_access
  • write_xact_type:write_xact
  • read_xact_type:read_xact
  • idle:idle_zero, idle_non_zero
  • pprot0:normal, privileged
  • pprot1:secure, non_secure
  • pprot2:data, instruction
  • cov_wait:wait_zero, wait_non_zero
  • pslverr:no_error, error
  • all_slaves:slvs_b
  • slaves_excluding_register_space:slvs_no_cfg_b
  • address_8:addr_range_min, addr_range_mid, addr_range_max_8
  • address_16:addr_range_min, addr_range_mid, addr_range_max_16
  • address_32:addr_range_min, addr_range_mid, addr_range_max_32
  • address_64:addr_range_min, addr_range_mid, addr_range_max_64
  • four_state_rd_wr_sequence:bin_RD_RD_RD_RD_SEQ, bin_RD_RD_RD_WR_SEQ, bin_RD_RD_WR_RD_SEQ, bin_RD_RD_WR_WR_SEQ, bin_RD_WR_RD_RD_SEQ, bin_RD_WR_RD_WR_SEQ, bin_RD_WR_WR_RD_SEQ, bin_RD_WR_WR_WR_SEQ, bin_WR_RD_RD_RD_SEQ, bin_WR_RD_RD_WR_SEQ, bin_WR_RD_WR_RD_SEQ, bin_WR_RD_WR_WR_SEQ, bin_WR_WR_RD_RD_SEQ, bin_WR_WR_RD_WR_SEQ, bin_WR_WR_WR_RD_SEQ, bin_WR_WR_WR_WR_SEQ
  • four_state_err_resp_sequence:bin_OK_OK_OK_ERR_SEQ, bin_OK_OK_ERR_OK_SEQ, bin_OK_OK_ERR_ERR_SEQ, bin_OK_ERR_OK_OK_SEQ, bin_OK_ERR_OK_ERR_SEQ, bin_OK_ERR_ERR_OK_SEQ, bin_OK_ERR_ERR_ERR_SEQ, bin_ERR_OK_OK_OK_SEQ, bin_ERR_OK_OK_ERR_SEQ, bin_ERR_OK_ERR_OK_SEQ, bin_ERR_OK_ERR_ERR_SEQ, bin_ERR_ERR_OK_OK_SEQ, bin_ERR_ERR_OK_ERR_SEQ, bin_ERR_ERR_ERR_OK_SEQ, bin_ERR_ERR_ERR_ERR_SEQ
  • pstrb_addr_aligned_unaligned16_coverpoint:wr_addr_unalign16, wr_addr_align16, rd_addr_unalign16, rd_addr_align16
  • pstrb_addr_aligned_unaligned32_coverpoint:wr_addr_unalign32, wr_addr_align32, rd_addr_unalign32, rd_addr_align32
  • pstrb_addr_aligned_unaligned64_coverpoint:wr_addr_unalign64, wr_addr_align64, rd_addr_unalign64, rd_addr_align64
Crosses transaction type and coverpoints. This cover group belongs to MASTER monitor.
trans_cross_read_address_16bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_16
Crosses READ transaction type and address when pdata_width is 16 bit. This cover group belongs to MASTER monitor.
trans_cross_read_address_16bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_16
Crosses READ transaction type and address when pdata_width is 16 bit. This cover group belongs to SLAVE monitor.
trans_cross_read_address_32bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_32
Crosses READ transaction type and address when pdata_width is 32 bit. This cover group belongs to MASTER monitor.
trans_cross_read_address_32bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_32
Crosses READ transaction type and address when pdata_width is 32 bit. This cover group belongs to SLAVE monitor.
trans_cross_read_address_64bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_64
Crosses READ transaction type and address when pdata_width is 64 bit. This cover group belongs to MASTER monitor.
trans_cross_read_address_64bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_64
Crosses READ transaction type and address when pdata_width is 64 bit. This cover group belongs to SLAVE monitor.
trans_cross_read_address_8bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_8
Crosses READ transaction type and address when pdata_width is 8 bit. This cover group belongs to MASTER monitor.
trans_cross_read_address_8bit
  • read_xact_type:read_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_8
Crosses READ transaction type and address when pdata_width is 8 bit. This cover group belongs to SLAVE monitor.
trans_cross_read_pprot
  • read_xact_type:read_xact
  • pprot0:normal, privileged
  • pprot1:secure, non_secure
  • pprot2:data, instruction
Crosses READ transaction type and pprot. This cover group belongs to MASTER monitor.

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_cross_read_pprot
  • read_xact_type:read_xact
  • pprot0:normal, privileged
  • pprot1:secure, non_secure
  • pprot2:data, instruction
Crosses READ transaction type and pprot. This cover group belongs to SLAVE monitor.

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_cross_read_pslverr
  • read_xact_type:read_xact
  • pslverr:no_error, error
Crosses READ transaction type and pslverr. This cover group belongs to MASTER monitor.
trans_cross_read_pslverr
  • read_xact_type:read_xact
  • pslverr:no_error, error
Crosses READ transaction type and pslverr. This cover group belongs to SLAVE monitor.
trans_cross_read_wait
  • read_xact_type:read_xact
  • cov_wait:wait_zero, wait_non_zero
Crosses READ transaction type and number of wait states. This cover group belongs to MASTER monitor.
trans_cross_read_wait
  • read_xact_type:read_xact
  • cov_wait:wait_zero, wait_non_zero
Crosses READ transaction type and number of wait states. This cover group belongs to SLAVE monitor.
trans_cross_write_address_16bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_16
Crosses WRITE transaction type and address when pdata_width is 16 bit . This cover group belongs to MASTER monitor.
trans_cross_write_address_16bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_16
Crosses WRITE transaction type and address when pdata_width is 16 bit . This cover group belongs to SLAVE monitor.
trans_cross_write_address_32bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_32
Crosses WRITE transaction type and address when pdata_width is 32 bit . This cover group belongs to MASTER monitor.
trans_cross_write_address_32bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_32
Crosses WRITE transaction type and address when pdata_width is 32 bit . This cover group belongs to SLAVE monitor.
trans_cross_write_address_64bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_64
Crosses WRITE transaction type and address when pdata_width is 64 bit. This cover group belongs to MASTER monitor.
trans_cross_write_address_64bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_64
Crosses WRITE transaction type and address when pdata_width is 64 bit. This cover group belongs to SLAVE monitor.
trans_cross_write_address_8bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_8
Crosses WRITE transaction type and address when pdata_width is 8 bit. This cover group belongs to MASTER monitor.
trans_cross_write_address_8bit
  • write_xact_type:write_xact
  • address:addr_range_min, addr_range_mid, addr_range_max_8
Crosses WRITE transaction type and address when pdata_width is 8 bit. This cover group belongs to SLAVE monitor.
trans_cross_write_pprot
  • write_xact_type:write_xact
  • pprot0:normal, privileged
  • pprot1:secure, non_secure
  • pprot2:data, instruction
Crosses WRITE transaction type and pprot. This cover group belongs to MASTER monitor.

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_cross_write_pprot
  • write_xact_type:write_xact
  • pprot0:normal, privileged
  • pprot1:secure, non_secure
  • pprot2:data, instruction
Crosses WRITE transaction type and pprot. This cover group belongs to SLAVE monitor.

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_cross_write_pslverr
  • write_xact_type:write_xact
  • pslverr:no_error, error
Crosses WRITE transaction type and pslverr. This cover group belongs to MASTER monitor.
trans_cross_write_pslverr
  • write_xact_type:write_xact
  • pslverr:no_error, error
Crosses WRITE transaction type and pslverr. This cover group belongs to SLAVE monitor.
trans_cross_write_pstrb
  • write_xact_type:write_xact
Crosses WRITE transaction type and pstrb. This cover group belongs to MASTER monitor.

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_cross_write_pstrb
  • write_xact_type:write_xact
Crosses WRITE transaction type and pstrb. This cover group belongs to SLAVE monitor.

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_cross_write_wait
  • write_xact_type:write_xact
  • cov_wait:wait_zero, wait_non_zero
Crosses WRITE transaction type and number of wait states. This cover group belongs to MASTER monitor.
trans_cross_write_wait
  • write_xact_type:write_xact
  • cov_wait:wait_zero, wait_non_zero
Crosses WRITE transaction type and number of wait states. This cover group belongs to SLAVE monitor.
trans_four_state_err_resp_sequence
  • four_state_err_resp_sequence:bin_OK_OK_OK_ERR_SEQ, bin_OK_OK_ERR_OK_SEQ, bin_OK_OK_ERR_ERR_SEQ, bin_OK_ERR_OK_OK_SEQ, bin_OK_ERR_OK_ERR_SEQ, bin_OK_ERR_ERR_OK_SEQ, bin_OK_ERR_ERR_ERR_SEQ, bin_ERR_OK_OK_OK_SEQ, bin_ERR_OK_OK_ERR_SEQ, bin_ERR_OK_ERR_OK_SEQ, bin_ERR_OK_ERR_ERR_SEQ, bin_ERR_ERR_OK_OK_SEQ, bin_ERR_ERR_OK_ERR_SEQ, bin_ERR_ERR_ERR_OK_SEQ, bin_ERR_ERR_ERR_ERR_SEQ
Covergroup: trans_four_state_err_resp_sequence

This cover group covers specific combinations of ERROR response for a sequence of four transactions. For eg. ERROR-ERROR-ERROR-ERROR or ERROR-OK-ERROR-OK etc. This covergroup is hit when completion of four transactions are observed in a specific combination as described above.
.
trans_four_state_err_resp_sequence
  • four_state_err_resp_sequence:bin_OK_OK_OK_ERR_SEQ, bin_OK_OK_ERR_OK_SEQ, bin_OK_OK_ERR_ERR_SEQ, bin_OK_ERR_OK_OK_SEQ, bin_OK_ERR_OK_ERR_SEQ, bin_OK_ERR_ERR_OK_SEQ, bin_OK_ERR_ERR_ERR_SEQ, bin_ERR_OK_OK_OK_SEQ, bin_ERR_OK_OK_ERR_SEQ, bin_ERR_OK_ERR_OK_SEQ, bin_ERR_OK_ERR_ERR_SEQ, bin_ERR_ERR_OK_OK_SEQ, bin_ERR_ERR_OK_ERR_SEQ, bin_ERR_ERR_ERR_OK_SEQ, bin_ERR_ERR_ERR_ERR_SEQ
Covergroup: trans_four_state_err_resp_sequence

This cover group covers specific combinations of ERROR response for a sequence of four transactions. For eg. ERROR-ERROR-ERROR-ERROR or ERROR-OK-ERROR-OK etc. This covergroup is hit when completion of four transactions are observed in a specific combination as described above.
.
trans_four_state_rd_wr_sequence
  • four_state_rd_wr_sequence:bin_RD_RD_RD_RD_SEQ, bin_RD_RD_RD_WR_SEQ, bin_RD_RD_WR_RD_SEQ, bin_RD_RD_WR_WR_SEQ, bin_RD_WR_RD_RD_SEQ, bin_RD_WR_RD_WR_SEQ, bin_RD_WR_WR_RD_SEQ, bin_RD_WR_WR_WR_SEQ, bin_WR_RD_RD_RD_SEQ, bin_WR_RD_RD_WR_SEQ, bin_WR_RD_WR_RD_SEQ, bin_WR_RD_WR_WR_SEQ, bin_WR_WR_RD_RD_SEQ, bin_WR_WR_RD_WR_SEQ, bin_WR_WR_WR_RD_SEQ, bin_WR_WR_WR_WR_SEQ
Covergroup: trans_four_state_rd_wr_sequence

This cover group covers specific combinations of read and write transactions, for a sequence of four transactions. For eg. Write-Write-Write-Write or Write-Read-Write-Read, etc. This covergroup is hit when completion of four transactions are observed in a specific combination as described above.
.
trans_four_state_rd_wr_sequence
  • four_state_rd_wr_sequence:bin_RD_RD_RD_RD_SEQ, bin_RD_RD_RD_WR_SEQ, bin_RD_RD_WR_RD_SEQ, bin_RD_RD_WR_WR_SEQ, bin_RD_WR_RD_RD_SEQ, bin_RD_WR_RD_WR_SEQ, bin_RD_WR_WR_RD_SEQ, bin_RD_WR_WR_WR_SEQ, bin_WR_RD_RD_RD_SEQ, bin_WR_RD_RD_WR_SEQ, bin_WR_RD_WR_RD_SEQ, bin_WR_RD_WR_WR_SEQ, bin_WR_WR_RD_RD_SEQ, bin_WR_WR_RD_WR_SEQ, bin_WR_WR_WR_RD_SEQ, bin_WR_WR_WR_WR_SEQ
Covergroup: trans_four_state_rd_wr_sequence

This cover group covers specific combinations of read and write transactions, for a sequence of four transactions. For eg. Write-Write-Write-Write or Write-Read-Write-Read, etc. This covergroup is hit when completion of four transactions are observed in a specific combination as described above.
.
trans_pslverr_signal_transition
  • pslverr:no_error, error
Coverage that Master works fine when PSLVERR is low by default and only goes high when PREADY and PENABLE are 1. This cover group belongs to MASTER monitor.
trans_pslverr_signal_transition
  • pslverr:no_error, error
Coverage that Master works fine when PSLVERR is low by default and only goes high when PREADY and PENABLE are 1. This cover group belongs to SLAVE monitor.
trans_pstrb_addr_aligned_unaligned16
  • addr_aligned_unaligned16_coverpoint:wr_addr_unalign16, wr_addr_align16, rd_addr_unalign16, rd_addr_align16
Covergroup: trans_pstrb_addr_aligned_unaligned16

This covergroup covers if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when the pdata_width is 16 bits. .

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_pstrb_addr_aligned_unaligned16
  • addr_aligned_unaligned16_coverpoint:wr_addr_unalign16, wr_addr_align16, rd_addr_unalign16, rd_addr_align16
Covergroup: trans_pstrb_addr_aligned_unaligned16

This covergroup covers if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when the pdata_width is 16 bits. .

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_pstrb_addr_aligned_unaligned32
  • addr_aligned_unaligned32_coverpoint:wr_addr_unalign32, wr_addr_align32, rd_addr_unalign32, rd_addr_align32
Covergroup: trans_pstrb_addr_aligned_unaligned32

This covergroup covers if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when the pdata_width is 32 bits. .

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_pstrb_addr_aligned_unaligned32
  • addr_aligned_unaligned32_coverpoint:wr_addr_unalign32, wr_addr_align32, rd_addr_unalign32, rd_addr_align32
Covergroup: trans_pstrb_addr_aligned_unaligned32

This covergroup covers if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when the pdata_width is 32 bits. .

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_pstrb_addr_aligned_unaligned64
  • addr_aligned_unaligned64_coverpoint:wr_addr_unalign64, wr_addr_align64, rd_addr_unalign64, rd_addr_align64
Covergroup: trans_pstrb_addr_aligned_unaligned64

This covergroup covers if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when the pdata_width is 64 bits. .

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_pstrb_addr_aligned_unaligned64
  • addr_aligned_unaligned64_coverpoint:wr_addr_unalign64, wr_addr_align64, rd_addr_unalign64, rd_addr_align64
Covergroup: trans_pstrb_addr_aligned_unaligned64

This covergroup covers if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when the pdata_width is 64 bits. .

Only applicable when svt_apb_system_configuration :: apb4_enable is set.
trans_read_x_on_prdata_when_pslverr
  • prdata_read_xact:x_on_prdata
Covergroup trans_read_x_on_prdata_when_pslverr to check if x on prdata when pslverrr = 1, pready = 1 and penable = 1 for read xact applicable for apb3/apb4 only.
trans_read_x_on_prdata_when_pslverr
  • prdata_read_xact:x_on_prdata
Covergroup trans_read_x_on_prdata_when_pslverr to check if x on prdata when pslverrr = 1, pready = 1 and penable = 1 for read xact applicable for ahb3/apb4 only.
transition_psel_penable_pready_low
  • psel_penable_pready_signal_states_low:idle_setup, setup_access_wait, acess_access
Covers the values of psel,penable,pready signals

Product: amba_svt - Other Coverage Details:

Covergroup Coverpoints Bins
signal_state_pprot
  • pprot_min_mid_max:pprot_range_min, pprot_range_mid, pprot_range_max
signal_state_pprot
  • pprot_min_mid_max:pprot_range_min, pprot_range_mid, pprot_range_max
signal_state_prdata
  • prdata_min_mid_max:prdata_range_min, prdata_range_mid, prdata_range_max
signal_state_prdata_0
  • prdata0_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_1
  • prdata1_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_10
  • prdata10_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_11
  • prdata11_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_12
  • prdata12_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_13
  • prdata13_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_14
  • prdata14_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_15
  • prdata15_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_2
  • prdata2_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_3
  • prdata3_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_4
  • prdata4_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_5
  • prdata5_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_6
  • prdata6_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_7
  • prdata7_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_8
  • prdata8_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_prdata_9
  • prdata9_min_mid_max:prdata_arrindex_range_min, prdata_arrindex_range_mid, prdata_arrindex_range_max
signal_state_psel
  • psel_min_mid_max:psel_range_min, psel_range_mid, psel_range_max
signal_state_pstrb
    signal_state_pstrb
      signal_state_pwdata
      • pwdata_min_mid_max:pwdata_range_min, pwdata_range_mid, pwdata_range_max
      signal_state_pwdata
      • pwdata_min_mid_max:pwdata_range_min, pwdata_range_mid, pwdata_range_max
      toggle_cov
      • signal_index:toggle_bit_0to1, toggle_bit_1to0
      toggle_cov
      • signal_index:toggle_bit_0to1, toggle_bit_1to0
      transition_psel_penable_pready
      • psel_penable_pready_signal_states:setup_access_wait, setup_access_no_wait, access_wait_access_completion, access_idle, access_setup
      transition_psel_penable_pready
      • psel_penable_pready_signal_states:setup_access_wait, setup_access_no_wait, access_wait_access_completion, access_idle, access_setup
      transition_psel_penable_pready_high
      • psel_penable_pready_high_signal_states:idle_setup, setup_access_no_wait, access_idle, access_setup
      transition_psel_penable_pready_high
      • psel_penable_pready_signal_states_high:idle_setup, setup_access_no_wait, access_idle, access_setup
      transition_psel_penable_pready_low
      • psel_penable_pready_low_signal_states:idle_setup, setup_access_wait, acess_access
      13 August 2024, Copyright © 2024 Synopsys, Inc.