VIP Smartsearch

VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.
How to download VIP smartsearch?
1. Get VIP Smartsearch (Available as a seperate run file).
2. Set environment variable
```
DESIGNWARE_HOME
```
  to required designware home location where VIP Smartsearch should be downloaded.
3. Run
```
vip_smartsearch_<version>.run
```
  file.
  VIP Smartsearch will be downloaded to the location
```
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
```

How to install VIP Smartsearch?

Please refer to the file

VIP_Smartsearch_installation_and_usage_guide.pdf

$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

for installation steps.

Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.
Mention your queries along with below details and send email to above email id.
Product: Verification IP
Sub Product: <vip_title>
Tool: VIP Smartsearch

APB SVT OVM Documentation - Protocol Checks Defined in VIP

Summary of Protocol Checks defined in APB SVT OVM Documentation:

Product Base	Group	Protocol Check Class
amba_svt	APB2	svt_apb_checker
APB3	svt_apb_checker
APB4 Protection Unit Support	svt_apb_checker
APB4 Write Strobes	svt_apb_checker

Product Base

Group

Protocol Check Class

APB4 Protection Unit Support

svt_apb_checker

APB4 Write Strobes

svt_apb_checker

Group	Sub Group	Protocol Check Instance name	Reference	Description	Check Intent	Pass Condition	Fail Condition	Applicable Device Type	Additional Information	Error Category	Protocol Check Class
APB2	State Transition	initial_bus_state_after_reset	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	After reset the bus initially should be in either IDLE or SETUP State	Checks that after reset de-assertion, APB Bus is in either IDLE or SETUP state.	APB Bus is in either IDLE or SETUP state after reset de-assertion. For master, either PSEL is zero or PENABLE is 0, immediately after reset de-assertion For slave, either PSEL or PENABLE sampled as 0, immediately after reset de-assertion	APB Bus is in ACCESS state after reset de-assertion. For master, PSEL of the selected slave is 1 and PENABLE is 1, immediately after reset de-assertion For slave, PSEL and PENABLE both sampled as 1, immediately after reset de-assertion	Active & Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Slave Selection	multiple_select_signals_active_during_transfer	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.4.2 APB bridge description	Only one select signal can be active during a transfer	Checks if multiple select signals asserted during transfer	Only one select signal asserted during transfer	Multiple select signals asserted during transfer	Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_prdata_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PRDATA must be valid when PSEL, PENABLE and PREADY are asserted for read transfer	Checks that PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer	PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer	PRDATA is X or Z when PSEL, PENABLE and PREADY are asserted for read transfer	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 The macro SVT_APB_SLAVE_DRIVE_X_IF_MEMDATA_X is not defined	ERROR	svt_apb_checker
APB2	Unaligned Transfers	address_not_aligned_when_unaligned_address_support_not_enabled	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus	Unaligned address should not be driven on PADDR when unaligned_address_support is not enabled	Checks if unaligned address is driven on PADDR when unaligned_address_support is not enabled.	Aligned address is driven on PADDR	Unaligned address is driven on PADDR	Passive Master, Active & Passive Slave	Group: APB2 Default severity: WARNING If unaligned address driving and sampling is required and need to bypass this check, please enable unaligned address support setting svt_apb_configuration :: unaligned_address_support to 1	WARNING	svt_apb_checker
APB2	Signal Stability	pwdata_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers	PWDATA must be stable until the write transfer completes	Checks if PWDATA changed value during write transfer	PWDATA is stable during write transfer	PWDATA is changed during write transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 If svt_apb_configuration :: check_valid_data_bytes_only_enable and svt_apb_system_configuration :: apb4_enable are set to 1, then check will be performed only on active data byte lanes based on pstrb.	ERROR	svt_apb_checker
APB2	Signal Stability	pwrite_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PWRITE must be stable until the transfer completes	Checks if PWRITE changed value during transfer	PWRITE is stable during transfer	PWRITE is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Stability	paddr_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PADDR must be stable until the transfer completes	Checks if PADDR changed value during transfer	PADDR is stable during transfer	PADDR is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Stability	psel_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PSEL must be stable until the transfer completes	Checks if PSEL changed value during transfer	PSEL is stable during the transfer	PSEL is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_pwdata_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PWDATA must be valid when PSEL is asserted for write transfer	Checks that PWDATA is not X or Z when PSEL is asserted for write transfer	PWDATA is not X or Z when PSEL is asserted for write transfer	PWDATA is X or Z when PSEL is asserted for write transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 If svt_apb_configuration :: check_valid_data_bytes_only_enable and svt_apb_system_configuration :: apb4_enable are set to 1, then check will be performed only on active data byte lanes based on pstrb.	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_penable_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PENABLE must be valid when PSEL is asserted	Checks that PENABLE is not X or Z when PSEL is asserted	PENABLE is not X or Z when PSEL is asserted	PENABLE is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_pwrite_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PWRITE must be valid when PSEL is asserted	Checks that PWRITE is not X or Z when PSEL is asserted	PWRITE is not X or Z when PSEL is asserted	PWRITE is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_paddr_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PADDR must be valid when PSEL is asserted	Checks that PADDR is not X or Z when PSEL is asserted	PADDR is not X or Z when PSEL is asserted	PADDR is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_psel_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSEL must be always valid	Checks that PSEL is not X or Z	PSEL is not X or Z	PSEL is X or Z	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	State Transition	penable_after_psel	AMBA APB Protocol Specification ARM IHI 0011A: 5.2.1 State diagram	PENABLE should be asserted after one clock cycle of PSEL being asserted	Checks that PENABLE is asserted after one clock cycle of PSEL being asserted.	PENABLE is asserted after one clock cycle of PSEL being asserted	PSEL and PENABLE asserted simultaneously PENABLE is not asserted after one clock cycle of PSEL being asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	Address Mapping	psel_match_with_address_map	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.5.2 APB slave description	Asserted PSEL should match with the address map	Checks that asserted PSEL matches with the address map. Refer to ARM IHI 0011A section 2.4, signal description of PSELx for the protocol info.	slave ID obtained by address decoding is equal to the slave ID that has PSEL asserted.	slave ID obtained by address decoding is not equal to the slave ID that has PSEL asserted.	Passive Master, Active & Passive Slave	In case of complex_memory_map enabled, pprot1 is also considered in address decoding.	ERROR	svt_apb_checker
APB2	State Transition	setup_to_setup	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	SETUP to SETUP is an illegal state transition	Checks that if illegal state transition occured from setup to setup	No state transition occured from setup to setup	Illegal state transition occured from setup to setup	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	APB2 State Transition	access_to_access	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	ACCESS to ACCESS is an illegal state transition in APB2	Checks that if illegal state transition occured from access to access in APB2. In APB3 state transition from access to access is valid transition.	No state transition occured from access to access in APB2	Illegal state transition occured from access to access in APB2	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	State Transition	setup_to_idle	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	SETUP to IDLE is an illegal state transition	Checks that if illegal state transition occured from setup to idle	No state transition occured from setup to idle	Illegal state transition occured from setup to idle	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB2	APB2 State Transition	bus_in_enable_state_for_one_clock	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.2.1 State diagram	ENABLE state lasts only for a single clock cycle in APB2	Checks that bus remains in ENABLE state for one clock cycle in APB2	Bus remains in ENABLE state for one clock cycle in APB2	Bus remains in ENABLE state for more than one clock cycle in APB2	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb3_enable and svt_apb_system_configuration :: apb4_enable are set to 0	ERROR	svt_apb_checker
APB3	Signal Validity	signal_valid_pslverr_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSLVERR must be valid when PSEL, PENABLE and PREADY are asserted	Checks that PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted	PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted	PSLVERR is X or Z when PSEL, PENABLE and PREADY are asserted	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB3	Signal Validity	signal_valid_pready_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PREADY must be valid when PSEL and PENABLE are asserted	Checks that PREADY is not X or Z when PSEL and PENABLE are asserted	PREADY is not X or Z when PSEL and PENABLE are asserted	PREADY is X or Z when PSEL and PENABLE are asserted	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB3	Transaction Timeout	pready_timeout_check	Synopsys Defined	PREADY should be asserted by the slave within the timeout period	Checks that PREADY signal is asserted by slave within timeout period slave_pready_timeout	PREADY signal is asserted by slave within timeout period slave_pready_timeout	PREADY signal is not asserted by slave within timeout period slave_pready_timeout	Passive Slave, Active & Passive Master	This check is applicable only when: svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1 svt_apb_system_configuration :: slave_pready_timeout is not equal to 0	ERROR	svt_apb_checker
APB3	Signal Stability	penable_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PENABLE must be stable until the transfer completes	Checks if PENABLE changed value during access phase of transfer	PENABLE high during access phase of transfer	PENABLE low during access phase of transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB3	State Transition	idle_to_access	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	IDLE to ACCESS is an illegal state transition	Checks that if illegal state transition occured from idle to access	No state transition occured from idle to access	Illegal state transition occured from idle to access	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1	ERROR	svt_apb_checker
APB4 Protection Unit Support	Signal Stability	pprot_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PPROT must be stable until the transfer completes	Checks if PPROT changed value during transfer	PPROT is stable during transfer	PPROT is changed during transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Protection Unit Support	Signal Validity	signal_valid_pprot_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PPROT must be valid when PSEL is asserted	Checks that PPROT is not X or Z when PSEL is asserted	PPROT is not X or Z when PSEL is asserted	PPROT is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	Signal Stability	pstrb_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers	PSTRB must be stable until the transfer completes	Checks if PSTRB changed value during write transfer	PSTRB is stable during write transfer	PSTRB is changed during write transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	PSTRB Validity	pstrb_low_for_read	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.2 Write strobes	All bits of PSTRB must be LOW for read transfer	Checks that PSTRB is low for read transfer	All bits of PSTRB are low for read transfer	Any bit of PSTRB is high for read transfer	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	Signal Validity	signal_valid_pstrb_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSTRB must be valid when PSEL is asserted	Checks that PSTRB is not X or Z when PSEL is asserted	PSTRB is not X or Z when PSEL is asserted	PSTRB is X or Z when PSEL is asserted	Passive Master, Active & Passive Slave	This check is applicable only when: svt_apb_configuration :: protocol_checks_enable is set to 1 svt_apb_system_configuration :: apb4_enable is set to 1	ERROR	svt_apb_checker
APB4 Write Strobes	Unaligned Transfers	pstrb_asserted_for_invalid_byte_in_unaligned_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus & 3.2 Write strobes	PSTRB should be correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled	Checks if PSTRB is correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled.	PSTRB is correctly asserted based on the address alignment	PSTRB is not correctly asserted based on the address alignment	Passive Master, Active & Passive Slave	Group: APB4 Default severity: ERROR Applicable for APB4 systems when unaligned address support is enabled using svt_apb_configuration :: unaligned_address_support configuration.	ERROR	svt_apb_checker

Group

Sub Group

Protocol Check Instance name

Reference

Description

Check Intent

Pass Condition

Fail Condition

Applicable Device Type

Additional Information

Error Category

Protocol Check Class

APB2

State Transition

initial_bus_state_after_reset

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

After reset the bus initially should be in either IDLE or SETUP State

Checks that after reset de-assertion, APB Bus is in either IDLE or SETUP state.

APB Bus is in either IDLE or SETUP state after reset de-assertion.

For master, either PSEL is zero or PENABLE is 0, immediately after reset de-assertion
For slave, either PSEL or PENABLE sampled as 0, immediately after reset de-assertion

APB Bus is in ACCESS state after reset de-assertion.

For master, PSEL of the selected slave is 1 and PENABLE is 1, immediately after reset de-assertion
For slave, PSEL and PENABLE both sampled as 1, immediately after reset de-assertion

Active & Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Slave Selection

multiple_select_signals_active_during_transfer

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.4.2 APB bridge description

Only one select signal can be active during a transfer

Checks if multiple select signals asserted during transfer

Only one select signal asserted during transfer

Multiple select signals asserted during transfer

Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_prdata_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PRDATA must be valid when PSEL, PENABLE and PREADY are asserted for read transfer

Checks that PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer

PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer

PRDATA is X or Z when PSEL, PENABLE and PREADY are asserted for read transfer

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
The macro SVT_APB_SLAVE_DRIVE_X_IF_MEMDATA_X is not defined

ERROR

APB2

Unaligned Transfers

address_not_aligned_when_unaligned_address_support_not_enabled

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus

Unaligned address should not be driven on PADDR when unaligned_address_support is not enabled

Checks if unaligned address is driven on PADDR when unaligned_address_support is not enabled.

Aligned address is driven on PADDR

Unaligned address is driven on PADDR

Passive Master, Active & Passive Slave

Group: APB2
Default severity: WARNING
If unaligned address driving and sampling is required and need to bypass this check, please enable unaligned address support setting svt_apb_configuration :: unaligned_address_support to 1

WARNING

APB2

Signal Stability

pwdata_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers

PWDATA must be stable until the write transfer completes

Checks if PWDATA changed value during write transfer

PWDATA is stable during write transfer

PWDATA is changed during write transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

If svt_apb_configuration :: check_valid_data_bytes_only_enable and svt_apb_system_configuration :: apb4_enable are set to 1, then check will be performed only on active data byte lanes based on pstrb.

ERROR

APB2

Signal Stability

pwrite_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PWRITE must be stable until the transfer completes

Checks if PWRITE changed value during transfer

PWRITE is stable during transfer

PWRITE is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Stability

paddr_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PADDR must be stable until the transfer completes

Checks if PADDR changed value during transfer

PADDR is stable during transfer

PADDR is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Stability

psel_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PSEL must be stable until the transfer completes

Checks if PSEL changed value during transfer

PSEL is stable during the transfer

PSEL is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_pwdata_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PWDATA must be valid when PSEL is asserted for write transfer

Checks that PWDATA is not X or Z when PSEL is asserted for write transfer

PWDATA is not X or Z when PSEL is asserted for write transfer

PWDATA is X or Z when PSEL is asserted for write transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_penable_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PENABLE must be valid when PSEL is asserted

Checks that PENABLE is not X or Z when PSEL is asserted

PENABLE is not X or Z when PSEL is asserted

PENABLE is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_pwrite_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PWRITE must be valid when PSEL is asserted

Checks that PWRITE is not X or Z when PSEL is asserted

PWRITE is not X or Z when PSEL is asserted

PWRITE is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_paddr_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PADDR must be valid when PSEL is asserted

Checks that PADDR is not X or Z when PSEL is asserted

PADDR is not X or Z when PSEL is asserted

PADDR is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Signal Validity

signal_valid_psel_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSEL must be always valid

Checks that PSEL is not X or Z

PSEL is not X or Z

PSEL is X or Z

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

State Transition

penable_after_psel

AMBA APB Protocol Specification ARM IHI 0011A: 5.2.1 State diagram

PENABLE should be asserted after one clock cycle of PSEL being asserted

Checks that PENABLE is asserted after one clock cycle of PSEL being asserted.

PENABLE is asserted after one clock cycle of PSEL being asserted

PSEL and PENABLE asserted simultaneously
PENABLE is not asserted after one clock cycle of PSEL being asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

Address Mapping

psel_match_with_address_map

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.5.2 APB slave description

Asserted PSEL should match with the address map

Checks that asserted PSEL matches with the address map. Refer to ARM IHI 0011A section 2.4, signal description of PSELx for the protocol info.

slave ID obtained by address decoding is equal to the slave ID that has PSEL asserted.

slave ID obtained by address decoding is not equal to the slave ID that has PSEL asserted.

Passive Master, Active & Passive Slave

In case of complex_memory_map enabled, pprot1 is also considered in address decoding.

ERROR

APB2

State Transition

setup_to_setup

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

SETUP to SETUP is an illegal state transition

Checks that if illegal state transition occured from setup to setup

No state transition occured from setup to setup

Illegal state transition occured from setup to setup

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

APB2 State Transition

access_to_access

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

ACCESS to ACCESS is an illegal state transition in APB2

Checks that if illegal state transition occured from access to access in APB2. In APB3 state transition from access to access is valid transition.

No state transition occured from access to access in APB2

Illegal state transition occured from access to access in APB2

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

State Transition

setup_to_idle

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

SETUP to IDLE is an illegal state transition

Checks that if illegal state transition occured from setup to idle

No state transition occured from setup to idle

Illegal state transition occured from setup to idle

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB2

APB2 State Transition

bus_in_enable_state_for_one_clock

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.2.1 State diagram

ENABLE state lasts only for a single clock cycle in APB2

Checks that bus remains in ENABLE state for one clock cycle in APB2

Bus remains in ENABLE state for one clock cycle in APB2

Bus remains in ENABLE state for more than one clock cycle in APB2

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb3_enable and svt_apb_system_configuration :: apb4_enable are set to 0

ERROR

APB3

Signal Validity

signal_valid_pslverr_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSLVERR must be valid when PSEL, PENABLE and PREADY are asserted

Checks that PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted

PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted

PSLVERR is X or Z when PSEL, PENABLE and PREADY are asserted

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB3

Signal Validity

signal_valid_pready_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PREADY must be valid when PSEL and PENABLE are asserted

Checks that PREADY is not X or Z when PSEL and PENABLE are asserted

PREADY is not X or Z when PSEL and PENABLE are asserted

PREADY is X or Z when PSEL and PENABLE are asserted

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB3

Transaction Timeout

pready_timeout_check

Synopsys Defined

PREADY should be asserted by the slave within the timeout period

Checks that PREADY signal is asserted by slave within timeout period slave_pready_timeout

PREADY signal is asserted by slave within timeout period slave_pready_timeout

PREADY signal is not asserted by slave within timeout period slave_pready_timeout

Passive Slave, Active & Passive Master

This check is applicable only when:

svt_apb_system_configuration :: apb3_enable or svt_apb_system_configuration :: apb4_enable is set to 1
svt_apb_system_configuration :: slave_pready_timeout is not equal to 0

ERROR

APB3

Signal Stability

penable_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PENABLE must be stable until the transfer completes

Checks if PENABLE changed value during access phase of transfer

PENABLE high during access phase of transfer

PENABLE low during access phase of transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB3

State Transition

idle_to_access

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

IDLE to ACCESS is an illegal state transition

Checks that if illegal state transition occured from idle to access

No state transition occured from idle to access

Illegal state transition occured from idle to access

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1

ERROR

APB4 Protection Unit Support

Signal Stability

pprot_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PPROT must be stable until the transfer completes

Checks if PPROT changed value during transfer

PPROT is stable during transfer

PPROT is changed during transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Protection Unit Support

Signal Validity

signal_valid_pprot_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PPROT must be valid when PSEL is asserted

Checks that PPROT is not X or Z when PSEL is asserted

PPROT is not X or Z when PSEL is asserted

PPROT is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

Signal Stability

pstrb_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers

PSTRB must be stable until the transfer completes

Checks if PSTRB changed value during write transfer

PSTRB is stable during write transfer

PSTRB is changed during write transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

PSTRB Validity

pstrb_low_for_read

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.2 Write strobes

All bits of PSTRB must be LOW for read transfer

Checks that PSTRB is low for read transfer

All bits of PSTRB are low for read transfer

Any bit of PSTRB is high for read transfer

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

Signal Validity

signal_valid_pstrb_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSTRB must be valid when PSEL is asserted

Checks that PSTRB is not X or Z when PSEL is asserted

PSTRB is not X or Z when PSEL is asserted

PSTRB is X or Z when PSEL is asserted

Passive Master, Active & Passive Slave

This check is applicable only when:

svt_apb_configuration :: protocol_checks_enable is set to 1
svt_apb_system_configuration :: apb4_enable is set to 1

ERROR

APB4 Write Strobes

Unaligned Transfers

pstrb_asserted_for_invalid_byte_in_unaligned_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus & 3.2 Write strobes

PSTRB should be correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled

Checks if PSTRB is correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled.

PSTRB is correctly asserted based on the address alignment

PSTRB is not correctly asserted based on the address alignment

Passive Master, Active & Passive Slave

Group: APB4
Default severity: ERROR
Applicable for APB4 systems when unaligned address support is enabled using svt_apb_configuration :: unaligned_address_support configuration.

ERROR

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APB SVT OVM Documentation - Protocol Checks Defined in VIP

Product: amba_svt - Protocol Checks Details:

All Group Sub Group Protocol Check Instance name Reference Description Check Intent Pass Condition Fail Condition Applicable Device Type Additional Information Error Category Protocol Check Class

VIP Smartsearch

APB SVT OVM Documentation - Protocol Checks Defined in VIP

Product: amba_svt - Protocol Checks Details:

Show/Hide All Group Sub Group Protocol Check Instance name Reference Description Check Intent Pass Condition Fail Condition Applicable Device Type Additional Information Error Category Protocol Check Class

All Group Sub Group Protocol Check Instance name Reference Description Check Intent Pass Condition Fail Condition Applicable Device Type Additional Information Error Category Protocol Check Class