VIP Smartsearch

X
  • VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.

  • How to download VIP smartsearch?

    1. Get VIP Smartsearch (Available as a seperate run file).
    2. Set environment variable 
      DESIGNWARE_HOME
      to required designware home location where VIP Smartsearch should be downloaded.
    3. Run 
      vip_smartsearch_<version>.run
      file.
      VIP Smartsearch will be downloaded to the location 
      $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

  • How to install VIP Smartsearch?

    Please refer to the file 
    VIP_Smartsearch_installation_and_usage_guide.pdf
    in 
    $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
    for installation steps.

  • Customer Support

    For more details about VIP smartsearch tool, contact support_center@synopsys.com.
    Mention your queries along with below details and send email to above email id.
    Product: Verification IP
    Sub Product: <vip_title>
    Tool: VIP Smartsearch
13 August 2024, Copyright © 2024 Synopsys, Inc.

APB SVT UVM Documentation - Sequence Page

Comprehensive Inheritance diagram for sequence classes:

Summary of Sequences defined in APB SVT UVM Documentation:

Product Base Group
amba_svt Ungrouped Sequences

Product: amba_svt - Sequence Details:

Sequence Group Sequences Sequences Description
default svt_apb_directed_tlm_generic_payload_sequence This sequence executes the UVM TLM Generic Payload Transaction in its ~m_gp~ property and returns once the response has been received.

The GP instance is not randomized before being sent to the sequencer.

 --
default svt_apb_master_base_sequence This sequence raises/drops objections in the pre/post_body so that root sequences raise objections but subsequences do not. All other master sequences in the collection extend from this base sequence. --
default apb_master_unalinged_write_read_data_compare_sequence This sequence generates alternate write and read transactions, with address, data and pstrb not randomized for read. This sequence can also be used for 64Bit address and Data width --
default apb_master_write_read_data_compare_sequence This sequence generates alternate write and read transactions, with address, data and pstrb not randomized for read. This sequence can also be used for 64Bit address and Data width --
default svt_apb_master_blocking_write_read_addr_sequence This sequence generates alternate write and read transactions for minimum, middle and maximum address values to traverse the addr range. --
default svt_apb_master_blocking_write_read_all_slave_data_sequence This sequence generates alternate write and read transactions for all existing slaves. The min, mid and max data values are written and read for each slave . --
default svt_apb_master_random_sequence This sequence generates random master transactions. --
default svt_apb_master_read_xact_sequence This sequence generates a single random read transaction. addr
Address to be read

default svt_apb_master_write_xact_sequence This sequence generates a single random write transaction. addr
Address to be written

data
Data to be written

default svt_apb_tlm_gp_to_apb_sequence This layering sequence converts TLM GP transactions into APB transaction(s) and sends them out on the driver. The sequence gets TLM GP transactions from the tlm_gp_seq_item_port on the parent sequencer. --
default svt_apb_slave_base_sequence This base sequence obtains the configuration from the sequencer during the pre_body callback. It does not raise or drop objections because slave sequences are reactive, and so are always running.

Sequencer: Slave agent sequencer

 --
default svt_apb_slave_memory_sequence This sequence generates memory responses to slave requests. This sequence gets the slave request from slave sequencer, randomizes the response, and then either updates the internal memory for write transations or updates the transaction with memory data for read transactions. If the requested address is outside of the configured bounds for the memory then the slave will return with a pslverr response.

This sequence runs forever, and so is not registered with the slave sequence library.

 --
default svt_apb_slave_random_response_sequence Abstract: class svt_apb_slave_random_response_sequence defines a sequence class that provides random slave response. The sequence receives a response object of type svt_apb_slave_transaction, from slave sequencer. The sequence class then randomizes the response with constraints and provides it to the slave driver within the slave agent. --
default svt_apb_slave_tlm_response_sequence This sequence is used as Reactive seuqnce which translates slave transactions into corresponding AMBA-PV extended TLM Generic Payload Transactions and forwards it via the resp_socket socket for fulfillment by an AMBA-PV Slave. The response returned by the socket is then sent back to the driver.

Automatically configured as the run_phase default sequence for every instance of the svt_apb_slave_sequencer if the use_pv_socket property in the port configuration is TRUE

 --
default svt_apb_system_base_sequence This sequence creates a reporter reference active_participating_slave_index
Initiating Slave index *
participating_slave_index
Initiating Slave index *
default svt_apb_master_random_transfer_sequence Abstract: svt_apb_master_random_transfer_sequence defines a sequence in which random APB transactions are issued and based on config_db flags and other values performs the self checks and necessary operations. Sequence is generated using `svt_xvm_do_on_with macros.

Execution phase: main_phase Sequencer: System sequencer

 --
default svt_apb_random_slave_write_transfer_with_random_pstrb_sequence Abstract: svt_apb_random_slave_write_transfer_with_random_pstrb_sequence defines a sequence in which a APB WRITE is followed by a APB READ to the same address and data integrity check is performed.

Execution phase: main_phase Sequencer: System sequencer

 sequence_length
sequence_length



13 August 2024, Copyright © 2024 Synopsys, Inc.