How to download VIP smartsearch?
DESIGNWARE_HOMEto required designware home location where VIP Smartsearch should be downloaded.
vip_smartsearch_<version>.runfile.
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
How to install VIP Smartsearch?
Please refer to the fileVIP_Smartsearch_installation_and_usage_guide.pdfin
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>for installation steps.
Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.Macros defined for AXI SVT OVM Documentation:
AMBA User Modifiable Macros
AMBA User Non-Modifiable Macros
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6
|
|
|
1
|
|
|
interconnect_env
|
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|
16
|
|
|
256
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
|
|
2
|
|
|
2
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|
4
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4
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3
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5
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|
4
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3
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2
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2
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|
2
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|
|
4
|
|
|
8
|
|
|
16
|
|
|
4
|
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT || xact.coherent_xact_type == svt_axi_transaction::WRITEBACK || xact.coherent_xact_type == svt_axi_transaction::READONCE ) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE || `ifdef SVT_ACE5_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH || xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH || `endif xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE || xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE || xact.coherent_xact_type == svt_axi_transaction::READUNIQUE || xact.coherent_xact_type == svt_axi_transaction::READCLEAN || xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY || xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED || xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID|| xact.coherent_xact_type == svt_axi_transaction::READONCE ) ) |
|
|
((xact.coherent_xact_type == svt_axi_master_transaction::READUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::CLEANUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::CLEANINVALID)|| (xact.coherent_xact_type == svt_axi_master_transaction::WRITEUNIQUE) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::MAKEINVALID)|| (xact.coherent_xact_type == svt_axi_master_transaction::MAKEUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::WRITELINEUNIQUE) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHARED) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHAREDPERSIST) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READONCECLEANINVALID) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READONCEMAKEINVALID) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READCLEAN)|| (xact.coherent_xact_type == svt_axi_master_transaction::READSHARED)|| (xact.coherent_xact_type == svt_axi_master_transaction::READNOTSHAREDDIRTY) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READCLEAN)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READSHARED)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READNOTSHAREDDIRTY) ) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCE) && (snoop.snoop_xact_type != svt_axi_snoop_transaction::MAKEINVALID) ) |
|
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2
| |
if define SVT_AXI_LOCK_WIDTH=1, also define SVT_AXI_LOCK_WIDTH_AS_ONE due to compilation warnings
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0.01
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|
|
0.01
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|
|
16
|
|
|
10
|
|
|
|
|
6
|
|
|
6
|
|
|
8
|
|
|
4
|
|
|
|
|
4
|
|
|
|
|
64
|
|
|
128
|
|
|
64
|
|
|
6
|
|
|
6
|
|
|
8
|
|
|
4
|
|
|
16
|
|
|
4
|
|
|
10
|
|
|
32
|
|
|
64
|
|
|
10
|
|
|
16
|
|
|
|
|
10
|
|
|
16
|
|
|
8
|
|
|
1024
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|
|
250
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|
|
8
|
|
|
|
|
16
|
|
|
|
|
16
|
|
|
|
|
16
|
|
|
|
|
16
|
|
|
8
|
|
|
8
|
|
|
16
|
|
|
1
|
|
|
32
|
|
|
20
|
|
|
9
|
|
|
4
|
|
|
1024
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|
|
4
|
|
|
128
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|
|
10
|
|
|
128
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|
|
|
|
|
|
|
|
|
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16
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|
|
4
|
|
|
8
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|
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1000
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8192
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|
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64
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|
|
64
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|
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256
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1
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|
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2
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(4*CEIL(SVT_AXI_MAX_DATA_WIDTH,128))
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16
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|
|
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|
4
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|
|
128
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|
|
4
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|
|
8
|
|
|
16
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|
|
16
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|
|
8
|
|
|
16
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|
|
4
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|
|
16
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|
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1
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|
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|
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1000
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8192
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|
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8
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|
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|
|
16
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|
|
0
|
|
|
0
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|
|
3
|
|
|
0
|
|
|
0
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|
|
0
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|
|
3
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|
|
0
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|
|
1
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|
|
0
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0.01
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|
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0.01
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256
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|
((SVT_AXI_MAX_DATA_WIDTH/8)> 8)?(8):(SVT_AXI_MAX_DATA_WIDTH/8)
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4
|
|
|
ACE_VERSION_1_0
| |
Default value of port configuration attribute ace_version. User can change this value to ACE_VERSION_2_0 to use ACE5 features, along with defining compile time macro SVT_ACE5_ENABLE.
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|
AXI3
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3
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4
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10
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10
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10
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|
4
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|
4
|
|
|
3
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|
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0.01
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|
|
0.01
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|
|
5
|
|
|
11
|
|
|
1
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|
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1
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|
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1
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1
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|
|
3
|
|
|
2
|
|
|
|
|
3
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|
|
3
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|
|
1
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|
|
1
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|
|
1
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|
|
3
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|
|
3
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|
|
1
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1
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3
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3
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1
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1
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3
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3
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3
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3
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3
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1
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1
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1
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3
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3
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1
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1
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|
|
3
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|
|
3
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3
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|
|
3
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3
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|
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1
|
|
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1
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|
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|
|
12
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|
|
100000
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|
|
|
svt_axi_slave_agent
|
|
|
((dividend / divisor) + ((dividend % divisor) != 0)) |
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|
|
`define var``_``val |
|
|
`ifdef SVT_UVM_TECHNOLOGY reporter `elsif SVT_OVM_TECHNOLOGY reporter `else log `endif |
|
|
32
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|
1
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|
|
2
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
3
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|
|
2
|
|
|
2
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|
|
1
|
|
|
0
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
128
|
|
|
|
|
|
|
|
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
2
|
|
|
15
|
|
|
7
|
|
|
11
|
|
|
14
|
|
|
6
|
|
|
10
|
|
|
0
|
|
|
1
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
11
|
|
|
15
|
|
|
15
|
|
|
11
|
|
|
10
|
|
|
14
|
|
|
14
|
|
|
10
|
|
|
1
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
7
|
|
|
7
|
|
|
15
|
|
|
15
|
|
|
6
|
|
|
6
|
|
|
14
|
|
|
14
|
|
|
|
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) ADDR('h%0x) SECURE('h%0h) RESP('h%0x)} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.port_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.snoop_xact_type.name:"null"), ((xact != null)?xact.snoop_addr:0), ((xact != null)?!xact.snoop_prot[1]:0), ((xact != null)?{xact.get_crresp_value()}:0)) |
|
|
0
|
|
|
( ( (sys_cfg.use_recommended_coherent_to_snoop_map == 1) && (SVT_AXI_RECOMMENDED_SNOOP_XACT(xact,snoop)) ) || ( (sys_cfg.use_recommended_coherent_to_snoop_map == 0) && (xact.get_xact_type() == svt_axi_master_transaction::COHERENT) && ( (SVT_AXI_LEGAL_SNOOP_MAPPING(xact,snoop)) ) ) ) |
|
|
1
|
|
|
4
|
|
|
2
|
|
|
0
|
|
|
1
|
|
|
3
|
|
|
17
|
|
|
8
|
|
|
9
|
|
|
10
|
|
|
11
|
|
|
12
|
|
|
13
|
|
|
14
|
|
|
15
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
5
|
|
|
6
|
|
|
7
|
|
|
16
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
13
|
|
|
|
3'b000
|
|
|
3'b101
|
|
|
3'b100
|
|
|
3'b111
|
|
|
3'b110
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
3
|
|
|
2
|
|
|
2
|
|
|
0
|
|
|
1
|
|
|
(xact_type == COHERENT) && ( (coherent_xact_type == READNOSNOOP) || (coherent_xact_type == READONCE) || (coherent_xact_type == READONCECLEANINVALID) || (coherent_xact_type == READONCEMAKEINVALID) || (coherent_xact_type == READSHARED) || (coherent_xact_type == READCLEAN) || (coherent_xact_type == READNOTSHAREDDIRTY) || (coherent_xact_type == READUNIQUE) || (coherent_xact_type == CLEANUNIQUE) || (coherent_xact_type == MAKEUNIQUE) || (coherent_xact_type == CLEANSHARED) || (coherent_xact_type == CLEANINVALID) || (coherent_xact_type == MAKEINVALID) || (coherent_xact_type == DVMCOMPLETE) || (coherent_xact_type == DVMMESSAGE) || (coherent_xact_type == READBARRIER) || (coherent_xact_type == CLEANSHAREDPERSIST) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER) ) |
|
|
2
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
9
|
|
|
8
|
|
|
30
|
|
|
6
|
|
|
31
|
|
|
11
|
|
|
12
|
|
|
19
|
|
|
10
|
|
|
7
|
|
|
35
|
|
|
13
|
|
|
3
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
2
|
|
|
5
|
|
|
25
|
|
|
26
|
|
|
27
|
|
|
18
|
|
|
20
|
|
|
17
|
|
|
34
|
|
|
21
|
|
|
33
|
|
|
16
|
|
|
14
|
|
|
37
|
|
|
32
|
|
|
15
|
|
|
24
|
|
|
23
|
|
|
36
|
|
|
(xact_type == COHERENT) && ( (coherent_xact_type == WRITENOSNOOP) || (coherent_xact_type == WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (coherent_xact_type == WRITEUNIQUEPTLSTASH) || (coherent_xact_type == WRITEUNIQUEFULLSTASH) || (coherent_xact_type == STASHONCEUNIQUE) || (coherent_xact_type == STASHONCESHARED) || (coherent_xact_type == STASHTRANSLATION) || (coherent_xact_type == CMO) || (coherent_xact_type == WRITEPTLCMO) || (coherent_xact_type == WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (coherent_xact_type == WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (coherent_xact_type == PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (coherent_xact_type == WRITEZERO) || `endif `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (coherent_xact_type == WRITENOSNPFULL) || `endif `endif (coherent_xact_type == WRITELINEUNIQUE) || (coherent_xact_type == WRITEBACK) || (coherent_xact_type == WRITECLEAN) || (coherent_xact_type == WRITEBARRIER) || (coherent_xact_type == WRITEEVICT) || (coherent_xact_type == EVICT) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || `endif (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) || (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT) || (xact.coherent_xact_type == svt_axi_transaction::EVICT) ) |
|
|
0
|
|
|
3'b010
|
|
|
3'b011
|
|
|
3'b000
|
|
|
3'b001
|
|
|
'b11
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
3
|
|
|
14
|
|
|
13
|
|
|
12
|
|
|
11
|
|
|
10
|
|
|
9
|
|
|
8
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
(((cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI3 || cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI4)&& (xact.get_xact_type() != svt_axi_transaction::IDLE)) || ((cfg.get_axi_interface_type() == svt_axi_port_configuration::ACE_LITE || cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI_ACE) && `ifdef SVT_ACE5_ENABLE (xact.get_xact_type() == svt_axi_transaction::ATOMIC) || `endif (xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP || `ifdef SVT_ACE5_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO || xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEZERO || `endif `endif xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP ) ) ) ) |
|
|
'b01
|
|
|
|
|
17
|
|
|
1
|
|
|
11
|
|
|
10
|
|
|
8
|
|
|
9
|
|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::ENDED) `else xact.get_end_realtime() `endif |
|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::STARTED) `else xact.get_begin_realtime() `endif |
|
|
svt_axi_ic_modport
|
|
|
svt_axi_ic_modport
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
5
|
|
|
3
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
4
|
|
|
5
|
|
|
2
|
|
|
3
|
|
|
3'b110
|
|
|
3'b111
|
|
|
3'b100
|
|
|
3'b101
|
|
|
4
|
|
|
5
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
12
|
|
|
(obj.get_xact_type() == svt_axi_transaction::DATA_STREAM) |
|
|
((obj.xact_type == svt_axi_transaction::READ) || ((obj.xact_type == svt_axi_transaction::COHERENT) && ((obj.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (obj.coherent_xact_type == svt_axi_transaction::READONCE) || (obj.coherent_xact_type == svt_axi_transaction::READSHARED) || (obj.coherent_xact_type == svt_axi_transaction::READCLEAN) || (obj.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (obj.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (obj.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (obj.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (obj.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (obj.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (obj.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (obj.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (obj.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (obj.coherent_xact_type == svt_axi_transaction::READBARRIER ) ) ) ) |
|
|
((obj.xact_type == svt_axi_transaction::WRITE) || ((obj.xact_type == svt_axi_transaction::COHERENT) && ((obj.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (obj.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (obj.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || `endif (obj.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (obj.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (obj.coherent_xact_type == svt_axi_transaction::WRITEEVICT) || (obj.coherent_xact_type == svt_axi_transaction::EVICT) || (obj.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) ) ) `ifdef SVT_ACE5_ENABLE || ((obj.xact_type == svt_axi_transaction::ATOMIC) && ((obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_ADD) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_CLR) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_EOR) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SET) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SMAX) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SMIN) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_UMAX) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_UMIN) ) ) `endif ) |
|
|
1
|
|
|
2
|
|
|
2
|
|
|
3
|
|
|
3
|
|
|
1'b0
|
|
|
0
|
|
|
svt_axi_master_if
|
|
|
0
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
0
|
|
|
6
|
|
|
1
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
4
|
|
|
3
|
|
|
5
|
|
|
svt_axi_master_transaction_scenario
|
|
|
svt_axi_master_transaction
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
|
|
0
|
|
|
1
|
|
|
16
|
|
|
16
|
|
|
1
|
|
|
5
|
|
|
$sformatf("{OBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) COHERENT_XACT_TYPE(%0s) ID('h%0x) SECURE('d%0d) ADDR('h%0x) } ", ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.coherent_xact_type.name:"null"), ((xact != null)?xact.id:0), ((xact != null)?!xact.prot_type[1]:0), ((xact != null)?xact.addr:0)) |
|
|
1'b1
|
|
|
0
|
|
|
2
|
|
|
0
|
|
|
7
|
|
|
6
|
|
|
5
|
|
|
4
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
64
|
|
|
'b00
|
|
|
1
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) %0s PORT_NAME(%0s) TYPE(%0s)%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s}", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf("AUTO_GENERATED_XACT('b%0b)",xact.is_auto_generated)):""):""), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null && xact.xact_type == svt_axi_transaction::WRITE)?($sformatf(" WLAST('b%0b)",xact.is_last_write_data_beat)):""), ((xact != null) && (xact.xact_type == svt_axi_transaction::READ)?($sformatf(" RLAST('b%0b)",xact.is_last_read_data_beat)):""), ((xact != null && xact.get_transmitted_channel() == svt_axi_transaction::WRITE)?($sformatf(" DATA_BEFORE_ADDR('b%0b)",xact.data_before_addr)):""), ((xact != null)?((xact.xact_type == svt_axi_transaction::COHERENT)?{$sformatf(" COHERENT_XACT_TYPE(%0s)",xact.coherent_xact_type.name)}:""):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TID('h%0x)",xact.tid)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TDEST('h%0x)",xact.tdest)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" ID('h%0x)",xact.id)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" PROT_TYPE(%0s)",xact.prot_type.name)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" ADDR('h%0x)",xact.addr)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" BURST(%0s)",xact.burst_type.name)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" SIZE(%0s)",xact.burst_size.name)):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" LENGTH('d%0d)",xact.burst_length)):($sformatf(" LENGTH('d%0d)",xact.stream_burst_length))):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" CACHE_TYPE('d%0d)",xact.cache_type)):"")) |
|
|
3
|
|
|
4
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
'b100
|
|
|
|
|
$sformatf("%0s('d%0d) : {TYPE(%0s) ID('h%0x) ADDR('h%0x)}", SVT_DATA_UTIL_ARG_TO_STRING(function_name), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.id:0), ((xact != null)?xact.addr:0)) |
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) %0s PORT_NAME(%0s) TYPE(%0s)%0s%0s LENGTH('h%0h)%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf("AUTO_GENERATED_XACT('b%0b)",xact.is_auto_generated)):""):""), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" BURST(%0s)",xact.burst_type.name)):""):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" SIZE(%0s)",xact.burst_size.name)):""):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?xact.burst_length:xact.stream_burst_length):0), ((xact != null && xact.xact_type == svt_axi_transaction::WRITE)?($sformatf(" WLAST('b%0b)",xact.is_last_write_data_beat)):""), ((xact != null) && (xact.xact_type == svt_axi_transaction::READ)?($sformatf(" RLAST('b%0b)",xact.is_last_read_data_beat)):""), ((xact != null && xact.get_transmitted_channel() == svt_axi_transaction::WRITE)?($sformatf(" DATA_BEFORE_ADDR('b%0b)",xact.data_before_addr)):""), ((xact != null)?((xact.xact_type == svt_axi_transaction::COHERENT)?{$sformatf(" COHERENT_XACT_TYPE(%0s)",xact.coherent_xact_type.name)}:""):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" ID('h%0x)",xact.id)):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" SECURE('h%0h)",!xact.prot_type[1])):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" ADDR('h%0x)",xact.addr)):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" CACHE_TYPE('h%0h)",xact.cache_type)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TID('h%0x)",xact.tid)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TDEST('h%0x)",xact.tdest)):""), ((xact != null)?(xact.atomic_type==svt_axi_transaction::EXCLUSIVE)?" EXCL":"":""), ((xact != null)?((xact.get_begin_time()==-1)?"":($sformatf(" START_TIME(%0t)",xact.get_begin_realtime()))):""), ((xact != null)?((xact.get_end_time()==-1)?"":($sformatf(" END_TIME(%0t)",xact.get_end_realtime()))):"")) |
|
|
0
|
|
|
1
|
|
|
2
|
|
|
0
|
|
|
0
|
|
|
1
|
|
|
3
|
|
|
5
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
( (xact.get_xact_type() == svt_axi_master_transaction::COHERENT) && ( ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::WRITEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHARED) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHAREDPERSIST) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCECLEANINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCEMAKEINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::MAKEINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READCLEAN) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READCLEAN) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READNOTSHAREDDIRTY) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READNOTSHAREDDIRTY) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READSHARED) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::MAKEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::WRITELINEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) ) ) |
|
|
2
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
2
|
|
|
`define var``_``val |
|
|
0
|
|
|
3
|
|
|
1
|
|
|
svt_axi_slave_if
|
|
|
1
|
|
|
0
|
|
|
6
|
|
|
0
|
|
|
5
|
|
|
3
|
|
|
2
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
svt_axi_slave_transaction_scenario_gen_callbacks
|
|
|
svt_axi_slave_transaction_scenario_gen
|
|
|
svt_axi_slave_transaction_scenario
|
|
|
svt_axi_slave_transaction
|
|
|
4
|
|
|
'b10
|
|
|
16
|
|
|
1
|
|
|
2
|
|
|
4
|
|
|
8
|
|
|
0
|
|
|
1
|
|
|
5
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
9
|
|
|
8
|
|
|
14
|
|
|
15
|
|
|
13
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
7
|
|
|
|
|
128
|
|
|
16
|
|
|
512
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) BURST_LENGTH('d%0d) TID('h%0x) TDEST('h%0x)%0s%0s} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), (((xact != null) && (xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.stream_burst_length:0), ((xact != null)?xact.tid:0), ((xact != null)?xact.tdest:0), ((xact != null)?((xact.get_begin_time()==-1)?"":($sformatf(" START_TIME(%0t)",xact.get_begin_realtime()))):""), ((xact != null)?((xact.get_end_time()==-1)?"":($sformatf(" END_TIME(%0t)",xact.get_end_realtime()))):"")) |
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
3
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
7
|
|
|
4
|
|
|
1
|
|
|
8
|
|
|
5
|
|
|
2
|
|
|
9
|
|
|
6
|
|
|
3
|
|
|
0
|
|
|
2
|
|
|
4
|
|
|
7
|
|
|
6
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
0
|
|
|
0
|
|
|
4
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
5
|
|
|
3
|
|
|
2
|
|
|
0
|
|
|
6
|
|
|
1
|
|
|
'b101
|
|
|
3
|
|
|
4
|
|
|
2
|
|
|
0
|
|
|
5
|
|
|
1
|
|
|
'b111
|
|
|
1
|
|
|
1
|
|
|
7
|
|
|
1
|
|
|
|
|
`define SVT_AXI_VALID_MASTER_IDX_0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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`define SVT_AXI_VALID_SLAVE_IDX_0 |
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10
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12
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14
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15
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2,4,8,16
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0
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1
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2
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0
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0
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1
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16
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0
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3
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2
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5
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17
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4
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7
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6
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9
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18
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11
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10
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13
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19
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12
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15
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14
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8
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2
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0
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1
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1
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( ( ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) || (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE) ) && (this_xact.is_coherent_xact_dropped == 1) ) || ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) && ( (this_xact.ack_status == svt_axi_transaction::ACCEPT) || (this_xact.ack_status == svt_axi_transaction::ABORTED) ) ) || ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (SVT_AXI_IS_TRANSMITTED_CHANNEL_WRITE(this_xact)) && ( ( (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) || (this_xact.write_resp_status == svt_axi_transaction::ABORTED) ) ) ) || `ifdef SVT_ACE5_ENABLE ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (`SVT_AXI_IS_TRANSMITTED_CHANNEL_READ_WRITE(this_xact)) && ( ( (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) || (this_xact.write_resp_status == svt_axi_transaction::ABORTED) || (this_xact.atomic_read_data_status == svt_axi_transaction::ACCEPT) || (this_xact.atomic_read_data_status == svt_axi_transaction::ABORTED) ) ) ) || `endif ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (SVT_AXI_IS_TRANSMITTED_CHANNEL_READ(this_xact)) && ( ( (this_xact.data_status == svt_axi_transaction::ACCEPT) || (this_xact.data_status == svt_axi_transaction::ABORTED) ) ) ) ) |
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1
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2
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1
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3
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1
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1
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0
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0
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`ifdef SVT_UVM_TECHNOLOGY `uvm_object_utils(obj) `elsif SVT_OVM_TECHNOLOGY ovm_object_utils(obj) `endif |
|
|
Handle of maximum address width supported by each master
|
|
|
128
| |
Handles of infinite snoop response sequeunces running on each master
|
|
|
128
|
|
|
2
|
|
|
|
`ifdef SVT_AMBA_DATA_UTIL_ENABLE_INTERNAL_MESSAGING svt_debug(id, msg) `else do begin end while(0) `endif |
|
|
svt_err_check_stats
|
|
|
|
|
|
6
|
|
|
slave_0,slave_1,slave_2,slave_3,slave_4,slave_5
|
|
|
`ifdef SVT_AMBA_DATA_UTIL_ENABLE_INTERNAL_MESSAGING svt_verbose(id, msg) `else do begin end while(0) `endif |
|
|
|
|
2
|
|
|
`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COMPARE) begin if (!svt_axi_cache_compare_hook(this.__vmm_rhs, this.__vmm_image)) begin this.__vmm_status = 0; end end `endif | |
Add some customized logic to compare the actual memory elements
|
|
|
`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COPY) begin svt_axi_cache_copy_hook(this.__vmm_rhs); end `endif | |
Add some customized logic to copy the actual memory elements
|
|
|
(xact_type == COHERENT) && ( (coherent_xact_type == CLEANUNIQUE) || (coherent_xact_type == MAKEUNIQUE) || (coherent_xact_type == CLEANSHARED) || (coherent_xact_type == CLEANINVALID) || (coherent_xact_type == CLEANSHAREDPERSIST) || (coherent_xact_type == MAKEINVALID) ) |
|
|
28
|
|
|
29
|
|
|
0
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SVT_AXI_MASTER_DRIVE_SIGNAL(tdata,{SVT_AXI_MAX_TDATA_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_TDATA_WIDTH{1'b``disable_sig_val}},tdata_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tstrb,{SVT_AXI_TSTRB_WIDTH{1'b``enable_sig_val}} ,{SVT_AXI_TSTRB_WIDTH{1'b``disable_sig_val}} ,tstrb_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tkeep,{SVT_AXI_TKEEP_WIDTH{1'b``enable_sig_val}} ,{SVT_AXI_TKEEP_WIDTH{1'b``disable_sig_val}} ,tkeep_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tid ,{SVT_AXI_MAX_TID_WIDTH{1'b``enable_sig_val}} ,{SVT_AXI_MAX_TID_WIDTH{1'b``disable_sig_val}} ,tid_enable ) SVT_AXI_MASTER_DRIVE_SIGNAL(tdest,{SVT_AXI_MAX_TDEST_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_TDEST_WIDTH{1'b``disable_sig_val}},tdest_enable) `ifdef SVT_AXI5_STREAM_CHECK_TYPE_INTERNAL_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(tdatachk,{CEIL(SVT_AXI_MAX_TDATA_WIDTH,8){1'b``enable_sig_val}},{CEIL(SVT_AXI_MAX_TDATA_WIDTH,8){1'b``disable_sig_val}},tdata_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tstrbchk,{CEIL(SVT_AXI_TSTRB_WIDTH,8){1'b``enable_sig_val}} ,{CEIL(SVT_AXI_TSTRB_WIDTH,8){1'b``disable_sig_val}} ,tstrb_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tkeepchk,{CEIL(SVT_AXI_TKEEP_WIDTH,8){1'b``enable_sig_val}} ,{CEIL(SVT_AXI_TKEEP_WIDTH,8){1'b``disable_sig_val}} ,tkeep_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tidchk ,{CEIL(SVT_AXI_MAX_TID_WIDTH,8){1'b``enable_sig_val}} ,{CEIL(SVT_AXI_MAX_TID_WIDTH,8){1'b``disable_sig_val}} ,tid_enable ) SVT_AXI_MASTER_DRIVE_SIGNAL(tdestchk,{CEIL(SVT_AXI_MAX_TDEST_WIDTH,8){1'b``enable_sig_val}},{CEIL(SVT_AXI_MAX_TDEST_WIDTH,8){1'b``disable_sig_val}},tdest_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tuserchk,{CEIL(SVT_AXI_MAX_TUSER_WIDTH,8){1'b``enable_sig_val}},{CEIL(SVT_AXI_MAX_TUSER_WIDTH,8){1'b``disable_sig_val}},tuser_enable) `endif SVT_AXI_MASTER_DRIVE_SIGNAL(tuser,{SVT_AXI_MAX_TUSER_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_TUSER_WIDTH{1'b``disable_sig_val}},tuser_enable) |
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`SVT_DATA_UTIL_IS_VALID_SUFFIX_INT_W_CONST(master_cfg[i].``param, ic_cfg.slave_cfg[i].``param, $psprintf(" based on master_cfg['d%0d].``param('d%0d) and ic_cfg.slave_cfg['d%0d].``param('d%0d) which should match", i,master_cfg[i].``param,i,ic_cfg.slave_cfg[i].``param)) |
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`SVT_DATA_UTIL_IS_VALID_SUFFIX_INT_W_CONST(slave_cfg[i].``param, ic_cfg.master_cfg[i].``param, $psprintf(" based on slave_cfg['d%0d].``param('d%0d) and ic_cfg.master_cfg['d%0d].``param('d%0d) which should match", i,master_cfg[i].``param,i,ic_cfg.slave_cfg[i].``param)) |
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0
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`ifdef SVT_VMM_TECHNOLOGY if (do_what == DO_COMPARE) begin if (!svt_axi_fifo_mem_compare_hook(this.__vmm_rhs, this.__vmm_image)) begin this.__vmm_status = 0; end end `endif | |
Add some customized logic to compare the actual memory elements
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`ifdef SVT_VMM_TECHNOLOGY if (do_what == DO_COPY) begin svt_axi_fifo_mem_copy_hook(this.__vmm_rhs); end `endif | |
Add some customized logic to copy the actual memory elements
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`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::ENDED) `else xact.get_end_realtime() `endif |
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`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::STARTED) `else xact.get_begin_realtime() `endif |
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((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
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((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
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`ifdef SVT_UVM_TECHNOLOGY svt_axi_ic_snoop_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_ic_snoop_input_port_type `else svt_axi_ic_snoop_input_port_type `endif |
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port_cfg.axi_interface_type
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(xact.xact_type == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || `endif (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER) ) |
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(xact.xact_type == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNPFULL) || `endif (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || (xact.coherent_xact_type == svt_axi_transaction::CMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEZERO) || `endif `endif (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) || (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (xact.coherent_xact_type == svt_axi_transaction::EVICT) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT) ) |
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if (SVT_AXI_MASTER_IS_SIGNAL_ENABLED(axi_signal_enable)) prop_name = observed_val; else prop_name = default_val; |
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((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
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if (suspended_snoop_xacts.size())begin driver_mp.axi_master_cb.acready <= 1'b0; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.acreadychk <= 1'b1; end else begin driver_mp.axi_master_cb.acready <= val; end |
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if (SVT_AXI_MASTER_IS_SIGNAL_ENABLED(sig_enable)) driver_mp.axi_master_cb.sig_name <= enable_sig_val; else driver_mp.axi_master_cb.sig_name <= disable_sig_val; |
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if (SVT_AXI_MASTER_IS_SIGNAL_ENABLED(axi_signal_enable)) begin if(!($cast(prop_name,observed_val))) svt_fatal("Failed when attempting to cast"); end else prop_name = default_val; |
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`ifdef SVT_UVM_TECHNOLOGY svt_axi_master_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_master_input_port_type `else svt_axi_master_input_port_type `endif |
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`ifdef SVT_UVM_TECHNOLOGY svt_axi_master_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_master_input_port_type `else svt_axi_master_input_port_type `endif |
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(cfg.axi_interface_type != svt_axi_port_configuration::AXI4_LITE) && ( (cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || (cfg.axi_signal == 1) ) |
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((xact.xact_type == svt_axi_transaction::READ) || (( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER)))) |
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xact_event_pool = xact.get_event_pool(); xact_ev = xact_event_pool.get(event_name); xact_ev.wait_trigger(); |
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ovm_event_pool xact_event_pool; ovm_event xact_ev; |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && (cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable)) begin observed_``sg_name = 1'b0; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
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((xact.xact_type == svt_axi_transaction::WRITE) || ((( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE)|| (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE)|| `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || (xact.coherent_xact_type == svt_axi_transaction::CMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEZERO) || `endif `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNPFULL) || `endif `endif (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK)|| (xact.coherent_xact_type == svt_axi_transaction::EVICT)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER))))) |
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8
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@groupname
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8
| |
@groupname
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1
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32
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4
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16
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`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COMPARE) begin if (!svt_axi_passive_cache_compare_hook(this.__vmm_rhs, this.__vmm_image)) begin this.__vmm_status = 0; end end `endif | |
Add some customized logic to compare the actual memory elements
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`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COPY) begin svt_axi_passive_cache_copy_hook(this.__vmm_rhs); end `endif | |
Add some customized logic to copy the actual memory elements
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0
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0
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if (SVT_AXI_PORT_MONITOR_IS_SIGNAL_ENABLED(axi_signal_enable)) prop_name = observed_val; else prop_name = default_val; |
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if (SVT_AXI_PORT_MONITOR_IS_SIGNAL_ENABLED(axi_signal_enable)) begin if(!($cast(prop_name,observed_val))) svt_error("SVT_AXI_PORT_MONITOR_ENUM_ASSIGN_SIGNAL_VAL",{"Failed to cast in macro for signal observed_val to prop_name"}); end else prop_name = default_val; |
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(cfg.axi_interface_type != svt_axi_port_configuration::AXI4_LITE) && ( (cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || (cfg.axi_signal_enable == 1) ) |
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(xact.transmitted_channel == svt_axi_transaction::READ) |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && (cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable)) begin observed_``sg_name = 1'b0; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
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(xact.transmitted_channel == svt_axi_transaction::WRITE) |
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driver_mp.axi_master_cb.araddr <= {SVT_AXI_MAX_ADDR_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.arvmidext <= {SVT_AXI_MAX_VMIDEXT_WIDTH{1'b``enable_sig_val}}; SVT_AXI_MASTER_DRIVE_SIGNAL(arid,{SVT_AXI_MAX_ID_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_ID_WIDTH{1'b``disable_sig_val}},arid_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arlen,{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``disable_sig_val}},arlen_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arsize,{SVT_AXI_SIZE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_SIZE_WIDTH{1'b``disable_sig_val}},arsize_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arburst,{SVT_AXI_BURST_WIDTH{1'b``enable_sig_val}},{SVT_AXI_BURST_WIDTH{1'b``disable_sig_val}},arburst_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arlock,{SVT_AXI_LOCK_WIDTH{1'b``enable_sig_val}},{SVT_AXI_LOCK_WIDTH{1'b``disable_sig_val}},arlock_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arcache,{SVT_AXI_CACHE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_CACHE_WIDTH{1'b``disable_sig_val}},arcache_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arprot,{SVT_AXI_PROT_WIDTH{1'b``enable_sig_val}},{SVT_AXI_PROT_WIDTH{1'b``disable_sig_val}},arprot_enable) `ifdef SVT_AXI_QVN_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(arvnet,{`SVT_AXI_QVN_ARVNET_WIDTH{1'b``enable_sig_val}},{`SVT_AXI_QVN_ARVNET_WIDTH{1'b``disable_sig_val}},qvn_enable) `endif `ifdef SVT_ACE5_ENABLE driver_mp.axi_master_cb.armpam <= {SVT_AXI_MAX_MPAM_WIDTH{1'b``enable_sig_val}}; SVT_AXI_MASTER_DRIVE_SIGNAL(aridunq,1'b``enable_sig_val,1'b``disable_sig_val,unique_id_enable) driver_mp.axi_master_cb.arloop <= {SVT_AXI_MAX_LOOP_R_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.arnsaid <= {SVT_AXI_MAX_NSAID_WIDTH{1'b``enable_sig_val}}; if(cfg.rdata_chunking_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(archunken,1'b``enable_sig_val,1'b``disable_sig_val,rdata_chunking_enable) `endif if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) || (cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) || (cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE)) begin if(cfg.arqos_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arqos,{SVT_AXI_QOS_WIDTH{1'b``enable_sig_val}},{SVT_AXI_QOS_WIDTH{1'b``disable_sig_val}},arqos_enable) if(cfg.arregion_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arregion,{SVT_AXI_REGION_WIDTH{1'b``enable_sig_val}},{SVT_AXI_REGION_WIDTH{1'b``disable_sig_val}},arregion_enable) end else begin driver_mp.axi_master_cb.arqos <= SVT_AXI_QOS_WIDTH'bz; driver_mp.axi_master_cb.arregion <= SVT_AXI_REGION_WIDTH'bz; end if (cfg.aruser_enable) begin driver_mp.axi_master_cb.aruser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.aruserchk <= ~{CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.aruser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.aruserchk <= {CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'bz}}; end |
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driver_mp.axi_slave_cb.rid <= {SVT_AXI_MAX_ID_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rresp <= {SVT_AXI_RESP_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rdata <= {SVT_AXI_MAX_DATA_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rlast <= 1'b``val; `ifdef SVT_ACE5_ENABLE if(cfg.unique_id_enable) driver_mp.axi_slave_cb.ridunq <= {1'b``val}; if(cfg.rdata_chunking_enable)begin driver_mp.axi_slave_cb.rchunkstrb <= {SVT_AXI_MAX_CHUNK_STROBE_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rchunknum <= {SVT_AXI_MAX_CHUNK_NUM_WIDTH{1'b``val}}; end if(cfg.enable_loopback_signaling)begin driver_mp.axi_slave_cb.rloop <= {SVT_AXI_MAX_LOOP_R_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.bloop <= {SVT_AXI_MAX_LOOP_W_WIDTH{1'b``val}}; end `endif if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL || cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_DATA) driver_mp.axi_slave_cb.rdatachk <= {CEIL(SVT_AXI_MAX_DATA_WIDTH,8){1'b``val}}; if(cfg.ruser_enable) begin driver_mp.axi_slave_cb.ruser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'b``val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.ruserchk <= ~{CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'b``val}}; end else begin driver_mp.axi_slave_cb.ruser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.ruserchk <= {CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'bz}}; end |
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EXCLUDE_UNSTARTED_XACT
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((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
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(((active_xact_queue.size() >= cfg.num_outstanding_xact) && (cfg.num_outstanding_xact != -1)) || ((active_read_xact_count >= cfg.num_read_outstanding_xact) && (cfg.num_outstanding_xact == -1))) |
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(((active_xact_queue.size() >= cfg.num_outstanding_xact) && (cfg.num_outstanding_xact != -1)) || ((active_write_xact_count >= cfg.num_write_outstanding_xact) && (cfg.num_outstanding_xact == -1))) |
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(((active_xact_queue.size() > cfg.num_outstanding_xact) && (cfg.num_outstanding_xact != -1)) || ((active_write_xact_count > cfg.num_write_outstanding_xact) && (cfg.num_outstanding_xact == -1))) |
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(cfg.axi_interface_type != svt_axi_port_configuration::AXI4_LITE) && ( (cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || (cfg.axi_signal == 1) ) |
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((xact.xact_type == svt_axi_transaction::READ) || (( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER)))) |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && ((cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable) || (!(cfg_enable)))) begin driver_mp.axi_slave_cb.``sg_name <= width'bZ; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4_LITE) && lite_disable) begin driver_mp.axi_slave_cb.``sg_name <= width'bZ; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI3) && axi3_disable) begin driver_mp.axi_slave_cb.``sg_name <= width'bZ; end else begin driver_mp.axi_slave_cb.``sg_name <= val; end |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && ((cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable) || (!(cfg_enable)))) begin observed_``sg_name = val; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4_LITE) && lite_disable) begin observed_``sg_name = val; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI3) && axi3_disable) begin observed_``sg_name = val; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && (cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable)) begin observed_``sg_name = 1'b0; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
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((xact.xact_type == svt_axi_transaction::WRITE) || ((( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE)|| `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || (xact.coherent_xact_type == svt_axi_transaction::CMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEZERO) || `endif `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNPFULL) || `endif `endif (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE)|| (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK)|| (xact.coherent_xact_type == svt_axi_transaction::EVICT)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER))))) |
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`ifdef SVT_UVM_TECHNOLOGY svt_axi_snoop_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_snoop_input_port_type `else svt_axi_snoop_input_port_type `endif |
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(master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (master_xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (master_xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (master_xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (master_xact.coherent_xact_type == svt_axi_transaction::READONCE) || (master_xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) ) |
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(master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (master_xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (master_xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (master_xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (master_xact.coherent_xact_type == svt_axi_transaction::READONCE) || (master_xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (master_xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (master_xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (master_xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (master_xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || (master_xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) ) |
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( /** Either this item has not been associated yet to any slave transaction, or if */ /** it is associated, then the slave_port_id should match that of the slave transaction */ /** since a single master transaction will not get routed to two different slaves */ /**((item.slave_port_id.size() == 0) || (slave_xact.port_cfg.port_id inside {item.slave_port_id})) && */ /** The exp_slave_port_id is set in the sys_xact based on the memory map. Unless slaves with */ /** overlapping addr is set (in which case the xact could be routed to another slave port), */ /** item.exp_slave_port_id and slave_xact.port_cfg.port_id should match */ (axi_sys_common_cfg.allow_slaves_with_overlapping_addr || is_amba_system_monitor || (slave_xact.port_cfg.port_id inside {item.exp_slave_port_id})) && ( ( ( (slave_xact.transmitted_channel == svt_axi_transaction::WRITE) && !( (slave_xact.converted_xact_type == svt_axi_transaction::COHERENT) && (slave_xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) ) && ( (item.master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (item.master_xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || (item.master_xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) ) ) && !item.is_xact_fully_mapped && (axi_sys_common_cfg.id_based_xact_correlation_enable && (!((item.master_xact.port_cfg.id_based_xact_correlation_enable && slave_xact.port_cfg.id_based_xact_correlation_enable) || !is_find_first_check_done) || (source_master_id == axi_sys_common_cfg.source_master_id_wu_wlu_xmit_to_slaves && axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type != svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) || ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (axi_sys_common_cfg.is_master_id_and_slave_id_correlated(item.master_xact,slave_xact)) ) ) ) ) || ( ( ( !( ( (item.master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (item.master_xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (item.master_xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (item.master_xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (item.master_xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) ) ) || ( (slave_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (slave_xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (slave_xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (slave_xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) ) ) ) && (item.master_xact.transmitted_channel == slave_xact.transmitted_channel) ) || ( (item.master_xact.converted_xact_type == slave_xact.converted_xact_type) && /** coherent_xact_type will match only when xact_type is COHERENT */ ( (item.master_xact.converted_xact_type != svt_axi_transaction::COHERENT) || (item.master_xact.coherent_xact_type == slave_xact.coherent_xact_type ) ) ) ) && !item.is_xact_fully_mapped && ( !axi_sys_common_cfg.id_based_xact_correlation_enable || !((item.master_xact.port_cfg.id_based_xact_correlation_enable && slave_xact.port_cfg.id_based_xact_correlation_enable) || !is_find_first_check_done) || ( ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (axi_sys_common_cfg.is_master_id_and_slave_id_correlated(item.master_xact,slave_xact)) ) || ( ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::STATIC_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (source_master_id == axi_sys_common_cfg.get_source_master_id_at_slave_from_master_id(item.master_xact.id,item.master_xact.port_cfg.port_id)) ) || ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::DYNAMIC_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (source_master_id == item.master_xact.dynamic_source_master_id_xmit_to_slaves) ) && (source_master_xact_id == axi_sys_common_cfg.get_master_xact_id_at_slave_from_master_id(item.master_xact.id,item.master_xact.port_cfg.port_id)) ) || ((item.master_xact.port_cfg.is_source_master_id_and_dest_slave_id_same == 1) && (slave_xact.id == item.master_xact.id)) ) ) ) ) || /** Dirty data may be written after all the other data is written in which case is_xact_fully_mapped will be set */ /** so don't check for is_xact_fully_mapped for dirty data write */ ( SVT_AXI_SYSTEM_MONITOR_IS_DIRTY_DATA_XACT(item.master_xact) && (slave_xact.transmitted_channel == svt_axi_transaction::WRITE) && (axi_sys_common_cfg.id_based_xact_correlation_enable && (!((item.master_xact.port_cfg.id_based_xact_correlation_enable && slave_xact.port_cfg.id_based_xact_correlation_enable) || !is_find_first_check_done) || (source_master_id == axi_sys_common_cfg.source_interconnect_id_xmit_to_slaves && axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type != svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES ) || ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (axi_sys_common_cfg.is_master_id_and_slave_id_correlated(item.master_xact,slave_xact)) ) ) ) ) ) && (SVT_AXI_GET_XACT_START_TIME(item.master_xact) <= SVT_AXI_GET_XACT_START_TIME(slave_xact)) && (item.master_xact.addr_status != svt_axi_transaction::ABORTED) && (item.master_xact.data_status != svt_axi_transaction::ABORTED) && (item.master_xact.write_resp_status != svt_axi_transaction::ABORTED) && ( ( (is_exact_match && (item.master_xact.cache_type[1] == 1'b0)) && (get_amba_min_byte_address(.xact(item.master_xact), .convert_to_global_addr(1), /** If tagged master and untagged slave is supported, get tagged address from master only if slave also uses it */ .use_tagged_addr(~axi_sys_common_cfg.support_tagged_master_and_untagged_slave), .convert_to_slave_addr(1), .requester_name(get_master_xact_requester_name(item.master_xact))) == slave_xact_min_addr) && (get_amba_max_byte_address(.xact(item.master_xact),.convert_to_global_addr(1), /** If tagged master and untagged slave is supported, get tagged address from master only if slave also uses it */ .use_tagged_addr(~axi_sys_common_cfg.support_tagged_master_and_untagged_slave), .convert_to_slave_addr(1), .requester_name(get_master_xact_requester_name(item.master_xact))) == slave_xact_max_addr) ) || ( (!is_exact_match || ((item.master_xact.cache_type[1] == 1'b1) || (axi_sys_common_cfg.master_to_slave_association_mode == 2))) && (is_amba_address_overlap(.xact(item.master_xact),.min_addr(slave_xact_min_addr), .max_addr(slave_xact_max_addr), .convert_to_global_addr(1), .use_tagged_addr(~axi_sys_common_cfg.support_tagged_master_and_untagged_slave), .convert_to_slave_addr(1), .requester_name(get_master_xact_requester_name(item.master_xact)))) ) ) ) |
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if ((port_cfg != null) && (port_cfg.``enablefieldwdth > 0)) begin `SVT_DATA_UTIL_COMPARE_BITVEC_SLICE(fieldname,fieldmaxwidth,port_cfg.``enablefieldwdth``-1,0) end else begin `SVT_DATA_UTIL_COMPARE_BITVEC(fieldname) end | |
Transaction Class Macros definition and utility methods definition
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if ((port_cfg != null) && (port_cfg.``enablefieldwdth > 0)) begin `SVT_DATA_UTIL_COMPARE_BITVEC_SLICE_SIZE_ARRAY(fieldname,fieldmaxwidth,port_cfg.``enablefieldwdth``-1,0) end else begin `SVT_DATA_UTIL_COMPARE_INT_SIZE_ARRAY(fieldname) end |
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( ( (xact.transmitted_channel == svt_axi_transaction::WRITE) && (xact.write_resp_status == svt_axi_transaction::ACCEPT ) && (xact.bresp == (xact.port_cfg.exclusive_access_enable == 1 && xact.atomic_type == svt_axi_transaction::EXCLUSIVE) ? svt_axi_transaction::EXOKAY : svt_axi_transaction::OKAY) ) || ( (xact.transmitted_channel == svt_axi_transaction::READ) && (xact.data_status == svt_axi_transaction::ACCEPT ) && (rresp == (xact.port_cfg.exclusive_access_enable == 1 && xact.atomic_type == svt_axi_transaction::EXCLUSIVE) ? svt_axi_transaction::EXOKAY : svt_axi_transaction::OKAY) ) ) |
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if (obj.data.size()) begin foreach (obj.data[i]) begin bit[SVT_AXI_MAX_DATA_WIDTH-1:0] _data_mask; _data_mask = ((1 << ((1 << obj.burst_size) << 3)) - 1); obj.data[i] = obj.data[i] & _data_mask; end end |
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if (obj.poison.size()) begin foreach (obj.poison[i]) begin bit[SVT_AXI_MAX_DATA_WIDTH/64-1:0] _poison_mask; if(obj.burst_size>3) _poison_mask = ((1 << ((1 << obj.burst_size) / 8)) - 1); else _poison_mask =1; obj.poison[i] = obj.poison[i] & _poison_mask; end end |
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if (obj.tag.size()) begin foreach (obj.tag[i]) begin bit[SVT_AXI_MAX_TAG_WIDTH-1:0] _tag_mask; _tag_mask =((1<<(((CEIL(((1 << obj.burst_size) << 3),128)))*4))-1); obj.tag[i] = obj.tag[i] & _tag_mask; end end |
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if (obj.data.size() != obj.wstrb.size()) begin svt_error("svt_axi_transaction", $sformatf("Cannot compare data because size of data array ('d%0d) is not equal to size of wstrb array ('d%0d). xact_type(%0s). coherent_xact_type(%0s). transmitted_channel(%0s) xact = %0s", obj.data.size(), obj.wstrb.size(), obj.xact_type.name(), obj.coherent_xact_type.name(), obj.transmitted_channel.name(),SVT_AXI_PRINT_PREFIX1(obj))); end foreach (obj.data[i]) begin bit[SVT_AXI_MAX_DATA_WIDTH-1:0] _data_mask; bit[(SVT_AXI_MAX_DATA_WIDTH/8)-1:0] _wstrb = obj.wstrb[i]; _data_mask = 'h0; foreach (_wstrb[i]) begin if (_wstrb[i] === 1'b1) _data_mask[i*8+:8] = 'hff; else _data_mask[i*8+:8] = 'h0; end obj.data[i] = obj.data[i] & _data_mask; end |
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if (obj.tag.size() != obj.tag_update.size()) begin svt_error("svt_axi_transaction", $sformatf("Cannot compare tag because size of tag array ('d%0d) is not equal to size of tag_update array ('d%0d). xact_type(%0s). coherent_xact_type(%0s). transmitted_channel(%0s) xact = %0s", obj.tag.size(), obj.tag_update.size(), obj.xact_type.name(), obj.coherent_xact_type.name(), obj.transmitted_channel.name(),SVT_AXI_PRINT_PREFIX1(obj))); end foreach (obj.tag[i]) begin bit[SVT_AXI_MAX_TAG_WIDTH-1:0] _tag_mask; bit[(SVT_AXI_MAX_TAGUPDATE_WIDTH)-1:0] _tag_update = obj.tag_update[i]; _tag_mask = 'h0; foreach (_tag_update[i]) begin if (_tag_update[i] === 1'b1) _tag_mask[i*4+:4] = 'hf; else _tag_mask[i*4+:4] = 'h0; end obj.tag[i] = obj.tag[i] & _tag_mask; end |
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`ifdef SVT_UVM_TECHNOLOGY begin uvm_event_pool xact_event_pool; uvm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `elsif SVT_OVM_TECHNOLOGY begin ovm_event_pool xact_event_pool; ovm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `else this_xact.notify.wait_for(vmm_data::ENDED); `endif |
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`ifdef SVT_UVM_TECHNOLOGY begin uvm_event_pool xact_event_pool; uvm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `elsif SVT_OVM_TECHNOLOGY begin ovm_event_pool xact_event_pool; ovm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `else this_xact.notify.wait_for(vmm_data::ENDED); `endif |
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driver_mp.axi_master_cb.awaddr <= {SVT_AXI_MAX_ADDR_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awatop <= {SVT_ACE5_ATOMIC_TYPE_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awmpam <= {SVT_AXI_MAX_MPAM_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awloop <= {SVT_AXI_MAX_LOOP_W_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awnsaid <= {SVT_AXI_MAX_NSAID_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awcmo <= {SVT_AXI_ACE_WCMO_WIDTH{1'b``enable_sig_val}}; SVT_AXI_MASTER_DRIVE_SIGNAL(awid,{SVT_AXI_MAX_ID_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_ID_WIDTH{1'b``disable_sig_val}},awid_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awlen,{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``disable_sig_val}},awlen_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awsize,{SVT_AXI_SIZE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_SIZE_WIDTH{1'b``disable_sig_val}},awsize_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awburst,{SVT_AXI_BURST_WIDTH{1'b``enable_sig_val}},{SVT_AXI_BURST_WIDTH{1'b``disable_sig_val}},awburst_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awlock,{SVT_AXI_LOCK_WIDTH{1'b``enable_sig_val}},{SVT_AXI_LOCK_WIDTH{1'b``disable_sig_val}},awlock_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awcache,{SVT_AXI_CACHE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_CACHE_WIDTH{1'b``disable_sig_val}},awcache_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awprot,{SVT_AXI_PROT_WIDTH{1'b``enable_sig_val}},{SVT_AXI_PROT_WIDTH{1'b``disable_sig_val}},awprot_enable) `ifdef SVT_AXI_QVN_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(awvnet,{`SVT_AXI_QVN_AWVNET_WIDTH{1'b``enable_sig_val}},{`SVT_AXI_QVN_AWVNET_WIDTH{1'b``disable_sig_val}},qvn_enable) `endif `ifdef SVT_ACE5_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(awidunq,1'b``enable_sig_val,1'b``disable_sig_val,unique_id_enable) `endif if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) || (cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) || (cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE)) begin if(cfg.awqos_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awqos,{SVT_AXI_QOS_WIDTH{1'b``enable_sig_val}},{SVT_AXI_QOS_WIDTH{1'b``disable_sig_val}},awqos_enable) if(cfg.awregion_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awregion,{SVT_AXI_REGION_WIDTH{1'b``enable_sig_val}},{SVT_AXI_REGION_WIDTH{1'b``disable_sig_val}},awregion_enable) end else begin driver_mp.axi_master_cb.awqos <= SVT_AXI_QOS_WIDTH'bz; driver_mp.axi_master_cb.awregion <= SVT_AXI_REGION_WIDTH'bz; end if (cfg.awuser_enable) begin driver_mp.axi_master_cb.awuser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.awuserchk <= ~{CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.awuser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.awuserchk <= {CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'bz}}; end |
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driver_mp.axi_master_cb.wdata <= {SVT_AXI_MAX_DATA_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL || cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_DATA ) driver_mp.axi_master_cb.wdatachk <= ~{CEIL(SVT_AXI_MAX_DATA_WIDTH,8){1'b``enable_sig_val}}; driver_mp.axi_master_cb.wstrb <= {SVT_AXI_MAX_DATA_WIDTH/8{1'b``enable_sig_val}}; `ifdef SVT_AXI_QVN_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(wvnet,{`SVT_AXI_QVN_WVNET_WIDTH{1'b``enable_sig_val}},{`SVT_AXI_QVN_WVNET_WIDTH{1'b``disable_sig_val}},qvn_enable) `endif if ((cfg.axi_interface_type == svt_axi_port_configuration :: AXI3 ) || (cfg.wid_for_non_axi3_enable == 1 )) begin driver_mp.axi_master_cb.wid <= {SVT_AXI_MAX_ID_WIDTH{1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.wid <= {SVT_AXI_MAX_ID_WIDTH{1'bz}}; end if (cfg.wuser_enable) begin driver_mp.axi_master_cb.wuser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.wuserchk <= ~{CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.wuser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.wuserchk <= {CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'bz}}; end SVT_AXI_MASTER_DRIVE_SIGNAL(wlast,{SVT_AXI_MAX_DATA_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_DATA_WIDTH{1'b``disable_sig_val}},wlast_enable) |
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driver_mp.axi_slave_cb.bid <= {SVT_AXI_MAX_ID_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.bresp <= {SVT_AXI_RESP_WIDTH{1'b``val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.brespchk <= ~{CEIL(SVT_AXI_MAX_BRESP_USER_WIDTH,8){1'b``val}}; `ifdef SVT_ACE5_ENABLE if(cfg.unique_id_enable) driver_mp.axi_slave_cb.bidunq <= 1'b``val; `endif if(cfg.buser_enable) begin driver_mp.axi_slave_cb.buser <= {SVT_AXI_MAX_BRESP_USER_WIDTH{1'b``val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.buserchk <= ~{CEIL(SVT_AXI_MAX_BRESP_USER_WIDTH,8){1'b``val}}; end else begin driver_mp.axi_slave_cb.buser <= {SVT_AXI_MAX_BRESP_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.buserchk <= {CEIL(SVT_AXI_MAX_BRESP_USER_WIDTH,8){1'bz}}; end |
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( ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) && (this_xact.ack_status == svt_axi_transaction::ACCEPT) ) || ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (this_xact.transmitted_channel == svt_axi_transaction::WRITE) && (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) ) || ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (this_xact.transmitted_channel == svt_axi_transaction::READ) && (this_xact.data_status == svt_axi_transaction::ACCEPT) ) ) |
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32
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if(!axi_sys_common_cfg.debug_system_monitor) svt_amba_debug(id, msg); else if(axi_sys_common_cfg.debug_system_monitor < 4) svt_amba_debug(id, msg) |
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`ifdef SVT_UVM_TECHNOLOGY ,reporter `elsif SVT_OVM_TECHNOLOGY ,reporter `else `endif |