VIP Smartsearch

VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.
How to download VIP smartsearch?
1. Get VIP Smartsearch (Available as a seperate run file).
2. Set environment variable
```
DESIGNWARE_HOME
```
  to required designware home location where VIP Smartsearch should be downloaded.
3. Run
```
vip_smartsearch_<version>.run
```
  file.
  VIP Smartsearch will be downloaded to the location
```
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
```

How to install VIP Smartsearch?

Please refer to the file

VIP_Smartsearch_installation_and_usage_guide.pdf

$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

for installation steps.

Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.
Mention your queries along with below details and send email to above email id.
Product: Verification IP
Sub Product: <vip_title>
Tool: VIP Smartsearch

Product Base	Group
amba_svt	AXI_PORT_MON_ATOMICTYPE_RESP * The Covergroups under this group are generated for response type for atomic tranactions for both read and write. It is constructed for whe config enable handle is asserted depending on the interface type.
AXI_PORT_MON_SEQUENCE * The Covergroups under this group are classified based on sequence and burst_type. It is constructed for interface_type_category AXI READ and WRITE.
AXI_PORT_MON_UNALIGNED_ADDRESS * The Covergroups under this group are classified for unaligned address transfer for read and write transaction and also changes as per the AXCACHE signal encodings with different configurable address widths. It is constructed and sampled for interface type AXI3.
AXI_PORT_OUTSTANDING_XACT_MODIFIABLE * The Covergroups under this covergroup are classified as read and write outstanding xact for different encodings for AXCACHE bit with same and different AXID signal.
ACE_PORT_MON_ARPROT_ARBARRIER * This Covergroup is cross coverage for readonce read xact type,domain type and prot signal. It is constructed when trans_cross_ace_arprot_arbarrier_memory_sync_enable is asserted.
ACE_PORT_MON_AWPROT_AWBARRIER * This Covergroup is cross coverage for writeunique write xact type,domain type and prot signal. It is constructed when trans_cross_ace_awprot_awbarrier_memory_sync_enable is asserted.
ACE_PORT_MON_ARDOMAIN_ARPROT * This Covergroup is cross coverage for readonce read xact type,domain type and prot signal. It is constructed when trans_cross_ace_readonce_ardomain_arprot_enable is asserted.
ACE_PORT_MON_AWDOMAIN_AWPROT * This Covergroup is cross coverage for writeunique write xact type,domain type and prot signal. It is constructed when trans_cross_ace_writeunique_awdomain_awprot_enable is asserted.
AXI_PORT_MON_ATOMICTYPE_CACHE * The Covergroups under this group are cross coverage of READ/WRITE Exclusive Access with all legel ARCache/AWCache values. The legal ARCACHE values for exclusive read access are Device Non-bufferable Device bufferable Normal Non-cacheable Non-bufferable Normal Non-cacheable Bufferable It is constructed and sampled when interface type is AXI3.
AXI_PORT_MON_ACE_DVM_MODES * The Covergroups under this group are cross coverage of DVM Branch Predictor invalidate message type,invalidate address modes and virtual address range configured for different address width. It is constructed when interface type is AXI_ACE or ACE_LITE.
AXI_PORT_MON_ACE_SNOOP_DVM_MODES * The Covergroups under this group are cross coverage of snoop DVM TLB Invalidate message type,invalidate address modes and virtual address configured for different address width. It is constructed when interface type is AXI_ACE or ACE_LITE.
AXI_PORT_MON_DVM_OVERLAP * The Covergroup under this group are cross coverage related to DVM overlap case in ACE-lite and ACE-VIP and it cover acvalid=1,acready=1, acsnoop= DVM , crvalid=1 and crready=1. It is constructed when interface type is AXI_ACE or ACE_LITE.
AXI_PORT_MON_VALID_READY_XACT_FLOW * The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after wvalid is deasserted, then coverpoint AWVALID_WVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.
AXI_STREAM_PORT_MON_XACT_FLOW * The Covergroups under this group captures delay scenarios for tvalid and tready signal when interface_type is AXI4_STREAM.
AXI_PORT_MON_MASTER_TO_SLAVE_PATH` * The Covergroup under this header captures attributes for coherant read and write type, for all slaves. This is constructed when interface type is AXI_ACE or ACE_LITE and trans_cross_master_to_slave_path_access_ace_enable is set to 1.
AXI_PORT_MON_XACT_FLOW * The Covergroups under this group capture all the write and read transaction control information Attributes under write channel & read channel are constructed only when axi_interface_type is set to AXI3,AXI4,AXI-ACE or ACE-LITE.
Ungrouped Functional Covergroups Functional Coverage with description
Other Covergroups Covergroups without description

Product Base

Group

amba_svt

AXI_PORT_MON_ATOMICTYPE_RESP

* The Covergroups under this group are generated for response type for atomic tranactions for both read and write. It is constructed for whe config enable handle is asserted depending on the interface type.

AXI_PORT_MON_SEQUENCE

* The Covergroups under this group are classified based on sequence and burst_type. It is constructed for interface_type_category AXI READ and WRITE.

AXI_PORT_MON_UNALIGNED_ADDRESS

* The Covergroups under this group are classified for unaligned address transfer for read and write transaction and also changes as per the AXCACHE signal encodings with different configurable address widths. It is constructed and sampled for interface type AXI3.

AXI_PORT_OUTSTANDING_XACT_MODIFIABLE

* The Covergroups under this covergroup are classified as read and write outstanding xact for different encodings for AXCACHE bit with same and different AXID signal.

ACE_PORT_MON_ARPROT_ARBARRIER

* This Covergroup is cross coverage for readonce read xact type,domain type and prot signal. It is constructed when trans_cross_ace_arprot_arbarrier_memory_sync_enable is asserted.

ACE_PORT_MON_AWPROT_AWBARRIER

* This Covergroup is cross coverage for writeunique write xact type,domain type and prot signal. It is constructed when trans_cross_ace_awprot_awbarrier_memory_sync_enable is asserted.

ACE_PORT_MON_ARDOMAIN_ARPROT

* This Covergroup is cross coverage for readonce read xact type,domain type and prot signal. It is constructed when trans_cross_ace_readonce_ardomain_arprot_enable is asserted.

ACE_PORT_MON_AWDOMAIN_AWPROT

* This Covergroup is cross coverage for writeunique write xact type,domain type and prot signal. It is constructed when trans_cross_ace_writeunique_awdomain_awprot_enable is asserted.

AXI_PORT_MON_ATOMICTYPE_CACHE

* The Covergroups under this group are cross coverage of READ/WRITE Exclusive Access with all legel ARCache/AWCache values. The legal ARCACHE values for exclusive read access are

Device Non-bufferable
Device bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable

It is constructed and sampled when interface type is AXI3.

AXI_PORT_MON_ACE_DVM_MODES

* The Covergroups under this group are cross coverage of DVM Branch Predictor invalidate message type,invalidate address modes and virtual address range configured for different address width. It is constructed when interface type is AXI_ACE or ACE_LITE.

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

* The Covergroups under this group are cross coverage of snoop DVM TLB Invalidate message type,invalidate address modes and virtual address configured for different address width. It is constructed when interface type is AXI_ACE or ACE_LITE.

AXI_PORT_MON_DVM_OVERLAP

* The Covergroup under this group are cross coverage related to DVM overlap case in ACE-lite and ACE-VIP and it cover acvalid=1,acready=1, acsnoop= DVM , crvalid=1 and crready=1. It is constructed when interface type is AXI_ACE or ACE_LITE.

AXI_PORT_MON_VALID_READY_XACT_FLOW

* The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after wvalid is deasserted, then coverpoint AWVALID_WVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

AXI_STREAM_PORT_MON_XACT_FLOW

* The Covergroups under this group captures delay scenarios for tvalid and tready signal when interface_type is AXI4_STREAM.

AXI_PORT_MON_MASTER_TO_SLAVE_PATH`

* The Covergroup under this header captures attributes for coherant read and write type, for all slaves. This is constructed when interface type is AXI_ACE or ACE_LITE and trans_cross_master_to_slave_path_access_ace_enable is set to 1.

AXI_PORT_MON_XACT_FLOW

* The Covergroups under this group capture all the write and read transaction control information Attributes under write channel & read channel are constructed only when axi_interface_type is set to AXI3,AXI4,AXI-ACE or ACE-LITE.

Ungrouped Functional Covergroups

Functional Coverage with description

Other Covergroups

Covergroups without description

Group	Subgroup	Covergroup	Coverpoints	Bins	Cross Coverage	Description
AXI_PORT_MON_ATOMICTYPE_RESP	AXI_PORT_MON_ATOMICTYPE_RRESP	trans_cross_axi_atomictype_rresp	read_xact_type atomic_type rresp	read_xact_type:read_xact atomic_type:normal, exclusive, locked rresp:okay_resp, exokay_resp, slverr_resp, decerr_resp	axi_atomictype_rresp	Covergroup: trans_cross_axi_atomictype_rresp This Covergroup triggers response type for atomic transactions. It is constructed and sampled when trans_cross_axi_atomictype_rresp_enable is asserted. Coverpoints: read_xact_type: Captures read transaction atomic_type: Captures transaction atomic type rresp: Captures transaction response Cross coverpoints: axi_atomictype_rresp: Crosses cover points read_xact_type, atomic_type,rresp. This covergroup is triggered when an exclusive READ transaction with rresp of exokay is observed
AXI_PORT_MON_ATOMICTYPE_RESP	AXI_PORT_MON_ATOMICTYPE_BRESP	trans_cross_axi_atomictype_bresp	write_xact_type atomic_type bresp	write_xact_type:write_xact atomic_type:normal, exclusive, locked bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp	axi_atomictype_bresp	Covergroup: trans_cross_axi_atomictype_bresp This covergroup is triggered when a exclusive Write transaction with bresp of okay/exokay is observed. It is constructed and sampled when interface category type is not AXI_READ_ONLY & trans_cross_axi_atomictype_bresp_enable is asserted. Coverpoints: write_xact_type: Captures write transaction atomic_type: Captures transaction atomic type bresp: Captures transaction response Cross coverpoints: axi_atomictype_bresp: Crosses cover points write_xact_type, atomic_type,bresp.
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_FIXED_BURST	trans_cross_axi_fixed_burst_wstrb	burst_type wstrb	burst_type:fixed_burst, incr_burst, wrap_burst wstrb:wstrb_all_ones_8, wstrb_all_ones_16, wstrb_all_ones_32, wstrb_all_ones_64, wstrb_all_ones_128, wstrb_all_ones_256, wstrb_all_ones_512, wstrb_all_ones_1024, wstrb_all_ones_2048, wstrb_all_ones_4096, wstrb_all_zeroes_8, wstrb_all_zeroes_16, wstrb_all_zeroes_32, wstrb_all_zeroes_64, wstrb_all_zeroes_128, wstrb_all_zeroes_256, wstrb_all_zeroes_512, wstrb_all_zeroes_1024, wstrb_all_zeroes_2048, wstrb_all_zeroes_4096, wstrb_all_one_zero_data_width_16, wstrb_all_zero_one_data_width_16, wstrb_all_one_zero_data_width_32, wstrb_all_zero_one_data_width_32, wstrb_all_one_zero_data_width_64, wstrb_all_zero_one_data_width_64, wstrb_all_one_zero_data_width_128, wstrb_all_zero_one_data_width_128, wstrb_all_one_zero_data_width_256, wstrb_all_zero_one_data_width_256, wstrb_all_one_zero_data_width_512, wstrb_all_zero_one_data_width_512, wstrb_all_one_zero_data_width_1024, wstrb_all_zero_one_data_width_1024, wstrb_all_one_zero_data_width_2048, wstrb_all_zero_one_data_width_2048, wstrb_all_one_zero_data_width_4096, wstrb_all_zero_one_data_width_4096	axi_fixed_burst_wstrb	Covergroup: trans_cross_axi_fixed_burst_wstrb This cover group crosses AXI Fixed burst type with write strobe It is constructed and sampled when interface type category is not AXI_READ_ONLY and trans_cross_axi_fixed_burst_wstrb_cov_enable is asserted. Covers the cross of fixed burst type, & WSTRB Coverpoints: burst_type: Captures transaction burst type wstrb: Captures write strobe values Cross coverpoints: axi_fixed_burst_wstrb : Crosses cover points burst_type,wstrb Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:3.4.1
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_EXCL_NORMAL_SEQUENCE	axi_four_excl_normal_sequence	four_excl_normal_sequence	four_excl_normal_sequence:bin_NR_NR_NR_EX_SEQ, bin_NR_NR_EX_NR_SEQ, bin_NR_NR_EX_EX_SEQ, bin_NR_EX_NR_NR_SEQ, bin_NR_EX_NR_EX_SEQ, bin_NR_EX_EX_NR_SEQ, bin_NR_EX_EX_EX_SEQ, bin_EX_NR_NR_NR_SEQ, bin_EX_NR_NR_EX_SEQ, bin_EX_NR_EX_NR_SEQ, bin_EX_NR_EX_EX_SEQ, bin_EX_EX_NR_NR_SEQ, bin_EX_EX_NR_EX_SEQ, bin_EX_EX_EX_NR_SEQ	--	Covergroup: axi_four_excl_normal_sequence This cover group covers specific combinations of exclusive and normal transactions, for a sequence of four transactions. For eg. Excl-Normal-Excl-Normal,Normal-Normal-Excl-Normal etc. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_four_excl_normal_sequence_cov_enable and exclusive_access_enable is asserted. Following sequences are supported: NR_NR_NR_EX NR_NR_EX_NR NR_NR_EX_EX NR_EX_NR_NR NR_EX_NR_EX NR_EX_EX_NR NR_EX_EX_EX EX_NR_NR_NR EX_NR_NR_EX EX_NR_EX_NR EX_NR_EX_EX EX_EX_NR_NR EX_EX_NR_EX EX_EX_EX_NR
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_RD_WR_BURST_SEQUENCE	axi_four_state_rd_wr_burst_sequence	four_state_rd_wr_burst_sequence	four_state_rd_wr_burst_sequence:bin_WR_WR_WR_WR_SEQ, bin_WR_RD_WR_RD_SEQ, bin_RD_WR_RD_WR_SEQ, bin_WR_WR_RD_RD_SEQ, bin_RD_RD_WR_WR_SEQ, bin_RD_RD_RD_RD_SEQ, bin_RD_RD_RD_WR_SEQ, bin_WR_WR_WR_RD_SEQ	--	Covergroup: axi_four_state_rd_wr_burst_sequence This cover group covers specific combinations of read and write transactions, for a sequence of four transactions. For eg. Write-Write-Write-Write or Write-Read-Write-Read, etc. This covergroup is hit when address phase completion of four transactions are observed in a specific combination as described above. When address phases of READ and WRITE transactions get completed at same time, it is not deterministic whether it is a read-write or write-read scenario. In such situation, either sequence containing read-write or write-read may get hit. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_four_state_rd_wr_burst_sequence_cov_enable is asserted. Following sequences are currently supported: WR_WR_WR_WR WR_RD_WR_RD WR_WR_RD_RD RD_RD_WR_WR RD_RD_RD_RD WR_WR_WR_RD RD_WR_RD_WR RD_RD_RD_WR Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:3.4.1
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_READ_BURST_SEQUENCE	axi_back_to_back_read_burst_sequence	back_to_back_read_burst_sequence	back_to_back_read_burst_sequence:back_to_back_read_burst_seq	--	Covergroup: axi_back_to_back_read_burst_sequence Coverage group for covering Back To Back READ BURST. This covergroup is triggered when address phase of first READ xact has completed and immediately next clock address phase of second READ xact has started. It is constructed when interface type category is not AXI_WRITE_ON;Y andtrans_axi_back_to_back_read_burst_sequence_enable is asserted. Bins hit for back to back read burst sequence
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_WRITE_BURST_SEQUENCE	axi_back_to_back_write_burst_sequence	back_to_back_write_burst_sequence	back_to_back_write_burst_sequence:back_to_back_write_burst_seq	--	Covergroup: axi_back_to_back_write_burst_sequence Coverage group for covering Back To Back WRITE BURST. This covergroup is triggered when address phase of first WRITE xact has completed and immediately next clock address phase of second WRITE xact has started. It is constructed when interface type category is not AXI_READ_ONLY andtrans_axi_back_to_back_write_burst_sequence_enable is asserted. Bins hit for back to back write burst sequence
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_WRITE_READ_SAMEID_OUT_OF_ORDER	axi_write_read_diff_id_completed_out_of_order	write_completed_out_of_order read_completed_out_of_order	write_completed_out_of_order:write_completed_OOO read_completed_out_of_order:read_completed_OOO	--	Covergroup: axi_write_read_diff_id_completed_out_of_order Coverage group for covering Read/Write Completed out of order with ARID != AWID This Covergroup is triggere for both read and write xact completed out of order. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_write_read_diff_id_completed_out_of_order_enable is asserted.
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_WRITE_READ_DIFFID_OUT_OF_ORDER	axi_write_read_same_id_completed_out_of_order	write_completed_out_of_order_same_id_as_read read_completed_out_of_order_same_id_as_write	write_completed_out_of_order_same_id_as_read:write_completed_OOO_same_id_as_read read_completed_out_of_order_same_id_as_write:read_completed_OOO_same_id_as_write	--	Covergroup: axi_write_read_same_id_completed_out_of_order Coverage group for covering Read/Write Completed out of order with ARID==AWID. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_write_read_same_id_completed_out_of_order_enable.
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_OUT_OF_ORDER_READ_RESP	trans_cross_axi_out_of_order_read_resp_count	axi_read_resp_OOO_count	axi_read_resp_OOO_count:read_rsp_ooo_count	--	Covergroup : trans_cross_axi_out_of_order_read_resp_count This Covergroup is for covering read_resp out_of_order count. It is constructed when interface type category is not AXI_WRITE_ONLY. Coverpoint : axi_read_resp_OOO_count : Captures read_resp out_of_order count
AXI_PORT_MON_SEQUENCE	AXI_PORT_MON_OUT_OF_ORDER_WRITE_RESP	trans_cross_axi_out_of_order_write_resp_count	axi_write_resp_OOO_count	axi_write_resp_OOO_count:write_rsp_ooo_count	--	Covergroup : trans_cross_axi_out_of_order_write_resp_count This Covergroup is for covering write_resp out_of_order count. It is constructed when interface type category is not AXI_READ_ONLY Coverpoint: axi_write_resp_OOO_count : Captures write_resp out_of_order count
AXI_PORT_MON_UNALIGNED_ADDRESS	AXI_PORT_MON_WSTRB_UNALIGNED_ADDRESS	axi_wstrb_to_signal_unaligned_start_address	wstrb_to_signal_unaligned_start_address	wstrb_to_signal_unaligned_start_address:wstrb_to_signal_unaligned_start_addr	--	Covergroup: axi_wstrb_to_signal_unaligned_start_address This cover group covers the scenario in which a master can provide an aligned address to a write transaction, and use the write strobes to indicate unaligned start address. It is constructed when trans_axi_wstrb_to_signal_unaligned_start_address_cov_enable is asserted. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:3.4.3
AXI_PORT_MON_UNALIGNED_ADDRESS	AXI_PORT_MON_ARCACHE_MODIFIABLE_UNALIGNED_TRANSFER_AXI3	trans_cross_axi3_arcache_modifiable_bit_read_unaligned_transfer	read_xact_type burst_type addr_offset transfer_size cache_type_modifiable_bit	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte cache_type_modifiable_bit:svt_axi_cache_modifiable_only	axi3_arcache_modifiable_bit_read_unaligned_transfer	Covergroup: trans_cross_axi3_arcache_modifiable_bit_read_unaligned_transfer This cover group crosses bit ARCACHE[1] with unaligned read transfers. It is constructed and sampled when interface type is AXI3 and trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_cov_enable is asserted. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type addr_offset: Captures transaction address offset information transfer_size: Captures transaction burst size cache_type_modifiable_bit: Captures ARCACHE[1] Cross coverpoints: axi3_read_arcache_modifiable_bit_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2
AXI_PORT_MON_UNALIGNED_ADDRESS	AXI_PORT_MON_ARCACHE_MODIFIABLE_UNALIGNED_TRANSFER_AXI4	trans_cross_axi4_arcache_modifiable_bit_read_unaligned_transfer	read_xact_type burst_type addr_offset transfer_size cache_type_modifiable_bit	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte cache_type_modifiable_bit:svt_axi_cache_modifiable_only	axi4_arcache_modifiable_bit_read_unaligned_transfer	Covergroup: trans_cross_axi4_arcache_modifiable_bit_read_unaligned_transfer This cover group crosses bit ARCACHE[1] with unaligned read transfers. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_cov_enable is asserted. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type addr_offset: Captures transaction address offset information transfer_size: Captures transaction burst size cache_type_modifiable_bit: Captures ARCACHE[1] Cross coverpoints: axi4_read_arcache_modifiable_bit_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2
AXI_PORT_MON_UNALIGNED_ADDRESS	AXI_PORT_MON_AWCACHE_MODIFIABLE_UNALIGNED_TRANSFER	trans_cross_axi3_awcache_modifiable_bit_write_unaligned_transfer	write_xact_type burst_type addr_offset transfer_size cache_type_modifiable_bit	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte cache_type_modifiable_bit:svt_axi_cache_modifiable_only	axi3_awcache_modifiable_bit_write_unaligned_transfer	Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer This cover group crosses bit AWCACHE[1] with unaligned write transfers. It is constructed and sampled when interface type is AXI3 and trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_cov_enable is asserted. Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type addr_offset: Captures transaction address offset information transfer_size: Captures transaction burst size cache_type_modifiable_bit: Captures AWCACHE[1] Cross coverpoints: axi3_awcache_modifiable_bit_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2
AXI_PORT_MON_UNALIGNED_ADDRESS	AXI_PORT_MON_AWCACHE_MODIFIABLE_UNALIGNED_TRANSFER_AXI4	trans_cross_axi4_awcache_modifiable_bit_write_unaligned_transfer	write_xact_type burst_type addr_offset transfer_size cache_type_modifiable_bit	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte cache_type_modifiable_bit:svt_axi_cache_modifiable_only	axi4_awcache_modifiable_bit_write_unaligned_transfer	Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer This cover group crosses bit AWCACHE[1] with unaligned write transfers. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_cov_enable is asserted. Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type addr_offset: Captures transaction address offset information transfer_size: Captures transaction burst size cache_type_modifiable_bit: Captures AWCACHE[1] Cross coverpoints: axi4_awcache_modifiable_bit_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, burst_length, cache_type_modifiable_bit Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2
AXI_PORT_OUTSTANDING_XACT_MODIFIABLE	AXI_PORT_READ_OUTSTANDING_XACT_MODIFIABLE	trans_axi_read_outstanding_xact_same_arid_cache_modifiable_bit	read_outstanding_xact_same_arid_cache_modifiable_bit	read_outstanding_xact_same_arid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable	--	Covergroup:trans_axi_read_outstanding_xact_same_arid_cache_modifiable_bit This coverpoint covers the scenario in which master can issue multiple outstanding READ transactions with same ARID,taking ARCACHE Modifiable bit into consideration. It is constructed and sampled when trans_axi_read_outstanding_xact_same_arid_cache_modifiable_bit_enable is asserted. Bins are interpreted as follows: cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=1 is followed by another transaction with ARCACHE[1]=1. cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=1 is followed by another transaction with ARCACHE[1]=0. cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=0 is followed by another transaction with ARCACHE[1]=1. cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=0 is followed by another transaction with ARCACHE[1]=0. Coverpoints: read_outstanding_xact_same_arid_cache_modifiable_bit Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1
AXI_PORT_OUTSTANDING_XACT_MODIFIABLE	AXI_PORT_READ_OUTSTANDING_XACT_ARID_MODIFIABLE	trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit	read_outstanding_xact_diff_arid_cache_modifiable_bit	read_outstanding_xact_diff_arid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable	--	Covergroup:trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit This coverpoint covers the scenario in which master can issue multiple outstanding READ transactions with different ARID,taking ARCACHE Modifiable bit into consideration. It is constructed and sampled when trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit_enable is asserted. Coverpoints:read_outstanding_xact_diff_arid_cache_modifiable_bit Bins are interpreted as follows: cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=1 is followed by another transaction with ARCACHE[0]=1. cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=1 is followed by another transaction with ARCACHE[0]=0. cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=0 is followed by another transaction with ARCACHE[0]=1. cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=0 is followed by another transaction with ARCACHE[0]=0. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1
AXI_PORT_OUTSTANDING_XACT_MODIFIABLE	AXI_PORT_READ_OUTSTANDING_XACT_ARID_DEVICE	trans_axi_read_outstanding_xact_diff_arid_device_cacheable_bit	read_outstanding_xact_diff_arid_device_cacheable_bit	read_outstanding_xact_diff_arid_device_cacheable_bit:device_nonbufferable_followed_by_device_nonbufferable, device_nonbufferable_followed_by_device_bufferable, device_bufferable_followed_by_device_nonbufferable, device_bufferable_followed_by_device_bufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable, normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_bufferable_followed_by_noncacheable_bufferable	--	Covergroup:trans_axi_read_outstanding_xact_diff_arid_device_cacheable_bit This coverpoint covers the scenario in which master can issue multiple outstanding READ transactions with different ARID,taking memory types by ARCACHE[3:0] into considera* It is constructed when trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit_enable is asserted. It is constructed and sampled when trans_axi_read_outstanding_xact_diff_arid_device_cacheable_bit_enable is asserted. Coverpoints:read_outstanding_xact_diff_arid_device_cacheable_bit Bins are interpreted as follows: device_nonbufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0000 is followed by another transaction with ARCACHE[3:0]= 4'b0000. device_nonbufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0000 is followed by another transaction with ARCACHE[3:0]= 4'b0001. device_bufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0001 is followed by another transaction with ARCACHE[3:0]= 4'b0000. device_bufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0001 is followed by another transaction with ARCACHE[3:0]= 4'b0001. normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0010 is followed by another transaction with ARCACHE[3:0]= 4'b0010. normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0010 is followed by another transaction with ARCACHE[3:0]= 4'b0011. normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0011 is followed by another transaction with ARCACHE[3:0]= 4'b0010. normal_noncacheable_bufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0011 is followed by another transaction with ARCACHE[3:0]= 4'b0011. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A4.4
AXI_PORT_OUTSTANDING_XACT_MODIFIABLE	AXI_PORT_WRITE_OUTSTANDING_XACT_AWID_MODIFIABLE	trans_axi_write_outstanding_xact_diff_awid_cache_modifiable_bit	write_outstanding_xact_diff_awid_cache_modifiable_bit	write_outstanding_xact_diff_awid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable	--	Covergroup:trans_axi_write_outstanding_xact_diff_awid_cache_modifiable_bit This coverpoint covers the scenario in which master can issue multiple outstanding WRITE transactions with diff AWID's,taking AWCACHE Modifiable bit into consideration. It is constructed and sampled when trans_axi_write_outstanding_xact_diff_awid_cache_modifiable_bit_enable is asserted. Coverpoints:write_outstanding_xact_diff_awid_cache_modifiable_bit Bins are interpreted as follows: cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=1 is followed by another transaction with AWCACHE[0]=1. cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=1 is followed by another transaction with AWCACHE[0]=0. cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=0 is followed by another transaction with AWCACHE[0]=1. cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=0 is followed by another transaction with AWCACHE[0]=0. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1
AXI_PORT_OUTSTANDING_XACT_MODIFIABLE	AXI_PORT_WRITE_OUTSTANDING_XACT_SAME_AWID_MODIFIABLE	trans_axi_write_outstanding_xact_same_awid_cache_modifiable_bit	write_outstanding_xact_same_awid_cache_modifiable_bit	write_outstanding_xact_same_awid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable	--	Covergroup:trans_axi_write_outstanding_xact_same_awid_cache_modifiable_bit This coverpoint covers the scenario in which master can issue multiple outstanding WRITE transactions with same AWID's,taking AWCACHE Modifiable bit into consideration. It is constructed when trans_axi_write_outstanding_xact_same_awid_cache_modifiable_bit_enable is asserted. Coverpoints:write_outstanding_xact_same_awid_cache_modifiable_bit Bins are interpreted as follows: cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=1 is followed by another transaction with AWCACHE[1]=1. cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=1 is followed by another transaction with AWCACHE[1]=0. cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=0 is followed by another transaction with AWCACHE[1]=1. cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=0 is followed by another transaction with AWCACHE[1]=0. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1
AXI_PORT_OUTSTANDING_XACT_MODIFIABLE	AXI_PORT_WRITE_OUTSTANDING_XACT_AWID_DEVICE	trans_axi_write_outstanding_xact_diff_awid_device_cacheable_bit	write_outstanding_xact_diff_awid_device_cacheable_bit	write_outstanding_xact_diff_awid_device_cacheable_bit:device_nonbufferable_followed_by_device_nonbufferable, device_nonbufferable_followed_by_device_bufferable, device_bufferable_followed_by_device_nonbufferable, device_bufferable_followed_by_device_bufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable, normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_bufferable_followed_by_noncacheable_bufferable	--	Covergroup:trans_axi_write_outstanding_xact_diff_awid_device_cacheable_bit This coverpoint covers the scenario in which master can issue multiple outstanding WRITE transactions with different AWID,taking memory types by AWCACHE[3:0] into consideration. It is constructed and sampled when trans_axi_write_outstanding_xact_diff_awid_device_cacheable_bit_enable is asserted. Coverpoints:write_outstanding_xact_diff_awid_device_cacheable_bit Bins are interpreted as follows: device_nonbufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0000 is followed by another transaction with AWCACHE[3:0]= 4'b0000. device_nonbufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0000 is followed by another transaction with AWCACHE[3:0]= 4'b0001. device_bufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0001 is followed by another transaction with AWCACHE[3:0]= 4'b0000. device_bufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0001 is followed by another transaction with AWCACHE[3:0]= 4'b0001. normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0010 is followed by another transaction with AWCACHE[3:0]= 4'b0010. normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0010 is followed by another transaction with AWCACHE[3:0]= 4'b0011. normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0011 is followed by another transaction with AWCACHE[3:0]= 4'b0010. normal_noncacheable_bufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0011 is followed by another transaction with AWCACHE[3:0]= 4'b0011. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A4.4
ACE_PORT_MON_ARPROT_ARBARRIER	--	trans_cross_ace_arprot_arbarrier_memory_sync	coherent_read_xact_type barrier_type prot_type	coherent_read_xact_type:coherent_readbarrier_xact barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged	arprot_arbarrier_memory_sync	Covergroup: trans_cross_ace_arprot_arbarrier_memory_sync It is constructed and sampled when trans_cross_ace_arprot_arbarrier_memory_sync_enable is asserted. Coverpoints: coherent_read_xact_type: Captures coherent read transaction barrier_type : Captures read barrier prot_type : Captures transaction protection type Cross coverpoints: arprot_arbarrier_memory_sync: Crosses cover points read transaction of barrier_type MEMORY_BARRIER & SYNC_BARRIER with arprot The following bins are ignored: bins that interset NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER bins that intersect transaction types other than READBARRIER Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6
ACE_PORT_MON_AWPROT_AWBARRIER	--	trans_cross_ace_awprot_awbarrier_memory_sync	coherent_write_xact_type barrier_type prot_type	coherent_write_xact_type:coherent_writebarrier_xact barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged	awprot_awbarrier_memory_sync	Covergroup: trans_cross_ace_awprot_awbarrier_memory_sync It is constructed and sampled when trans_cross_ace_awprot_awbarrier_memory_sync_enable is asserted. Coverpoints: coherent_write_xact_type: Captures coherent write transaction barrier_type : Captures write barrier prot_type : Captures transaction protection type Cross coverpoints: awprot_awbarrier_memory_sync: Crosses cover points write transaction of barrier_type MEMORY_BARRIER & SYNC_BARRIER with awprot The following bins are ignored: bins that interset NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER bins that intersect transaction types other than WRITEBARRIER Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6
ACE_PORT_MON_ARDOMAIN_ARPROT	--	trans_cross_ace_readonce_ardomain_arprot	coherent_read_xact_type domain_type prot_type	coherent_read_xact_type:coherent_readonce_xact domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged	readonce_ardomain_arprot	Covergroup: trans_cross_ace_readonce_ardomain_arprot It is constructed and sampled when trans_cross_ace_readonce_ardomain_arprot_enable is asserted. Coverpoints: coherent_read_xact_type: Captures readonce coherent read transaction domain_type : Captures domain type prot_type : Captures transaction protection type Cross coverpoints: readonce_ardomain_arprot : Crosses cover points coherent_read_xact_type and domain_type and prot_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6
ACE_PORT_MON_AWDOMAIN_AWPROT	--	trans_cross_ace_writeunique_awdomain_awprot	coherent_write_xact_type domain_type prot_type	coherent_write_xact_type:coherent_writeunique_xact domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged	writeunique_awdomain_awprot	Covergroup: trans_cross_ace_writeunique_awdomain_awprot It is constructed and sampled when trans_cross_ace_writeunique_awdomain_awprot_enable is asserted Coverpoints: coherent_write_xact_type: Captures writeunique coherent write transaction domain_type : Captures domain type prot_type : Captures transaction protection type Cross coverpoints: writeunique_awdomain_awprot : Crosses cover points coherent_write_xact_type and domain_type and prot_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6
AXI_PORT_MON_ATOMICTYPE_CACHE	AXI_PORT_MON_ATOMICTYPE_ARCACHE_AXI3	trans_cross_axi_atomictype_exclusive_arcache_axi3	read_xact_type atomic_type cache_type	read_xact_type:read_xact atomic_type:normal, exclusive, locked cache_type:device_noncacheable_nonbufferable, device_bufferable_or_modifiable_only, cacheable_but_do_not_alloc, cacheable_and_bufferable_but_do_not_alloc	axi_atomictype_exclusive_arcache	Covergroup: trans_cross_axi_atomictype_exclusive_arcache_axi3 This covergroup is cross coverage of READ Exclusive Access with all legel ARCache values. The legal ARCACHE values for exclusive read access are Device Non-bufferable Device bufferable Normal Non-cacheable Non-bufferable Normal Non-cacheable Bufferable The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI3 and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted. Coverpoints: read_xact_type: Captures read transaction atomic_type: Captures transaction atomic type cache_type: Captures transaction cache type Cross coverpoints: axi_atomictype_exclusive_arcache: Crosses cover points read_xact_type, atomic_type,cache_type. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4
AXI_PORT_MON_ATOMICTYPE_CACHE	AXI_PORT_MON_ATOMICTYPE_ARCACHE_AXI4	trans_cross_axi_atomictype_exclusive_arcache_axi4	read_xact_type atomic_type cache_type	read_xact_type:read_xact atomic_type:normal, exclusive, locked cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable	axi_atomictype_exclusive_arcache	Covergroup: trans_cross_axi_atomictype_exclusive_arcache_axi4 This covergroup is cross coverage of READ Exclusive Access with all legel ARCache values. The legal ARCACHE values for exclusive read access are Device Non-bufferable Device bufferable Normal Non-cacheable Non-bufferable Normal Non-cacheable Bufferable The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted. Coverpoints: read_xact_type: Captures read transaction atomic_type: Captures transaction atomic type cache_type: Captures transaction cache type Cross coverpoints: axi_atomictype_exclusive_arcache: Crosses cover points read_xact_type, atomic_type,cache_type. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4
AXI_PORT_MON_ATOMICTYPE_CACHE	AXI_PORT_MON_ATOMICTYPE_AWCACHE_EXCLUSIVE_AXI4	trans_cross_axi_atomictype_exclusive_awcache_axi4	write_xact_type atomic_type cache_type	write_xact_type:write_xact atomic_type:normal, exclusive, locked cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable	axi_atomictype_exclusive_awcache	Covergroup: trans_cross_axi_atomictype_exclusive_awcache_axi4 This covergroup is cross coverage of WRITE Exclusive Access with all legel AWCache values for exclusive access. The legal AWCACHE values for exclusive write access are Device bufferable Device Non-bufferable Normal Non-cacheable Non-bufferable Normal Non-cacheable Bufferable The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_atomictype_exclusive_awcache_enable is asserted. Coverpoints: write_xact_type: Captures write transaction atomic_type: Captures transaction atomic type cache_type: Captures transaction cache type Cross coverpoints: axi_atomictype_exclusive_awcache: Crosses cover points write_xact_type, atomic_type,cache_type. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4
AXI_PORT_MON_ATOMICTYPE_CACHE	AXI_PORT_MON_ATOMICTYPE_AWCACHE_EXCLUSIVE_AXI3	trans_cross_axi_atomictype_exclusive_awcache_axi3	write_xact_type atomic_type cache_type	write_xact_type:write_xact atomic_type:normal, exclusive, locked cache_type:device_noncacheable_nonbufferable, device_bufferable_or_modifiable_only, cacheable_but_do_not_alloc, cacheable_and_bufferable_but_do_not_alloc	axi_atomictype_exclusive_awcache	Covergroup: trans_cross_axi_atomictype_exclusive_awcache_axi3 This covergroup is cross coverage of WRITE Exclusive Access with all legel AWCache values for exclusive access. The legal AWCACHE values for exclusive write access are Device bufferable Device Non-bufferable Normal Non-cacheable Non-bufferable Normal Non-cacheable Bufferable The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI_ACE and trans_cross_axi_atomictype_exclusive_awcache_enable is asserted. Coverpoints: write_xact_type: Captures write transaction atomic_type: Captures transaction atomic type cache_type: Captures transaction cache type Cross coverpoints: axi_atomictype_exclusive_awcache: Crosses cover points write_xact_type, atomic_type,cache_type. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB63TO16	trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb63to16	ardvm_message_type ardvm_va araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb63to32_firstpart	ardvm_message_type:message_branch_predictor_invalidate ardvm_va:invalidate_by_va, invalidate_not_by_va araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_branch_predictor_modes_virtaddr_msb63to16	Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb63to16 This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 Cross coverpoints: dvm_branch_predictor_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB55TO16	trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb55to16	ardvm_message_type ardvm_va araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb55to32_firstpart	ardvm_message_type:message_branch_predictor_invalidate ardvm_va:invalidate_by_va, invalidate_not_by_va araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_branch_predictor_modes_virtaddr_msb55to16	Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb55to16 This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 Cross coverpoints: dvm_branch_predictor_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB47TO16	trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb47to16	ardvm_message_type ardvm_va araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb47to32_firstpart	ardvm_message_type:message_branch_predictor_invalidate ardvm_va:invalidate_by_va, invalidate_not_by_va araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_branch_predictor_modes_virtaddr_msb47to16	Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb47to16 This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 Cross coverpoints: dvm_branch_predictor_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB43TO16	trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb43to16	ardvm_message_type ardvm_va araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb43to32_firstpart	ardvm_message_type:message_branch_predictor_invalidate ardvm_va:invalidate_by_va, invalidate_not_by_va araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_branch_predictor_modes_virtaddr_msb43to16	Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb43to16 This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 Cross coverpoints: dvm_branch_predictor_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB39TO16	trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb39to16	ardvm_message_type ardvm_va araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb39to32_firstpart	ardvm_message_type:message_branch_predictor_invalidate ardvm_va:invalidate_by_va, invalidate_not_by_va araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_branch_predictor_modes_virtaddr_msb39to16	Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb39to16 This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 Cross coverpoints: dvm_branch_predictor_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB63TO16	trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb63to32_firstpart dvm_message_phy_inst_cache_invl_bits	ardvm_message_type:message_physical_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16	Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16 This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation Cross coverpoints: dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB55TO16	trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb55to32_firstpart dvm_message_phy_inst_cache_invl_bits	ardvm_message_type:message_physical_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16	Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16 This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation Cross coverpoints: dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB47TO16	trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb47to32_firstpart dvm_message_phy_inst_cache_invl_bits	ardvm_message_type:message_physical_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16	Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16 This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation Cross coverpoints: dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB43TO16	trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb43to32_firstpart dvm_message_phy_inst_cache_invl_bits	ardvm_message_type:message_physical_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16	Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16 This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation Cross coverpoints: dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB39TO16	trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb39to32_firstpart dvm_message_phy_inst_cache_invl_bits	ardvm_message_type:message_physical_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16	Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16 This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation Cross coverpoints: dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB63TO16	trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb63to32_firstpart dvm_message_virt_inst_cache_invl_bits	ardvm_message_type:message_virtual_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16	Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16 This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message Cross coverpoints: dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB55TO16	trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb55to32_firstpart dvm_message_virt_inst_cache_invl_bits	ardvm_message_type:message_virtual_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16	Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16 This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message Cross coverpoints: dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB47TO16	trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb47to32_firstpart dvm_message_virt_inst_cache_invl_bits	ardvm_message_type:message_virtual_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16	Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16 This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message Cross coverpoints: dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB43TO16	trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb43to32_firstpart dvm_message_virt_inst_cache_invl_bits	ardvm_message_type:message_virtual_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16	Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16 This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message Cross coverpoints: dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB39TO16	trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16	ardvm_message_type araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb39to32_firstpart dvm_message_virt_inst_cache_invl_bits	ardvm_message_type:message_virtual_instruction_cache_invalidate araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16	Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16 This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: ardvm_message_type : Captures DVM Message Type araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message Cross coverpoints: dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB63TO16	trans_cross_ace_dvm_firstpart_addr_range_msb63to16	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb63to32_firstpart	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_firstpart_addr_range_msb63to16	Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb63to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32] and ARADDR[31:16]. The total virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 Cross coverpoints: dvm_firstpart_addr_range_msb63to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB55TO16	trans_cross_ace_dvm_firstpart_addr_range_msb55to16	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb55to32_firstpart	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_firstpart_addr_range_msb55to16	Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb55to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32] and ARADDR[31:16]. The total Virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 Cross coverpoints: dvm_firstpart_addr_range_msb55to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB47TO16	trans_cross_ace_dvm_firstpart_addr_range_msb47to16	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb47to32_firstpart	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_firstpart_addr_range_msb47to16	Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb47to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32] and ARADDR[31:16]. The total virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 Cross coverpoints: dvm_firstpart_addr_range_msb47to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB43TO16	trans_cross_ace_dvm_firstpart_addr_range_msb43to16	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb43to32_firstpart	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_firstpart_addr_range_msb43to16	Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb43to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32] and ARADDR[31:16]. The total virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 Cross coverpoints: dvm_firstpart_addr_range_msb43to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB39TO16	trans_cross_ace_dvm_firstpart_addr_range_msb39to16	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb39to32_firstpart	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_firstpart_addr_range_msb39to16	Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb39to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32] and ARADDR[31:16]. The total virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 Cross coverpoints: dvm_firstpart_addr_range_msb39to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_64	trans_cross_ace_dvm_firstpart_secondpart_addr_range_64	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb63to32_firstpart araddr_dvm_secondpart_64	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 araddr_dvm_secondpart_64:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4	dvm_firstpart_secondpart_addr_range_64	Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_64 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[63:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 araddr_dvm_secondpart_64 : Captures SecondPart of DVM of width64 Cross coverpoints: dvm_firstpart_secondpart_addr_range_64 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and araddr_dvm_secondpart_64. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_56	trans_cross_ace_dvm_firstpart_secondpart_addr_range_56	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb55to32_firstpart araddr_dvm_secondpart_56	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 araddr_dvm_secondpart_56:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4	dvm_firstpart_secondpart_addr_range_56	Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_56 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[55:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 araddr_dvm_secondpart_56 : Captures SecondPart of DVM of width56 Cross coverpoints: dvm_firstpart_secondpart_addr_range_56 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and araddr_dvm_secondpart_56 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_48	trans_cross_ace_dvm_firstpart_secondpart_addr_range_48	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb47to32_firstpart araddr_dvm_secondpart_48	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 araddr_dvm_secondpart_48:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4	dvm_firstpart_secondpart_addr_range_48	Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_48 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[47:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 araddr_dvm_secondpart_48 : Captures SecondPart of DVM of width48 Cross coverpoints: dvm_firstpart_secondpart_addr_range_48 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and araddr_dvm_secondpart_48 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_44	trans_cross_ace_dvm_firstpart_secondpart_addr_range_44	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb43to32_firstpart araddr_dvm_secondpart_44	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 araddr_dvm_secondpart_44:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4	dvm_firstpart_secondpart_addr_range_44	Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_44 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[43:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 araddr_dvm_secondpart_44 : Captures SecondPart of DVM of width44 Cross coverpoints: dvm_firstpart_secondpart_addr_range_44 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and araddr_dvm_secondpart_44 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_DVM_MODES	AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_40	trans_cross_ace_dvm_firstpart_secondpart_addr_range_40	araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb39to32_firstpart araddr_dvm_secondpart_40	araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 araddr_dvm_secondpart_40:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3	dvm_firstpart_secondpart_addr_range_40	Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_40 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[39:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 araddr_dvm_secondpart_40 : Captures SecondPart of DVM of width40 Cross coverpoints: dvm_firstpart_secondpart_addr_range_40 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and araddr_dvm_secondpart_40 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB63TO16	trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb63to16	acdvm_message_type acdvm_hypervisor_type acdvm_security_type acdvm_addr_mode_bits acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb63to32_firstpart	acdvm_message_type:message_tlb_invalidate acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el acdvm_security_type:no_secure, secure, secure_and_no_secure acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3	dvm_snoop_tlbinvl_modes_virtaddr_msb63to16	Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb63to16 This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: acdvm_message_type : Captures DVM Message Type acdvm_hypervisor_type : Captures OS type acdvm_security_type : Captures Security type acdvm_addr_mode_bits : Captures addr invalidate modes acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width32 Cross coverpoints: dvm_snoop_tlbinvl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB55TO16	trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb55to16	acdvm_message_type acdvm_hypervisor_type acdvm_security_type acdvm_addr_mode_bits acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb55to32_firstpart	acdvm_message_type:message_tlb_invalidate acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el acdvm_security_type:no_secure, secure, secure_and_no_secure acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_snoop_tlbinvl_modes_virtaddr_msb55to16	Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb55to16 This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: acdvm_message_type : Captures DVM Message Type acdvm_hypervisor_type : Captures OS type acdvm_security_type : Captures Security type acdvm_addr_mode_bits : Captures addr invalidate modes acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 Cross coverpoints: dvm_snoop_tlbinvl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB43TO16	trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb43to16	acdvm_message_type acdvm_hypervisor_type acdvm_security_type acdvm_addr_mode_bits acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb43to32_firstpart	acdvm_message_type:message_tlb_invalidate acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el acdvm_security_type:no_secure, secure, secure_and_no_secure acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_snoop_tlbinvl_modes_virtaddr_msb43to16	Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb43to16 This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: acdvm_message_type : Captures DVM Message Type acdvm_hypervisor_type : Captures OS type acdvm_security_type : Captures Security type acdvm_addr_mode_bits : Captures addr invalidate modes acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width12 Cross coverpoints: dvm_snoop_tlbinvl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB39TO16	trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb39to16	acdvm_message_type acdvm_hypervisor_type acdvm_security_type acdvm_addr_mode_bits acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb39to32_firstpart	acdvm_message_type:message_tlb_invalidate acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el acdvm_security_type:no_secure, secure, secure_and_no_secure acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_snoop_tlbinvl_modes_virtaddr_msb39to16	Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb39to16 This covergroup is cross coverage ofsnoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: acdvm_message_type : Captures DVM Message Type acdvm_hypervisor_type : Captures OS type acdvm_security_type : Captures Security type acdvm_addr_mode_bits : Captures addr invalidate modes acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 Cross coverpoints: dvm_snoop_tlbinvl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB47TO16	trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb47to32_firstpart snoop_dvm_message_phy_inst_cache_invl_bits	acdvm_message_type:message_physical_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb47to16	Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16 This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB63TO16	trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb63to32_firstpart snoop_dvm_message_phy_inst_cache_invl_bits	acdvm_message_type:message_physical_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3 snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb63to16	Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16 This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB55TO16	trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb55to32_firstpart snoop_dvm_message_phy_inst_cache_invl_bits	acdvm_message_type:message_physical_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb55to16	Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16 This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB43TO16	trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb43to32_firstpart snoop_dvm_message_phy_inst_cache_invl_bits	acdvm_message_type:message_physical_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb43to16	Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16 This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB39TO16	trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb39to32_firstpart snoop_dvm_message_phy_inst_cache_invl_bits	acdvm_message_type:message_physical_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache	dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb39to16	Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16 This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB63TO16	trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb63to32_firstpart snoop_dvm_message_virt_inst_cache_invl_bits	acdvm_message_type:message_virtual_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3 snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb63to16	Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16 This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB55TO16	trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb55to32_firstpart snoop_dvm_message_virt_inst_cache_invl_bits	acdvm_message_type:message_virtual_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb55to16	Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16 This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB47TO16	trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb47to32_firstpart snoop_dvm_message_virt_inst_cache_invl_bits	acdvm_message_type:message_virtual_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb47to16	Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16 This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB43TO16	trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb43to32_firstpart snoop_dvm_message_virt_inst_cache_invl_bits	acdvm_message_type:message_virtual_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb43to16	Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16 This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB39TO16	trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16	acdvm_message_type acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb39to32_firstpart snoop_dvm_message_virt_inst_cache_invl_bits	acdvm_message_type:message_virtual_instruction_cache_invalidate acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os	dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb39to16	Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16 This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: acdvm_message_type : Captures DVM Message Type acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc Cross coverpoints: dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_typ and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpar and snoop_dvm_message_virt_inst_cache_invl_bits Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB63TO16	trans_cross_ace_snoop_dvm_firstpart_addr_range_msb63to16	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb63to32_firstpart	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3	snoop_dvm_firstpart_addr_range_msb63to16	Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb63to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32] and ARADDR[31:16]. The total virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 Cross coverpoints: snoop_dvm_firstpart_addr_range_msb63to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB55TO16	trans_cross_ace_snoop_dvm_firstpart_addr_range_msb55to16	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb55to32_firstpart	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	snoop_dvm_firstpart_addr_range_msb55to16	Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb55to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32] and ARADDR[31:16]. The total virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 Cross coverpoints: snoop_dvm_firstpart_addr_range_msb55to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB47TO16	trans_cross_ace_snoop_dvm_firstpart_addr_range_msb47to16	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb47to32_firstpart	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	snoop_dvm_firstpart_addr_range_msb47to16	Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb47to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32] and ARADDR[31:16]. The total virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 Cross coverpoints: snoop_dvm_firstpart_addr_range_msb47to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB43TO16	trans_cross_ace_snoop_dvm_firstpart_addr_range_msb43to16	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb43to32_firstpart	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	snoop_dvm_firstpart_addr_range_msb43to16	Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb43to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32] and ARADDR[31:16]. The total virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 Cross coverpoints: snoop_dvm_firstpart_addr_range_msb43to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB39TO16	trans_cross_ace_snoop_dvm_firstpart_addr_range_msb39to16	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb39to32_firstpart	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	snoop_dvm_firstpart_addr_range_msb39to16	Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb39to16 This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32] and ARADDR[31:16]. The total virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 Cross coverpoints: snoop_dvm_firstpart_addr_range_msb39to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_64	trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_64	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb63to32_firstpart acaddr_dvm_secondpart_64	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3 acaddr_dvm_secondpart_64:dvm_acaddr_secondpart_range_1, dvm_acaddr_secondpart_range_2, dvm_acaddr_secondpart_range_3, dvm_acaddr_secondpart_range_4	snoop_dvm_firstpart_secondpart_addr_range_64	Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_64 This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[63:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[63:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32 acaddr_dvm_secondpart_64 : Captures SecondPart of DVM of width64 Cross coverpoints: snoop_dvm_firstpart_secondpart_addr_range_64 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and acaddr_dvm_secondpart_64 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_56	trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_56	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb55to32_firstpart acaddr_dvm_secondpart_56	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 acaddr_dvm_secondpart_56:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4	snoop_dvm_firstpart_secondpart_addr_range_56	Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_56 This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[55:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[55:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 acaddr_dvm_secondpart_56 : Captures SecondPart of DVM of width56 Cross coverpoints: snoop_dvm_firstpart_secondpart_addr_range_56 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and acaddr_dvm_secondpart_56 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_48	trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_48	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb47to32_firstpart acaddr_dvm_secondpart_48	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3 acaddr_dvm_secondpart_48:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4	snoop_dvm_firstpart_secondpart_addr_range_48	Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_48 This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[47:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[47:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 acaddr_dvm_secondpart_48 : Captures SecondPart of DVM of width48 Cross coverpoints: snoop_dvm_firstpart_secondpart_addr_range_48 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and acaddr_dvm_secondpart_48 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_44	trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_44	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb43to32_firstpart acaddr_dvm_secondpart_44	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 acaddr_dvm_secondpart_44:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4	snoop_dvm_firstpart_secondpart_addr_range_44	Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_44 This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[43:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[43:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12 acaddr_dvm_secondpart_44 : Captures SecondPart of DVM of width44 Cross coverpoints: snoop_dvm_firstpart_secondpart_addr_range_44 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and acaddr_dvm_secondpart_44 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_40	trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_40	acaddr_dvm_firstpart_va_or_vmid acaddr_dvm_firstpart_va_or_asid acaddr_dvm_msb39to32_firstpart acaddr_dvm_secondpart_40	acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4 acaddr_dvm_secondpart_40:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3	snoop_dvm_firstpart_secondpart_addr_range_40	Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_40 This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[39:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[39:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 acaddr_dvm_secondpart_40 : Captures SecondPart of DVM of width40 Cross coverpoints: snoop_dvm_firstpart_secondpart_addr_range_40 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart and acaddr_dvm_secondpart_40 Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB63TO16	trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb63to16	ardvm_message_type ardvm_hypervisor_type ardvm_security_type ardvm_addr_mode_bits araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb63to32_firstpart	ardvm_message_type:message_tlb_invalidate ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el ardvm_security_type:no_secure, secure, secure_and_no_secure ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_tlbinvl_modes_virtaddr_msb63to16	Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb63to16 This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_hypervisor_type : Captures OS type ardvm_security_type : Captures Security type ardvm_addr_mode_bits : Captures addr invalidate modes araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width32 Cross coverpoints: dvm_tlbinvl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB55TO16	trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb55to16	ardvm_message_type ardvm_hypervisor_type ardvm_security_type ardvm_addr_mode_bits araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb55to32_firstpart	ardvm_message_type:message_tlb_invalidate ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el ardvm_security_type:no_secure, secure, secure_and_no_secure ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_tlbinvl_modes_virtaddr_msb55to16	Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb55to16 This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_hypervisor_type : Captures OS type ardvm_security_type : Captures Security type ardvm_addr_mode_bits : Captures addr invalidate modes araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24 Cross coverpoints: dvm_tlbinvl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB47TO16	trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb47to16	ardvm_message_type ardvm_hypervisor_type ardvm_security_type ardvm_addr_mode_bits araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb47to32_firstpart	ardvm_message_type:message_tlb_invalidate ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el ardvm_security_type:no_secure, secure, secure_and_no_secure ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3	dvm_tlbinvl_modes_virtaddr_msb47to16	Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb47to16 This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_hypervisor_type : Captures OS type ardvm_security_type : Captures Security type ardvm_addr_mode_bits : Captures addr invalidate modes araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16 Cross coverpoints: dvm_tlbinvl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB43TO16	trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb43to16	ardvm_message_type ardvm_hypervisor_type ardvm_security_type ardvm_addr_mode_bits araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb43to32_firstpart	ardvm_message_type:message_tlb_invalidate ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el ardvm_security_type:no_secure, secure, secure_and_no_secure ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_tlbinvl_modes_virtaddr_msb43to16	Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb43to16 This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_hypervisor_type : Captures OS type ardvm_security_type : Captures Security type ardvm_addr_mode_bits : Captures addr invalidate modes araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width12 Cross coverpoints: dvm_tlbinvl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_ACE_SNOOP_DVM_MODES	AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB39TO16	trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb39to16	ardvm_message_type ardvm_hypervisor_type ardvm_security_type ardvm_addr_mode_bits araddr_dvm_firstpart_va_or_vmid araddr_dvm_firsrpart_va_or_asid araddr_dvm_msb39to32_firstpart	ardvm_message_type:message_tlb_invalidate ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el ardvm_security_type:no_secure, secure, secure_and_no_secure ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4 araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4 araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4	dvm_tlbinvl_modes_virtaddr_msb39to16	Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb39to16 This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40. Coverpoints: ardvm_message_type : Captures DVM Message Type ardvm_hypervisor_type : Captures OS type ardvm_security_type : Captures Security type ardvm_addr_mode_bits : Captures addr invalidate modes araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8 Cross coverpoints: dvm_tlbinvl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_ARVALID_ARREADY_COVER_ACVALID_ACREADY_ACSNOOP	trans_cross_dvm_overlap_arvalid_arready_cover_acvalid_acready_acsnoop	arvalid arready_0 acvalid acready acsnoop	arvalid:arvalid_val arready_0:arready_val_0 acvalid:acvalid_val_1, acvalid_val_0 acready:acready_val_1, acready_val_0 acsnoop:acsnoop_val	overlap_case_dvm_arvalid_arready_acvalid_acready_acsnoop	Covergroup: trans_cross_dvm_overlap_arvalid_arready_cover_acvalid_acready_acsnoop This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when ARVALID == 1 and ARREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: arvalid : Captures ARVALID == 1 arready_0 : Captures ARREADY == 0 acvalid : Captures ACVALID == 1 acready : Captures ACREADY == 1 acsnnop : Captures ACSNOOP == DVM Cross coverpoints: overlap_case_dvm_arvalid_arready_acvalid_acready_acsnoop : Crosses coverpoints arvaild and arready_0 and acvalid and acready and acsnoop
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_AWVALID_AWREADY_COVER_ACVALID_ACREADY_ACSNOOP	trans_cross_dvm_overlap_awvalid_awready_cover_acvalid_acready_acsnoop	awvalid awready_0 acvalid acready acsnoop	awvalid:awvalid_val awready_0:awready_val_0 acvalid:acvalid_val_1, acvalid_val_0 acready:acready_val_1, acready_val_0 acsnoop:acsnoop_val	overlap_case_dvm_awvalid_high_awready_low_acvalid_acready_acsnoop	Covergroup: trans_cross_dvm_overlap_awvalid_awready_cover_acvalid_acready_acsnoop This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when AWVALID == 1 & AWREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: awvalid : Captures AWVALID == 1 awready_0 : Captures AWREADY == 0 acvalid : Captures ACVALID == 1 acready : Captures ACREADY == 1 acsnnop : Captures ACSNOOP == DVM Cross coverpoints: overlap_case_dvm_awvalid_high_awready_low_acvalid_acready_acsnoop : Crosse coverpoints awvalid and awready_0 and acvalid and acready and acsnoop
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_RVALID_RREADY_COVER_ACVALID_ACREADY_ACSNOOP	trans_cross_dvm_overlap_rvalid_rready_cover_acvalid_acready_acsnoop	rvalid_1 rready_0 acvalid acready acsnoop	rvalid_1:rvalid_val_1 rready_0:rready_val_0 acvalid:acvalid_val_1, acvalid_val_0 acready:acready_val_1, acready_val_0 acsnoop:acsnoop_val	overlap_case_dvm_rvalid_high_rready_low_acvalid_acready_acsnoop	Covergroup: trans_cross_dvm_overlap_rvalid_rready_cover_acvalid_acready_acsnoop This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when RVALID == 1 & RREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: rvalid_1 : Captures RVALID == 1 rready_0 : Captures RREADY == 0 acvalid : Captures ACVALID == 1 acready : Captures ACREADY == 1 acsnnop : Captures ACSNOOP == DVM Cross coverpoints: overlap_case_dvm_rvalid_high_rready_low_acvalid_acready_acsnoop : Crosses coverpoints rvalid_1 and rready_0 and acvalid and cready and acsnoop
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_BVALID_BREADY_COVER_ACVALID_ACREADY_ACSNOOP	trans_cross_dvm_overlap_bvalid_bready_cover_acvalid_acready_acsnoop	bvalid_1 bready_0 acvalid acready acsnoop	bvalid_1:bvalid_val_1 bready_0:bready_val_0 acvalid:acvalid_val_1, acvalid_val_0 acready:acready_val_1, acready_val_0 acsnoop:acsnoop_val	overlap_case_dvm_bvalid_high_bready_low_acvalid_acready_acsnoop	Covergroup: trans_cross_dvm_overlap_bvalid_bready_cover_acvalid_acready_acsnoop This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when BVALID == 1 & BREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: bvalid_1 : Captures BVALID == 1 bready_0 : Captures BREADY == 0 acvalid : Captures ACVALID == 1 acready : Captures ACREADY == 1 acsnnop : Captures ACSNOOP == DVM Cross coverpoints: overlap_case_dvm_bvalid_high_bready_low_acvalid_acready_acsnoop : Crosses coverpoints bvalid_1 and bready_0 and acvalid and acready and acsnoop
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_ARVALID_ARREADY_COVER_CRVALID_CRREADY	trans_cross_dvm_overlap_arvalid_arready_cover_crvalid_crready	arvalid arready_0 crvalid crready	arvalid:arvalid_val arready_0:arready_val_0 crvalid:crvalid_val_1, crvalid_val_0 crready:crready_val_1, crready_val_0	overlap_case_dvm_arvalid_high_arready_low_crvalid_crready	Covergroup: trans_cross_dvm_overlap_arvalid_arready_cover_crvalid_crready This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when ARVALID == 1 and ARREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: arvalid : Captures ARVALID == 1 arready_0 : Captures ARREADY == 0 crvalid : Captures CRVALID == 1 crready : Captures CRREADY == 1 Cross coverpoints: overlap_case_dvm_arvalid_high_arready_low_crvalid_crready : Crosses coverpoints arvalid and arready_0 and crvalid and crready
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_AWVALID_AWREADY_COVER_CRVALID_CRREADY	trans_cross_dvm_overlap_awvalid_awready_cover_crvalid_crready	awvalid awready_0 crvalid crready	awvalid:awvalid_val awready_0:awready_val_0 crvalid:crvalid_val_1, crvalid_val_0 crready:crready_val_1, crready_val_0	overlap_case_dvm_awvalid_high_awready_low_crvalid_crready	Covergroup: trans_cross_dvm_overlap_awvalid_awready_cover_crvalid_crready This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when AWVALID == 1 & AWREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: awvalid : Captures AWVALID == 1 awready_0 : Captures AWREADY == 0 crvalid : Captures CRVALID == 1 crready : Captures CRREADY == 1 Cross coverpoints: overlap_case_dvm_awvalid_high_awready_low_crvalid_crready : Crosses coverpoints awvalid and awready_0 and crvalid and crready
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_RVALID_RREADY_COVER_CRVALID_CRREADY	trans_cross_dvm_overlap_rvalid_rready_cover_crvalid_crready	rvalid_1 rready_0 crvalid crready	rvalid_1:rvalid_val_1 rready_0:rready_val_0 crvalid:crvalid_val_1, crvalid_val_0 crready:crready_val_1, crready_val_0	overlap_case_dvm_rvalid_high_rready_low_crvalid_crready	Covergroup: trans_cross_dvm_overlap_rvalid_rready_cover_crvalid_crready This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when RVALID == 1 & RREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: rvalid_1 : Captures RVALID == 1 rready_0 : Captures RREADY == 0 crvalid : Captures CRVALID == 1 crready : Captures CRREADY == 1 Cross coverpoints: overlap_case_dvm_rvalid_high_rready_low_crvalid_crready : Crosses coverpoints rvalid_1 and rready_0 and crvalid and crready
AXI_PORT_MON_DVM_OVERLAP	AXI_PORT_MON_DVM_OVERLAP_BVALID_BREADY_COVER_CRVALID_CRREADY	trans_cross_dvm_overlap_bvalid_bready_cover_crvalid_crready	bvalid_1 bready_0 crvalid crready	bvalid_1:bvalid_val_1 bready_0:bready_val_0 crvalid:crvalid_val_1, crvalid_val_0 crready:crready_val_1, crready_val_0	overlap_case_dvm_bvalid_high_bready_low_crvalid_crready	Covergroup: trans_cross_dvm_overlap_bvalid_bready_cover_crvalid_crready This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when BVALID == 1 & BREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: bvalid_1 : Captures BVALID == 1 bready_0 : Captures BREADY == 0 crvalid : Captures CRVALID == 1 crready : Captures CRREADY == 1 Cross coverpoints: overlap_case_dvm_bvalid_high_bready_low_crvalid_crready : Crosses coverpoints bvalid_1 and bready_0 and crvalid and crready
AXI_PORT_MON_VALID_READY_XACT_FLOW	--	signal_master_slave_valid_ready_dependency	AWVALID_AWREADY_Dependency AWVALID_WREADY_Dependency AWVALID_RVALID_Dependency AWVALID_BVALID_Dependency WVALID_AWREADY_Dependency WVALID_WREADY_Dependency WVALID_RVALID_Dependency WVALID_BVALID_Dependency RREADY_AWREADY_Dependency RREADY_WREADY_Dependency RREADY_RVALID_Dependency RREADY_BVALID_Dependency BREADY_AWREADY_Dependency BREADY_WREADY_Dependency BREADY_RVALID_Dependency BREADY_BVALID_Dependency	AWVALID_AWREADY_Dependency:AWVALID_and_AWREADY AWVALID_WREADY_Dependency:AWVALID_and_WREADY AWVALID_RVALID_Dependency:AWVALID_and_RVALID AWVALID_BVALID_Dependency:AWVALID_and_BVALID WVALID_AWREADY_Dependency:WVALID_and_AWREADY WVALID_WREADY_Dependency:WVALID_and_WREADY WVALID_RVALID_Dependency:WVALID_and_RVALID WVALID_BVALID_Dependency:WVALID_and_BVALID RREADY_AWREADY_Dependency:RREADY_and_AWREADY RREADY_WREADY_Dependency:RREADY_and_WREADY RREADY_RVALID_Dependency:RREADY_and_RVALID RREADY_BVALID_Dependency:RREADY_and_BVALID BREADY_AWREADY_Dependency:BREADY_and_AWREADY BREADY_WREADY_Dependency:BREADY_and_WREADY BREADY_RVALID_Dependency:BREADY_and_RVALID BREADY_BVALID_Dependency:BREADY_and_BVALID	--	Covergroup: signal_master_slave_valid_ready_dependency The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after AWREADY is deasserted, then coverpoint AWVALID_AWREADY_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1. Coverpoints: AWVALID_AWREADY_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency) after AWREADY is deasserted. AWVALID_WREADY_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_wready_dependency) after WREADY is deasserted. AWVALID_RVALID_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_rvalid_dependency) after RVALID is deasserted. AWVALID_BVALID_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_bvalid_dependency) after BVALID is deasserted. WVALID_AWREADY_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_awready_dependency) after AWREADY is deasserted. WVALID_WREADY_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_wready_dependency) after WREADY is deasserted. WVALID_RVALID_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_rvalid_dependency) after RVALID is deasserted. WVALID_BVALID_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_bvalid_dependency) after BVALID is deasserted. RREADY_AWREADY_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_awready_dependency) after AWREADY is deasserted. RREADY_WREADY_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_wready_dependency) after WREADY is deasserted. RREADY_RVALID_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_rvalid_dependency) after RVALID is deasserted. RREADY_BVALID_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_bvalid_dependency) after BVALID is deasserted. BREADY_AWREADY_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_awready_dependency) after AWREADY is deasserted. BREADY_WREADY_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_wready_dependency) after WREADY is deasserted. BREADY_RVALID_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_rvalid_dependency) after RVALID is deasserted. BREADY_BVALID_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_bvalid_dependency) after BVALID is deasserted.
AXI_PORT_MON_VALID_READY_XACT_FLOW	--	signal_master_valid_ready_dependency	AWVALID_WVALID_Dependency AWVALID_RREADY_Dependency AWVALID_BREADY_Dependency WVALID_AWVALID_Dependency WVALID_RREADY_Dependency WVALID_BREADY_Dependency RREADY_AWVALID_Dependency RREADY_WVALID_Dependency RREADY_BREADY_Dependency BREADY_AWVALID_Dependency BREADY_WVALID_Dependency BREADY_RREADY_Dependency	AWVALID_WVALID_Dependency:AWVALID_and_WVALID AWVALID_RREADY_Dependency:AWVALID_and_RREADY AWVALID_BREADY_Dependency:AWVALID_and_BREADY WVALID_AWVALID_Dependency:WVALID_and_AWVALID WVALID_RREADY_Dependency:AWVALID_and_RREADY WVALID_BREADY_Dependency:WVALID_and_BREADY RREADY_AWVALID_Dependency:RREADY_and_AWVALID RREADY_WVALID_Dependency:RREADY_and_WVALID RREADY_BREADY_Dependency:RREADY_and_BREADY BREADY_AWVALID_Dependency:BREADY_and_AWVALID BREADY_WVALID_Dependency:BREADY_and_WVALID BREADY_RREADY_Dependency:BREADY_and_RREADY	--	Covergroup: signal_master_valid_ready_dependency The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after wvalid is deasserted, then coverpoint AWVALID_WVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1. Coverpoints: AWVALID_WVALID_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency) after WVALID is deasserted. AWVALID_RREADY_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_rready_dependency) after RREADY is deasserted. AWVALID_BREADY_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_bready_dependency) after BREADY is deasserted. WVALID_AWVALID_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_awvalid_dependency) after AWVALID is deasserted. WVALID_RREADY_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_rready_dependency) after RREADY is deasserted. WVALID_BREADY_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_bready_dependency) after BREADY is deasserted. RREADY_AWVALID_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_awvalid_dependency) after AWVALID is deasserted. RREADY_WVALID_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_wvalid_dependency) after WVALID is deasserted. RREADY_BREADY_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_bready_dependency) after BREADY is deasserted. BREADY_AWVALID_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_awvalid_dependency) after AWVALID is deasserted. BREADY_WVALID_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_wvalid_dependency) after WVALID is deasserted. BREADY_RREADY_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_rready_dependency) after RREADY is deasserted.
AXI_PORT_MON_VALID_READY_XACT_FLOW	--	signal_slave_master_valid_ready_dependency	AWREADY_AWVALID_Dependency AWREADY_WVALID_Dependency AWREADY_RVALID_Dependency AWREADY_BVALID_Dependency WREADY_AWVALID_Dependency WREADY_WVALID_Dependency WREADY_RREADY_Dependency WREADY_BREADY_Dependency RVALID_AWREADY_Dependency RVALID_WREADY_Dependency RVALID_RREADY_Dependency RVALID_BREADY_Dependency BVALID_AWREADY_Dependency BVALID_WREADY_Dependency BVALID_RREADY_Dependency BVALID_BREADY_Dependency	AWREADY_AWVALID_Dependency:AWREADY_and_AWVALID AWREADY_WVALID_Dependency:AWREADY_and_WVALID AWREADY_RVALID_Dependency:AWREADY_and_RVALID AWREADY_BVALID_Dependency:AWREADY_and_BVALID WREADY_AWVALID_Dependency:WREADY_and_AWVALID WREADY_WVALID_Dependency:WREADY_and_WVALID WREADY_RREADY_Dependency:WREADY_and_RREADY WREADY_BREADY_Dependency:WREADY_and_BREADY RVALID_AWREADY_Dependency:RVALID_and_AWREADY RVALID_WREADY_Dependency:RVALID_and_WREADY RVALID_RREADY_Dependency:RVALID_and_RREADY RVALID_BREADY_Dependency:RVALID_and_BREADY BVALID_AWREADY_Dependency:BVALID_and_AWREADY BVALID_WREADY_Dependency:BVALID_and_WREADY BVALID_RREADY_Dependency:BVALID_and_RREADY BVALID_BREADY_Dependency:BVALID_and_BREADY	--	Covergroup: signal_slave_master_valid_ready_dependency The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWREADY has to remain deasserted for N clocks (user input) after AWVALID is deasserted, then coverpoint AWREADY_AWVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1. Coverpoints: AWREADY_AWVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_awvalid_dependency) after AWVALIDis deasserted. AWREADY_WVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_wvalid_dependency) after WVALID is deasserted. AWREADY_RVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_rvalid_dependency) after RVALID is deasserted. AWREADY_BVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_bvalid_dependency) after BVALID is deasserted. WREADY_AWVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_awvalid_dependency) after AWVALID is deasserted. WREADY_WVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_wvalid_dependency) after WVALID is deasserted. WREADY_RREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_rready_dependency) after RREADY is deasserted. WREADY_BREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_bready_dependency) after BREADY is deasserted. RVALID_AWREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_awready_dependency) after AWREADY is deasserted. RVALID_WREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_wready_dependency) after WREADY is deasserted. RVALID_RREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_rready_dependency) after RREADY is deasserted. RVALID_BREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_bready_dependency) after BREADY is deasserted. BVALID_AWREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_awready_dependency) afterAWREADY is deasserted. BVALID_WREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_wready_dependency) after WREADY is deasserted. BVALID_RREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_rready_dependency) after RREADY is deasserted. BVALID_BREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_bready_dependency) after BREADY is deasserted.
AXI_PORT_MON_VALID_READY_XACT_FLOW	--	signal_slave_valid_ready_dependency	WREADY_ARREADY_Dependency WREADY_RVALID_Dependency WREADY_BVALID_Dependency ARREADY_WREADY_Dependency ARREADY_RVALID_Dependency ARREADY_BVALID_Dependency RVALID_ARREADY_Dependency RVALID_WREADY_Dependency RVALID_BVALID_Dependency BVALID_ARREADY_Dependency BVALID_WREADY_Dependency BVALID_RVALID_Dependency	WREADY_ARREADY_Dependency:WREADY_and_ARREADY WREADY_RVALID_Dependency:WREADY_and_RVALID WREADY_BVALID_Dependency:WREADY_and_BVALID ARREADY_WREADY_Dependency:ARREADY_and_WREADY ARREADY_RVALID_Dependency:ARREADY_and_RVALID ARREADY_BVALID_Dependency:ARREADY_and_BVALID RVALID_ARREADY_Dependency:RVALID_and_ARREADY RVALID_WREADY_Dependency:RVALID_and_WREADY RVALID_BVALID_Dependency:RVALID_and_BVALID BVALID_ARREADY_Dependency:BVALID_and_ARREADY BVALID_WREADY_Dependency:BVALID_and_WREADY BVALID_RVALID_Dependency:BVALID_and_RVALID	--	Covergroup: signal_slave_valid_ready_dependency The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal WREADY has to remain deasserted for N clocks (user input) after arready is deasserted, then coverpoint WREADY_ARREADY_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_wready_arready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1. Coverpoints: WREADY_ARREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_arready_dependency) after ARREADY is deasserted. WREADY_RVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_rvalid_dependency) after RVALID is deasserted. WREADY_BVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_bvalid_dependency) after BVALID is deasserted. ARREADY_WREADY_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_wready_dependency) after WREADY is deasserted. ARREADY_RVALID_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_rvalid_dependency) after RVALID is deasserted. ARREADY_BVALID_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_bvalid_dependency) after BVALID is deasserted. RVALID_ARREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_arready_dependency) after ARREADY is deasserted. RVALID_WREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_wready_dependency) after WREADY is deasserted. RVALID_BVALID_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_bvalid_dependency) after BVALID is deasserted. BVALID_ARREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_arready_dependency) after ARREADY is deasserted. BVALID_WREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_wready_dependency) after WREADY is deasserted. BVALID_RVALID_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_rvalid_dependency) after RVALID is deasserted.
AXI_STREAM_PORT_MON_XACT_FLOW	--	trans_axi4_stream_delay	TVALID_Delay TREADY_Delay	TVALID_Delay:tvalid_delay_min, tvalid_delay_mid, tvalid_delay_max TREADY_Delay:tready_delay_min, tready_delay_mid, tready_delay_max	--	Covergroup: trans_meta_axi_read This Covergroup captures delay scenarios for tvalid signal for AXI4_STREAM. It is constructed and sampled when interface type is AXI4_STREAM & trans_axi4_stream_delay_enable is asserted. Coverpoints: TVALID_Delay: Captures min, mid and max range of delay signal tvalid TREADY_Delay: Captures min, mid and max range of delay signal tready
AXI_STREAM_PORT_MON_XACT_FLOW	--	trans_cross_stream_xact_type_tid_tdest	stream_xact_type stream_tid stream_tdest	stream_xact_type:byte_stream, continuous_aligned_stream, continuous_unaligned_stream, sparse_stream, user_stream stream_tid:tid_within_range stream_tdest:tdest_within_range	trans_cross_stream_xact_type_tid trans_cross_stream_xact_type_tdest trans_cross_stream_xact_type_tid_tdest	Covergroup: trans_cross_stream_xact_type_tid_tdest This Covergroup captures stream xact_type, stream tid and stream tdest. It is constructed when interface_type is AXI4_STREAM and trans_cross_stream_xact_type_tid_tdest_enable set to 1. Coverpoints: stream_xact_type: Captures the type of stream stream_tid: Captures the value of TID stream_tdest: Captures the value of TDEST Cross coverpoints: trans_cross_stream_xact_type_tid_tdest: Crosses cover points stream_xact_type, stream_tid and stream_tdest trans_cross_stream_xact_type_tid: Crosses coverpoints stream_xact_type and stream_tid trans_cross_stream_xact_type_tdest: Crosses coverpoints stream_xact_type and stream_tdest
AXI_STREAM_PORT_MON_XACT_FLOW	--	trans_meta_axi4_stream	TVALID_to_TREADY_Delay TVALID_to_prev_TVALID_Delay TVALID_before_TREADY TREADY_before_TVALID	TVALID_to_TREADY_Delay:tvalid_to_tready_delay_min, tvalid_to_tready_delay_mid, tvalid_to_tready_delay_max TVALID_to_prev_TVALID_Delay:tvalid_to_prev_tvalid_delay_min, tvalid_to_prev_tvalid_delay_mid, tvalid_to_prev_tvalid_delay_max TVALID_before_TREADY:tvalid_before_tready TREADY_before_TVALID:tready_before_tvalid	--	Covergroup: trans_meta_axi4_stream This Covergroup captures delay scenarios for tvalid and tready for AXI4_STREAM. It is constructed and sampled when interface type is AXI4_STREAM & trans_meta_axi4_stream_enable is asserted. Coverpoints: TVALID_to_TREADY_Delay: Captures min, mid and max range of delays between signals tvalid and tready TVALID_to_prev_TVALID_Delay: Captures min, mid and max range of delays between current and previous tvalid signals TVALID_before_TREADY: Captures if TVALID signal comes before TREADY signal TREADY_before_TVALID: Captures if TREADY signal comes before TVALID signal
AXI_PORT_MON_MASTER_TO_SLAVE_PATH`	AXI_PORT_MON_MASTER_TO_SLAVE_PATH_ACCESS_ACE	trans_cross_master_to_slave_path_access_ace	coherent_read_xact_type coherent_write_xact_type all_slaves slaves_excluding_register_space	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact all_slaves:slvs_b slaves_excluding_register_space:slvs_no_cfg_b	cross_read_xact_type_with_slave cross_write_xact_type_with_slave	This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI_ACE or ACE_LITE and trans_cross_master_to_slave_path_access_ace_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_ace Coverpoints: all_slaves : Captures all participating path cov slaves slaves_excluding_register_space : Captures all non axi/ace register address space slaves coherent_read_xact_type: Captures readonce coherent read transaction coherent_write_xact_type: Captures coherent write transaction Cross coverpoints: cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6
AXI_PORT_MON_MASTER_TO_SLAVE_PATH`	AXI_PORT_MON_MASTER_TO_SLAVE_PATH_ACCESS_AXI4	trans_cross_master_to_slave_path_access_axi4	all_slaves slaves_excluding_register_space write_xact_type read_xact_type axi_ex_xact_type atomic_type burst_type axi_burst_size axi_response_type cache_type burst_length axi_address_aligned axi_wstrb_beat_0 axi_wstrb_beat_1 axi_wstrb_beat_2 axi_wstrb_beat_3 axi_wstrb_beat_15	all_slaves:slvs_b slaves_excluding_register_space:slvs_no_cfg_b write_xact_type:write_xact read_xact_type:read_xact axi_ex_xact_type:exclusive_type atomic_type:normal, locked burst_type:fixed_burst, incr_burst, wrap_burst axi_burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit axi_response_type:axi_okay_response, axi_exokay_response, axi_slverr_response, axi_decerr_response, axi_exokay_fail_response cache_type:rd_device_non_bufferable, rd_device_bufferable, rd_normal_non_cacheable_non_bufferable, rd_normal_non_cacheable_bufferable, rd_write_through_no_allocate, rd_write_through_read_allocate, rd_write_through_write_allocate, rd_write_through_read_and_write_allocate, rd_write_back_no_allocate, rd_write_back_read_allocate, rd_write_back_write_allocate, rd_write_back_read_and_write_allocate, wr_device_non_bufferable, wr_device_bufferable, wr_normal_non_cacheable_non_bufferable, wr_normal_non_cacheable_bufferable, wr_write_through_no_allocate, wr_write_through_read_allocate, wr_write_through_write_allocate, wr_write_through_read_and_write_allocate, wr_write_back_no_allocate, wr_write_back_read_allocate, wr_write_back_write_allocate, wr_write_back_read_and_write_allocate burst_length:burst_length axi_address_aligned:axi_8bit_aligned_address, axi_16bit_aligned_address, axi_32bit_aligned_address, axi_64bit_aligned_address, axi_128bit_aligned_address, axi_256bit_aligned_address	cache_len_1_all_okay cache_len_reduced_all_okay cache_len_reduced_ignore_response cache_all_okay_fixed cache_all_slverr_fixed cache_all_okay_fixed_unaligned cache_ignore_resp_fixed_unaligned master_to_slave_all_okay master_to_slave_ignore_response master_to_slave_decerr_len_1 master_to_slave_slverr_len_1 master_to_slave_decerr master_to_slave_slverr master_to_all_slave_ignore_response cross_xact_type_len_1_wstrb cross_xact_type_len_2_wstrb cross_xact_type_len_3_wstrb cross_xact_type_len_4_wstrb cross_xact_type_len_16_wstrb cross_aligned_unaligned_addr_asize cross_aligned_unaligned_addr_asize_ignore_resp master_to_slave_x_wr_okay_addr_align master_to_slave_x_wr_fail_addr_align master_to_slave_x_wr_decerr master_to_slave_x_wr_slverr master_to_slave_x_wr_okay_wstrb master_to_slave_x_wr_fail_wstrb	This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI4 and trans_cross_master_to_slave_path_access_axi4_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_axi4 Coverpoints: all_slaves : Captures all participating path cov slaves slaves_excluding_register_space : Captures all non axi/ace register address space slaves coherent_read_xact_type: Captures readonce coherent read transaction coherent_write_xact_type: Captures coherent write transaction Cross coverpoints: cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6
AXI_PORT_MON_XACT_FLOW	--	trans_ar_aw_stalled_for_ac_channel	axi_ar_aw_stalled_for_ac_channel	axi_ar_aw_stalled_for_ac_channel:readonce_stalled_for_snoop, readshared_stalled_for_snoop, readclean_stalled_for_snoop, readnotshareddirty_stalled_for_snoop, readunique_stalled_for_snoop, cleanunique_stalled_for_snoop, makeunique_stalled_for_snoop, cleanshared_stalled_for_snoop, cleaninvalid_stalled_for_snoop, makeinvalid_stalled_for_snoop, writeunique_stalled_for_snoop, writelineunique_stalled_for_snoop	--	Covergroup: trans_ar_aw_stalled_for_ac_channel This Covergroup captures stalled read and write transaction y interconnect when request is issued from master. It is constructed when interface_type is AXI_ACE & interface_category is AXI_READ_WRITE and trans_ar_aw_stalled_for_ac_channel_enable set to 1. Coverpoints: axi_ar_aw_stalled_for_ac_channel: This is covered when read transaction on AR channel OR WriteUnique/WriteLineUnique transactions on AW channel from a master are stalled by interconnect, while waiting for the snoop response from the same master. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_axi_write_handshake_delay	last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay last_AWVALID_AWREADY_handshake_to_next_AWVALID_Delay last_AWVALID_AWREADY_handshake_to_next_AWREADY_Delay last_AWREADY_to_next_AWVALID_AWREADY_handshake_Delay last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay last_WVALID_WREADY_handshake_to_next_WVALID_Delay last_WVALID_WREADY_handshake_to_next_WREADY_Delay last_WREADY_to_next_WVALID_WREADY_handshake_Delay last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay last_BVALID_BREADY_handshake_to_next_BVALID_Delay last_BVALID_BREADY_handshake_to_next_BREADY_Delay last_BVALID_to_next_BVALID_Delay last_BREADY_to_next_BREADY_Delay last_BREADY_to_next_BVALID_BREADY_handshake_Delay	last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay:last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_min, last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_mid, last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_max last_AWVALID_AWREADY_handshake_to_next_AWVALID_Delay:last_awvalid_awready_handshake_to_next_awvalid_delay_min, last_awvalid_awready_handshake_to_next_awvalid_delay_mid, last_awvalid_awready_handshake_to_next_awvalid_delay_max last_AWVALID_AWREADY_handshake_to_next_AWREADY_Delay:last_awvalid_awready_handshake_to_next_awready_delay_min, last_awvalid_awready_handshake_to_next_awready_delay_mid, last_awvalid_awready_handshake_to_next_awready_delay_max last_AWREADY_to_next_AWVALID_AWREADY_handshake_Delay:last_awready_to_next_awvalid_awready_handshake_delay_min, last_awready_to_next_awvalid_awready_handshake_delay_mid, last_awready_to_next_awvalid_awready_handshake_delay_max last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay:last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_min, last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_mid, last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_max last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay:last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_min, last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_mid, last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_max last_WVALID_WREADY_handshake_to_next_WVALID_Delay:last_wvalid_wready_handshake_to_next_wvalid_delay_min, last_wvalid_wready_handshake_to_next_wvalid_delay_mid, last_wvalid_wready_handshake_to_next_wvalid_delay_max last_WVALID_WREADY_handshake_to_next_WREADY_Delay:last_wvalid_wready_handshake_to_next_wready_delay_min, last_wvalid_wready_handshake_to_next_wready_delay_mid, last_wvalid_wready_handshake_to_next_wready_delay_max last_WREADY_to_next_WVALID_WREADY_handshake_Delay:last_wready_to_next_wvalid_wready_handshake_delay_min, last_wready_to_next_wvalid_wready_handshake_delay_mid, last_wready_to_next_wvalid_wready_handshake_delay_max last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay:last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_min, last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_mid, last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_max last_BVALID_BREADY_handshake_to_next_BVALID_Delay:last_bvalid_bready_handshake_to_next_bvalid_delay_min, last_bvalid_bready_handshake_to_next_bvalid_delay_mid, last_bvalid_bready_handshake_to_next_bvalid_delay_max last_BVALID_BREADY_handshake_to_next_BREADY_Delay:last_bvalid_bready_handshake_to_next_bready_delay_min, last_bvalid_bready_handshake_to_next_bready_delay_mid, last_bvalid_bready_handshake_to_next_bready_delay_max last_BVALID_to_next_BVALID_Delay:last_BVALID_to_next_BVALID_delay_min, last_BVALID_to_next_BVALID_delay_mid, last_BVALID_to_next_BVALID_delay_max last_BREADY_to_next_BREADY_Delay:last_BREADY_to_next_BREADY_delay_min, last_BREADY_to_next_BREADY_delay_mid, last_BREADY_to_next_BREADY_delay_max last_BREADY_to_next_BVALID_BREADY_handshake_Delay:last_bready_to_next_bvalid_bready_handshake_delay_min, last_bready_to_next_bvalid_bready_handshake_delay_mid, last_bready_to_next_bvalid_bready_handshake_delay_max	--	Covergroup: trans_axi_write_handshake_delay This Covergroup captures handshaking between valid and ready signal for diferent delay scenarios for write address and write data channels. It is constructed and sampled when interface type is not AXI_READ_ONLY. Coverpoints: last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay:Captures min, mid and max range of delays between last awvalid_awready handshake to the next awvalid_awready handshake last_AWVALID_AWREADY_handshake_to_next_AWVALID_Delay: Captures min,mid and max range of delays between last awvalid_awready handshake to the next awvalid last_AWVALID_AWREADY_handshake_to_next_AWREADY_Delay: Captures min,mid and max range of delays between last awvalid_awready handshake to the next awready last_AWREADY_to_next_AWVALID_AWREADY_handshake_Delay: Captures min,mid and max range of delays between last awready to the next awvalid_awready handshake last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wvalid_wready handshake last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay: Captures min, mid and max range of delays between last wvalid_wready data beat handshake to the next wvalid_wready data beat handshake last_WVALID_WREADY_handshake_to_next_WVALID_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wvalid last_WVALID_WREADY_handshake_to_next_WREADY_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wready last_WREADY_to_next_WVALID_WREADY_handshake_Delay: Captures min,mid and max range of delays between last wready to the next wvalid_wready handshake last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay:Captures min, mid and max range of delays between last bvalid_bready handshake to the next bvalid_bready handshake last_BVALID_BREADY_handshake_to_next_BVALID_Delay: Captures min, mid and max range of delays between last bvalid_bready handshake to the next bvalid last_BVALID_BREADY_handshake_to_next_BREADY_Delay: Captures min, mid and max range of delays between last bvalid_bready handshake to the next bready last_BVALID_to_next_BVALID_Delay: Captures min, mid and max range of delays between last bvalid to the next bvalid last_BREADY_to_next_BREADY_Delay: Captures min, mid and max range of delays between last bready to the next bready last_BREADY_to_next_BVALID_BREADY_handshake_Delay: Captures min, mid and max range of delays between last bready to the next bvalid_bready handshake
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_ace_acdvmmessage_acdvmresp	acdvm_message_type acdvm_resp	acdvm_message_type:message_tlb_invalidate, message_branch_predictor_invalidate, message_physical_instruction_cache_invalidate, message_virtual_instruction_cache_invalidate, message_synchronization, message_hint acdvm_resp:message_accept, message_reject	acdvmmessage_acdvmresp	Covergroup: trans_cross_ace_acdvmmessage_acdvmresp This covergroup captures snoop dvm message and response type. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acdvmmessage_acdvmresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: acdvm_message_type : Captures DVM message on acaddr[14:12] acdvm_resp : Capture DVM response on crresp, accept = 5'b00000 and reject = 5'b00010 Cross coverpoints: acdvmmessage_acdvmresp : Crosses coverpoints acdvm_message_type and acdvm_resp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_ace_awsnoop_awaddr	coherent_write_xact_type addr	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact addr:addr_range_min, addr_range_mid, addr_range_max	awsnoop_awaddr	Covergroup: trans_cross_ace_awsnoop_awaddr This Covergroup captures coherant write transaction and address. It is constructed and sampled when trans_cross_ace_awsnoop_awaddr_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction addr : Captures transaction write address Cross coverpoints: awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_ace_awsnoop_awburst	coherent_write_xact_type burst_type slave_port_id	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact burst_type:fixed_burst, incr_burst, wrap_burst slave_port_id:slave_id	awsnoop_awburst	Covergroup: trans_cross_ace_awsnoop_awburst This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_category is not AXI_READ_ONLY and trans_cross_ace_awsnoop_awburst_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction burst_type: Captures transaction burst type Cross coverpoints: awsnoop_awburst_ : Crosses cover points coherent_write_xact_type ,burst_type and slave_port_id
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_ace_awsnoop_awlen	coherent_write_xact_type burst_length slave_port_id	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact burst_length:burst_length slave_port_id:slave_id	awsnoop_awlen	Covergroup : trans_cross_ace_awsnoop_awlen This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction burst_length: Captures transaction burst length Cross coverpoints: awsnoop_awlen : Crosses cover points coherent_write_xact_type ,burst_length and slave_port_id
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_ace_awsnoop_awsize	coherent_write_xact_type burst_size slave_port_id	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit slave_port_id:slave_id	awsnoop_awsize	Covergroup : trans_cross_ace_awsnoop_awsize This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction burst_size: Captures transaction burst sizes Cross coverpoints: awsnoop_awsize : Crosses cover points coherent_write_xact_type ,burst_size and slave_port_id
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_awunique_awsnoop_awbar	coherent_write_xact_type awunique_val barrier_type	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact awunique_val:is_not_unique, is_unique barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization	awunique_awsnoop_awbar	Covergroup: trans_cross_awunique_awsnoop_awbar This Covergroup captures coherant write xact_type,awunique_val,barrier_type and awunique_awsnoop_awbar values for write transaction. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_READ_ONLY and awunique_enable set to 1. Coverpoints: coherent_write_xact_type: Captures write transction type. Includes WRITENOSNOOP, WRITEUNIQUE, WRITELINEUNIQUE, WRITECLEAN, WRITEBACK, EVICT, WRITEBARRIER and WRITEEVICT awunique_val: Captures the value of signal AWUNIQUE in above transactions barrier_type: Captures the value of barrier type (AWBAR), in above transactions awunique_awsnoop_awbar: Cross of coherent_write_xact_type, awunique_val and barrier_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_axi3_awburst_awlen	write_xact_type burst_type burst_length	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length	axi3_awburst_awlen	This covergroup captures attributes of write transaction type,burst_type and burst_length for AXI3 interface Covergroup: trans_cross_axi3_awburst_awlen It is constructed abd sampled when interface type set to AXI3. Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type burst_length: Captures ranges of burst_length Cross coverpoints: axi3_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_axi3_awburst_awlen_awaddr	write_xact_type burst_type burst_length addr	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length addr:addr_range_min, addr_range_mid, addr_range_max	axi3_awburst_awlen_awaddr	This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI3. Covergroup: trans_cross_axi3_awburst_awlen_awaddr Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length addr: Captures min, mid and max range of transaction address Cross coverpoints: axi3_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_axi3_awburst_awlen_bresp	write_xact_type burst_type burst_length bresp	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp	axi3_awburst_awlen_bresp	This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction. It is constructed and sampled when interface type is set to AXI3. Covergroup: trans_cross_axi3_awburst_awlen_bresp Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length bresp: Captures transaction response Cross coverpoints: axi3_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_axi4_awburst_awlen	write_xact_type burst_type burst_length	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length	axi4_awburst_awlen	This covergroup captures attributes of write transaction type,burst_type and burst_length for AXI4 interface Covergroup: trans_cross_axi4_awburst_awlen It is constructed abd sampled when interface type set to AXI4. Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type burst_length: Captures ranges of burst_length Cross coverpoints: axi4_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_axi4_awburst_awlen_awaddr	write_xact_type burst_type burst_length addr	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length addr:addr_range_min, addr_range_mid, addr_range_max	axi4_awburst_awlen_awaddr	This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI4. Covergroup: trans_cross_axi4_awburst_awlen_awaddr Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length addr: Captures min, mid and max range of transaction address Cross coverpoints: axi4_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_axi4_awburst_awlen_bresp	write_xact_type burst_type burst_length bresp	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp	axi4_awburst_awlen_bresp	This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction It is constructed and sampled when interface type is set to AXI4. Covergroup: trans_cross_axi4_awburst_awlen_bresp Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length bresp: Captures transaction response Cross coverpoints: axi4_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_cross_axi_awburst_awqos	write_xact_type burst_type qos	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst qos:qos_range_0_1, qos_range_2_3, qos_range_4_7, qos_range_8_15	axi_awburst_awqos	This covergroup captures attributes of burst_type and qos for AXI transaction at subordinate. Covergroup: trans_cross_axi_awburst_awqos It is constructed when interface type can be AXI4, AXI-ACE or ACE-LITE. It is sampled when transaction type is set to WRITE OR READ_WRITE Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type qos: Captures ranges of QOS values Cross coverpoints: axi_awburst_awqos: Crosses cover points write_xact_type, burst_type and qos
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_master_ace_write_during_speculative_fetch	ace_write_during_speculative_fetch	ace_write_during_speculative_fetch:overlapping_write_during_readonce, overlapping_write_during_readclean, overlapping_write_during_readnotshareddirty, overlapping_write_during_readunique, overlapping_write_during_readshared	--	Covergroup: trans_master_ace_write_during_speculative_fetch It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_write_during_speculative_fetch_enable set to 1. Coverpoints: ace_write_during_speculative_fetch: This cover point covers the following condition: A master issues a read transaction. This results in interconnect generating snoop transactions towards other masters within the domain. The interconnect also generates speculative read transaction for this location. Speculative transaction returns data while the snoop transactions do not return data. The snoop transactions may not return data, either because there is no entry in the snooped masters' caches or a WRITEBACK/WRITECLEAN of dirty data is in progress. The interconnect now detects that a write transaction (the WRITEBACK/WRITECLEAN which is in progress) is received for the same address for which it did a speculative fetch. In such situation, interconnect performs another read from main memory, as originally received data from speculative read is now stale At least One ACE master needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_master_ace_xacts_with_high_priority_from_other_master_during_barrier	ace_xacts_with_high_priority_from_other_master_during_barrier	ace_xacts_with_high_priority_from_other_master_during_barrier:xacts_from_other_master_during_barrier	--	Covergroup: trans_master_ace_xacts_with_high_priority_from_other_master_during_barrier It is constructed and sampled when system_ace_xacts_with_high_priority_from_other_master_during_barrier_enable ,barrier_enable and system_monitor_enable set to 1. Coverpoints: ace_xacts_with_high_priority_from_other_master_during_barrier: This cover point covers the following condition: When the interconnect receives barrier from a master, then all other transactions launched by other masters in that domain may be stalled. This cover point covers condition where master issues transactions with non-zero QOS value. Then another master issues a barrier transaction within the same domain. Two or more ACE/ACE_LITE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_XACT_FLOW	trans_meta_axi_write	AWVALID_to_AWREADY_Delay WVALID_to_WREADY_Delay BVALID_to_BREADY_Delay AWVALID_to_prev_AWVALID_Delay WVALID_to_prev_WVALID_Delay AWVALID_to_first_WVALID_Delay last_wdata_handshake_to_BVALID_Delay AWVALID_before_AWREADY AWREADY_before_AWVALID BVALID_before_BREADY BREADY_before_BVALID WVALID_before_WREADY WREADY_before_WVALID AWVALID_before_WREADY WREADY_before_AWVALID AWREADY_before_WVALID WVALID_before_AWREADY AWVALID_before_WVALID WVALID_before_AWVALID	AWVALID_to_AWREADY_Delay:awvalid_to_awready_delay_min, awvalid_to_awready_delay_mid, awvalid_to_awready_delay_max WVALID_to_WREADY_Delay:wvalid_to_wready_delay_min, wvalid_to_wready_delay_mid, wvalid_to_wready_delay_max BVALID_to_BREADY_Delay:bvalid_to_bready_delay_min, bvalid_to_bready_delay_mid, bvalid_to_bready_delay_max AWVALID_to_prev_AWVALID_Delay:awvalid_to_prev_awvalid_delay_min, awvalid_to_prev_awvalid_delay_mid, awvalid_to_prev_awvalid_delay_max WVALID_to_prev_WVALID_Delay:wvalid_to_prev_wvalid_delay_min, wvalid_to_prev_wvalid_delay_mid, wvalid_to_prev_wvalid_delay_max AWVALID_to_first_WVALID_Delay:awvalid_to_first_wvalid_delay_min, awvalid_to_first_wvalid_delay_mid, awvalid_to_first_wvalid_delay_max last_wdata_handshake_to_BVALID_Delay:last_wdata_handshake_to_bvalid_delay_min, last_wdata_handshake_to_bvalid_delay_mid, last_wdata_handshake_to_bvalid_delay_max AWVALID_before_AWREADY:awvalid_before_awready AWREADY_before_AWVALID:awready_before_awvalid BVALID_before_BREADY:bvalid_before_bready BREADY_before_BVALID:bready_before_bvalid WVALID_before_WREADY:wvalid_before_wready WREADY_before_WVALID:wready_before_wvalid AWVALID_before_WREADY:awvalid_before_wready WREADY_before_AWVALID:wready_before_awvalid AWREADY_before_WVALID:awready_before_wvalid WVALID_before_AWREADY:wvalid_before_awready AWVALID_before_WVALID:awvalid_before_wvalid WVALID_before_AWVALID:wvalid_before_awvalid	--	Covergroup: trans_meta_axi_write This Covergroup captures delay and predelay scenarios for handshake between valid and ready signal for write address, write data,write response channels It is constructed sampled when interface type is not AXI_READ_ONLY & trans_meta_axi_write_enable is asserted. Coverpoints: AWVALID_to_AWREADY_Delay: Captures min, mid and max range of delays between signals awvalid and awready WVALID_to_WREADY_Delay: Captures min, mid and max range of delays between signals wvalid and wready BVALID_to_BWREADY_Delay: Captures min, mid and max range of delays between signals bvalid and bready AWVALID_to_prev_AWVALID_Delay: Captures min, mid and max range of delays between current and previous awvalid signals WVALID_to_prev_WVALID_Delay: Captures min, mid and max range of delays between current and previous wvalid signals AWVALID_to_first_WVALID_Delay: Captures min, mid and max range of delays between awvalid and first wvalid signals last_wdata_handshake_to_BVALID_Delay: Captures min, mid and max range of delays between last write data handshake to bvalid signals AWVALID_before_AWREADY: Captures if AWVALID signal comes before AWREADY signal AWREADY_before_AWVALID: Captures if AWREADY signal comes before AWVALID signal BVALID_before_BREADY: Captures if BVALID signal comes before BREADY signal BREADY_before_BVALID: Captures if BREADY signal comes before BVALID signal WVALID_before_WREADY: Captures if WVALID signal comes before WREADY signal WREADY_before_WVALID: Captures if WREADY signal comes before WVALID signal or WREADY,WVALID signals are comes at same time AWVALID_before_WREADY: Captures if AWVALID signal comes before WREADY signal WREADY_before_AWVALID: Captures if WREADY signal comes before AWVALID signal AWREADY_before_WVALID: Captures if AWREADY signal comes before WVALID signal WVALID_before_AWREADY: Captures if WVALID signal comes before AWREADY signal AWVALID_before_WVALID: Captures if AWVALID signal comes before WVALID signal WVALID_before_AWVALID: Captures if WVALID signal comes before AWVALID signal
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_axi_read_handshake_delay	last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay last_ARVALID_ARREADY_handshake_to_next_ARVALID_Delay last_ARVALID_ARREADY_handshake_to_next_ARREADY_Delay last_ARREADY_to_next_ARVALID_ARREADY_handshake_Delay last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay last_RVALID_RREADY_handshake_to_next_RVALID_Delay last_RVALID_RREADY_handshake_to_next_RREADY_Delay last_RREADY_to_next_RVALID_RREADY_handshake_Delay last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay	last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay:last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_min, last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_mid, last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_max last_ARVALID_ARREADY_handshake_to_next_ARVALID_Delay:last_arvalid_arready_handshake_to_next_arvalid_delay_min, last_arvalid_arready_handshake_to_next_arvalid_delay_mid, last_arvalid_arready_handshake_to_next_arvalid_delay_max last_ARVALID_ARREADY_handshake_to_next_ARREADY_Delay:last_arvalid_arready_handshake_to_next_arready_delay_min, last_arvalid_arready_handshake_to_next_arready_delay_mid, last_arvalid_arready_handshake_to_next_arready_delay_max last_ARREADY_to_next_ARVALID_ARREADY_handshake_Delay:last_arready_to_next_arvalid_arready_handshake_delay_min, last_arready_to_next_arvalid_arready_handshake_delay_mid, last_arready_to_next_arvalid_arready_handshake_delay_max last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay:last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_min, last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_mid, last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_max last_RVALID_RREADY_handshake_to_next_RVALID_Delay:last_rvalid_rready_handshake_to_next_rvalid_delay_min, last_rvalid_rready_handshake_to_next_rvalid_delay_mid, last_rvalid_rready_handshake_to_next_rvalid_delay_max last_RVALID_RREADY_handshake_to_next_RREADY_Delay:last_rvalid_rready_handshake_to_next_rready_delay_min, last_rvalid_rready_handshake_to_next_rready_delay_mid, last_rvalid_rready_handshake_to_next_rready_delay_max last_RREADY_to_next_RVALID_RREADY_handshake_Delay:last_rready_to_next_rvalid_rready_handshake_delay_min, last_rready_to_next_rvalid_rready_handshake_delay_mid, last_rready_to_next_rvalid_rready_handshake_delay_max last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay:last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_min, last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_mid, last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_max	--	Covergroup: trans_axi_read_handshake_delay This Covergroup captures handshaking between valid and ready signal for diferent delay scenarios for read address and read data channels. It is constructed and sampled when interface type is not AXI_WRITE_ONLY. Coverpoints: last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay:Captures min, mid and max range of delays between last arvalid_arready handshake to the next arvalid_arready handshake last_ARVALID_ARREADY_handshake_to_next_ARVALID_Delay: Captures min,mid and max range of delays between last arvalid_arready handshake to the next arvalid last_ARVALID_ARREADY_handshake_to_next_ARREADY_Delay: Captures min,mid and max range of delays between last arvalid_arready handshake to the next arready last_ARREADY_to_next_ARVALID_ARREADY_handshake_Delay: Captures min,mid and max range of delays between last arready to the next arvalid_arready handshake last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay:Captures min, mid and max range of delays between last rvalid_rready handshake to the next rvalid_rready handshake last_RVALID_RREADY_handshake_to_next_RVALID_Delay: Captures min,mid and max range of delays between last rvalid_rready handshake to the next rvalid last_RVALID_RREADY_handshake_to_next_RREADY_Delay: Captures min,mid and max range of delays between last rvalid_rready handshake to the next rready last_RREADY_to_next_RVALID_RREADY_handshake_Delay: Captures min,mid and max range of delays between last rready to the next rvalid_rready handshake last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay: Captures min, mid and max range of delays between last rvalid_rready data beat handshake to the next rvalid_rready data beat handshake
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_araddr	coherent_read_xact_type addr	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact addr:addr_range_min, addr_range_mid, addr_range_max	arsnoop_araddr	Covergroup: trans_cross_ace_arsnoop_araddr This Covergroup captures coherant read xact_type and address ranges for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_araddr_enable set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction addr : Captures transaction read address Cross coverpoints: arsnoop_araddr : Crosses cover points coherent_read_xact_type and addr
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_arbar	coherent_read_xact_type barrier_type	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization	arsnoop_arbar	Covergroup: trans_cross_ace_arsnoop_arbar This Covergroup captures coherant read xact_type and barrier_type for read transaction. It is constructed and sampled when when trans_cross_ace_arsnoop_arbar_enable and barrier_type set to 1 . Coverpoints: coherent_read_xact_type: Captures coherent read transaction barrier_type : Captures read barrier Cross coverpoints: arsnoop_arbar : Crosses cover points coherent_read_xact_type and barrier_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_arburst	coherent_read_xact_type burst_type slave_port_id	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact burst_type:fixed_burst, incr_burst, wrap_burst slave_port_id:slave_id	arsnoop_arburst	Covergroup: trans_cross_ace_arsnoop_arburst This Covergroup captures coherant read xact_type,burst_type and slave_port_id for read transaction. It is constructed and sampled when interface_type is not AXI_WRITE_ONLY & trans_cross_ace_arsnoop_arburst_enable is set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction burst_type: Captures transaction burst type Cross coverpoints: arsnoop_arburst : Crosses cover points coherent_read_xact_type and burst_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_arcache	coherent_read_xact_type cache_type slave_port_id	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable, write_through_no_allocate, write_through_read_allocate, write_through_write_allocate, write_through_read_and_write_allocate, write_back_no_allocate, write_back_read_allocate, write_back_write_allocate, write_back_read_and_write_allocate slave_port_id:slave_id	arsnoop_arcache	Covergroup: trans_cross_ace_arsnoop_arcache This Covergroup captures coherant read xact_type,cache signal and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_arcache_enable set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction cache_type : Captures transaction cache type Cross coverpoints: arsnoop_arcache : Crosses cover points coherent_read_xact_type and cache_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_ardomain	coherent_read_xact_type domain_type slave_port_id	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable slave_port_id:slave_id	arsnoop_ardomain	Covergroup: trans_cross_ace_arsnoop_ardomain This Covergroup captures coherant read xact_type,domain_type and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_ardomain_enable set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction domain_type : Captures transaction cache type Cross coverpoints: arsnoop_ardomain : Crosses cover points coherent_read_xact_type and cache_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_ardomain_arcache	coherent_read_xact_type domain_type cache_type	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable, write_through_no_allocate, write_through_read_allocate, write_through_write_allocate, write_through_read_and_write_allocate, write_back_no_allocate, write_back_read_allocate, write_back_write_allocate, write_back_read_and_write_allocate	arsnoop_ardomain_arcache	Covergroup: trans_cross_ace_arsnoop_ardomain_arcache This Covergroup captures coherant read xact_type,domain_type and cache signal for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_ardomain_arcache_enable set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction domain_type : Captures domain type cache_type : Captures cache_type Cross coverpoints: arsnoop_ardomain_arcache : Crosses cover points coherent_read_xact_type and domain_type and cache_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_arlen	coherent_read_xact_type burst_length slave_port_id	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact burst_length:burst_length slave_port_id:slave_id	arsnoop_arlen	Covergroup: trans_cross_ace_arsnoop_arlen This Covergroup captures coherant read xact_type,burst_length and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_arlen_enable is set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction burst_length: Captures transaction burst length Cross coverpoints: arsnoop_arlen : Crosses cover points coherent_read_xact_type and burst_length
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_ace_arsnoop_arsize	coherent_read_xact_type burst_size slave_port_id	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit slave_port_id:slave_id	arsnoop_arsize	Covergroup: trans_cross_ace_arsnoop_arsize This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction burst_size: Captures transaction burst size Cross coverpoints: arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi3_arburst_arlen	read_xact_type burst_type burst_length	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length	axi3_arburst_arlen	Covergroup: trans_cross_axi3_arburst_arlen This covergroup captures attributes of burst_type & burst_length for read transaction. It is constructed and sampled when interface type is AXI3 & trans_cross_axi3_arburst_arlen is asserted Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length Cross coverpoints: axi3_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi3_arburst_arlen_araddr	read_xact_type burst_type burst_length addr	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length addr:addr_range_min, addr_range_mid, addr_range_max	axi3_arburst_arlen_araddr	Covergroup: trans_cross_axi3_arburst_arlen_araddr This covergroup captures attributes of burst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI3. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length addr: Captures min, mid and max range of transaction address Cross coverpoints: axi3_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi3_arburst_arlen_araddr_arsize	read_xact_type burst_type burst_length addr burst_size	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length addr:addr_range_min, addr_range_mid, addr_range_max burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit	axi3_arburst_arlen_araddr_arsize	Covergroup: trans_cross_axi3_arburst_arlen_araddr_arsize This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for read transaction. It is constructed and sampled when interface_type is AXI3. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length addr: Captures min, mid and max range of transaction address burst_size: Captures transaction burst size Cross coverpoints: axi3_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi3_arburst_arlen_arlock	read_xact_type burst_type burst_length atomic_type	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length atomic_type:normal, exclusive, locked	axi3_arburst_arlen_arlock	Covergroup: trans_cross_axi3_arburst_arlen_arlock This covergroup captures attributes of burst_type,burst_length and atomic_type for read locked transaction. It is constructed and sampled when interface_type is AXI3. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length atomic_type: Captures transaction atomic type Cross coverpoints: axi3_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi3_arburst_arlen_arprot	read_xact_type burst_type burst_length prot_type	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged	axi3_arburst_arlen_arprot	Covergroup: trans_cross_axi3_arburst_arlen_arprot This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI3. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length prot_type: Captures transaction protection type Cross coverpoints: axi3_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi3_arburst_arlen_arsize	read_xact_type burst_type burst_length burst_size	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit	axi3_arburst_arlen_arsize	Covergroup: trans_cross_axi3_arburst_arlen_arsize This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface_type is AXI3. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length burst_size: Captures transaction burst size Cross coverpoints: axi3_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi3_arburst_arlen_rresp	read_xact_type burst_type burst_length rresp	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length rresp:okay_resp, exokay_resp, slverr_resp, decerr_resp	axi3_arburst_arlen_rresp	Covergroup: trans_cross_axi3_arburst_arlen_rresp This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI3. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length rresp: Captures transaction response Cross coverpoints: axi3_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi4_arburst_arlen	read_xact_type burst_type burst_length	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length	axi4_arburst_arlen	Covergroup: trans_cross_axi4_arburst_arlen This covergroup captures attributes of burst_type & burst_length for read transaction It is constructed and sampled when interface type is set to AXI4. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length Cross coverpoints: axi4_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi4_arburst_arlen_araddr	read_xact_type burst_type burst_length addr	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length addr:addr_range_min, addr_range_mid, addr_range_max	axi4_arburst_arlen_araddr	Covergroup: trans_cross_axi4_arburst_arlen_araddr This covergroup captures attributes of burst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length addr: Captures min, mid and max range of transaction address Cross coverpoints: axi4_arburst_arlen_araddr: Crosses cover points read_xact_type, burst_type, burst_length, addr
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi4_arburst_arlen_araddr_arsize	read_xact_type burst_type burst_length addr burst_size	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length addr:addr_range_min, addr_range_mid, addr_range_max burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit	axi4_arburst_arlen_araddr_arsize	Covergroup: trans_cross_axi4_arburst_arlen_araddr_arsize This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for read transaction. It is constructed and sampled when interface_type is AXI4. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length addr: Captures min, mid and max range of transaction address burst_size: Captures transaction burst size Cross coverpoints: axi4_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi4_arburst_arlen_arlock	read_xact_type burst_type burst_length atomic_type	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length atomic_type:normal, exclusive, locked	axi4_arburst_arlen_arlock	Covergroup: trans_cross_axi4_arburst_arlen_arlock This covergroup captures attributes of burst_type,burst_length and atomic_type for read locked transaction. It is constructed and sampled when interface_type is AXI4. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length atomic_type: Captures transaction atomic type Cross coverpoints: axi4_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi4_arburst_arlen_arprot	read_xact_type burst_type burst_length prot_type	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged	axi4_arburst_arlen_arprot	Covergroup: trans_cross_axi4_arburst_arlen_arprot This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI4. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length prot_type: Captures transaction protection type Cross coverpoints: axi4_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi4_arburst_arlen_arsize	read_xact_type burst_type burst_length burst_size	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit	axi4_arburst_arlen_arsize	Covergroup: trans_cross_axi4_arburst_arlen_arsize This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface_type is AXI4. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length burst_size: Captures transaction burst size Cross coverpoints: axi4_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi4_arburst_arlen_rresp	read_xact_type burst_type burst_length rresp	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length rresp:okay_resp, exokay_resp, slverr_resp, decerr_resp	axi4_arburst_arlen_rresp	Covergroup: trans_cross_axi4_arburst_arlen_rresp This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length rresp: Captures transaction response Cross coverpoints: axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi_arburst_arlen_arcache	read_xact_type burst_type burst_length cache_type	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst burst_length:burst_length cache_type:non_cacheable_non_bufferable, bufferable_or_modifiable_only, cacheable_but_no_alloc, cacheable_bufferable_but_no_alloc, cacheable_write_through_allocate_on_read_only, cacheable_write_back_allocate_on_read_only, cacheable_write_through_allocate_on_write_only, cacheable_write_back_allocate_on_write_only, cacheable_write_through_allocate_on_both_read_write, cacheable_write_back_allocate_on_both_read_write	axi_arburst_arlen_arcache	Covergroup: trans_cross_axi_arburst_arlen_arcache This covergroup captures attributes of burst_type,burst_length and cache_type for read transaction. It is constructed and sampled when trans_cross_axi_arburst_arlen_arcache_enable is asserted . Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type burst_length: Captures transaction burst length cache_type: Captures transaction cache type Cross coverpoints: axi_arburst_arlen_arcache: Crosses cover points read_xact_type, burst_type, burst_length, cache_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_cross_axi_arburst_arqos	read_xact_type burst_type qos	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst qos:qos_range_0_1, qos_range_2_3, qos_range_4_7, qos_range_8_15	axi_arburst_arqos	This covergroup captures attributes of burst_type and qos for AXI transaction at subordinate. Covergroup: trans_cross_axi_arburst_arqos It is constructed when interface type can be AXI4. It is sampled when transaction type is set to WRITE OR READ_WRITE Coverpoints: read_xact_type: Captures write transaction burst_type: Captures transaction burst type qos: Captures ranges of QOS values Cross coverpoints: axi_awburst_awqos: Crosses cover points write_xact_type, burst_type and qos
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_XACT_FLOW	trans_meta_axi_read	ARVALID_to_ARREADY_Delay RVALID_to_RREADY_Delay ARVALID_to_prev_ARVALID_Delay RVALID_to_prev_RVALID_Delay ARVALID_to_first_RVALID_Delay ARVALID_before_ARREADY ARREADY_before_ARVALID RVALID_before_RREADY RREADY_before_RVALID	ARVALID_to_ARREADY_Delay:arvalid_to_arready_delay_min, arvalid_to_arready_delay_mid, arvalid_to_arready_delay_max RVALID_to_RREADY_Delay:rvalid_to_rready_delay_min, rvalid_to_rready_delay_mid, rvalid_to_rready_delay_max ARVALID_to_prev_ARVALID_Delay:arvalid_to_prev_arvalid_delay_min, arvalid_to_prev_arvalid_delay_mid, arvalid_to_prev_arvalid_delay_max RVALID_to_prev_RVALID_Delay:rvalid_to_prev_rvalid_delay_min, rvalid_to_prev_rvalid_delay_mid, rvalid_to_prev_rvalid_delay_max ARVALID_to_first_RVALID_Delay:arvalid_to_first_rvalid_delay_min, arvalid_to_first_rvalid_delay_mid, arvalid_to_first_rvalid_delay_max ARVALID_before_ARREADY:arvalid_before_arready ARREADY_before_ARVALID:arready_before_arvalid RVALID_before_RREADY:rvalid_before_rready RREADY_before_RVALID:rready_before_rvalid	--	Covergroup: trans_meta_axi_read This Covergroup captures delay and predelay scenarios for handshake between valid and ready signal for read address, and read data channels. It is constructed and sampled when interface type is not AXI_WRITE_ONLY & trans_meta_axi_read_enable is asserted. Coverpoints: ARVALID_to_ARREADY_Delay: Captures min, mid and max range of delays between signals arvalid and arready RVALID_to_RREADY_Delay: Captures min, mid and max range of delays between signals rvalid and rready ARVALID_to_prev_ARVALID_Delay: Captures min, mid and max range of delays between current and previous arvalid signals RVALID_to_prev_RVALID_Delay: Captures min, mid and max range of delays between current and previous rvalid signals ARVALID_to_first_RVALID_Delay: Captures min, mid and max range of delays between arvalid and first rvalid signals ARVALID_before_ARREADY: Captures if ARVALID signal comes before ARREADY signal ARREADY_before_ARVALID: Captures if ARREADY signal comes before ARVALID signal RVALID_before_RREADY: Captures if RVALID signal comes before RREADY signal RREADY_before_RVALID: Captures if RREADY signal comes before RVALID signal
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_ace_barrier_outstanding_xact	barrier_outstanding_xact	barrier_outstanding_xact:barrier_outstanding_xact_range_low, barrier_outstanding_xact_range_med, barrier_outstanding_xact_range_max	--	Covergroup: trans_ace_barrier_outstanding_xact This Covergroup captures barrier outstanding transaction. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_ace_barrier_outstanding_xact_enable & barrier enable set to 1. Coverpoints: barrier_outstanding_xact : Captures total number of read and write barrier outstanding transactions. When svt_axi_port_configuration :: axi_interface_type is configured as AXI_ACE maximum number of 256 outstanding transactions is tracked. When svt_axi_port_configuration :: axi_interface_type is configured as ACE_LITE, outstanding transactions greater than 256 are also tracked. This is as per section C8.4.1 of AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613"
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid	num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid	num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid:num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid	--	Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid This covergroup captures the number of outstanding transactions with DVM TLBI requests with different ARID. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid_enable = 1 svt_axi_port_configuration :: cov_num_outstanding_xacts_range_enable = 0 svt_axi_port_configuration :: id_width != 0 svt_axi_port_configuration :: read_chan_id_width > 0 If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. Coverpoints: num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid: The number of bins will be equal to the programmed value of User-defined macron SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. If user does not override this macro then this covergroup will create 256 bins for ARID width greater than 8. Example: If outstanding DVM TLBI transactions have the following IDs: ARID1 ARID1 ARID2 ARID3 ARID4 ARID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with ARID1,ARID2 ARID3 ARID4 ARID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique ARID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique ARID values further bins will keep getting hit. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range	num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range	num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range:num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_0, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_1, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_2, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_3, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_4, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_5, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_6, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_7	--	Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range This covergroup captures the range of arid values for transactions with DVM TLBI requests. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_enable = 1 svt_axi_port_configuration :: cov_num_outstanding_xacts_range_enable = 1 svt_axi_port_configuration :: read_chan_id_width >= 3 If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. Coverpoints: num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range: This will construct eight different bins to cover all the possible ranges of arid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is Example: If id_wdith is 7 then num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range can be 0 to 127 and that will be cover under defined 8 bins as follows. num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_0 [0 : 15] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_1 [16 : 31] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_2 [32 : 47] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_3 [48 : 63] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_4 [64 : 79] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_5 [80 : 95] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_6 [96 : 111] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_7 [112 : 127] Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid	num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid	num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid:num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid	--	Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid This covergroup captures the number of outstanding transactions with DVM TLBI requests with a matching ARID. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid_enable = 1 Configured value of svt_axi_port_configuration :: cov_bins_dvm_tlbi_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_read_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support. Coverpoints: num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid: The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_dvm_tlbi_num_outstanding_xacts and the default value of which is 64. Example: If outstanding DVM TLBI transactions have the following IDs: ARID1 ARID1 ARID3 ARID1 ARID3 ARID2 and svt_axi_port_configuration :: cov_same_id_in_dvm_tlbi_outstanding_xacts is programmed to ARID1. The bins hit will be 1,2 and 3 as there are 3 outstanding DVM TLBI transactions matching with ARID1. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_ace_num_outstanding_snoop_xacts	num_outstanding_snoop_xacts	num_outstanding_snoop_xacts:num_outstanding_snoop_xacts	--	Covergroup: trans_ace_num_outstanding_snoop_xacts It is constructed and sampled when interface_type is AXI_ACE and trans_ace_num_outstanding_snoop_xacts_enable set to 1. Coverpoints: num_outstanding_snoop_xacts: Captures the number of outstanding snoop transactions.The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_snoop_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_snoop_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_snoop_xact which indicates the number of outstanding snoop transactions VIP can support. Applicable only for master and when svt_axi_port_configuration :: axi_interface_type is ACE. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_diff_arid	read_outstanding_xacts_with_diff_arid	read_outstanding_xacts_with_diff_arid:read_outstanding_xacts_with_diff_arid	--	Covergroup: trans_axi_num_outstanding_xacts_with_diff_arid It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_arid_enable & id_width set to 1 and cov_num_outstanding_xacts_range_enable set to 0. Coverpoints: read_outstanding_xacts_with_diff_arid: Captures the number of outstanding read transactions with different ARID value. The number of bins will be equal to the programmed value of User-defined macro SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. So, if user does not override this macro then this covergroup will create 256 bins for ARID width greater than 8 If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins. Example: If outstanding transactions have the following IDs: ARID1 ARID1 ARID2 ARID3 ARID4 ARID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with ARID1,ARID2 ARID3 ARID4 ARID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique ARID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique ARID values further bins will keep getting hit. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_diff_arid_range	read_outstanding_xacts_with_diff_arid_range	read_outstanding_xacts_with_diff_arid_range:read_outstanding_xacts_with_diff_arid_range_0, read_outstanding_xacts_with_diff_arid_range_1, read_outstanding_xacts_with_diff_arid_range_2, read_outstanding_xacts_with_diff_arid_range_3, read_outstanding_xacts_with_diff_arid_range_4, read_outstanding_xacts_with_diff_arid_range_5, read_outstanding_xacts_with_diff_arid_range_6, read_outstanding_xacts_with_diff_arid_range_7	--	Covergroup: trans_axi_num_outstanding_xacts_with_diff_arid_range It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_arid_range_enable & cov_num_outstanding_xacts_range_enable set to 1 and read_chan_id_width >=3. Coverpoints: read_outstanding_xacts_with_diff_arid_range: This cover group captures the range of arid values of outstanding read transactions. This covergroup will construct eight different bins to cover all the possible ranges of arid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins. Example: If id_wdith is 7 then read_outstanding_xacts_with_diff_arid_range can be 0 to 127 and that will be cover under defined 8 bins as follows. read_outstanding_xacts_with_diff_arid_range_0 [0 : 15] read_outstanding_xacts_with_diff_arid_range_1 [16 : 31] read_outstanding_xacts_with_diff_arid_range_2 [32 : 47] read_outstanding_xacts_with_diff_arid_range_3 [48 : 63] read_outstanding_xacts_with_diff_arid_range_4 [64 : 79] read_outstanding_xacts_with_diff_arid_range_5 [80 : 95] read_outstanding_xacts_with_diff_arid_range_6 [96 : 111] read_outstanding_xacts_with_diff_arid_range_7 [112 : 127] Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_diff_awid	write_outstanding_xacts_with_diff_awid	write_outstanding_xacts_with_diff_awid:write_outstanding_xacts_with_diff_awid	--	Covergroup: trans_axi_num_outstanding_xacts_with_diff_awid It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_awid_enable & cov_num_outstanding_xacts_range_enable set to 1 ,num_outstanding_xacts is not -1 and id_width is not 0. Coverpoints: write_outstanding_xacts_with_diff_awid: Captures the number of outstanding write transactions with different AWID. The number of bins will be equal to the programmed value of User-defined macro SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. So, if user does not override this macro then this covergroup will create 256 bins for AWID width greater than 8 If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: write_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins. Example: If outstanding transactions have the following IDs: AWID1 AWID1 AWID2 AWID3 AWID4 AWID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with AWID1,AWID2 AWID3 AWID4 AWID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique AWID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique AWID values further bins will keep getting hit. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_diff_awid_range	write_outstanding_xacts_with_diff_awid_range	write_outstanding_xacts_with_diff_awid_range:write_outstanding_xacts_with_diff_awid_range_0, write_outstanding_xacts_with_diff_awid_range_1, write_outstanding_xacts_with_diff_awid_range_2, write_outstanding_xacts_with_diff_awid_range_3, write_outstanding_xacts_with_diff_awid_range_4, write_outstanding_xacts_with_diff_awid_range_5, write_outstanding_xacts_with_diff_awid_range_6, write_outstanding_xacts_with_diff_awid_range_7	--	Covergroup: trans_axi_num_outstanding_xacts_with_diff_awid_range It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_awid_range_enable & cov_num_outstanding_xacts_range_enable set to 1 ,num_outstanding_xacts is not -1 and write_chan_id_width >= 3. Coverpoints: write_outstanding_xacts_with_diff_awid_range: This cover group captures the range of awid values of outstanding write transactions. This covergroup will construct eight different bins to cover all the possible ranges of awid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins. Example: If id_wdith is 7 then write_outstanding_xacts_with_diff_awid_range can be 0 to 127 and that will be cover under defined 8 bins as follows. write_outstanding_xacts_with_diff_awid_range_0 [0 : 15] write_outstanding_xacts_with_diff_awid_range_1 [16 : 31] write_outstanding_xacts_with_diff_awid_range_2 [32 : 47] write_outstanding_xacts_with_diff_awid_range_3 [48 : 63] write_outstanding_xacts_with_diff_awid_range_4 [64 : 79] write_outstanding_xacts_with_diff_awid_range_5 [80 : 95] write_outstanding_xacts_with_diff_awid_range_6 [96 : 111] write_outstanding_xacts_with_diff_awid_range_7 [112 : 127] Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_multiple_same_arid	read_outstanding_same_id num_outstanding_read	read_outstanding_same_id:read_same_arid num_outstanding_read:read_outstanding_xacts	cross_same_id_with_num_outstanding_xacts	Covergroup: trans_axi_num_outstanding_xacts_with_multiple_same_arid This covergroup captures the number of outstanding read transactions with same ARID values which is in progress, if master is programmed with multiple same ids. For Example : If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], then the master will have three different ids ARID1, ARID2 and ARID3.This covergroup will cross all the 3 ids with svt_axi_port_configuration :: num_outstanding_xact. If number of outstanding transactions are 50 with ARID1,then bins read_same_arid_1, read_outstanding_xacts_with_same_arid_1 to read_outstanding_xacts_with_same_arid_50 will get hit. It is constructed and sampled when interface_category is not AXI_WRITE_ONLY and num_outstanding_xact is not -1 & trans_axi_num_outstanding_xacts_with_multiple_same_arid_enable set to 1. Coverpoints: read_outstanding_same_id: Captures the same id values programmed in svt_axi_port_configuration :: cov_multi_same_ids num_outstanding_read : Captures number of outstanding read transactions with a matching ARID values to the one programmed in svt_axi_port_configuration :: cov_multi_same_ids. The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support. Example: If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], cov_multi_same_ids[0] = ARID1, cov_multi_same_ids[1] = ARID2, cov_multi_same_ids[1] = ARID3 and outstanding transactions have the following IDs: ARID1 ARID2 ARID1 ARID4 ARID3 ARID1 ARID3 ARID5 ARID2. The bins of read_outstanding_same_id hit will be read_same_arid_1,read_same_arid_2 and read_same_arid_3, bins of cross_same_id_with_num_outstanding_xacts hit will be read_same_arid_1 with read_outstanding_xacts_3,read_same_arid_2 with read_outstanding_xacts_2, read_same_arid_3 with read_outstanding_xacts_1 as there are 3 outstanding transactions matching with ARID1, 2 outstanding transactions with ARID2 and 1 outstanding transaction with ARID3. Cross Coverpoints : cross_same_id_with_num_outstanding_xacts: Crosses coverpoints read_outstanding_same_id and num_outstanding_read Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_multiple_same_awid	write_outstanding_same_id num_outstanding_write	write_outstanding_same_id:write_same_awid num_outstanding_write:write_outstanding_xacts	cross_same_id_with_num_outstanding_xacts	Covergroup: trans_axi_num_outstanding_xacts_with_multiple_same_awid This covergroup captures the number of outstanding write transactions with same AWID values which is in progress, if master is programmed with multiple same ids. For Example : If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], then the master will have three different ids AWID1, AWID2 and AWID3.This covergroup will cross all the 3 ids with svt_axi_port_configuration :: num_outstanding_xact. If number of outstanding transactions are 50 with AWID1,then bins write_same_awid_1, write_outstanding_xacts_with_same_awid_1 to write_outstanding_xacts_with_same_awid_50 will get hit. It is constructed and sampled when trans_axi_num_outstanding_xacts_with_multiple_same_awid_enable set to 1 & num_outstanding_xacts is not -1. Coverpoints: write_outstanding_same_id: Captures the same id values programmed in svt_axi_port_configuration :: cov_multi_same_ids num_outstanding_write : Captures number of outstanding write transactions with a matching AWID values to the one programmed in svt_axi_port_configuration :: cov_multi_same_ids. The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support. Example: If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], cov_multi_same_ids[0] = AWID1, cov_multi_same_ids[1] = AWID2, cov_multi_same_ids[1] = AWID3 and outstanding transactions have the following IDs: AWID1 AWID2 AWID1 AWID4 AWID3 AWID1 AWID3 AWID5 AWID2. The bins of write_outstanding_same_id hit will be write_same_awid_1,write_same_awid_2 and write_same_awid_3, bins of cross_same_id_with_num_outstanding_xacts hit will be write_same_awid_1 with write_outstanding_xacts_3,write_same_awid_2 with write_outstanding_xacts_2, write_same_awid_3 with write_outstanding_xacts_1 as there are 3 outstanding transactions matching with AWID1, 2 outstanding transactions with AWID2 and 1 outstanding transaction with AWID3. Cross Coverpoints : cross_same_id_with_num_outstanding_xacts: Crosses Coverpoints write_outstanding_same_id, num_outstanding_write . Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_same_arid	read_outstanding_xacts_with_same_arid	read_outstanding_xacts_with_same_arid:read_outstanding_xacts_with_same_arid	--	Covergroup: trans_axi_num_outstanding_xacts_with_same_arid It is constructed and sampled when interface_ category is not AXI_WRITE_ONLY and trans_axi_num_outstanding_xacts_with_same_arid_enable set to 1 & num_outstanding_xact is not -1. Coverpoints: read_outstanding_xacts_with_same_arid: Captures the number of outstanding read transactions with a matching ARID value to the one programmed in svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts. The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support. Example: If outstanding transactions have the following IDs: ARID1 ARID1 ARID3 ARID1 ARID3 ARID2 and svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts is programmed to ARID1. The bins hit will be 1,2 and 3 as there are 3 outstanding transactions matching with ARID1. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_axi_num_outstanding_xacts_with_same_awid	write_outstanding_xacts_with_same_awid	write_outstanding_xacts_with_same_awid:write_outstanding_xacts_with_same_awid	--	Covergroup: trans_axi_num_outstanding_xacts_with_same_awid It is constructed and sampled when interface_category is not AXI_READ_ONLY and trans_axi_num_outstanding_xacts_with_same_awid_enable set to 1 & num_outstanding_xacts is not -1. Coverpoints: write_outstanding_xacts_with_same_awid: Captures the number of outstanding write transactions with a matching AWID value to the one programmed in svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts. The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support. Example: If outstanding transactions have the following IDs: AWID1 AWID1 AWID3 AWID1 AWID3 AWID2 and svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts is programmed to AWID1. The bins hit will be 1, 2 and 3 as there are 3 outstanding transactions matching with AWID1. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_cross_axi_outstanding_xact	total_outstanding_xact outstanding_write_xact outstanding_read_xact	total_outstanding_xact:total_outstanding_xact outstanding_write_xact:write_outstanding_xact outstanding_read_xact:read_outstanding_xact	--	This covergroup captures attributes for total outstanding xact , outstanding write xact and outstanding read xact. It is constructed when trans_cross_axi_outstanding_xact_enable is set to 1. Covergroup: trans_cross_axi_outstanding_xact Coverpoints: total_outstanding_xact : Captures total number of outstanding(read/write) transactions outstanding_write_xact : Captures number of outstanding write transactions outstanding_read_xact : Captures number of outstanding read transactions
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_master_ace_barrier_response_with_outstanding_xacts	ace_completed_barrier_type	ace_completed_barrier_type:outstanding_xacts_during_memory_barrier, outstanding_xacts_during_sync_barrier	--	Covergroup: trans_master_ace_barrier_response_with_outstanding_xacts It is constructed and sampled when system_ace_barrier_response_with_outstanding_xacts_enable ,barrier_enable and system_monitor_enable set to 1. system_ace_barrier_response_with_outstanding_xacts_enable Coverpoints: ace_completed_barrier_type: This is covered when there are outstanding transactions in the queue of a master when the response to a barrier is received. There are multiple ways in which an interconnect can handle barriers. Some interconnects may send response to a barrier only after all outstanding transactions are complete. Others may forward the barrier downstream and wait for the response of the downstream barrier before responding to the original barrier. In such a case there could be outstanding transactions in the queue of the master when a barrier response is received. This coverpoint covers the latter behaviour. One or more ACE/ACE_LITE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.3
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_master_num_outstanding_dvm_syncs	num_outstanding_dvm_sync_xacts	num_outstanding_dvm_sync_xacts:outstanding_dvm_syncs_less_than_256, outstanding_dvm_syncs_equals_256	--	Covergroup: trans_master_num_outstanding_dvm_syncs This covergroup captures outstanding dvm based snoop transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1. Coverpoints: num_outstanding_dvm_sync_xacts: Captures number of outstanding dvm sync snoop transactions. Note that a master is allowed to send only one outstanding DVM sync transaction (ie, a DVM sync transaction to which a DVM complete is not yet received). Therefore a maximum of 256 outstanding DVM sync snoop transactions is possible only in a system with atleast 257 masters capable of sending DVM transactions. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C12.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_non_barrier_xact_after_256_outstanding_barrier_xact	non_barrier_after_256_outstanding_barrier_xact	non_barrier_after_256_outstanding_barrier_xact:write_xact_after_256_outstanding_barrier_xact	--	Covergroup: trans_non_barrier_xact_after_256_outstanding_barrier_xact This Covergroup captures barrier outstanding transaction. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_non_barrier_xact_after_256_outstanding_barrier_xact_enable & barrier enable set to 1. Coverpoints: non_barrier_after_256_outstanding_barrier_xact: Captures if active transactions on write channel occur after 256 barrier outstanding transactions are accepted by slave component Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_outstanding_read_with_same_id_to_different_slaves	axi_outstanding_read_with_same_id_to_different_slaves	axi_outstanding_read_with_same_id_to_different_slaves:outstanding_with_same_id_to_different_slaves	--	Covergroup: trans_outstanding_read_with_same_id_to_different_slaves This Covergroup captures outstanding read request having same id for different slaves. This covergroup is constructed for all master interface types except AXI4_STREAM and only if the number of slaves in the system (svt_axi_system_configuration :: num_slaves) is greater than 1 and trans_outstanding_read_with_same_id_to_different_slaves_enable set to 1. Coverpoints: axi_outstanding_read_with_same_id_to_different_slaves: This is covered when: A master issues two outstanding read transactions with the same ID These read transactions are targeted to two different slaves Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_OUTSTANDING_XACT_FLOW	trans_outstanding_write_with_same_id_to_different_slaves	axi_outstanding_write_with_same_id_to_different_slaves	axi_outstanding_write_with_same_id_to_different_slaves:outstanding_with_same_id_to_different_slaves	--	Covergroup: trans_outstanding_write_with_same_id_to_different_slaves This Covergroup captures outstanding write request having same id for different slaves. This covergroup is constructed for all master interface types and only if the number of slaves in the system (svt_axi_system_configuration :: num_slaves) is greater than 1 and trans_outstanding_read_with_same_id_to_different_slaves_enable set to 1. Coverpoints: axi_outstanding_read_with_same_id_to_different_slaves: This is covered when: A master issues two outstanding write transactions with the same ID These write transactions are targeted to two different slaves Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_INTERLEAVING_DEPTH	trans_cross_axi_write_interleaving_depth	write_data_interleave	write_data_interleave:write_data_interleave_depth	--	This covergroup captures attributes for write data interleave depth. It is constructed when interface type is set to AXI3 . Covergroup: trans_cross_axi_write_interleaving_depth Coverpoints: write_data_interleave : Captures write data interleave depth
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITERESP_XACT_FLOW	trans_cross_ace_awsnoop_bresp	coherent_write_xact_type bresp slave_port_id	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp slave_port_id:slave_id	awsnoop_bresp	Covergroup: trans_cross_ace_awsnoop_bresp This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction bresp : Captures write response Cross coverpoints: awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITERESP_XACT_FLOW	trans_cross_exclusive_writenosnoop_domain_type	coherent_write_xact_type bresp domain_type	coherent_write_xact_type:coherent_writenosnoop_xact bresp:exokay_resp domain_type:domain_non_shareable, domain_system_shareable	awsnoop_awdomain_bresp	Covergroup : trans_cross_exclusive_writenosnoop_domain_type This Covergroup captures coherant writenosnoop_xact_type,write_resp and domain_type for write transaction. It is constructed and sampled when trans_cross_exclusive_writenosnoop_domain_type_enable and exclusive_access_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent writenosnoop transaction bresp : Captures exokay write response domain_type : Captures NONSHAREABLE & SYSTEMSHAREABLE domain types Cross coverpoints: awsnoop_awdomain_bresp : Crosses cover points coherent_write_xact_type, domain_type and bresp The EXOKAY response is permitted for WriteNoSnoop with domain innershareable & outershareable. Rest all other bins are ignored.
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITECACHE_XACT_FLOW	trans_cross_ace_awsnoop_awcache	coherent_write_xact_type cache_type slave_port_id	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable, write_through_no_allocate, write_through_read_allocate, write_through_write_allocate, write_through_read_and_write_allocate, write_back_no_allocate, write_back_read_allocate, write_back_write_allocate, write_back_read_and_write_allocate slave_port_id:slave_id	awsnoop_awcache	Covergroup: trans_cross_ace_awsnoop_awcache This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction cache_type : Captures cache type Cross coverpoints: awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITECACHE_XACT_FLOW	trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate	coherent_write_xact_type initial_cache_line_state final_cache_line_state	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_sharedclean	awsnoop_cacheinitialstate_cachefinalstate	Covergroup: trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate This Covergroup captures coherant read xact_type ,initial and final cacheline state for write transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_READ_ONLY & trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate_enable set to 1 & update_cache_for_non_coherent_xacts set to 0. Coverpoints: coherent_write_xact_type : Captures coherent Write transaction initial_cache_line_state : Captures initial cache line state final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states Cross coverpoints: awsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITECACHE_XACT_FLOW	trans_cross_ace_awsnoop_update_cache_cacheinitialstate_cachefinalstate	coherent_write_xact_type initial_cache_line_state final_cache_line_state	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_sharedclean	awsnoop_update_cache_cacheinitialstate_cachefinalstate	Covergroup: trans_cross_ace_awsnoop_update_cache_cacheinitialstate_cachefinalstate This Covergroup captures coherant read xact_type ,initial and final cacheline state for write transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_READ_ONLY & trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate_enable & update_cache_for_non_coherent_xacts set to 1. Coverpoints: coherent_write_xact_type : Captures coherent Write transaction initial_cache_line_state : Captures initial cache line state final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states Cross coverpoints: awsnoop_update_cache_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITEDOMAIN_XACT_FLOW	trans_cross_ace_awsnoop_awdomain	coherent_write_xact_type domain_type slave_port_id	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable slave_port_id:slave_id	awsnoop_awdomain	Covergroup : trans_cross_ace_awsnoop_awdomain This Covergroup captures coherant write xact_type,domain and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction domain_type : Captures domain type Cross coverpoints: awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_ace_concurrent_overlapping_arsnoop_acsnoop	coherent_read_xact_type snoop_xact_type	coherent_read_xact_type:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_overlapping_arsnoop_acsnoop This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_read_xact_type:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on read channel of master . This excludes READNOSNOOP,DVMMESSAGE,DVMCOMPLETE,READBARRIER transactions The bins in this covergroup will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address Two ACE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_ace_concurrent_overlapping_arsnoop_acsnoop_one_ace_acelite	coherent_read_xact_type snoop_xact_type	coherent_read_xact_type:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_overlapping_arsnoop_acsnoop_one_ace_acelite This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_read_xact_type:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on read channel of master . This excludes READNOSNOOP,DVMMESSAGE,DVMCOMPLETE,READBARRIER transactions The bins in this covergroup will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address Atleast one ACE and one ACE_LITE master needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_axi_snoop	ACVALID_to_ACREADY_Delay ACVALID_to_CRVALID_Delay CRVALID_to_CRREADY_Delay ACVALID_to_prev_ACVALID_Delay ACVALID_before_ACREADY ACREADY_before_ACVALID CRVALID_before_CRREADY CRREADY_before_CRVALID	ACVALID_to_ACREADY_Delay:acvalid_to_acready_delay_min, acvalid_to_acready_delay_mid, acvalid_to_acready_delay_max ACVALID_to_CRVALID_Delay:acvalid_to_crvalid_delay_min, acvalid_to_crvalid_delay_mid, acvalid_to_crvalid_delay_max CRVALID_to_CRREADY_Delay:crvalid_to_crready_delay_min, crvalid_to_crready_delay_mid, crvalid_to_crready_delay_max ACVALID_to_prev_ACVALID_Delay:acvalid_to_prev_acvalid_delay_min, acvalid_to_prev_acvalid_delay_mid, acvalid_to_prev_acvalid_delay_max ACVALID_before_ACREADY:acvalid_before_acready ACREADY_before_ACVALID:acready_before_acvalid CRVALID_before_CRREADY:crvalid_before_crready CRREADY_before_CRVALID:crready_before_crvalid	--	Covergroup: trans_axi_snoop This Covergroup captures delay scenarios between valid and ready signal for snoop address and snoop data. It is constructed when trans_axi_snoop_enable is set to 1 and interface type is AXI_ACE or ACE_LITE. Coverpoints: ACVALID_to_ACREADY_Delay: Captures min, mid and max range of delays between signals acvalid and acready ACVALID_to_CRVALID_Delay: Captures min, mid and max range of delays between signals acvalid and crvalid CRVALID_to_CRREADY_Delay: Captures min, mid and max range of delays between signals crvalid and crready ACVALID_to_prev_ACVALID_Delay: Captures min, mid and max range of delays between current and previous acvalid signals ACVALID_before_ACREADY: Captures if ACVALID signal comes before ACREADY signal ACREADY_before_ACVALID: Captures if ACREADY signal comes before ACVALID signal CRVALID_before_CRREADY: Captures if CRVALID signal comes before CRREADY signal CRREADY_before_CRVALID: Captures if CRREADY signal comes before CRVALID signal
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_axi_snoop_data_phase	CDVALID_to_prev_CDVALID_Delay CDVALID_to_CDREADY_Delay CDVALID_before_CDREADY CDREADY_before_CDVALID	CDVALID_to_prev_CDVALID_Delay:cdvalid_to_prev_cdvalid_delay_min, cdvalid_to_prev_cdvalid_delay_mid, cdvalid_to_prev_cdvalid_delay_max CDVALID_to_CDREADY_Delay:cdvalid_to_cdready_delay_min, cdvalid_to_cdready_delay_mid, cdvalid_to_cdready_delay_max CDVALID_before_CDREADY:cdvalid_before_cdready CDREADY_before_CDVALID:cdready_before_cdvalid	--	Covergroup: trans_axi_snoop_data_phase This Covergroup captures valid to ready delay scenario for snoop channel. It is constructed when trans_axi_snoop_enable is set to 1. Coverpoints: CDVALID_to_prev_CDVALID_Delay CDVALID_to_CDREADY_Delay CDVALID_before_CDREADY: Captures if CDVALID signal comes before CDREADY signal CDREADY_before_CDVALID: Captures if CDREADY signal comes before CDVALID signal
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_cross_ace_acsnoop_acaddr	snoop_xact_type snoop_addr	snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact snoop_addr:addr_range_min, addr_range_mid, addr_range_max	acsnoop_acaddr	Covergroup: trans_cross_ace_acsnoop_acaddr This Covergroup captures snoop xact type and address. It is constructed when trans_cross_ace_acsnoop_acaddr_enable is asserted. Coverpoints: snoop_xact_type: Captures Snoop transaction snoop_addr: Captures Snoop address Cross coverpoints: acsnoop_acaddr : Crosses cover points snoop_xact_type and snoop_addr
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_cross_ace_acsnoop_acaddr_one_ace_acelite	snoop_xact_type snoop_addr	snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact snoop_addr:addr_range_min, addr_range_mid, addr_range_max	acsnoop_acaddr	Covergroup: trans_cross_ace_acsnoop_acaddr_one_ace_acelite This Covergroup captures snoop xact type and address. It is constructed when trans_cross_ace_acsnoop_acaddr_enable is asserted. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. Coverpoints: snoop_xact_type: Captures Snoop transaction snoop_addr: Captures Snoop address Cross coverpoints: acsnoop_acaddr : Crosses cover points snoop_xact_type and snoop_addr
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_cross_ace_acsnoop_acprot	snoop_xact_type snoop_prot	snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact snoop_prot:data_secure_normal, data_non_secure_normal	acsnoop_acprot	Covergroup: trans_cross_ace_acsnoop_acprot This Covergroup captures snoop xact type and protection signal It is constructed when trans_cross_ace_acsnoop_acprot_enable is asserted. Coverpoints: snoop_xact_type: Captures Snoop transaction snoop_prot: Captures Snoop protection type Cross coverpoints: acsnoop_acprot : Crosses cover points snoop_xact_type and snoop_prot
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_cross_ace_acsnoop_acprot_one_ace_acelite	snoop_xact_type snoop_prot	snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact snoop_prot:data_secure_normal, data_non_secure_normal	acsnoop_acprot	Covergroup: trans_cross_ace_acsnoop_acprot_one_ace_lite This Covergroup captures snoop xact type and protection signal. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when trans_cross_ace_acsnoop_acprot_enable is asserted. Coverpoints: snoop_xact_type: Captures Snoop transaction snoop_prot: Captures Snoop protection type Cross coverpoints: acsnoop_acprot : Crosses cover points snoop_xact_type and snoop_prot
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_cross_ace_awsnoop_awbar	coherent_write_xact_type barrier_type	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization	awsnoop_awbar	Covergroup: trans_cross_ace_awsnoop_awbar This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awbar_enable and barrier_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction barrier_type : Captures write barrier Cross coverpoints: awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_readunique_snoop_resp_datatransfer_with_clean_cacheline	snoop_resp_datatransfer_with_clean_cacheline	snoop_resp_datatransfer_with_clean_cacheline:snoop_no_datatransfer, snoop_with_datatransfer	--	Covergroup: trans_master_readunique_snoop_resp_datatransfer_with_clean_cacheline This Covergroup captures snoop rersponse for readunique data transfer. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE . Coverpoints: snoop_resp_datatransfer_with_clean_cacheline: Captures whether data was transferred for READUNIQUE snoop when the cache was in a clean state. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.3.3
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr	snoop_xact_type	snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact	--	Covergroup: trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr This Covergroup captures snoop responses with data transfer when a WRITEUNIQUE or WRITELINEUNIQUE to the same address is in progress. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE . Coverpoints: snoop_xact_type: Captures snoop transactions other than DVM transactions and MAKEINVALID. MAKEINVALID transactions are not captured because it is recommended that MAKEINVALID does not transfer data. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr_one_ace_acelite	snoop_xact_type	snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact	--	Covergroup: trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr_one_ace_acelite This Covergroup captures snoop responses with data transfer when a WRITEUNIQUE or WRITELINEUNIQUE to the same address is in progress, when only one ACE master and one or more ACE_LITE masters present in the system. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE . Coverpoints: snoop_xact_type: Captures snoop transactions READONCE,CLEANSHARED,CLEANINVALID. Other transactions are not captured because ACE_LITE master cant fire READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict	memory_update_excluding_writeevict snoop_xact_type	memory_update_excluding_writeevict:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeback_xact, coherent_writeclean_xact, coherent_evict_xact snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	trans_cross_memory_update_snoop_xact_to_same_address	Covergroup: trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict This Covergroup captures read transaction for for same address snooped to master. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_READ_ONLY. Coverpoints: memory_update_excluding_writeevict: Captures WRITEBACK,WRITECLEAN,EVICT,WRITEUNIQUE and WRITELINEUNIQUE transactions to the same address as a snoop. WRITENOSNOOP transactions to non overlapping addresses are captured because WRITENOSNOOP is issued to non-shareable region and another master may not access the same address as that of a WRITENOSNOOP through a snoop. snoop_xact_type: Captures snoop transactions other than DVM transactions Cross Coverpoints : trans_cross_memory_update_snoop_xact_to_same_address: Crosses memory_update_excluding_writeevict and snoop_xact_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict_one_ace_acelite	memory_update_excluding_writeevict snoop_xact_type	memory_update_excluding_writeevict:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeback_xact, coherent_writeclean_xact, coherent_evict_xact snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	trans_cross_memory_update_snoop_xact_to_same_address	Covergroup: trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict_one_ace_acelite This Covergroup captures write transaction for memory update and snoop based dvm unset type. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_READ_ONLY. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. Coverpoints: memory_update_excluding_writeevict: Captures WRITEBACK,WRITECLEAN,EVICT,WRITEUNIQUE and WRITELINEUNIQUE transactions to the same address as a snoop. WRITENOSNOOP transactions to non overlapping addresses are captured because WRITENOSNOOP is issued to non-shareable region and another master may not access the same address as that of a WRITENOSNOOP through a snoop. snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions Cross Coverpoints : trans_cross_memory_update_snoop_xact_to_same_address: Crosses memory_update_excluding_writeevict and snoop_xact_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_snoop_to_same_addr_as_writeevict	write_evict_xact snoop_xact_type	write_evict_xact:coherent_writeevict_xact snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	trans_cross_writeevict_snoop_xact_to_same_address	Covergroup: trans_master_snoop_to_same_addr_as_writeevict This Covergroup captures write transaction for same address as snoop and snoop transaction except dvm based. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE writeevict_enable set to 1. Coverpoints: write_evict_xact: Captures WRITEEVICT transactions to the same address as a snoop. snoop_xact_type: Captures snoop transactions other than DVM transactions Cross Coverpoints : trans_cross_writeevict_snoop_xact_to_same_address: Crosses write_evict_xact and snoop_xact_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_snoop_to_same_addr_as_writeevict_one_ace_acelite	write_evict_xact snoop_xact_type	write_evict_xact:coherent_writeevict_xact snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	trans_cross_writeevict_snoop_xact_to_same_address	Covergroup: trans_master_snoop_to_same_addr_as_writeevict_one_ace_acelite This Covergroup captures write evict and snoop xact transaction. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE writeevict_enable set to 1. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. Coverpoints: write_evict_xact: Captures WRITEEVICT transactions to the same address as a snoop. snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions Cross Coverpoints : trans_cross_writeevict_snoop_xact_to_same_address: Crosses write_evict_xact and snoop_xact_type Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOP_XACT_FLOW	trans_master_snoop_to_same_address_as_read_xact	read_xact_to_same_address_as_snoop	read_xact_to_same_address_as_snoop:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact	--	Covergroup: trans_master_snoop_to_same_address_as_read_xact This Covergroup captures read transaction for for same address snooped to master. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_WRITE_ONLY. Coverpoints: read_xact_to_same_address_as_snoop: Captures read transactions to the same address as a snoop to the master. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp	coherent_write_xact_type_gen_snoop snoop_xact_type snoop_crresp_on_ace_port snoop_crresp_wu	coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp The bins in covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp is applicable only for ACE Masters .The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that * generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port :Coverpoint of cresp. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite	coherent_write_xact_type_gen_snoop snoop_xact_type snoop_crresp_on_ace_port snoop_crresp_wu	coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with non overlapping address The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite is applicable only for ACE Masters .The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite needs at least one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Coverpoint of cresp. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled	coherent_write_xact_type_gen_snoop snoop_xact_type snoop_crresp_on_ace_port snoop_crresp_wu	coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled is applicable only for ACE Masters.The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled needs at least one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : coverpoint of cresp. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled	coherent_write_xact_type_gen_snoop snoop_xact_type snoop_crresp_on_ace_port snoop_crresp_wu	coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writeevict_xact snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled is applicable only for ACE Masters. The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled needs atleast one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master. This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Coverpoint of cresp. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled	coherent_write_xact_type_gen_snoop snoop_xact_type snoop_crresp_on_ace_port snoop_crresp_wu	coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enable The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled is applicable only for ACE Masters .The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that * generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled	coherent_write_xact_type_gen_snoop snoop_xact_type snoop_crresp_on_ace_port snoop_crresp_wu	coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writeevict_xact snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	ace_concurrent_overlap_snoop_xact	Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled is applicable only for ACE Masters .The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER. Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that * generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_cross_ace_acsnoop_crresp	snoop_xact_type snoop_crresp snoop_crresp_wu	snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact snoop_crresp:cresp_x0000, cresp_x1000, cresp_x0001, cresp_x1001, cresp_x0101, cresp_x1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	acsnoop_crresp acsnoop_crresp_wasunique	Covergroup: trans_cross_ace_acsnoop_crresp This Covergroup captures snoop xact_type, rresp_type(unique and notunique) . It is constructed when trans_cross_ace_acsnoop_crresp_enable is set to 1. Coverpoints: snoop_xact_type: Captures Snoop transaction snoop_crresp: Captures Snoop response type Cross coverpoints: acsnoop_crresp : Crosses cover points snoop_xact_type and snoop_crresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_cross_ace_acsnoop_crresp_one_ace_acelite	snoop_xact_type snoop_crresp snoop_crresp_wu	snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact snoop_crresp:cresp_x0000, cresp_x1000, cresp_x0001, cresp_x1001, cresp_x0101, cresp_x1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique	acsnoop_crresp acsnoop_crresp_wasunique	Covergroup: trans_cross_ace_acsnoop_crresp_one_ace_acelite This Covergroup captures snoop xact_type, rresp_type(unique and notunique) . This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when trans_cross_ace_acsnoop_crresp_enable is set to 1. Coverpoints: snoop_xact_type: Captures Snoop transaction snoop_crresp: Captures Snoop response type Cross coverpoints: acsnoop_crresp : Crosses cover points snoop_xact_type and snoop_crresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_master_ace_coherent_and_ace_snoop_response_association	coh_xact_from_ace snoop_crresp_from_ace snoop_crresp_wu ace_init_cache_state ace_final_cache_state snoop_xact_on_ace_master	coh_xact_from_ace:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, writeunique_coherent, writelineunique_coherent snoop_crresp_from_ace:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique ace_init_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state ace_final_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state snoop_xact_on_ace_master:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	coh_xact_ace_snp_resp_ace_init_final_cache_state	Covergroup: trans_master_ace_coherent_and_ace_snoop_response_association Covergroup for all coherent transactions generated from ACE master and the correponding Snoop transactions on ACE-Masters and snoop response from ACE-Masters for these snoop transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there are two ACE master s in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_coherent_and_ace_snoop_response_association_enable to 1. Coverpoints: coh_xact_from_ace: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE Master snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE master resulted in this snoop transaction and snoop response and subsequently hit bins of coverpoint cmds_from_ace. System Monitor provides this information to Port Monitor. snoop_xact_on_ace_master: This coverpoint has bins corresponding to each of the valid snoop transaction type on ACE master snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique) ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master. ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master. Cross Coverpoints: coh_xact_ace_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace, snoop_xact_on_ace_master,snp_crresp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace	ace_coh_and_snp_association	ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readonce_coherent_to_readclean_snoop, readonce_coherent_to_readnotshareddirty_snoop, readonce_coherent_to_readshared_snoop, readonce_coherent_to_readunique_snoop, readonce_coherent_to_cleaninvalid_snoop, readonce_coherent_to_cleanshared_snoop, readclean_coherent_to_readclean_snoop, readclean_coherent_to_readnotshareddirty_snoop, readclean_coherent_to_readshared_snoop, readclean_coherent_to_readunique_snoop, readclean_coherent_to_cleaninvalid_snoop, readnotshareddirty_coherent_to_readclean_snoop, readnotshareddirty_coherent_to_readnotshareddirty_snoop, readnotshareddirty_coherent_to_readshared_snoop, readnotshareddirty_coherent_to_readunique_snoop, readnotshareddirty_coherent_to_cleaninvalid_snoop, readshared_coherent_to_readclean_snoop, readshared_coherent_to_readnotshareddirty_snoop, readshared_coherent_to_readshared_snoop, readshared_coherent_to_readunique_snoop, readshared_coherent_to_cleaninvalid_snoop, readunique_coherent_to_readunique_snoop, readunique_coherent_to_cleaninvalid_snoop, cleanunique_coherent_to_readunique_snoop, cleanunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_readunique_snoop, makeunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_makeinvalid_snoop, cleanshared_coherent_to_readunique_snoop, cleanshared_coherent_to_cleaninvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_readunique_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_readunique_snoop, makeinvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_readunique_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_readunique_snoop, writelineunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop	--	Covergroup: system_ace_coherent_and_snoop_association_recommended_and_optional_ace This Covergroup captures optional snoop transactions to snooped masters when coherant transaction is received from initiating master. It is constructed when interface_type is AXI_ACE and system_ace_coherent_and_snoop_association_enable set to 1. Coverpoints: ace_coh_and_snp_association: This is covered when the interconnect issues recommended and optional snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace_lite	ace_coh_and_snp_association	ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readonce_coherent_to_readclean_snoop, readonce_coherent_to_readnotshareddirty_snoop, readonce_coherent_to_readshared_snoop, readonce_coherent_to_readunique_snoop, readonce_coherent_to_cleaninvalid_snoop, readonce_coherent_to_cleanshared_snoop, cleanshared_coherent_to_readunique_snoop, cleanshared_coherent_to_cleaninvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_readunique_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_readunique_snoop, makeinvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_readunique_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_readunique_snoop, writelineunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop	--	Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace_lite Coverpoints: ace_coh_and_snp_association: This is covered when the interconnect issues recommended and optional snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id	coh_xact_t1_ace_lite coh_xact_t2_ace_lite snoop_crresp_0_t1 snoop_crresp_0_t2 coh_xact_id	coh_xact_t1_ace_lite:writeunique_coherent, writelineunique_coherent coh_xact_t2_ace_lite:writeunique_coherent, writelineunique_coherent snoop_crresp_0_t1:cresp_0, cresp_1 snoop_crresp_0_t2:cresp_0, cresp_1 coh_xact_id:ace_lite_xact_id	coh_xact_ace_lite_xacts_ace_snp_resp_specific_id	Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id Covergroup for back to back combination of CLEANINVALID and MAKEINVALID coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id_enable to 1. Coverpoints: coh_xact_t1_ace_lite: This coverpoint has bins corresponding to first transaction of a back to back transactions from an ACE-Lite Master coh_xact_t2_ace_lite: This coverpoint has bins corresponding to second transaction of a back to back transactions from an ACE-Lite Master snoop_crresp_0_t1 & snoop_crresp_0_t2: This coverpoint has bins for all possible values of CRRESP[0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master. Cross Coverpoints: coh_xact_ace_lite_xacts_ace_snp_resp_specific_id: This is the cross-coverage between coh_xact_t1_ace_lite, snoop_crresp_0_t1, coh_xact_t2_ace_lite, snoop_crresp_0_t2, coh_xact_id. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id	coh_xact_from_ace_lite snoop_crresp_from_ace snoop_crresp_wu ace_init_cache_state ace_final_cache_state	coh_xact_from_ace_lite:readonce_coherent, cleanshared_coherent, cleaninvalid_coherent, makeinvalid_coherent, writeunique_coherent, writelineunique_coherent snoop_crresp_from_ace:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique ace_init_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state ace_final_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state	coh_xact_ace_lite_snp_resp_ace_init_final_cache_state	Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id Covergroup for all coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be sampled only when transaction is having configured specific id. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id_enable set to 1. Coverpoints: coh_xact_from_ace_lite: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE-Lite Master snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE-Lite master resulted in this snoop response and subsequently hit bins of coverpoint cmds_from_ace_lite. System Monitor provides this information to Port Monitor. snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique) ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master. ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master. Cross Coverpoints: coh_xact_ace_lite_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace_lite, snp_resp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_SNOOPRESP_XACT_FLOW	trans_master_snoop_resp_during_wu_wlu_to_same_addr	snoop_crresp snoop_crresp_wu awunique_val	snoop_crresp:cresp_x0000, cresp_x1000, cresp_x0001, cresp_x1001 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique awunique_val:is_not_unique, is_unique	snoop_resp_awunique	Covergroup: trans_master_snoop_resp_during_wu_wlu_to_same_addr This Covergroup captures snoop response type,WasUnique bit ,awunique value and snoop response with awunique value. It is constructed and sampled when interface_type is AXI_ACE and interface_category is not AXI_READ_ONLY. Coverpoints: snoop_crresp: Captures snoop response values snoop_crresp_wu: Captures value of WasUnique bit in snoop response awunique_val: Captures the value of signal AWUNIQUE for WRITEUNIQUE and WRITELINEUNIQUE transactions Cross Coverpoints: snoop_resp_awunique: Cross of snoop_crresp, snoop_crresp_wu and awunique_val Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITEDOMAINBARRIER_XACT_FLOW	trans_cross_ace_awdomain_awbarrier_memory_sync	coherent_write_xact_type barrier_type domain_type	coherent_write_xact_type:coherent_writebarrier_xact barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable	awdomain_awbarrier_memory_sync	Covergroup: trans_cross_ace_awdomain_awbarrier_memory_sync This Covergroup captures barrier_type and domain_type for write transaction. It is constructed and sampled when trans_cross_ace_awdomain_awbarrier_memory_sync_enable Coverpoints: coherent_write_xact_type: Captures coherent write transaction barrier_type : Captures write barrier domain_type : Captures domain type Cross coverpoints: awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type MEMORY_BARRIER & SYNC_BARRIER with awdomain As barrier types are memory & sync therefore, ignoring bins intersect with NORMAL_ACCESS_RESPECT_BARRIER & NORMAL_ACCESS_IGNORE_BARRIER and ignoring all other non-writebarrier bins.
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITEDOMAINBARRIER_XACT_FLOW	trans_cross_ace_awdomain_awbarrier_respect_ignore	coherent_write_xact_type barrier_type domain_type	coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable	awdomain_awbarrier_respect_ignore	Covergroup : trans_cross_ace_awdomain_awbarrier_respect_ignore This Covergroup captures coherant write xact_type and barrier_type for write transaction. It is constructed and sampled when trans_cross_ace_awdomain_awbarrier_respect_ignore_enable is set to 1. Coverpoints: coherent_write_xact_type: Captures coherent write transaction barrier_type : Captures non write barrier (all other coherent transactions) as its normal access with respect or ignore barrier domain_type : Captures domain type Cross coverpoints: awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with awdomain As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are WRITEBARRIER with Memory & Sync
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READCACHE_XACT_FLOW	trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate	coherent_read_xact_type initial_cache_line_state final_cache_line_state	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_uniquedirty, final_state_sharedclean, final_state_shareddirty	arsnoop_cacheinitialstate_cachefinalstate	Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate This Covergroup captures coherant read xact_type ,initial and final cacheline state for read transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_WRITE_ONLY & trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_enable is set 1. Coverpoints: coherent_read_xact_type : Captures coherent read transaction initial_cache_line_state : Captures initial cache line state final_cache_line_state : Capture final cache line state Cross coverpoints: arsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_read_xact_type initial_cache_line_state and final_cache_line_state
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READCACHE_XACT_FLOW	trans_cross_ace_arsnoop_update_cache_cacheinitialstate_cachefinalstate	coherent_read_xact_type initial_cache_line_state final_cache_line_state	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_uniquedirty, final_state_sharedclean, final_state_shareddirty	arsnoop_update_cache_cacheinitialstate_cachefinalstate	Covergroup: trans_cross_ace_arsnoop_update_cache_cacheinitialstate_cachefinalstate This Covergroup captures coherant read xact_type ,initial and final cacheline state for read transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_WRITE_ONLY & trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_enable & update_cache_for_non_coherent_xacts is set 1. Coverpoints: coherent_read_xact_type : Captures coherent read transaction initial_cache_line_state : Captures initial cache line state final_cache_line_state : Capture final cache line state Cross coverpoints: arsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_read_xact_type initial_cache_line_state and final_cache_line_state
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READRESP_XACT_FLOW	trans_cross_ace_ardvmmessage_ardvmresp	ardvm_message_type ardvm_resp	ardvm_message_type:message_tlb_invalidate, message_branch_predictor_invalidate, message_physical_instruction_cache_invalidate, message_virtual_instruction_cache_invalidate, message_synchronization, message_hint ardvm_resp:message_accept, message_reject	ardvmmessage_ardvmresp	Covergroup: trans_cross_ace_ardvmmessage_ardvmresp This Covergroup captures coherant read xact_type and response type for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_ardvmmessage_ardvmresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 Coverpoints: ardvm_message_type : Captures DVM message on araddr[14:12] ardvm_resp : Capture DVM response on rresp [4:0], accept = 4'b0000 and reject = 4'b0010 Cross coverpoints: ardvmmessage_ardvmresp : Crosses coverpoints ardvm_message_type and ardvm_resp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READRESP_XACT_FLOW	trans_cross_ace_arsnoop_coh_rresp	coherent_read_xact_type coh_rresp slave_port_id	coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact coh_rresp:coherent_rresp_shared_clean, coherent_rresp_shared_dirty, coherent_rresp_unique_clean, coherent_rresp_unique_dirty slave_port_id:slave_id	arsnoop_coh_rresp	Covergroup: trans_cross_ace_arsnoop_coh_rresp This Covergroup captures coherant read xact_type,response type and slave_port_id for read transaction. It is constructed and sampled when interface type is not ACE_LITE and AXI_WRITE_ONLY. and trans_cross_ace_arsnoop_coh_rresp_enable set to 1. Coverpoints: coherent_read_xact_type: Captures coherent read transaction coh_rresp : Captures read coherent response Cross coverpoints: arsnoop_coh_rresp : Crosses cover points coherent_read_xact_type and coh_rresp
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_ORDERING_XACT_FLOW	trans_master_back_to_back_write_ordering	xact_back_to_back_write_ordering	xact_back_to_back_write_ordering:back_to_back_write_with_same_id	--	Covergroup: trans_master_back_to_back_write_ordering This Covergroup captures back to back write transactions for same id. It is constructed when port_kind is AXI_MASTER and interface_type is not AXI4_STREAM & interface_category is not AXI_READ_ONLY. Coverpoints: xact_back_to_back_write_ordering: Captures if back-to-back write transactions with the same id is observed Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_ORDERING_XACT_FLOW	trans_master_write_after_read_ordering	xact_write_after_read_ordering	xact_write_after_read_ordering:write_after_read_with_write_completing_first, write_after_read_with_read_completing_first	--	Covergroup: trans_master_write_after_read_ordering This Covergroup captures write transaction after read happens. It is constructed when port_kind is AXI_MASTER and interface_type is not AXI4_STREAM & interface_category is AXI_READ_WRITE. Coverpoints: xact_write_after_read_ordering: Captures the order of completion of a write transaction issued after a read Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_ORDERING_XACT_FLOW	trans_xact_ordering_after_barrier	axi_xact_ordering_after_barrier	axi_xact_ordering_after_barrier:read_xact_overtake_barrier_response, read_xact_fallbehind_barrier_response, write_xact_overtake_barrier_response, write_xact_fallbehind_barrier_response	--	Covergroup: trans_xact_ordering_after_barrier This Covergroup captures read & write transaction ordering for barrier response scenarios. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_ordering_after_barrier_enable & barrier enable set to 1. Coverpoints: axi_xact_ordering_after_barrier: This is covered when a master issues transactions between issuing a barrier transaction on the address channel and receiving the read and write barrier responses. Such transactions have no ordering guarantee with respect to the barrier. On the address channel, these transactions are permitted to remain after the barrier transaction or they are permitted to overtake the barrier transaction. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_NARROW_TRANSFER	trans_cross_axi_read_narrow_transfer_arlen_araddr	read_xact_type transfer_size addr_offset	read_xact_type:read_xact transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f	axi_read_narrow_transfer_arlen_araddr	Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr This Covergroup captures transfer size and address offset for read narrow transfer. It is constrcuted and sampled when trans_cross_axi_read_narrow_transfer_arlen_araddr_enable is asserted. Coverpoints: read_xact_type: Captures read transaction transfer_size: Captures transaction burst size addr_offset: Captures transaction address offset information Cross coverpoints: axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_NARROW_TRANSFER	trans_cross_axi_write_narrow_transfer_awlen_awaddr	write_xact_type transfer_size addr_offset	write_xact_type:write_xact transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f	axi_write_narrow_transfer_awlen_awaddr	Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer It is constructed and sampled when trans_cross_axi_write_narrow_transfer_awlen_awaddr_enable is asserted. Coverpoints: write_xact_type: Captures write transaction transfer_size: Captures transaction burst size addr_offset: Captures transaction address offset information Cross coverpoints: axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_READ_UNALIGNED_TRANSFER	trans_cross_axi_read_unaligned_transfer	read_xact_type burst_type addr_offset transfer_size	read_xact_type:read_xact burst_type:fixed_burst, incr_burst, wrap_burst addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte	axi_read_unaligned_transfer	Covergroup: trans_cross_axi_read_unaligned_transfer This Covergroup captures burst_type,burst_length, transfer size and address offset for read unaligned transfer. It is constructed and sampled when trans_cross_axi_read_unaligned_transfer_enable. Coverpoints: read_xact_type: Captures read transaction burst_type: Captures transaction burst type addr_offset: Captures transaction address offset information transfer_size: Captures transaction burst size Cross coverpoints: axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_WRITE_UNALIGNED_TRANSFER	trans_cross_axi_write_unaligned_transfer	write_xact_type burst_type addr_offset transfer_size	write_xact_type:write_xact burst_type:fixed_burst, incr_burst, wrap_burst addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte	axi_write_unaligned_transfer	Covergroup: trans_cross_axi_write_unaligned_transfer This Covergrpoup captures following signals for unaligned write transfer. It is constructed and sampled when trans_cross_axi_write_unaligned_transfer_enable is asserted. Coverpoints: write_xact_type: Captures write transaction burst_type: Captures transaction burst type addr_offset: Captures transaction address offset information transfer_size: Captures transaction burst size Cross coverpoints: axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_DIRTYDATA_XACT_FLOW	trans_master_ace_cross_cache_line_dirty_data_write	ace_cross_cache_line_dirty_data_write	ace_cross_cache_line_dirty_data_write:readonce_cross_cache_line_dirty_data_write, writeunique_cross_cache_line_dirty_data_write	--	Covergroup: trans_master_ace_cross_cache_line_dirty_data_write This is a system-level covergroup which works by enabling sys_cfg field system_which captures dirty data for write cache line. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE ,interface_category is AXI_READ_WRITE and system_ace_cross_cache_line_dirty_data_write_enable set to 1. Coverpoints: ace_cross_cache_line_dirty_data_write: This is covered under the following conditions: The interconnect may need to snoop multiple cachelines for a WRITEUNIQUE or READONCE transaction because it spans multiple cache lines Atleast two of these snoop transactions return dirty data The interconnect writes the dirty data of the snoop transactions to slave One or more ACE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_DIRTYDATA_XACT_FLOW	trans_master_ace_dirty_data_write	ace_dirty_data_write	ace_dirty_data_write:readonce_dirty_data_write, readclean_dirty_data_write, readnotshreaddirty_dirty_data_write, cleaninvalid_dirty_data_write, cleanshared_dirty_data_write, cleanunique_dirty_data_write, writeunique_dirty_data_write	--	Covergroup: trans_master_ace_dirty_data_write This is a system-level covergroup which works by enabling sys_cfg field system_ace_dirty_data_write_enable. It is constructed and sampled when interface_type is AXI_ACE,interface_category is AXI_READ_WRITE and system_ace_dirty_data_write_enable set to 1. Coverpoints: master_xact_of_ic_dirty_data_write: This is covered when the interconnect issues a write to the slave because dirty data was returned by one of the snoop responses and that dirty data could not be returned to the master that initiated the original transaction Two or more ACE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_DIRTYDATA_XACT_FLOW	trans_master_ace_dirty_data_write_one_ace_acelite	ace_dirty_data_write	ace_dirty_data_write:readonce_dirty_data_write, cleaninvalid_dirty_data_write, cleanshared_dirty_data_write, writeunique_dirty_data_write	--	Covergroup: trans_master_ace_dirty_data_write_one_ace_acelite This is a system-level covergroup which works by enabling sys_cfg field system_ace_dirty_data_write_enable. It is constructed and sampled when interface_type is ACE_LITE ,interface_category is AXI_READ_WRITE and system_ace_dirty_data_write_enable set to 1. Coverpoints: master_xact_of_ic_dirty_data_write: This is covered when the interconnect issues a write to the slave because dirty data was returned by one of the snoop responses and that dirty data could not be returned to the master that initiated the original transaction One ACE and one or more ACE_LITE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_DIRTYDATA_XACT_FLOW	trans_master_ace_snoop_and_memory_returns_data	ace_snoop_and_memory_data_timing ace_snoop_and_memory_returns_data_xact_type	ace_snoop_and_memory_data_timing:snoop_data_before_memory_data, snoop_data_along_with_memory_data, snoop_data_after_memory_data, snoop_returns_data_and_memory_not_returns_data ace_snoop_and_memory_returns_data_xact_type:readonce_snoop_and_memory_returns_data, readclean_snoop_and_memory_returns_data, readnotshreaddirty_snoop_and_memory_returns_data, readunique_snoop_and_memory_returns_data, readshared_snoop_and_memory_returns_data	snoop_memory_timing_and_xact_cross	Covergroup: trans_master_ace_snoop_and_memory_returns_data It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_snoop_and_memory_returns_data_enable set to 1. Coverpoints: ace_snoop_and_memory_read_timing: This cover point covers possible relative timings of snoop generation by the interconnect with respect to receiving speculative read data by the interconnect and bin snoop_returns_data_and_memory_not_returns_data covers if a transaction is found with snoop data transfer and without associated slave transaction. The various timings covered are: snoop issued before the first read data beat is received through speculative read transaction snoop issued after the last beat of read data is received through speculative read transaction snoop issued while the read data is being received through speculative read transaction ace_snoop_and_memory_returns_data_xact_type: Covers the various coherent transaction types for which speculative read was issued. The transaction types covered are READONCE, READCLEAN READNOSHAREDDIRTY, READUNIQUE and READSHARED transactions At least two ACE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_ace_coherent_and_snoop_association_recommended_ace	ace_coh_and_snp_association	ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readclean_coherent_to_readclean_snoop, readnotshareddirty_coherent_to_readnotshareddirty_snoop, readshared_coherent_to_readshared_snoop, readunique_coherent_to_readunique_snoop, cleanunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_makeinvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop	--	Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_ace This Covergroup captures scenari when master issues coherant transaction , interconnect recommends snooop based transaction to snooped masters. It is constructed and sampled when interface _type is AXI_ACE and system_ace_coherent_and_snoop_association_enable set to 1. Coverpoints: ace_coh_and_snp_association: This is covered when the interconnect issues recommended snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_ace_coherent_and_snoop_association_recommended_ace_lite	ace_coh_and_snp_association	ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop	--	Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_ace_lite This Covergroup captures scenario when master issues coherant transaction , interconnect recommends snooop based transaction to snooped masters. It is constructed and sampled when interface _type is ACE_LITE . Coverpoints: ace_coh_and_snp_association: This is covered when the interconnect issues recommended snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_ace_concurrent_overlapping_coherent_xacts	coherent_xact_on_ace_master_port coherent_xact_on_other_ace_master_port_in_system	coherent_xact_on_ace_master_port:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_writeunique_xact, coherent_writelineunique_xact coherent_xact_on_other_ace_master_port_in_system:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_writeunique_xact, coherent_writelineunique_xact	ace_concurrent_overlapping	Covergroup: trans_master_ace_concurrent_overlapping_coherent_xacts The covergroup trans_master_ace_concurrent_overlapping_coherent_xacts covers coherent transactions initiated from different ACE masters concurrently on the same address. The covergroup needs atlease two ACE masters to be present in the system. It is constructed and sampled when interface_type is AXI_ACE and system_ace_concurrent_overlapping_coherent_xacts_enable set to 1. Coverpoints: coherent_xact_on_ace_master_port: This coverpoint covers svt_axi_transaction :: coherent_xact_type transaction . All coherent transactions capable of generating snoop are bins of this coverpoint . coherent_xact_on_other_ace_master_port_in_system : This coverpoint covers svt_axi_transaction :: coherent_xact_type transactions . All coherent transactions capable of generating snoop are bins of this coverpoint . Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_ace_concurrent_readunique_cleanunique	ace_concurrent_readunique_cleanunique	ace_concurrent_readunique_cleanunique:readunique_readunique, readunique_cleanunique, cleanunique_cleannique	--	Covergroup: trans_master_ace_concurrent_readunique_cleanunique This Covergroup captures scenario for ACE master initiating simultanous ReadUnique or CleanUnique transactions. It is consstructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_concurrent_readunique_cleanunique_enable set to 1. Coverpoints: ace_concurrent_readunique_cleanunique: This is covered when multiple ACE masters concurrently(that are simultaneously active) initiate ReadUnique or CleanUnique transactions. Two or more ACE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_ace_lite_coherent_and_ace_snoop_response_association	coh_xact_from_ace_lite snoop_crresp_from_ace snoop_crresp_wu ace_init_cache_state ace_final_cache_state associate_snoop_xact_for_coh_xact_from_acelite_master	coh_xact_from_ace_lite:readonce_coherent, cleanshared_coherent, cleaninvalid_coherent, makeinvalid_coherent, writeunique_coherent, writelineunique_coherent snoop_crresp_from_ace:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101 snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique ace_init_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state ace_final_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state associate_snoop_xact_for_coh_xact_from_acelite_master:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact	coh_xact_ace_lite_snp_resp_ace_init_final_cache_state	Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association Covergroup for all coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_enable set to 1. Coverpoints: coh_xact_from_ace_lite: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE-Lite Master snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE-Lite master resulted in this snoop response and subsequently hit bins of coverpoint cmds_from_ace_lite. System Monitor provides this information to Port Monitor. associate_snoop_xact_for_coh_xact_from_acelite_master: This coverpoint has bins corresponding to valid snoop transactions issued to ACE master for coherent xacts from ACE-Lite Master snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique) ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master. ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master. Cross Coverpoints: coh_xact_ace_lite_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace_lite,associate_snoop_xact_for_coh_xact_from_acelite_master, snp_resp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_ace_no_cached_copy_overlapping_coherent_xact	ace_no_cached_copy_overlap_coh_xact	ace_no_cached_copy_overlap_coh_xact:overlap_readonce_readonce, overlap_writeunique_writeunique, overlap_writelineunique_writelineunique	--	Covergroup: trans_master_ace_no_cached_copy_overlapping_coherent_xact This Covergroup captures no cached copy for overlapping coherant transaction. It is constructed and sampled when interface_type is AXI_ACE and system_ace_no_cached_copy_overlapping_coherent_xact_enable set to 1. Coverpoints: no_cached_copy_overlap_coh_xact: This coverpoint has following bins overlap_readonce_readonce: This bin gets hit when two or more masters issue readonce coherent transactions to overlapping cacheline simultaneously. overlap_writeunique_writeunique: This bin gets hit when two or more masters issue writeunique coherent transactions to overlapping cacheline simultaneously. overlap_writelineunique_writelineunique: This bin gets hit when two or more masters issue writelineunique coherent transactions to overlapping cacheline simultaneously. Two or more ACE / ACE_LITE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_ace_store_overlapping_coherent_xact	ace_store_overlap_coh_xact	ace_store_overlap_coh_xact:overlap_readunique_readunique, overlap_cleanunique_cleanunique, overlap_makeunique_makeunique	--	Covergroup: trans_master_ace_store_overlapping_coherent_xact This Covergroup captures overlapped coherant transaction for readunique and cleanunique . It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_store_overlapping_coherent_xact_enable set to 1. Coverpoints: store_overlap_coh_xact: This cover point has follwoing bins overlap_readunique_readunique: This bin gets hit when two or more masters issue readunique coherent transactions to overlapping cacheline simultaneously. overlap_cleanunique_cleanunique: This bin gets hit when two or more masters issue cleanunique coherent transactions to overlapping cacheline simultaneously. overlap_makeunique_makeunique: This bin gets hit when two or more masters issue makeunique coherent transactions to overlapping cacheline simultaneously. Two or more ACE masters needed for this covergroup Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C4.10
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_coherent_unmatched_excl_access	unmatched_excl_access	unmatched_excl_access:unmatched_excl_store_access, unmatched_excl_load_access	--	Covergroup: trans_master_coherent_unmatched_excl_access This Covergroup captures coherant transactions for exclusive access. It is constructed when interface_type is AXI_ACE and exclusive_access_enable set to 1. Coverpoints: unmatched_excl_access: Captures exclusive load accesses which did not have a corresponding exclusive store access and exclusive store accesses which did not have a corresponding exclusive load access. The unmatched_excl_load_access is hit when a second exclusive load access to the same ID is received before an exclusive store to that ID. The unmatched_excl_store_access is hit when there is no prior exclusive load to an exclusive store (CLEANUNIQUE) transaction. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C9.6
AXI_PORT_MON_XACT_FLOW	AXI_PORT_MON_COHERANT_XACT_FLOW	trans_master_concurrent_coherent_exclusive_access	num_coherent_exl_access	num_coherent_exl_access:one_thread, more_than_one_thread	--	Covergroup: trans_master_concurrent_coherent_exclusive_access This Covergroup captures coherant transactions for exclusive access. It is constructed when interface_type is AXI_ACE and exclusive_access_enable set to 1. Coverpoints: num_coherent_exl_access: Number of concurrent coherent exclusive accesses on different IDs Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C9.6

Group

Subgroup

Covergroup

Coverpoints

Bins

Cross Coverage

Description

AXI_PORT_MON_ATOMICTYPE_RESP

AXI_PORT_MON_ATOMICTYPE_RRESP

trans_cross_axi_atomictype_rresp

read_xact_type:read_xact
atomic_type:normal, exclusive, locked
rresp:okay_resp, exokay_resp, slverr_resp, decerr_resp

axi_atomictype_rresp

Covergroup: trans_cross_axi_atomictype_rresp

This Covergroup triggers response type for atomic transactions. It is constructed and sampled when trans_cross_axi_atomictype_rresp_enable is asserted. Coverpoints:

read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
rresp: Captures transaction response

Cross coverpoints:

axi_atomictype_rresp: Crosses cover points read_xact_type, atomic_type,rresp. This covergroup is triggered when an exclusive READ transaction with rresp of exokay is observed

AXI_PORT_MON_ATOMICTYPE_RESP

AXI_PORT_MON_ATOMICTYPE_BRESP

trans_cross_axi_atomictype_bresp

write_xact_type:write_xact
atomic_type:normal, exclusive, locked
bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp

axi_atomictype_bresp

Covergroup: trans_cross_axi_atomictype_bresp

This covergroup is triggered when a exclusive Write transaction with bresp of okay/exokay is observed. It is constructed and sampled when interface category type is not AXI_READ_ONLY & trans_cross_axi_atomictype_bresp_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
bresp: Captures transaction response

Cross coverpoints:
axi_atomictype_bresp: Crosses cover points write_xact_type, atomic_type,bresp.

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_FIXED_BURST

trans_cross_axi_fixed_burst_wstrb

burst_type:fixed_burst, incr_burst, wrap_burst
wstrb:wstrb_all_ones_8, wstrb_all_ones_16, wstrb_all_ones_32, wstrb_all_ones_64, wstrb_all_ones_128, wstrb_all_ones_256, wstrb_all_ones_512, wstrb_all_ones_1024, wstrb_all_ones_2048, wstrb_all_ones_4096, wstrb_all_zeroes_8, wstrb_all_zeroes_16, wstrb_all_zeroes_32, wstrb_all_zeroes_64, wstrb_all_zeroes_128, wstrb_all_zeroes_256, wstrb_all_zeroes_512, wstrb_all_zeroes_1024, wstrb_all_zeroes_2048, wstrb_all_zeroes_4096, wstrb_all_one_zero_data_width_16, wstrb_all_zero_one_data_width_16, wstrb_all_one_zero_data_width_32, wstrb_all_zero_one_data_width_32, wstrb_all_one_zero_data_width_64, wstrb_all_zero_one_data_width_64, wstrb_all_one_zero_data_width_128, wstrb_all_zero_one_data_width_128, wstrb_all_one_zero_data_width_256, wstrb_all_zero_one_data_width_256, wstrb_all_one_zero_data_width_512, wstrb_all_zero_one_data_width_512, wstrb_all_one_zero_data_width_1024, wstrb_all_zero_one_data_width_1024, wstrb_all_one_zero_data_width_2048, wstrb_all_zero_one_data_width_2048, wstrb_all_one_zero_data_width_4096, wstrb_all_zero_one_data_width_4096

axi_fixed_burst_wstrb

Covergroup: trans_cross_axi_fixed_burst_wstrb

This cover group crosses AXI Fixed burst type with write strobe It is constructed and sampled when interface type category is not AXI_READ_ONLY and trans_cross_axi_fixed_burst_wstrb_cov_enable is asserted. Covers the cross of fixed burst type, & WSTRB

Coverpoints:

burst_type: Captures transaction burst type
wstrb: Captures write strobe values

Cross coverpoints:

axi_fixed_burst_wstrb : Crosses cover points burst_type,wstrb

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:3.4.1

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_EXCL_NORMAL_SEQUENCE

axi_four_excl_normal_sequence

four_excl_normal_sequence

four_excl_normal_sequence:bin_NR_NR_NR_EX_SEQ, bin_NR_NR_EX_NR_SEQ, bin_NR_NR_EX_EX_SEQ, bin_NR_EX_NR_NR_SEQ, bin_NR_EX_NR_EX_SEQ, bin_NR_EX_EX_NR_SEQ, bin_NR_EX_EX_EX_SEQ, bin_EX_NR_NR_NR_SEQ, bin_EX_NR_NR_EX_SEQ, bin_EX_NR_EX_NR_SEQ, bin_EX_NR_EX_EX_SEQ, bin_EX_EX_NR_NR_SEQ, bin_EX_EX_NR_EX_SEQ, bin_EX_EX_EX_NR_SEQ

Covergroup: axi_four_excl_normal_sequence

This cover group covers specific combinations of exclusive and normal transactions, for a sequence of four transactions. For eg. Excl-Normal-Excl-Normal,Normal-Normal-Excl-Normal etc. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_four_excl_normal_sequence_cov_enable and exclusive_access_enable is asserted.
Following sequences are supported:

NR_NR_NR_EX
NR_NR_EX_NR
NR_NR_EX_EX
NR_EX_NR_NR
NR_EX_NR_EX
NR_EX_EX_NR
NR_EX_EX_EX
EX_NR_NR_NR
EX_NR_NR_EX
EX_NR_EX_NR
EX_NR_EX_EX
EX_EX_NR_NR
EX_EX_NR_EX
EX_EX_EX_NR

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_RD_WR_BURST_SEQUENCE

axi_four_state_rd_wr_burst_sequence

four_state_rd_wr_burst_sequence

four_state_rd_wr_burst_sequence:bin_WR_WR_WR_WR_SEQ, bin_WR_RD_WR_RD_SEQ, bin_RD_WR_RD_WR_SEQ, bin_WR_WR_RD_RD_SEQ, bin_RD_RD_WR_WR_SEQ, bin_RD_RD_RD_RD_SEQ, bin_RD_RD_RD_WR_SEQ, bin_WR_WR_WR_RD_SEQ

Covergroup: axi_four_state_rd_wr_burst_sequence

This cover group covers specific combinations of read and write transactions, for a sequence of four transactions. For eg. Write-Write-Write-Write or Write-Read-Write-Read, etc. This covergroup is hit when address phase completion of four transactions are observed in a specific combination as described above. When address phases of READ and WRITE transactions get completed at same time, it is not deterministic whether it is a read-write or write-read scenario. In such situation, either sequence containing read-write or write-read may get hit. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_four_state_rd_wr_burst_sequence_cov_enable is asserted.
Following sequences are currently supported:

WR_WR_WR_WR
WR_RD_WR_RD
WR_WR_RD_RD
RD_RD_WR_WR
RD_RD_RD_RD
WR_WR_WR_RD
RD_WR_RD_WR
RD_RD_RD_WR

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:3.4.1

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_READ_BURST_SEQUENCE

axi_back_to_back_read_burst_sequence

back_to_back_read_burst_sequence

back_to_back_read_burst_sequence:back_to_back_read_burst_seq

Covergroup: axi_back_to_back_read_burst_sequence

Coverage group for covering Back To Back READ BURST. This covergroup is triggered when address phase of first READ xact has completed and immediately next clock address phase of second READ xact has started. It is constructed when interface type category is not AXI_WRITE_ON;Y andtrans_axi_back_to_back_read_burst_sequence_enable is asserted.

Bins hit for back to back read burst sequence

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_WRITE_BURST_SEQUENCE

axi_back_to_back_write_burst_sequence

back_to_back_write_burst_sequence

back_to_back_write_burst_sequence:back_to_back_write_burst_seq

Covergroup: axi_back_to_back_write_burst_sequence

Coverage group for covering Back To Back WRITE BURST. This covergroup is triggered when address phase of first WRITE xact has completed and immediately next clock address phase of second WRITE xact has started. It is constructed when interface type category is not AXI_READ_ONLY andtrans_axi_back_to_back_write_burst_sequence_enable is asserted.

Bins hit for back to back write burst sequence

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_WRITE_READ_SAMEID_OUT_OF_ORDER

axi_write_read_diff_id_completed_out_of_order

write_completed_out_of_order:write_completed_OOO
read_completed_out_of_order:read_completed_OOO

Covergroup: axi_write_read_diff_id_completed_out_of_order

Coverage group for covering Read/Write Completed out of order with ARID != AWID This Covergroup is triggere for both read and write xact completed out of order. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_write_read_diff_id_completed_out_of_order_enable is asserted.

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_WRITE_READ_DIFFID_OUT_OF_ORDER

axi_write_read_same_id_completed_out_of_order

write_completed_out_of_order_same_id_as_read:write_completed_OOO_same_id_as_read
read_completed_out_of_order_same_id_as_write:read_completed_OOO_same_id_as_write

Covergroup: axi_write_read_same_id_completed_out_of_order

Coverage group for covering Read/Write Completed out of order with ARID==AWID. It is constructed when interface type category is AXI_READ_WRITE and trans_axi_write_read_same_id_completed_out_of_order_enable.

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_OUT_OF_ORDER_READ_RESP

trans_cross_axi_out_of_order_read_resp_count

axi_read_resp_OOO_count

axi_read_resp_OOO_count:read_rsp_ooo_count

Covergroup : trans_cross_axi_out_of_order_read_resp_count

This Covergroup is for covering read_resp out_of_order count. It is constructed when interface type category is not AXI_WRITE_ONLY.

Coverpoint :

axi_read_resp_OOO_count : Captures read_resp out_of_order count

AXI_PORT_MON_SEQUENCE

AXI_PORT_MON_OUT_OF_ORDER_WRITE_RESP

trans_cross_axi_out_of_order_write_resp_count

axi_write_resp_OOO_count

axi_write_resp_OOO_count:write_rsp_ooo_count

Covergroup : trans_cross_axi_out_of_order_write_resp_count

This Covergroup is for covering write_resp out_of_order count. It is constructed when interface type category is not AXI_READ_ONLY

Coverpoint:

axi_write_resp_OOO_count : Captures write_resp out_of_order count

AXI_PORT_MON_UNALIGNED_ADDRESS

AXI_PORT_MON_WSTRB_UNALIGNED_ADDRESS

axi_wstrb_to_signal_unaligned_start_address

wstrb_to_signal_unaligned_start_address

wstrb_to_signal_unaligned_start_address:wstrb_to_signal_unaligned_start_addr

Covergroup: axi_wstrb_to_signal_unaligned_start_address

This cover group covers the scenario in which a master can provide an aligned address to a write transaction, and use the write strobes to indicate unaligned start address. It is constructed when trans_axi_wstrb_to_signal_unaligned_start_address_cov_enable is asserted.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:3.4.3

AXI_PORT_MON_UNALIGNED_ADDRESS

AXI_PORT_MON_ARCACHE_MODIFIABLE_UNALIGNED_TRANSFER_AXI3

trans_cross_axi3_arcache_modifiable_bit_read_unaligned_transfer

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte
cache_type_modifiable_bit:svt_axi_cache_modifiable_only

axi3_arcache_modifiable_bit_read_unaligned_transfer

Covergroup: trans_cross_axi3_arcache_modifiable_bit_read_unaligned_transfer

This cover group crosses bit ARCACHE[1] with unaligned read transfers. It is constructed and sampled when interface type is AXI3 and trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_cov_enable is asserted.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi3_read_arcache_modifiable_bit_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

AXI_PORT_MON_UNALIGNED_ADDRESS

AXI_PORT_MON_ARCACHE_MODIFIABLE_UNALIGNED_TRANSFER_AXI4

trans_cross_axi4_arcache_modifiable_bit_read_unaligned_transfer

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte
cache_type_modifiable_bit:svt_axi_cache_modifiable_only

axi4_arcache_modifiable_bit_read_unaligned_transfer

Covergroup: trans_cross_axi4_arcache_modifiable_bit_read_unaligned_transfer

This cover group crosses bit ARCACHE[1] with unaligned read transfers. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_cov_enable is asserted.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi4_read_arcache_modifiable_bit_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

AXI_PORT_MON_UNALIGNED_ADDRESS

AXI_PORT_MON_AWCACHE_MODIFIABLE_UNALIGNED_TRANSFER

trans_cross_axi3_awcache_modifiable_bit_write_unaligned_transfer

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte
cache_type_modifiable_bit:svt_axi_cache_modifiable_only

axi3_awcache_modifiable_bit_write_unaligned_transfer

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer

This cover group crosses bit AWCACHE[1] with unaligned write transfers. It is constructed and sampled when interface type is AXI3 and trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_cov_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi3_awcache_modifiable_bit_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

AXI_PORT_MON_UNALIGNED_ADDRESS

AXI_PORT_MON_AWCACHE_MODIFIABLE_UNALIGNED_TRANSFER_AXI4

trans_cross_axi4_awcache_modifiable_bit_write_unaligned_transfer

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte
cache_type_modifiable_bit:svt_axi_cache_modifiable_only

axi4_awcache_modifiable_bit_write_unaligned_transfer

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer

This cover group crosses bit AWCACHE[1] with unaligned write transfers. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_cov_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi4_awcache_modifiable_bit_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, burst_length, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

AXI_PORT_OUTSTANDING_XACT_MODIFIABLE

AXI_PORT_READ_OUTSTANDING_XACT_MODIFIABLE

trans_axi_read_outstanding_xact_same_arid_cache_modifiable_bit

read_outstanding_xact_same_arid_cache_modifiable_bit

read_outstanding_xact_same_arid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable

Covergroup:trans_axi_read_outstanding_xact_same_arid_cache_modifiable_bit

This coverpoint covers the scenario in which master can issue multiple outstanding READ transactions with same ARID,taking ARCACHE Modifiable bit into consideration. It is constructed and sampled when trans_axi_read_outstanding_xact_same_arid_cache_modifiable_bit_enable is asserted.

Bins are interpreted as follows:

cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=1 is followed by another transaction with ARCACHE[1]=1.
cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=1 is followed by another transaction with ARCACHE[1]=0.
cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=0 is followed by another transaction with ARCACHE[1]=1.
cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[1]=0 is followed by another transaction with ARCACHE[1]=0.

Coverpoints:

read_outstanding_xact_same_arid_cache_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1

AXI_PORT_OUTSTANDING_XACT_MODIFIABLE

AXI_PORT_READ_OUTSTANDING_XACT_ARID_MODIFIABLE

trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit

read_outstanding_xact_diff_arid_cache_modifiable_bit

read_outstanding_xact_diff_arid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable

Covergroup:trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit

This coverpoint covers the scenario in which master can issue multiple outstanding READ transactions with different ARID,taking ARCACHE Modifiable bit into consideration. It is constructed and sampled when trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit_enable is asserted.

Coverpoints:read_outstanding_xact_diff_arid_cache_modifiable_bit

Bins are interpreted as follows:

cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=1 is followed by another transaction with ARCACHE[0]=1.
cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=1 is followed by another transaction with ARCACHE[0]=0.
cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=0 is followed by another transaction with ARCACHE[0]=1.
cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with ARCACHE[0]=0 is followed by another transaction with ARCACHE[0]=0.
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1

AXI_PORT_OUTSTANDING_XACT_MODIFIABLE

AXI_PORT_READ_OUTSTANDING_XACT_ARID_DEVICE

trans_axi_read_outstanding_xact_diff_arid_device_cacheable_bit

read_outstanding_xact_diff_arid_device_cacheable_bit

read_outstanding_xact_diff_arid_device_cacheable_bit:device_nonbufferable_followed_by_device_nonbufferable, device_nonbufferable_followed_by_device_bufferable, device_bufferable_followed_by_device_nonbufferable, device_bufferable_followed_by_device_bufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable, normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_bufferable_followed_by_noncacheable_bufferable

Covergroup:trans_axi_read_outstanding_xact_diff_arid_device_cacheable_bit

This coverpoint covers the scenario in which master can issue multiple outstanding READ transactions with different ARID,taking memory types by ARCACHE[3:0] into considera* It is constructed when trans_axi_read_outstanding_xact_diff_arid_cache_modifiable_bit_enable is asserted. It is constructed and sampled when trans_axi_read_outstanding_xact_diff_arid_device_cacheable_bit_enable is asserted.

Coverpoints:read_outstanding_xact_diff_arid_device_cacheable_bit

Bins are interpreted as follows:

device_nonbufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0000 is followed by another transaction with ARCACHE[3:0]= 4'b0000.
device_nonbufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0000 is followed by another transaction with ARCACHE[3:0]= 4'b0001.
device_bufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0001 is followed by another transaction with ARCACHE[3:0]= 4'b0000.
device_bufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0001 is followed by another transaction with ARCACHE[3:0]= 4'b0001.
normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0010 is followed by another transaction with ARCACHE[3:0]= 4'b0010.
normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0010 is followed by another transaction with ARCACHE[3:0]= 4'b0011.
normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0011 is followed by another transaction with ARCACHE[3:0]= 4'b0010.
normal_noncacheable_bufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with ARCACHE[3:0]= 4'b0011 is followed by another transaction with ARCACHE[3:0]= 4'b0011.
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A4.4

AXI_PORT_OUTSTANDING_XACT_MODIFIABLE

AXI_PORT_WRITE_OUTSTANDING_XACT_AWID_MODIFIABLE

trans_axi_write_outstanding_xact_diff_awid_cache_modifiable_bit

write_outstanding_xact_diff_awid_cache_modifiable_bit

write_outstanding_xact_diff_awid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable

Covergroup:trans_axi_write_outstanding_xact_diff_awid_cache_modifiable_bit

This coverpoint covers the scenario in which master can issue multiple outstanding WRITE transactions with diff AWID's,taking AWCACHE Modifiable bit into consideration. It is constructed and sampled when trans_axi_write_outstanding_xact_diff_awid_cache_modifiable_bit_enable is asserted.

Coverpoints:write_outstanding_xact_diff_awid_cache_modifiable_bit Bins are interpreted as follows:

cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=1 is followed by another transaction with AWCACHE[0]=1.
cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=1 is followed by another transaction with AWCACHE[0]=0.
cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=0 is followed by another transaction with AWCACHE[0]=1.
cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[0]=0 is followed by another transaction with AWCACHE[0]=0.
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1

AXI_PORT_OUTSTANDING_XACT_MODIFIABLE

AXI_PORT_WRITE_OUTSTANDING_XACT_SAME_AWID_MODIFIABLE

trans_axi_write_outstanding_xact_same_awid_cache_modifiable_bit

write_outstanding_xact_same_awid_cache_modifiable_bit

write_outstanding_xact_same_awid_cache_modifiable_bit:cache_nonmodifiable_followed_by_nonmodifiable, cache_nonmodifiable_followed_by_modifiable, cache_modifiable_followed_by_nonmodifiable, cache_modifiable_followed_by_modifiable

Covergroup:trans_axi_write_outstanding_xact_same_awid_cache_modifiable_bit

This coverpoint covers the scenario in which master can issue multiple outstanding WRITE transactions with same AWID's,taking AWCACHE Modifiable bit into consideration. It is constructed when trans_axi_write_outstanding_xact_same_awid_cache_modifiable_bit_enable is asserted.

Coverpoints:write_outstanding_xact_same_awid_cache_modifiable_bit Bins are interpreted as follows:

cache_modifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=1 is followed by another transaction with AWCACHE[1]=1.
cache_modifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=1 is followed by another transaction with AWCACHE[1]=0.
cache_nonmodifiable_followed_by_modifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=0 is followed by another transaction with AWCACHE[1]=1.
cache_nonmodifiable_followed_by_nonmodifiable: Bin is hit when an outstanding transaction with AWCACHE[1]=0 is followed by another transaction with AWCACHE[1]=0.
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A5.1

AXI_PORT_OUTSTANDING_XACT_MODIFIABLE

AXI_PORT_WRITE_OUTSTANDING_XACT_AWID_DEVICE

trans_axi_write_outstanding_xact_diff_awid_device_cacheable_bit

write_outstanding_xact_diff_awid_device_cacheable_bit

write_outstanding_xact_diff_awid_device_cacheable_bit:device_nonbufferable_followed_by_device_nonbufferable, device_nonbufferable_followed_by_device_bufferable, device_bufferable_followed_by_device_nonbufferable, device_bufferable_followed_by_device_bufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable, normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable, normal_noncacheable_bufferable_followed_by_noncacheable_bufferable

Covergroup:trans_axi_write_outstanding_xact_diff_awid_device_cacheable_bit

This coverpoint covers the scenario in which master can issue multiple outstanding WRITE transactions with different AWID,taking memory types by AWCACHE[3:0] into consideration. It is constructed and sampled when trans_axi_write_outstanding_xact_diff_awid_device_cacheable_bit_enable is asserted.

Coverpoints:write_outstanding_xact_diff_awid_device_cacheable_bit

Bins are interpreted as follows:

device_nonbufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0000 is followed by another transaction with AWCACHE[3:0]= 4'b0000.
device_nonbufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0000 is followed by another transaction with AWCACHE[3:0]= 4'b0001.
device_bufferable_followed_by_device_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0001 is followed by another transaction with AWCACHE[3:0]= 4'b0000.
device_bufferable_followed_by_device_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0001 is followed by another transaction with AWCACHE[3:0]= 4'b0001.
normal_noncacheable_nonbufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0010 is followed by another transaction with AWCACHE[3:0]= 4'b0010.
normal_noncacheable_nonbufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0010 is followed by another transaction with AWCACHE[3:0]= 4'b0011.
normal_noncacheable_bufferable_followed_by_noncacheable_nonbufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0011 is followed by another transaction with AWCACHE[3:0]= 4'b0010.
normal_noncacheable_bufferable_followed_by_noncacheable_bufferable: Bin is hit when an outstanding transaction with AWCACHE[3:0]= 4'b0011 is followed by another transaction with AWCACHE[3:0]= 4'b0011.
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613 ; section A4.4

ACE_PORT_MON_ARPROT_ARBARRIER

trans_cross_ace_arprot_arbarrier_memory_sync

coherent_read_xact_type:coherent_readbarrier_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

arprot_arbarrier_memory_sync

Covergroup: trans_cross_ace_arprot_arbarrier_memory_sync

It is constructed and sampled when trans_cross_ace_arprot_arbarrier_memory_sync_enable is asserted.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
barrier_type : Captures read barrier
prot_type : Captures transaction protection type

Cross coverpoints:

arprot_arbarrier_memory_sync: Crosses cover points read transaction of barrier_type MEMORY_BARRIER & SYNC_BARRIER with arprot

The following bins are ignored:

bins that interset NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER
bins that intersect transaction types other than READBARRIER
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

ACE_PORT_MON_AWPROT_AWBARRIER

trans_cross_ace_awprot_awbarrier_memory_sync

coherent_write_xact_type:coherent_writebarrier_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

awprot_awbarrier_memory_sync

Covergroup: trans_cross_ace_awprot_awbarrier_memory_sync

It is constructed and sampled when trans_cross_ace_awprot_awbarrier_memory_sync_enable is asserted.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier
prot_type : Captures transaction protection type

Cross coverpoints:

awprot_awbarrier_memory_sync: Crosses cover points write transaction of barrier_type MEMORY_BARRIER & SYNC_BARRIER with awprot

The following bins are ignored:

bins that interset NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER
bins that intersect transaction types other than WRITEBARRIER
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

ACE_PORT_MON_ARDOMAIN_ARPROT

trans_cross_ace_readonce_ardomain_arprot

coherent_read_xact_type:coherent_readonce_xact
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

readonce_ardomain_arprot

Covergroup: trans_cross_ace_readonce_ardomain_arprot

It is constructed and sampled when trans_cross_ace_readonce_ardomain_arprot_enable is asserted.

Coverpoints:

coherent_read_xact_type: Captures readonce coherent read transaction
domain_type : Captures domain type
prot_type : Captures transaction protection type

Cross coverpoints:

readonce_ardomain_arprot : Crosses cover points coherent_read_xact_type and domain_type and prot_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

ACE_PORT_MON_AWDOMAIN_AWPROT

trans_cross_ace_writeunique_awdomain_awprot

coherent_write_xact_type:coherent_writeunique_xact
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

writeunique_awdomain_awprot

Covergroup: trans_cross_ace_writeunique_awdomain_awprot

It is constructed and sampled when trans_cross_ace_writeunique_awdomain_awprot_enable is asserted

Coverpoints:

coherent_write_xact_type: Captures writeunique coherent write transaction
domain_type : Captures domain type
prot_type : Captures transaction protection type

Cross coverpoints:

writeunique_awdomain_awprot : Crosses cover points coherent_write_xact_type and domain_type and prot_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

AXI_PORT_MON_ATOMICTYPE_CACHE

AXI_PORT_MON_ATOMICTYPE_ARCACHE_AXI3

trans_cross_axi_atomictype_exclusive_arcache_axi3

read_xact_type:read_xact
atomic_type:normal, exclusive, locked
cache_type:device_noncacheable_nonbufferable, device_bufferable_or_modifiable_only, cacheable_but_do_not_alloc, cacheable_and_bufferable_but_do_not_alloc

axi_atomictype_exclusive_arcache

Covergroup: trans_cross_axi_atomictype_exclusive_arcache_axi3

This covergroup is cross coverage of READ Exclusive Access with all legel ARCache values. The legal ARCACHE values for exclusive read access are

Device Non-bufferable
Device bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI3 and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_arcache: Crosses cover points read_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4

AXI_PORT_MON_ATOMICTYPE_CACHE

AXI_PORT_MON_ATOMICTYPE_ARCACHE_AXI4

trans_cross_axi_atomictype_exclusive_arcache_axi4

read_xact_type:read_xact
atomic_type:normal, exclusive, locked
cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable

axi_atomictype_exclusive_arcache

Covergroup: trans_cross_axi_atomictype_exclusive_arcache_axi4

This covergroup is cross coverage of READ Exclusive Access with all legel ARCache values. The legal ARCACHE values for exclusive read access are

Device Non-bufferable
Device bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_arcache: Crosses cover points read_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4

AXI_PORT_MON_ATOMICTYPE_CACHE

AXI_PORT_MON_ATOMICTYPE_AWCACHE_EXCLUSIVE_AXI4

trans_cross_axi_atomictype_exclusive_awcache_axi4

write_xact_type:write_xact
atomic_type:normal, exclusive, locked
cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable

axi_atomictype_exclusive_awcache

Covergroup: trans_cross_axi_atomictype_exclusive_awcache_axi4

This covergroup is cross coverage of WRITE Exclusive Access with all legel AWCache values for exclusive access. The legal AWCACHE values for exclusive write access are

Device bufferable
Device Non-bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_atomictype_exclusive_awcache_enable is asserted.
Coverpoints:
write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_awcache: Crosses cover points write_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4

AXI_PORT_MON_ATOMICTYPE_CACHE

AXI_PORT_MON_ATOMICTYPE_AWCACHE_EXCLUSIVE_AXI3

trans_cross_axi_atomictype_exclusive_awcache_axi3

write_xact_type:write_xact
atomic_type:normal, exclusive, locked
cache_type:device_noncacheable_nonbufferable, device_bufferable_or_modifiable_only, cacheable_but_do_not_alloc, cacheable_and_bufferable_but_do_not_alloc

axi_atomictype_exclusive_awcache

Covergroup: trans_cross_axi_atomictype_exclusive_awcache_axi3

This covergroup is cross coverage of WRITE Exclusive Access with all legel AWCache values for exclusive access. The legal AWCACHE values for exclusive write access are

Device bufferable
Device Non-bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI_ACE and trans_cross_axi_atomictype_exclusive_awcache_enable is asserted.
Coverpoints:
write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_awcache: Crosses cover points write_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB63TO16

trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb63to16

ardvm_message_type:message_branch_predictor_invalidate
ardvm_va:invalidate_by_va, invalidate_not_by_va
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_branch_predictor_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB55TO16

trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb55to16

ardvm_message_type:message_branch_predictor_invalidate
ardvm_va:invalidate_by_va, invalidate_not_by_va
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_branch_predictor_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB47TO16

trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb47to16

ardvm_message_type:message_branch_predictor_invalidate
ardvm_va:invalidate_by_va, invalidate_not_by_va
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_branch_predictor_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB43TO16

trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb43to16

ardvm_message_type:message_branch_predictor_invalidate
ardvm_va:invalidate_by_va, invalidate_not_by_va
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_branch_predictor_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_BRANCH_INVL_VIRT_MSB39TO16

trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb39to16

ardvm_message_type:message_branch_predictor_invalidate
ardvm_va:invalidate_by_va, invalidate_not_by_va
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_branch_predictor_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB63TO16

trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

ardvm_message_type:message_physical_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB55TO16

trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

ardvm_message_type:message_physical_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB47TO16

trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

ardvm_message_type:message_physical_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB43TO16

trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

ardvm_message_type:message_physical_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_PHY_CACHE_VIRT_MSB39TO16

trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

ardvm_message_type:message_physical_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB63TO16

trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

ardvm_message_type:message_virtual_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB55TO16

trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

ardvm_message_type:message_virtual_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB47TO16

trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

ardvm_message_type:message_virtual_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB43TO16

trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

ardvm_message_type:message_virtual_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_CACHE_VIRT_MSB39TO16

trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

ardvm_message_type:message_virtual_instruction_cache_invalidate
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB63TO16

trans_cross_ace_dvm_firstpart_addr_range_msb63to16

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_firstpart_addr_range_msb63to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb63to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32] and ARADDR[31:16]. The total virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32

Cross coverpoints:

dvm_firstpart_addr_range_msb63to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB55TO16

trans_cross_ace_dvm_firstpart_addr_range_msb55to16

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_firstpart_addr_range_msb55to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb55to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32] and ARADDR[31:16]. The total Virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_firstpart_addr_range_msb55to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB47TO16

trans_cross_ace_dvm_firstpart_addr_range_msb47to16

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_firstpart_addr_range_msb47to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb47to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32] and ARADDR[31:16]. The total virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_firstpart_addr_range_msb47to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB43TO16

trans_cross_ace_dvm_firstpart_addr_range_msb43to16

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_firstpart_addr_range_msb43to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb43to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32] and ARADDR[31:16]. The total virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12

Cross coverpoints:

dvm_firstpart_addr_range_msb43to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_ADDR_MSB39TO16

trans_cross_ace_dvm_firstpart_addr_range_msb39to16

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_firstpart_addr_range_msb39to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb39to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32] and ARADDR[31:16]. The total virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_firstpart_addr_range_msb39to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_64

trans_cross_ace_dvm_firstpart_secondpart_addr_range_64

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
araddr_dvm_secondpart_64:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4

dvm_firstpart_secondpart_addr_range_64

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_64

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[63:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
araddr_dvm_secondpart_64 : Captures SecondPart of DVM of width64

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_64 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and araddr_dvm_secondpart_64.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_56

trans_cross_ace_dvm_firstpart_secondpart_addr_range_56

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
araddr_dvm_secondpart_56:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4

dvm_firstpart_secondpart_addr_range_56

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_56

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[55:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
araddr_dvm_secondpart_56 : Captures SecondPart of DVM of width56

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_56 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and araddr_dvm_secondpart_56

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_48

trans_cross_ace_dvm_firstpart_secondpart_addr_range_48

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
araddr_dvm_secondpart_48:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4

dvm_firstpart_secondpart_addr_range_48

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_48

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[47:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
araddr_dvm_secondpart_48 : Captures SecondPart of DVM of width48

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_48 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and araddr_dvm_secondpart_48

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_44

trans_cross_ace_dvm_firstpart_secondpart_addr_range_44

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
araddr_dvm_secondpart_44:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4

dvm_firstpart_secondpart_addr_range_44

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_44

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[43:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
araddr_dvm_secondpart_44 : Captures SecondPart of DVM of width44

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_44 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and araddr_dvm_secondpart_44

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_DVM_MODES

AXI_PORT_MON_ACE_DVM_FIRSTPART_SECONDPART_ADDR_40

trans_cross_ace_dvm_firstpart_secondpart_addr_range_40

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
araddr_dvm_secondpart_40:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3

dvm_firstpart_secondpart_addr_range_40

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_40

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[39:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
araddr_dvm_secondpart_40 : Captures SecondPart of DVM of width40

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_40 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and araddr_dvm_secondpart_40

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB63TO16

trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb63to16

acdvm_message_type:message_tlb_invalidate
acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
acdvm_security_type:no_secure, secure, secure_and_no_secure
acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3

dvm_snoop_tlbinvl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb63to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width32

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB55TO16

trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb55to16

acdvm_message_type:message_tlb_invalidate
acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
acdvm_security_type:no_secure, secure, secure_and_no_secure
acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_snoop_tlbinvl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb55to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB43TO16

trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb43to16

acdvm_message_type:message_tlb_invalidate
acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
acdvm_security_type:no_secure, secure, secure_and_no_secure
acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_snoop_tlbinvl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb43to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width12

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_MODES_MSB39TO16

trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb39to16

acdvm_message_type:message_tlb_invalidate
acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
acdvm_security_type:no_secure, secure, secure_and_no_secure
acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_snoop_tlbinvl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb39to16

This covergroup is cross coverage ofsnoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB47TO16

trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

acdvm_message_type:message_physical_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB63TO16

trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

acdvm_message_type:message_physical_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3
snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB55TO16

trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

acdvm_message_type:message_physical_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB43TO16

trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

acdvm_message_type:message_physical_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_PHY_MODES_MSB39TO16

trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

acdvm_message_type:message_physical_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
snoop_dvm_message_phy_inst_cache_invl_bits:invl_by_pa_with_virt_index_sec_phy_inst_cache, invl_by_pa_with_virt_index_non_sec_phy_inst_cache

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB63TO16

trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

acdvm_message_type:message_virtual_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3
snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB55TO16

trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

acdvm_message_type:message_virtual_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB47TO16

trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

acdvm_message_type:message_virtual_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB43TO16

trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

acdvm_message_type:message_virtual_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_VIRT_MODES_MSB39TO16

trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

acdvm_message_type:message_virtual_instruction_cache_invalidate
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
snoop_dvm_message_virt_inst_cache_invl_bits:invl_all_non_sec_guest_os, invl_by_asid_and_va_non_sec_guest_os

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_typ and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpar and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB63TO16

trans_cross_ace_snoop_dvm_firstpart_addr_range_msb63to16

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3

snoop_dvm_firstpart_addr_range_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb63to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32] and ARADDR[31:16]. The total virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb63to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB55TO16

trans_cross_ace_snoop_dvm_firstpart_addr_range_msb55to16

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

snoop_dvm_firstpart_addr_range_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb55to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32] and ARADDR[31:16]. The total virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb55to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB47TO16

trans_cross_ace_snoop_dvm_firstpart_addr_range_msb47to16

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

snoop_dvm_firstpart_addr_range_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb47to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32] and ARADDR[31:16]. The total virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb47to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB43TO16

trans_cross_ace_snoop_dvm_firstpart_addr_range_msb43to16

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

snoop_dvm_firstpart_addr_range_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb43to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32] and ARADDR[31:16]. The total virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb43to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_MODES_MSB39TO16

trans_cross_ace_snoop_dvm_firstpart_addr_range_msb39to16

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

snoop_dvm_firstpart_addr_range_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb39to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32] and ARADDR[31:16]. The total virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb39to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_64

trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_64

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb63to32_firstpart:dvm_acaddr_firstpart_range_1, dvm_acaddr_firstpart_range_2, dvm_acaddr_firstpart_range_3
acaddr_dvm_secondpart_64:dvm_acaddr_secondpart_range_1, dvm_acaddr_secondpart_range_2, dvm_acaddr_secondpart_range_3, dvm_acaddr_secondpart_range_4

snoop_dvm_firstpart_secondpart_addr_range_64

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_64

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[63:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[63:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
acaddr_dvm_secondpart_64 : Captures SecondPart of DVM of width64

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_64 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and acaddr_dvm_secondpart_64

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_56

trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_56

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
acaddr_dvm_secondpart_56:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4

snoop_dvm_firstpart_secondpart_addr_range_56

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_56

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[55:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[55:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
acaddr_dvm_secondpart_56 : Captures SecondPart of DVM of width56

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_56 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and acaddr_dvm_secondpart_56

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_48

trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_48

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3
acaddr_dvm_secondpart_48:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4

snoop_dvm_firstpart_secondpart_addr_range_48

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_48

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[47:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[47:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
acaddr_dvm_secondpart_48 : Captures SecondPart of DVM of width48

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_48 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and acaddr_dvm_secondpart_48

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_44

trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_44

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
acaddr_dvm_secondpart_44:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3, dvm_araddr_secondpart_range_4

snoop_dvm_firstpart_secondpart_addr_range_44

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_44

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[43:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[43:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
acaddr_dvm_secondpart_44 : Captures SecondPart of DVM of width44

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_44 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and acaddr_dvm_secondpart_44

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_FIRSTPART_SECONDPART_40

trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_40

acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4
acaddr_dvm_secondpart_40:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3

snoop_dvm_firstpart_secondpart_addr_range_40

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_40

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[39:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[39:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
acaddr_dvm_secondpart_40 : Captures SecondPart of DVM of width40

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_40 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart and acaddr_dvm_secondpart_40

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB63TO16

trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb63to16

ardvm_message_type:message_tlb_invalidate
ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
ardvm_security_type:no_secure, secure, secure_and_no_secure
ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb63to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_tlbinvl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width32

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB55TO16

trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb55to16

ardvm_message_type:message_tlb_invalidate
ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
ardvm_security_type:no_secure, secure, secure_and_no_secure
ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb55to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_tlbinvl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB47TO16

trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb47to16

ardvm_message_type:message_tlb_invalidate
ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
ardvm_security_type:no_secure, secure, secure_and_no_secure
ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_tlbinvl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB43TO16

trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb43to16

ardvm_message_type:message_tlb_invalidate
ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
ardvm_security_type:no_secure, secure, secure_and_no_secure
ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb43to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_tlbinvl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width12

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_ACE_SNOOP_DVM_MODES

AXI_PORT_MON_ACE_SNOOP_DVM_TLBINVL_VIRT_MSB39TO16

trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb39to16

ardvm_message_type:message_tlb_invalidate
ardvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
ardvm_security_type:no_secure, secure, secure_and_no_secure
ardvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_msb39to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3, dvm_araddr_firstpart_range_4

dvm_tlbinvl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_ARVALID_ARREADY_COVER_ACVALID_ACREADY_ACSNOOP

trans_cross_dvm_overlap_arvalid_arready_cover_acvalid_acready_acsnoop

arvalid:arvalid_val
arready_0:arready_val_0
acvalid:acvalid_val_1, acvalid_val_0
acready:acready_val_1, acready_val_0
acsnoop:acsnoop_val

overlap_case_dvm_arvalid_arready_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_arvalid_arready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when ARVALID == 1 and ARREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

arvalid : Captures ARVALID == 1
arready_0 : Captures ARREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_arvalid_arready_acvalid_acready_acsnoop : Crosses coverpoints arvaild and arready_0 and acvalid and acready and acsnoop

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_AWVALID_AWREADY_COVER_ACVALID_ACREADY_ACSNOOP

trans_cross_dvm_overlap_awvalid_awready_cover_acvalid_acready_acsnoop

awvalid:awvalid_val
awready_0:awready_val_0
acvalid:acvalid_val_1, acvalid_val_0
acready:acready_val_1, acready_val_0
acsnoop:acsnoop_val

overlap_case_dvm_awvalid_high_awready_low_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_awvalid_awready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when AWVALID == 1 & AWREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

awvalid : Captures AWVALID == 1
awready_0 : Captures AWREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_awvalid_high_awready_low_acvalid_acready_acsnoop : Crosse coverpoints awvalid and awready_0 and acvalid and acready and acsnoop

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_RVALID_RREADY_COVER_ACVALID_ACREADY_ACSNOOP

trans_cross_dvm_overlap_rvalid_rready_cover_acvalid_acready_acsnoop

rvalid_1:rvalid_val_1
rready_0:rready_val_0
acvalid:acvalid_val_1, acvalid_val_0
acready:acready_val_1, acready_val_0
acsnoop:acsnoop_val

overlap_case_dvm_rvalid_high_rready_low_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_rvalid_rready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when RVALID == 1 & RREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

rvalid_1 : Captures RVALID == 1
rready_0 : Captures RREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_rvalid_high_rready_low_acvalid_acready_acsnoop : Crosses coverpoints rvalid_1 and rready_0 and acvalid and cready and acsnoop

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_BVALID_BREADY_COVER_ACVALID_ACREADY_ACSNOOP

trans_cross_dvm_overlap_bvalid_bready_cover_acvalid_acready_acsnoop

bvalid_1:bvalid_val_1
bready_0:bready_val_0
acvalid:acvalid_val_1, acvalid_val_0
acready:acready_val_1, acready_val_0
acsnoop:acsnoop_val

overlap_case_dvm_bvalid_high_bready_low_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_bvalid_bready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when BVALID == 1 & BREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

bvalid_1 : Captures BVALID == 1
bready_0 : Captures BREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_bvalid_high_bready_low_acvalid_acready_acsnoop : Crosses coverpoints bvalid_1 and bready_0 and acvalid and acready and acsnoop

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_ARVALID_ARREADY_COVER_CRVALID_CRREADY

trans_cross_dvm_overlap_arvalid_arready_cover_crvalid_crready

arvalid:arvalid_val
arready_0:arready_val_0
crvalid:crvalid_val_1, crvalid_val_0
crready:crready_val_1, crready_val_0

overlap_case_dvm_arvalid_high_arready_low_crvalid_crready

Covergroup: trans_cross_dvm_overlap_arvalid_arready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when ARVALID == 1 and ARREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

arvalid : Captures ARVALID == 1
arready_0 : Captures ARREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_arvalid_high_arready_low_crvalid_crready : Crosses coverpoints arvalid and arready_0 and crvalid and crready

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_AWVALID_AWREADY_COVER_CRVALID_CRREADY

trans_cross_dvm_overlap_awvalid_awready_cover_crvalid_crready

awvalid:awvalid_val
awready_0:awready_val_0
crvalid:crvalid_val_1, crvalid_val_0
crready:crready_val_1, crready_val_0

overlap_case_dvm_awvalid_high_awready_low_crvalid_crready

Covergroup: trans_cross_dvm_overlap_awvalid_awready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when AWVALID == 1 & AWREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

awvalid : Captures AWVALID == 1
awready_0 : Captures AWREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_awvalid_high_awready_low_crvalid_crready : Crosses coverpoints awvalid and awready_0 and crvalid and crready

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_RVALID_RREADY_COVER_CRVALID_CRREADY

trans_cross_dvm_overlap_rvalid_rready_cover_crvalid_crready

rvalid_1:rvalid_val_1
rready_0:rready_val_0
crvalid:crvalid_val_1, crvalid_val_0
crready:crready_val_1, crready_val_0

overlap_case_dvm_rvalid_high_rready_low_crvalid_crready

Covergroup: trans_cross_dvm_overlap_rvalid_rready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when RVALID == 1 & RREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

rvalid_1 : Captures RVALID == 1
rready_0 : Captures RREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_rvalid_high_rready_low_crvalid_crready : Crosses coverpoints rvalid_1 and rready_0 and crvalid and crready

AXI_PORT_MON_DVM_OVERLAP

AXI_PORT_MON_DVM_OVERLAP_BVALID_BREADY_COVER_CRVALID_CRREADY

trans_cross_dvm_overlap_bvalid_bready_cover_crvalid_crready

bvalid_1:bvalid_val_1
bready_0:bready_val_0
crvalid:crvalid_val_1, crvalid_val_0
crready:crready_val_1, crready_val_0

overlap_case_dvm_bvalid_high_bready_low_crvalid_crready

Covergroup: trans_cross_dvm_overlap_bvalid_bready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when BVALID == 1 & BREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

bvalid_1 : Captures BVALID == 1
bready_0 : Captures BREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_bvalid_high_bready_low_crvalid_crready : Crosses coverpoints bvalid_1 and bready_0 and crvalid and crready

AXI_PORT_MON_VALID_READY_XACT_FLOW

signal_master_slave_valid_ready_dependency

AWVALID_AWREADY_Dependency:AWVALID_and_AWREADY
AWVALID_WREADY_Dependency:AWVALID_and_WREADY
AWVALID_RVALID_Dependency:AWVALID_and_RVALID
AWVALID_BVALID_Dependency:AWVALID_and_BVALID
WVALID_AWREADY_Dependency:WVALID_and_AWREADY
WVALID_WREADY_Dependency:WVALID_and_WREADY
WVALID_RVALID_Dependency:WVALID_and_RVALID
WVALID_BVALID_Dependency:WVALID_and_BVALID
RREADY_AWREADY_Dependency:RREADY_and_AWREADY
RREADY_WREADY_Dependency:RREADY_and_WREADY
RREADY_RVALID_Dependency:RREADY_and_RVALID
RREADY_BVALID_Dependency:RREADY_and_BVALID
BREADY_AWREADY_Dependency:BREADY_and_AWREADY
BREADY_WREADY_Dependency:BREADY_and_WREADY
BREADY_RVALID_Dependency:BREADY_and_RVALID
BREADY_BVALID_Dependency:BREADY_and_BVALID

Covergroup: signal_master_slave_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after AWREADY is deasserted, then coverpoint AWVALID_AWREADY_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

AWVALID_AWREADY_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency) after AWREADY is deasserted.
AWVALID_WREADY_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_wready_dependency) after WREADY is deasserted.
AWVALID_RVALID_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_rvalid_dependency) after RVALID is deasserted.
AWVALID_BVALID_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_bvalid_dependency) after BVALID is deasserted.
WVALID_AWREADY_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_awready_dependency) after AWREADY is deasserted.
WVALID_WREADY_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_wready_dependency) after WREADY is deasserted.
WVALID_RVALID_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_rvalid_dependency) after RVALID is deasserted.
WVALID_BVALID_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_bvalid_dependency) after BVALID is deasserted.
RREADY_AWREADY_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_awready_dependency) after AWREADY is deasserted.
RREADY_WREADY_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_wready_dependency) after WREADY is deasserted.
RREADY_RVALID_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_rvalid_dependency) after RVALID is deasserted.
RREADY_BVALID_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_bvalid_dependency) after BVALID is deasserted.
BREADY_AWREADY_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_awready_dependency) after AWREADY is deasserted.
BREADY_WREADY_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_wready_dependency) after WREADY is deasserted.
BREADY_RVALID_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_rvalid_dependency) after RVALID is deasserted.
BREADY_BVALID_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_bvalid_dependency) after BVALID is deasserted.

AXI_PORT_MON_VALID_READY_XACT_FLOW

signal_master_valid_ready_dependency

AWVALID_WVALID_Dependency:AWVALID_and_WVALID
AWVALID_RREADY_Dependency:AWVALID_and_RREADY
AWVALID_BREADY_Dependency:AWVALID_and_BREADY
WVALID_AWVALID_Dependency:WVALID_and_AWVALID
WVALID_RREADY_Dependency:AWVALID_and_RREADY
WVALID_BREADY_Dependency:WVALID_and_BREADY
RREADY_AWVALID_Dependency:RREADY_and_AWVALID
RREADY_WVALID_Dependency:RREADY_and_WVALID
RREADY_BREADY_Dependency:RREADY_and_BREADY
BREADY_AWVALID_Dependency:BREADY_and_AWVALID
BREADY_WVALID_Dependency:BREADY_and_WVALID
BREADY_RREADY_Dependency:BREADY_and_RREADY

Covergroup: signal_master_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after wvalid is deasserted, then coverpoint AWVALID_WVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

AWVALID_WVALID_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency) after WVALID is deasserted.
AWVALID_RREADY_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_rready_dependency) after RREADY is deasserted.
AWVALID_BREADY_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_bready_dependency) after BREADY is deasserted.
WVALID_AWVALID_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_awvalid_dependency) after AWVALID is deasserted.
WVALID_RREADY_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_rready_dependency) after RREADY is deasserted.
WVALID_BREADY_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_bready_dependency) after BREADY is deasserted.
RREADY_AWVALID_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_awvalid_dependency) after AWVALID is deasserted.
RREADY_WVALID_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_wvalid_dependency) after WVALID is deasserted.
RREADY_BREADY_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_bready_dependency) after BREADY is deasserted.
BREADY_AWVALID_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_awvalid_dependency) after AWVALID is deasserted.
BREADY_WVALID_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_wvalid_dependency) after WVALID is deasserted.
BREADY_RREADY_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_rready_dependency) after RREADY is deasserted.

AXI_PORT_MON_VALID_READY_XACT_FLOW

signal_slave_master_valid_ready_dependency

AWREADY_AWVALID_Dependency:AWREADY_and_AWVALID
AWREADY_WVALID_Dependency:AWREADY_and_WVALID
AWREADY_RVALID_Dependency:AWREADY_and_RVALID
AWREADY_BVALID_Dependency:AWREADY_and_BVALID
WREADY_AWVALID_Dependency:WREADY_and_AWVALID
WREADY_WVALID_Dependency:WREADY_and_WVALID
WREADY_RREADY_Dependency:WREADY_and_RREADY
WREADY_BREADY_Dependency:WREADY_and_BREADY
RVALID_AWREADY_Dependency:RVALID_and_AWREADY
RVALID_WREADY_Dependency:RVALID_and_WREADY
RVALID_RREADY_Dependency:RVALID_and_RREADY
RVALID_BREADY_Dependency:RVALID_and_BREADY
BVALID_AWREADY_Dependency:BVALID_and_AWREADY
BVALID_WREADY_Dependency:BVALID_and_WREADY
BVALID_RREADY_Dependency:BVALID_and_RREADY
BVALID_BREADY_Dependency:BVALID_and_BREADY

Covergroup: signal_slave_master_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWREADY has to remain deasserted for N clocks (user input) after AWVALID is deasserted, then coverpoint AWREADY_AWVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

AWREADY_AWVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_awvalid_dependency) after AWVALIDis deasserted.
AWREADY_WVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_wvalid_dependency) after WVALID is deasserted.
AWREADY_RVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_rvalid_dependency) after RVALID is deasserted.
AWREADY_BVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_bvalid_dependency) after BVALID is deasserted.
WREADY_AWVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_awvalid_dependency) after AWVALID is deasserted.
WREADY_WVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_wvalid_dependency) after WVALID is deasserted.
WREADY_RREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_rready_dependency) after RREADY is deasserted.
WREADY_BREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_bready_dependency) after BREADY is deasserted.
RVALID_AWREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_awready_dependency) after AWREADY is deasserted.
RVALID_WREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_wready_dependency) after WREADY is deasserted.
RVALID_RREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_rready_dependency) after RREADY is deasserted.
RVALID_BREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_bready_dependency) after BREADY is deasserted.
BVALID_AWREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_awready_dependency) afterAWREADY is deasserted.
BVALID_WREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_wready_dependency) after WREADY is deasserted.
BVALID_RREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_rready_dependency) after RREADY is deasserted.
BVALID_BREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_bready_dependency) after BREADY is deasserted.

AXI_PORT_MON_VALID_READY_XACT_FLOW

signal_slave_valid_ready_dependency

WREADY_ARREADY_Dependency:WREADY_and_ARREADY
WREADY_RVALID_Dependency:WREADY_and_RVALID
WREADY_BVALID_Dependency:WREADY_and_BVALID
ARREADY_WREADY_Dependency:ARREADY_and_WREADY
ARREADY_RVALID_Dependency:ARREADY_and_RVALID
ARREADY_BVALID_Dependency:ARREADY_and_BVALID
RVALID_ARREADY_Dependency:RVALID_and_ARREADY
RVALID_WREADY_Dependency:RVALID_and_WREADY
RVALID_BVALID_Dependency:RVALID_and_BVALID
BVALID_ARREADY_Dependency:BVALID_and_ARREADY
BVALID_WREADY_Dependency:BVALID_and_WREADY
BVALID_RVALID_Dependency:BVALID_and_RVALID

Covergroup: signal_slave_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal WREADY has to remain deasserted for N clocks (user input) after arready is deasserted, then coverpoint WREADY_ARREADY_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_wready_arready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

WREADY_ARREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_arready_dependency) after ARREADY is deasserted.
WREADY_RVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_rvalid_dependency) after RVALID is deasserted.
WREADY_BVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_bvalid_dependency) after BVALID is deasserted.
ARREADY_WREADY_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_wready_dependency) after WREADY is deasserted.
ARREADY_RVALID_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_rvalid_dependency) after RVALID is deasserted.
ARREADY_BVALID_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_bvalid_dependency) after BVALID is deasserted.
RVALID_ARREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_arready_dependency) after ARREADY is deasserted.
RVALID_WREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_wready_dependency) after WREADY is deasserted.
RVALID_BVALID_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_bvalid_dependency) after BVALID is deasserted.
BVALID_ARREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_arready_dependency) after ARREADY is deasserted.
BVALID_WREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_wready_dependency) after WREADY is deasserted.
BVALID_RVALID_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_rvalid_dependency) after RVALID is deasserted.

AXI_STREAM_PORT_MON_XACT_FLOW

trans_axi4_stream_delay

TVALID_Delay:tvalid_delay_min, tvalid_delay_mid, tvalid_delay_max
TREADY_Delay:tready_delay_min, tready_delay_mid, tready_delay_max

Covergroup: trans_meta_axi_read

This Covergroup captures delay scenarios for tvalid signal for AXI4_STREAM. It is constructed and sampled when interface type is AXI4_STREAM & trans_axi4_stream_delay_enable is asserted.

Coverpoints:

TVALID_Delay: Captures min, mid and max range of delay signal tvalid
TREADY_Delay: Captures min, mid and max range of delay signal tready

AXI_STREAM_PORT_MON_XACT_FLOW

trans_cross_stream_xact_type_tid_tdest

stream_xact_type:byte_stream, continuous_aligned_stream, continuous_unaligned_stream, sparse_stream, user_stream
stream_tid:tid_within_range
stream_tdest:tdest_within_range

trans_cross_stream_xact_type_tid
trans_cross_stream_xact_type_tdest
trans_cross_stream_xact_type_tid_tdest

Covergroup: trans_cross_stream_xact_type_tid_tdest

This Covergroup captures stream xact_type, stream tid and stream tdest. It is constructed when interface_type is AXI4_STREAM and trans_cross_stream_xact_type_tid_tdest_enable set to 1.

Coverpoints:

stream_xact_type: Captures the type of stream
stream_tid: Captures the value of TID
stream_tdest: Captures the value of TDEST

Cross coverpoints:

trans_cross_stream_xact_type_tid_tdest: Crosses cover points stream_xact_type, stream_tid and stream_tdest
trans_cross_stream_xact_type_tid: Crosses coverpoints stream_xact_type and stream_tid
trans_cross_stream_xact_type_tdest: Crosses coverpoints stream_xact_type and stream_tdest

AXI_STREAM_PORT_MON_XACT_FLOW

trans_meta_axi4_stream

TVALID_to_TREADY_Delay:tvalid_to_tready_delay_min, tvalid_to_tready_delay_mid, tvalid_to_tready_delay_max
TVALID_to_prev_TVALID_Delay:tvalid_to_prev_tvalid_delay_min, tvalid_to_prev_tvalid_delay_mid, tvalid_to_prev_tvalid_delay_max
TVALID_before_TREADY:tvalid_before_tready
TREADY_before_TVALID:tready_before_tvalid

Covergroup: trans_meta_axi4_stream

This Covergroup captures delay scenarios for tvalid and tready for AXI4_STREAM. It is constructed and sampled when interface type is AXI4_STREAM & trans_meta_axi4_stream_enable is asserted.

Coverpoints:

TVALID_to_TREADY_Delay: Captures min, mid and max range of delays between signals tvalid and tready
TVALID_to_prev_TVALID_Delay: Captures min, mid and max range of delays between current and previous tvalid signals
TVALID_before_TREADY: Captures if TVALID signal comes before TREADY signal
TREADY_before_TVALID: Captures if TREADY signal comes before TVALID signal

AXI_PORT_MON_MASTER_TO_SLAVE_PATH`

AXI_PORT_MON_MASTER_TO_SLAVE_PATH_ACCESS_ACE

trans_cross_master_to_slave_path_access_ace

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
all_slaves:slvs_b
slaves_excluding_register_space:slvs_no_cfg_b

cross_read_xact_type_with_slave
cross_write_xact_type_with_slave

This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI_ACE or ACE_LITE and trans_cross_master_to_slave_path_access_ace_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_ace

Coverpoints:

all_slaves : Captures all participating path cov slaves
slaves_excluding_register_space : Captures all non axi/ace register address space slaves
coherent_read_xact_type: Captures readonce coherent read transaction
coherent_write_xact_type: Captures coherent write transaction

Cross coverpoints:

cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type
cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

AXI_PORT_MON_MASTER_TO_SLAVE_PATH`

AXI_PORT_MON_MASTER_TO_SLAVE_PATH_ACCESS_AXI4

trans_cross_master_to_slave_path_access_axi4

all_slaves:slvs_b
slaves_excluding_register_space:slvs_no_cfg_b
write_xact_type:write_xact
read_xact_type:read_xact
axi_ex_xact_type:exclusive_type
atomic_type:normal, locked
burst_type:fixed_burst, incr_burst, wrap_burst
axi_burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit
axi_response_type:axi_okay_response, axi_exokay_response, axi_slverr_response, axi_decerr_response, axi_exokay_fail_response
cache_type:rd_device_non_bufferable, rd_device_bufferable, rd_normal_non_cacheable_non_bufferable, rd_normal_non_cacheable_bufferable, rd_write_through_no_allocate, rd_write_through_read_allocate, rd_write_through_write_allocate, rd_write_through_read_and_write_allocate, rd_write_back_no_allocate, rd_write_back_read_allocate, rd_write_back_write_allocate, rd_write_back_read_and_write_allocate, wr_device_non_bufferable, wr_device_bufferable, wr_normal_non_cacheable_non_bufferable, wr_normal_non_cacheable_bufferable, wr_write_through_no_allocate, wr_write_through_read_allocate, wr_write_through_write_allocate, wr_write_through_read_and_write_allocate, wr_write_back_no_allocate, wr_write_back_read_allocate, wr_write_back_write_allocate, wr_write_back_read_and_write_allocate
burst_length:burst_length
axi_address_aligned:axi_8bit_aligned_address, axi_16bit_aligned_address, axi_32bit_aligned_address, axi_64bit_aligned_address, axi_128bit_aligned_address, axi_256bit_aligned_address

cache_len_1_all_okay
cache_len_reduced_all_okay
cache_len_reduced_ignore_response
cache_all_okay_fixed
cache_all_slverr_fixed
cache_all_okay_fixed_unaligned
cache_ignore_resp_fixed_unaligned
master_to_slave_all_okay
master_to_slave_ignore_response
master_to_slave_decerr_len_1
master_to_slave_slverr_len_1
master_to_slave_decerr
master_to_slave_slverr
master_to_all_slave_ignore_response
cross_xact_type_len_1_wstrb
cross_xact_type_len_2_wstrb
cross_xact_type_len_3_wstrb
cross_xact_type_len_4_wstrb
cross_xact_type_len_16_wstrb
cross_aligned_unaligned_addr_asize
cross_aligned_unaligned_addr_asize_ignore_resp
master_to_slave_x_wr_okay_addr_align
master_to_slave_x_wr_fail_addr_align
master_to_slave_x_wr_decerr
master_to_slave_x_wr_slverr
master_to_slave_x_wr_okay_wstrb
master_to_slave_x_wr_fail_wstrb

This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI4 and trans_cross_master_to_slave_path_access_axi4_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_axi4

Coverpoints:

all_slaves : Captures all participating path cov slaves
slaves_excluding_register_space : Captures all non axi/ace register address space slaves
coherent_read_xact_type: Captures readonce coherent read transaction
coherent_write_xact_type: Captures coherent write transaction

Cross coverpoints:

cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type
cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

AXI_PORT_MON_XACT_FLOW

trans_ar_aw_stalled_for_ac_channel

axi_ar_aw_stalled_for_ac_channel

axi_ar_aw_stalled_for_ac_channel:readonce_stalled_for_snoop, readshared_stalled_for_snoop, readclean_stalled_for_snoop, readnotshareddirty_stalled_for_snoop, readunique_stalled_for_snoop, cleanunique_stalled_for_snoop, makeunique_stalled_for_snoop, cleanshared_stalled_for_snoop, cleaninvalid_stalled_for_snoop, makeinvalid_stalled_for_snoop, writeunique_stalled_for_snoop, writelineunique_stalled_for_snoop

Covergroup: trans_ar_aw_stalled_for_ac_channel

This Covergroup captures stalled read and write transaction y interconnect when request is issued from master. It is constructed when interface_type is AXI_ACE & interface_category is AXI_READ_WRITE and trans_ar_aw_stalled_for_ac_channel_enable set to 1.

Coverpoints:

axi_ar_aw_stalled_for_ac_channel: This is covered when read transaction on AR channel OR WriteUnique/WriteLineUnique transactions on AW channel from a master are stalled by interconnect, while waiting for the snoop response from the same master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_axi_write_handshake_delay

last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay:last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_min, last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_mid, last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_max
last_AWVALID_AWREADY_handshake_to_next_AWVALID_Delay:last_awvalid_awready_handshake_to_next_awvalid_delay_min, last_awvalid_awready_handshake_to_next_awvalid_delay_mid, last_awvalid_awready_handshake_to_next_awvalid_delay_max
last_AWVALID_AWREADY_handshake_to_next_AWREADY_Delay:last_awvalid_awready_handshake_to_next_awready_delay_min, last_awvalid_awready_handshake_to_next_awready_delay_mid, last_awvalid_awready_handshake_to_next_awready_delay_max
last_AWREADY_to_next_AWVALID_AWREADY_handshake_Delay:last_awready_to_next_awvalid_awready_handshake_delay_min, last_awready_to_next_awvalid_awready_handshake_delay_mid, last_awready_to_next_awvalid_awready_handshake_delay_max
last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay:last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_min, last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_mid, last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_max
last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay:last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_min, last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_mid, last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_max
last_WVALID_WREADY_handshake_to_next_WVALID_Delay:last_wvalid_wready_handshake_to_next_wvalid_delay_min, last_wvalid_wready_handshake_to_next_wvalid_delay_mid, last_wvalid_wready_handshake_to_next_wvalid_delay_max
last_WVALID_WREADY_handshake_to_next_WREADY_Delay:last_wvalid_wready_handshake_to_next_wready_delay_min, last_wvalid_wready_handshake_to_next_wready_delay_mid, last_wvalid_wready_handshake_to_next_wready_delay_max
last_WREADY_to_next_WVALID_WREADY_handshake_Delay:last_wready_to_next_wvalid_wready_handshake_delay_min, last_wready_to_next_wvalid_wready_handshake_delay_mid, last_wready_to_next_wvalid_wready_handshake_delay_max
last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay:last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_min, last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_mid, last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_max
last_BVALID_BREADY_handshake_to_next_BVALID_Delay:last_bvalid_bready_handshake_to_next_bvalid_delay_min, last_bvalid_bready_handshake_to_next_bvalid_delay_mid, last_bvalid_bready_handshake_to_next_bvalid_delay_max
last_BVALID_BREADY_handshake_to_next_BREADY_Delay:last_bvalid_bready_handshake_to_next_bready_delay_min, last_bvalid_bready_handshake_to_next_bready_delay_mid, last_bvalid_bready_handshake_to_next_bready_delay_max
last_BVALID_to_next_BVALID_Delay:last_BVALID_to_next_BVALID_delay_min, last_BVALID_to_next_BVALID_delay_mid, last_BVALID_to_next_BVALID_delay_max
last_BREADY_to_next_BREADY_Delay:last_BREADY_to_next_BREADY_delay_min, last_BREADY_to_next_BREADY_delay_mid, last_BREADY_to_next_BREADY_delay_max
last_BREADY_to_next_BVALID_BREADY_handshake_Delay:last_bready_to_next_bvalid_bready_handshake_delay_min, last_bready_to_next_bvalid_bready_handshake_delay_mid, last_bready_to_next_bvalid_bready_handshake_delay_max

Covergroup: trans_axi_write_handshake_delay

This Covergroup captures handshaking between valid and ready signal for diferent delay scenarios for write address and write data channels. It is constructed and sampled when interface type is not AXI_READ_ONLY.

Coverpoints:

last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay:Captures min, mid and max range of delays between last awvalid_awready handshake to the next awvalid_awready handshake
last_AWVALID_AWREADY_handshake_to_next_AWVALID_Delay: Captures min,mid and max range of delays between last awvalid_awready handshake to the next awvalid
last_AWVALID_AWREADY_handshake_to_next_AWREADY_Delay: Captures min,mid and max range of delays between last awvalid_awready handshake to the next awready
last_AWREADY_to_next_AWVALID_AWREADY_handshake_Delay: Captures min,mid and max range of delays between last awready to the next awvalid_awready handshake
last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wvalid_wready handshake
last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay: Captures min, mid and max range of delays between last wvalid_wready data beat handshake to the next wvalid_wready data beat handshake
last_WVALID_WREADY_handshake_to_next_WVALID_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wvalid
last_WVALID_WREADY_handshake_to_next_WREADY_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wready
last_WREADY_to_next_WVALID_WREADY_handshake_Delay: Captures min,mid and max range of delays between last wready to the next wvalid_wready handshake
last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay:Captures min, mid and max range of delays between last bvalid_bready handshake to the next bvalid_bready handshake
last_BVALID_BREADY_handshake_to_next_BVALID_Delay: Captures min, mid and max range of delays between last bvalid_bready handshake to the next bvalid
last_BVALID_BREADY_handshake_to_next_BREADY_Delay: Captures min, mid and max range of delays between last bvalid_bready handshake to the next bready
last_BVALID_to_next_BVALID_Delay: Captures min, mid and max range of delays between last bvalid to the next bvalid
last_BREADY_to_next_BREADY_Delay: Captures min, mid and max range of delays between last bready to the next bready
last_BREADY_to_next_BVALID_BREADY_handshake_Delay: Captures min, mid and max range of delays between last bready to the next bvalid_bready handshake

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_ace_acdvmmessage_acdvmresp

acdvm_message_type:message_tlb_invalidate, message_branch_predictor_invalidate, message_physical_instruction_cache_invalidate, message_virtual_instruction_cache_invalidate, message_synchronization, message_hint
acdvm_resp:message_accept, message_reject

acdvmmessage_acdvmresp

Covergroup: trans_cross_ace_acdvmmessage_acdvmresp

This covergroup captures snoop dvm message and response type. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acdvmmessage_acdvmresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

acdvm_message_type : Captures DVM message on acaddr[14:12]
acdvm_resp : Capture DVM response on crresp, accept = 5'b00000 and reject = 5'b00010

Cross coverpoints:

acdvmmessage_acdvmresp : Crosses coverpoints acdvm_message_type and acdvm_resp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_ace_awsnoop_awaddr

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
addr:addr_range_min, addr_range_mid, addr_range_max

awsnoop_awaddr

Covergroup: trans_cross_ace_awsnoop_awaddr

This Covergroup captures coherant write transaction and address. It is constructed and sampled when trans_cross_ace_awsnoop_awaddr_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
addr : Captures transaction write address

Cross coverpoints:

awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_ace_awsnoop_awburst

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
burst_type:fixed_burst, incr_burst, wrap_burst
slave_port_id:slave_id

awsnoop_awburst

Covergroup: trans_cross_ace_awsnoop_awburst

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_category is not AXI_READ_ONLY and trans_cross_ace_awsnoop_awburst_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_type: Captures transaction burst type

Cross coverpoints:

awsnoop_awburst_ : Crosses cover points coherent_write_xact_type ,burst_type and slave_port_id

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_ace_awsnoop_awlen

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
burst_length:burst_length
slave_port_id:slave_id

awsnoop_awlen

Covergroup : trans_cross_ace_awsnoop_awlen

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_length: Captures transaction burst length

Cross coverpoints:

awsnoop_awlen : Crosses cover points coherent_write_xact_type ,burst_length and slave_port_id

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_ace_awsnoop_awsize

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit
slave_port_id:slave_id

awsnoop_awsize

Covergroup : trans_cross_ace_awsnoop_awsize

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type ,burst_size and slave_port_id

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_awunique_awsnoop_awbar

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
awunique_val:is_not_unique, is_unique
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization

awunique_awsnoop_awbar

Covergroup: trans_cross_awunique_awsnoop_awbar

This Covergroup captures coherant write xact_type,awunique_val,barrier_type and awunique_awsnoop_awbar values for write transaction. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_READ_ONLY and awunique_enable set to 1.

Coverpoints:

coherent_write_xact_type: Captures write transction type. Includes WRITENOSNOOP, WRITEUNIQUE, WRITELINEUNIQUE, WRITECLEAN, WRITEBACK, EVICT, WRITEBARRIER and WRITEEVICT
awunique_val: Captures the value of signal AWUNIQUE in above transactions
barrier_type: Captures the value of barrier type (AWBAR), in above transactions
awunique_awsnoop_awbar: Cross of coherent_write_xact_type, awunique_val and barrier_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_axi3_awburst_awlen

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length

axi3_awburst_awlen

This covergroup captures attributes of write transaction type,burst_type and burst_length for AXI3 interface Covergroup: trans_cross_axi3_awburst_awlen

It is constructed abd sampled when interface type set to AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures ranges of burst_length

Cross coverpoints:

axi3_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_axi3_awburst_awlen_awaddr

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max

axi3_awburst_awlen_awaddr

This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI3.

Covergroup: trans_cross_axi3_awburst_awlen_awaddr

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi3_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_axi3_awburst_awlen_bresp

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp

axi3_awburst_awlen_bresp

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction. It is constructed and sampled when interface type is set to AXI3.

Covergroup: trans_cross_axi3_awburst_awlen_bresp

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response

Cross coverpoints:

axi3_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_axi4_awburst_awlen

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length

axi4_awburst_awlen

This covergroup captures attributes of write transaction type,burst_type and burst_length for AXI4 interface Covergroup: trans_cross_axi4_awburst_awlen

It is constructed abd sampled when interface type set to AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures ranges of burst_length

Cross coverpoints:

axi4_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_axi4_awburst_awlen_awaddr

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max

axi4_awburst_awlen_awaddr

This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI4.

Covergroup: trans_cross_axi4_awburst_awlen_awaddr

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi4_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_axi4_awburst_awlen_bresp

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp

axi4_awburst_awlen_bresp

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction It is constructed and sampled when interface type is set to AXI4.

Covergroup: trans_cross_axi4_awburst_awlen_bresp

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response

Cross coverpoints:

axi4_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_cross_axi_awburst_awqos

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
qos:qos_range_0_1, qos_range_2_3, qos_range_4_7, qos_range_8_15

axi_awburst_awqos

This covergroup captures attributes of burst_type and qos for AXI transaction at subordinate. Covergroup: trans_cross_axi_awburst_awqos

It is constructed when interface type can be AXI4, AXI-ACE or ACE-LITE. It is sampled when transaction type is set to WRITE OR READ_WRITE

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
qos: Captures ranges of QOS values

Cross coverpoints:

axi_awburst_awqos: Crosses cover points write_xact_type, burst_type and qos

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_master_ace_write_during_speculative_fetch

ace_write_during_speculative_fetch

ace_write_during_speculative_fetch:overlapping_write_during_readonce, overlapping_write_during_readclean, overlapping_write_during_readnotshareddirty, overlapping_write_during_readunique, overlapping_write_during_readshared

Covergroup: trans_master_ace_write_during_speculative_fetch

It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_write_during_speculative_fetch_enable set to 1.

Coverpoints:

ace_write_during_speculative_fetch: This cover point covers the following condition: A master issues a read transaction. This results in interconnect generating snoop transactions towards other masters within the domain. The interconnect also generates speculative read transaction for this location. Speculative transaction returns data while the snoop transactions do not return data. The snoop transactions may not return data, either because there is no entry in the snooped masters' caches or a WRITEBACK/WRITECLEAN of dirty data is in progress. The interconnect now detects that a write transaction (the WRITEBACK/WRITECLEAN which is in progress) is received for the same address for which it did a speculative fetch. In such situation, interconnect performs another read from main memory, as originally received data from speculative read is now stale
At least One ACE master needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_master_ace_xacts_with_high_priority_from_other_master_during_barrier

ace_xacts_with_high_priority_from_other_master_during_barrier

ace_xacts_with_high_priority_from_other_master_during_barrier:xacts_from_other_master_during_barrier

Covergroup: trans_master_ace_xacts_with_high_priority_from_other_master_during_barrier

It is constructed and sampled when system_ace_xacts_with_high_priority_from_other_master_during_barrier_enable ,barrier_enable and system_monitor_enable set to 1.

Coverpoints:

ace_xacts_with_high_priority_from_other_master_during_barrier: This cover point covers the following condition: When the interconnect receives barrier from a master, then all other transactions launched by other masters in that domain may be stalled. This cover point covers condition where master issues transactions with non-zero QOS value. Then another master issues a barrier transaction within the same domain.
Two or more ACE/ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_XACT_FLOW

trans_meta_axi_write

AWVALID_to_AWREADY_Delay:awvalid_to_awready_delay_min, awvalid_to_awready_delay_mid, awvalid_to_awready_delay_max
WVALID_to_WREADY_Delay:wvalid_to_wready_delay_min, wvalid_to_wready_delay_mid, wvalid_to_wready_delay_max
BVALID_to_BREADY_Delay:bvalid_to_bready_delay_min, bvalid_to_bready_delay_mid, bvalid_to_bready_delay_max
AWVALID_to_prev_AWVALID_Delay:awvalid_to_prev_awvalid_delay_min, awvalid_to_prev_awvalid_delay_mid, awvalid_to_prev_awvalid_delay_max
WVALID_to_prev_WVALID_Delay:wvalid_to_prev_wvalid_delay_min, wvalid_to_prev_wvalid_delay_mid, wvalid_to_prev_wvalid_delay_max
AWVALID_to_first_WVALID_Delay:awvalid_to_first_wvalid_delay_min, awvalid_to_first_wvalid_delay_mid, awvalid_to_first_wvalid_delay_max
last_wdata_handshake_to_BVALID_Delay:last_wdata_handshake_to_bvalid_delay_min, last_wdata_handshake_to_bvalid_delay_mid, last_wdata_handshake_to_bvalid_delay_max
AWVALID_before_AWREADY:awvalid_before_awready
AWREADY_before_AWVALID:awready_before_awvalid
BVALID_before_BREADY:bvalid_before_bready
BREADY_before_BVALID:bready_before_bvalid
WVALID_before_WREADY:wvalid_before_wready
WREADY_before_WVALID:wready_before_wvalid
AWVALID_before_WREADY:awvalid_before_wready
WREADY_before_AWVALID:wready_before_awvalid
AWREADY_before_WVALID:awready_before_wvalid
WVALID_before_AWREADY:wvalid_before_awready
AWVALID_before_WVALID:awvalid_before_wvalid
WVALID_before_AWVALID:wvalid_before_awvalid

Covergroup: trans_meta_axi_write

This Covergroup captures delay and predelay scenarios for handshake between valid and ready signal for write address, write data,write response channels It is constructed sampled when interface type is not AXI_READ_ONLY & trans_meta_axi_write_enable is asserted.

Coverpoints:

AWVALID_to_AWREADY_Delay: Captures min, mid and max range of delays between signals awvalid and awready
WVALID_to_WREADY_Delay: Captures min, mid and max range of delays between signals wvalid and wready
BVALID_to_BWREADY_Delay: Captures min, mid and max range of delays between signals bvalid and bready
AWVALID_to_prev_AWVALID_Delay: Captures min, mid and max range of delays between current and previous awvalid signals
WVALID_to_prev_WVALID_Delay: Captures min, mid and max range of delays between current and previous wvalid signals
AWVALID_to_first_WVALID_Delay: Captures min, mid and max range of delays between awvalid and first wvalid signals
last_wdata_handshake_to_BVALID_Delay: Captures min, mid and max range of delays between last write data handshake to bvalid signals
AWVALID_before_AWREADY: Captures if AWVALID signal comes before AWREADY signal
AWREADY_before_AWVALID: Captures if AWREADY signal comes before AWVALID signal
BVALID_before_BREADY: Captures if BVALID signal comes before BREADY signal
BREADY_before_BVALID: Captures if BREADY signal comes before BVALID signal
WVALID_before_WREADY: Captures if WVALID signal comes before WREADY signal
WREADY_before_WVALID: Captures if WREADY signal comes before WVALID signal or WREADY,WVALID signals are comes at same time
AWVALID_before_WREADY: Captures if AWVALID signal comes before WREADY signal
WREADY_before_AWVALID: Captures if WREADY signal comes before AWVALID signal
AWREADY_before_WVALID: Captures if AWREADY signal comes before WVALID signal
WVALID_before_AWREADY: Captures if WVALID signal comes before AWREADY signal
AWVALID_before_WVALID: Captures if AWVALID signal comes before WVALID signal
WVALID_before_AWVALID: Captures if WVALID signal comes before AWVALID signal

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_axi_read_handshake_delay

last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay:last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_min, last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_mid, last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_max
last_ARVALID_ARREADY_handshake_to_next_ARVALID_Delay:last_arvalid_arready_handshake_to_next_arvalid_delay_min, last_arvalid_arready_handshake_to_next_arvalid_delay_mid, last_arvalid_arready_handshake_to_next_arvalid_delay_max
last_ARVALID_ARREADY_handshake_to_next_ARREADY_Delay:last_arvalid_arready_handshake_to_next_arready_delay_min, last_arvalid_arready_handshake_to_next_arready_delay_mid, last_arvalid_arready_handshake_to_next_arready_delay_max
last_ARREADY_to_next_ARVALID_ARREADY_handshake_Delay:last_arready_to_next_arvalid_arready_handshake_delay_min, last_arready_to_next_arvalid_arready_handshake_delay_mid, last_arready_to_next_arvalid_arready_handshake_delay_max
last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay:last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_min, last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_mid, last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_max
last_RVALID_RREADY_handshake_to_next_RVALID_Delay:last_rvalid_rready_handshake_to_next_rvalid_delay_min, last_rvalid_rready_handshake_to_next_rvalid_delay_mid, last_rvalid_rready_handshake_to_next_rvalid_delay_max
last_RVALID_RREADY_handshake_to_next_RREADY_Delay:last_rvalid_rready_handshake_to_next_rready_delay_min, last_rvalid_rready_handshake_to_next_rready_delay_mid, last_rvalid_rready_handshake_to_next_rready_delay_max
last_RREADY_to_next_RVALID_RREADY_handshake_Delay:last_rready_to_next_rvalid_rready_handshake_delay_min, last_rready_to_next_rvalid_rready_handshake_delay_mid, last_rready_to_next_rvalid_rready_handshake_delay_max
last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay:last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_min, last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_mid, last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_max

Covergroup: trans_axi_read_handshake_delay

This Covergroup captures handshaking between valid and ready signal for diferent delay scenarios for read address and read data channels. It is constructed and sampled when interface type is not AXI_WRITE_ONLY.

Coverpoints:

last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay:Captures min, mid and max range of delays between last arvalid_arready handshake to the next arvalid_arready handshake
last_ARVALID_ARREADY_handshake_to_next_ARVALID_Delay: Captures min,mid and max range of delays between last arvalid_arready handshake to the next arvalid
last_ARVALID_ARREADY_handshake_to_next_ARREADY_Delay: Captures min,mid and max range of delays between last arvalid_arready handshake to the next arready
last_ARREADY_to_next_ARVALID_ARREADY_handshake_Delay: Captures min,mid and max range of delays between last arready to the next arvalid_arready handshake
last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay:Captures min, mid and max range of delays between last rvalid_rready handshake to the next rvalid_rready handshake
last_RVALID_RREADY_handshake_to_next_RVALID_Delay: Captures min,mid and max range of delays between last rvalid_rready handshake to the next rvalid
last_RVALID_RREADY_handshake_to_next_RREADY_Delay: Captures min,mid and max range of delays between last rvalid_rready handshake to the next rready
last_RREADY_to_next_RVALID_RREADY_handshake_Delay: Captures min,mid and max range of delays between last rready to the next rvalid_rready handshake
last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay: Captures min, mid and max range of delays between last rvalid_rready data beat handshake to the next rvalid_rready data beat handshake

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_araddr

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
addr:addr_range_min, addr_range_mid, addr_range_max

arsnoop_araddr

Covergroup: trans_cross_ace_arsnoop_araddr

This Covergroup captures coherant read xact_type and address ranges for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_araddr_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
addr : Captures transaction read address

Cross coverpoints:

arsnoop_araddr : Crosses cover points coherent_read_xact_type and addr

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_arbar

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization

arsnoop_arbar

Covergroup: trans_cross_ace_arsnoop_arbar

This Covergroup captures coherant read xact_type and barrier_type for read transaction. It is constructed and sampled when when trans_cross_ace_arsnoop_arbar_enable and barrier_type set to 1 .

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
barrier_type : Captures read barrier

Cross coverpoints:

arsnoop_arbar : Crosses cover points coherent_read_xact_type and barrier_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_arburst

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
burst_type:fixed_burst, incr_burst, wrap_burst
slave_port_id:slave_id

arsnoop_arburst

Covergroup: trans_cross_ace_arsnoop_arburst

This Covergroup captures coherant read xact_type,burst_type and slave_port_id for read transaction. It is constructed and sampled when interface_type is not AXI_WRITE_ONLY & trans_cross_ace_arsnoop_arburst_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_type: Captures transaction burst type

Cross coverpoints:

arsnoop_arburst : Crosses cover points coherent_read_xact_type and burst_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_arcache

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable, write_through_no_allocate, write_through_read_allocate, write_through_write_allocate, write_through_read_and_write_allocate, write_back_no_allocate, write_back_read_allocate, write_back_write_allocate, write_back_read_and_write_allocate
slave_port_id:slave_id

arsnoop_arcache

Covergroup: trans_cross_ace_arsnoop_arcache

This Covergroup captures coherant read xact_type,cache signal and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_arcache_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
cache_type : Captures transaction cache type

Cross coverpoints:

arsnoop_arcache : Crosses cover points coherent_read_xact_type and cache_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_ardomain

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable
slave_port_id:slave_id

arsnoop_ardomain

Covergroup: trans_cross_ace_arsnoop_ardomain

This Covergroup captures coherant read xact_type,domain_type and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_ardomain_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures transaction cache type

Cross coverpoints:

arsnoop_ardomain : Crosses cover points coherent_read_xact_type and cache_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_ardomain_arcache

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable
cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable, write_through_no_allocate, write_through_read_allocate, write_through_write_allocate, write_through_read_and_write_allocate, write_back_no_allocate, write_back_read_allocate, write_back_write_allocate, write_back_read_and_write_allocate

arsnoop_ardomain_arcache

Covergroup: trans_cross_ace_arsnoop_ardomain_arcache

This Covergroup captures coherant read xact_type,domain_type and cache signal for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_ardomain_arcache_enable set to 1. Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures domain type
cache_type : Captures cache_type

Cross coverpoints:

arsnoop_ardomain_arcache : Crosses cover points coherent_read_xact_type and domain_type and cache_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_arlen

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
burst_length:burst_length
slave_port_id:slave_id

arsnoop_arlen

Covergroup: trans_cross_ace_arsnoop_arlen

This Covergroup captures coherant read xact_type,burst_length and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_arlen_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_length: Captures transaction burst length

Cross coverpoints:

arsnoop_arlen : Crosses cover points coherent_read_xact_type and burst_length

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_ace_arsnoop_arsize

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit
slave_port_id:slave_id

arsnoop_arsize

Covergroup: trans_cross_ace_arsnoop_arsize

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi3_arburst_arlen

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length

axi3_arburst_arlen

Covergroup: trans_cross_axi3_arburst_arlen

This covergroup captures attributes of burst_type & burst_length for read transaction. It is constructed and sampled when interface type is AXI3 & trans_cross_axi3_arburst_arlen is asserted Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi3_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi3_arburst_arlen_araddr

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max

axi3_arburst_arlen_araddr

Covergroup: trans_cross_axi3_arburst_arlen_araddr

This covergroup captures attributes of burst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi3_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi3_arburst_arlen_araddr_arsize

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi3_arburst_arlen_araddr_arsize

Covergroup: trans_cross_axi3_arburst_arlen_araddr_arsize

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for read transaction. It is constructed and sampled when interface_type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi3_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi3_arburst_arlen_arlock

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
atomic_type:normal, exclusive, locked

axi3_arburst_arlen_arlock

Covergroup: trans_cross_axi3_arburst_arlen_arlock

This covergroup captures attributes of burst_type,burst_length and atomic_type for read locked transaction. It is constructed and sampled when interface_type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi3_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi3_arburst_arlen_arprot

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

axi3_arburst_arlen_arprot

Covergroup: trans_cross_axi3_arburst_arlen_arprot

This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi3_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi3_arburst_arlen_arsize

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi3_arburst_arlen_arsize

Covergroup: trans_cross_axi3_arburst_arlen_arsize

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface_type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi3_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi3_arburst_arlen_rresp

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
rresp:okay_resp, exokay_resp, slverr_resp, decerr_resp

axi3_arburst_arlen_rresp

Covergroup: trans_cross_axi3_arburst_arlen_rresp

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI3. Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi3_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi4_arburst_arlen

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length

axi4_arburst_arlen

Covergroup: trans_cross_axi4_arburst_arlen

This covergroup captures attributes of burst_type & burst_length for read transaction It is constructed and sampled when interface type is set to AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi4_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi4_arburst_arlen_araddr

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max

axi4_arburst_arlen_araddr

Covergroup: trans_cross_axi4_arburst_arlen_araddr

This covergroup captures attributes of burst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi4_arburst_arlen_araddr: Crosses cover points read_xact_type, burst_type, burst_length, addr

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi4_arburst_arlen_araddr_arsize

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi4_arburst_arlen_araddr_arsize

Covergroup: trans_cross_axi4_arburst_arlen_araddr_arsize

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for read transaction. It is constructed and sampled when interface_type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi4_arburst_arlen_arlock

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
atomic_type:normal, exclusive, locked

axi4_arburst_arlen_arlock

Covergroup: trans_cross_axi4_arburst_arlen_arlock

This covergroup captures attributes of burst_type,burst_length and atomic_type for read locked transaction. It is constructed and sampled when interface_type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi4_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi4_arburst_arlen_arprot

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

axi4_arburst_arlen_arprot

Covergroup: trans_cross_axi4_arburst_arlen_arprot

This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi4_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi4_arburst_arlen_arsize

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi4_arburst_arlen_arsize

Covergroup: trans_cross_axi4_arburst_arlen_arsize

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface_type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi4_arburst_arlen_rresp

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
rresp:okay_resp, exokay_resp, slverr_resp, decerr_resp

axi4_arburst_arlen_rresp

Covergroup: trans_cross_axi4_arburst_arlen_rresp

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi_arburst_arlen_arcache

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
cache_type:non_cacheable_non_bufferable, bufferable_or_modifiable_only, cacheable_but_no_alloc, cacheable_bufferable_but_no_alloc, cacheable_write_through_allocate_on_read_only, cacheable_write_back_allocate_on_read_only, cacheable_write_through_allocate_on_write_only, cacheable_write_back_allocate_on_write_only, cacheable_write_through_allocate_on_both_read_write, cacheable_write_back_allocate_on_both_read_write

axi_arburst_arlen_arcache

Covergroup: trans_cross_axi_arburst_arlen_arcache

This covergroup captures attributes of burst_type,burst_length and cache_type for read transaction. It is constructed and sampled when trans_cross_axi_arburst_arlen_arcache_enable is asserted .

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_arburst_arlen_arcache: Crosses cover points read_xact_type, burst_type, burst_length, cache_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_cross_axi_arburst_arqos

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
qos:qos_range_0_1, qos_range_2_3, qos_range_4_7, qos_range_8_15

axi_arburst_arqos

This covergroup captures attributes of burst_type and qos for AXI transaction at subordinate. Covergroup: trans_cross_axi_arburst_arqos

It is constructed when interface type can be AXI4. It is sampled when transaction type is set to WRITE OR READ_WRITE

Coverpoints:

read_xact_type: Captures write transaction
burst_type: Captures transaction burst type
qos: Captures ranges of QOS values

Cross coverpoints:

axi_awburst_awqos: Crosses cover points write_xact_type, burst_type and qos

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_XACT_FLOW

trans_meta_axi_read

ARVALID_to_ARREADY_Delay:arvalid_to_arready_delay_min, arvalid_to_arready_delay_mid, arvalid_to_arready_delay_max
RVALID_to_RREADY_Delay:rvalid_to_rready_delay_min, rvalid_to_rready_delay_mid, rvalid_to_rready_delay_max
ARVALID_to_prev_ARVALID_Delay:arvalid_to_prev_arvalid_delay_min, arvalid_to_prev_arvalid_delay_mid, arvalid_to_prev_arvalid_delay_max
RVALID_to_prev_RVALID_Delay:rvalid_to_prev_rvalid_delay_min, rvalid_to_prev_rvalid_delay_mid, rvalid_to_prev_rvalid_delay_max
ARVALID_to_first_RVALID_Delay:arvalid_to_first_rvalid_delay_min, arvalid_to_first_rvalid_delay_mid, arvalid_to_first_rvalid_delay_max
ARVALID_before_ARREADY:arvalid_before_arready
ARREADY_before_ARVALID:arready_before_arvalid
RVALID_before_RREADY:rvalid_before_rready
RREADY_before_RVALID:rready_before_rvalid

Covergroup: trans_meta_axi_read

This Covergroup captures delay and predelay scenarios for handshake between valid and ready signal for read address, and read data channels. It is constructed and sampled when interface type is not AXI_WRITE_ONLY & trans_meta_axi_read_enable is asserted.

Coverpoints:

ARVALID_to_ARREADY_Delay: Captures min, mid and max range of delays between signals arvalid and arready
RVALID_to_RREADY_Delay: Captures min, mid and max range of delays between signals rvalid and rready
ARVALID_to_prev_ARVALID_Delay: Captures min, mid and max range of delays between current and previous arvalid signals
RVALID_to_prev_RVALID_Delay: Captures min, mid and max range of delays between current and previous rvalid signals
ARVALID_to_first_RVALID_Delay: Captures min, mid and max range of delays between arvalid and first rvalid signals
ARVALID_before_ARREADY: Captures if ARVALID signal comes before ARREADY signal
ARREADY_before_ARVALID: Captures if ARREADY signal comes before ARVALID signal
RVALID_before_RREADY: Captures if RVALID signal comes before RREADY signal
RREADY_before_RVALID: Captures if RREADY signal comes before RVALID signal

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_ace_barrier_outstanding_xact

barrier_outstanding_xact

barrier_outstanding_xact:barrier_outstanding_xact_range_low, barrier_outstanding_xact_range_med, barrier_outstanding_xact_range_max

Covergroup: trans_ace_barrier_outstanding_xact

This Covergroup captures barrier outstanding transaction. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_ace_barrier_outstanding_xact_enable & barrier enable set to 1.

Coverpoints:

barrier_outstanding_xact : Captures total number of read and write barrier outstanding transactions. When svt_axi_port_configuration :: axi_interface_type is configured as AXI_ACE maximum number of 256 outstanding transactions is tracked. When svt_axi_port_configuration :: axi_interface_type is configured as ACE_LITE, outstanding transactions greater than 256 are also tracked. This is as per section C8.4.1 of AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613"

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid:num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid

Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid

Coverpoints:

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid: The number of bins will be equal to the programmed value of User-defined macron SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. If user does not override this macro then this covergroup will create 256 bins for ARID width greater than 8.
Example: If outstanding DVM TLBI transactions have the following IDs: ARID1 ARID1 ARID2 ARID3 ARID4 ARID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with ARID1,ARID2 ARID3 ARID4 ARID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique ARID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique ARID values further bins will keep getting hit.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range:num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_0, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_1, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_2, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_3, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_4, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_5, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_6, num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_7

Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range

Coverpoints:

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range: This will construct eight different bins to cover all the possible ranges of arid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is
Example: If id_wdith is 7 then num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range can be 0 to 127 and that will be cover under defined 8 bins as follows.
num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_0 [0 : 15] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_1 [16 : 31] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_2 [32 : 47] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_3 [48 : 63] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_4 [64 : 79] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_5 [80 : 95] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_6 [96 : 111] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_7 [112 : 127]

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid

num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid

num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid:num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid

Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid

This covergroup captures the number of outstanding transactions with DVM TLBI requests with a matching ARID. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid_enable = 1 Configured value of svt_axi_port_configuration :: cov_bins_dvm_tlbi_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_read_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.

Coverpoints:

num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid: The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_dvm_tlbi_num_outstanding_xacts and the default value of which is 64.
Example: If outstanding DVM TLBI transactions have the following IDs: ARID1 ARID1 ARID3 ARID1 ARID3 ARID2 and svt_axi_port_configuration :: cov_same_id_in_dvm_tlbi_outstanding_xacts is programmed to ARID1. The bins hit will be 1,2 and 3 as there are 3 outstanding DVM TLBI transactions matching with ARID1.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_ace_num_outstanding_snoop_xacts

num_outstanding_snoop_xacts

num_outstanding_snoop_xacts:num_outstanding_snoop_xacts

Covergroup: trans_ace_num_outstanding_snoop_xacts

It is constructed and sampled when interface_type is AXI_ACE and trans_ace_num_outstanding_snoop_xacts_enable set to 1.

Coverpoints:

num_outstanding_snoop_xacts: Captures the number of outstanding snoop transactions.The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_snoop_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_snoop_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_snoop_xact which indicates the number of outstanding snoop transactions VIP can support.
Applicable only for master and when svt_axi_port_configuration :: axi_interface_type is ACE.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_diff_arid

read_outstanding_xacts_with_diff_arid

read_outstanding_xacts_with_diff_arid:read_outstanding_xacts_with_diff_arid

Covergroup: trans_axi_num_outstanding_xacts_with_diff_arid

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_arid_enable & id_width set to 1 and cov_num_outstanding_xacts_range_enable set to 0.

Coverpoints:

read_outstanding_xacts_with_diff_arid: Captures the number of outstanding read transactions with different ARID value. The number of bins will be equal to the programmed value of User-defined macro SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. So, if user does not override this macro then this covergroup will create 256 bins for ARID width greater than 8
If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example: If outstanding transactions have the following IDs: ARID1 ARID1 ARID2 ARID3 ARID4 ARID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with ARID1,ARID2 ARID3 ARID4 ARID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique ARID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique ARID values further bins will keep getting hit.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_diff_arid_range

read_outstanding_xacts_with_diff_arid_range

read_outstanding_xacts_with_diff_arid_range:read_outstanding_xacts_with_diff_arid_range_0, read_outstanding_xacts_with_diff_arid_range_1, read_outstanding_xacts_with_diff_arid_range_2, read_outstanding_xacts_with_diff_arid_range_3, read_outstanding_xacts_with_diff_arid_range_4, read_outstanding_xacts_with_diff_arid_range_5, read_outstanding_xacts_with_diff_arid_range_6, read_outstanding_xacts_with_diff_arid_range_7

Covergroup: trans_axi_num_outstanding_xacts_with_diff_arid_range

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_arid_range_enable & cov_num_outstanding_xacts_range_enable set to 1 and read_chan_id_width >=3.

Coverpoints:

read_outstanding_xacts_with_diff_arid_range: This cover group captures the range of arid values of outstanding read transactions. This covergroup will construct eight different bins to cover all the possible ranges of arid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example: If id_wdith is 7 then read_outstanding_xacts_with_diff_arid_range can be 0 to 127 and that will be cover under defined 8 bins as follows.
read_outstanding_xacts_with_diff_arid_range_0 [0 : 15] read_outstanding_xacts_with_diff_arid_range_1 [16 : 31] read_outstanding_xacts_with_diff_arid_range_2 [32 : 47] read_outstanding_xacts_with_diff_arid_range_3 [48 : 63] read_outstanding_xacts_with_diff_arid_range_4 [64 : 79] read_outstanding_xacts_with_diff_arid_range_5 [80 : 95] read_outstanding_xacts_with_diff_arid_range_6 [96 : 111] read_outstanding_xacts_with_diff_arid_range_7 [112 : 127]

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_diff_awid

write_outstanding_xacts_with_diff_awid

write_outstanding_xacts_with_diff_awid:write_outstanding_xacts_with_diff_awid

Covergroup: trans_axi_num_outstanding_xacts_with_diff_awid

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_awid_enable & cov_num_outstanding_xacts_range_enable set to 1 ,num_outstanding_xacts is not -1 and id_width is not 0.

Coverpoints:

write_outstanding_xacts_with_diff_awid: Captures the number of outstanding write transactions with different AWID. The number of bins will be equal to the programmed value of User-defined macro SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. So, if user does not override this macro then this covergroup will create 256 bins for AWID width greater than 8
If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: write_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example:
If outstanding transactions have the following IDs: AWID1 AWID1 AWID2 AWID3 AWID4 AWID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with AWID1,AWID2 AWID3 AWID4 AWID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique AWID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique AWID values further bins will keep getting hit.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_diff_awid_range

write_outstanding_xacts_with_diff_awid_range

write_outstanding_xacts_with_diff_awid_range:write_outstanding_xacts_with_diff_awid_range_0, write_outstanding_xacts_with_diff_awid_range_1, write_outstanding_xacts_with_diff_awid_range_2, write_outstanding_xacts_with_diff_awid_range_3, write_outstanding_xacts_with_diff_awid_range_4, write_outstanding_xacts_with_diff_awid_range_5, write_outstanding_xacts_with_diff_awid_range_6, write_outstanding_xacts_with_diff_awid_range_7

Covergroup: trans_axi_num_outstanding_xacts_with_diff_awid_range

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_awid_range_enable & cov_num_outstanding_xacts_range_enable set to 1 ,num_outstanding_xacts is not -1 and write_chan_id_width >= 3.

Coverpoints:

write_outstanding_xacts_with_diff_awid_range: This cover group captures the range of awid values of outstanding write transactions. This covergroup will construct eight different bins to cover all the possible ranges of awid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example: If id_wdith is 7 then write_outstanding_xacts_with_diff_awid_range can be 0 to 127 and that will be cover under defined 8 bins as follows.
write_outstanding_xacts_with_diff_awid_range_0 [0 : 15] write_outstanding_xacts_with_diff_awid_range_1 [16 : 31] write_outstanding_xacts_with_diff_awid_range_2 [32 : 47] write_outstanding_xacts_with_diff_awid_range_3 [48 : 63] write_outstanding_xacts_with_diff_awid_range_4 [64 : 79] write_outstanding_xacts_with_diff_awid_range_5 [80 : 95] write_outstanding_xacts_with_diff_awid_range_6 [96 : 111] write_outstanding_xacts_with_diff_awid_range_7 [112 : 127]

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_multiple_same_arid

read_outstanding_same_id:read_same_arid
num_outstanding_read:read_outstanding_xacts

cross_same_id_with_num_outstanding_xacts

Covergroup: trans_axi_num_outstanding_xacts_with_multiple_same_arid

This covergroup captures the number of outstanding read transactions with same ARID values which is in progress, if master is programmed with multiple same ids. For Example : If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], then the master will have three different ids ARID1, ARID2 and ARID3.This covergroup will cross all the 3 ids with svt_axi_port_configuration :: num_outstanding_xact. If number of outstanding transactions are 50 with ARID1,then bins read_same_arid_1, read_outstanding_xacts_with_same_arid_1 to read_outstanding_xacts_with_same_arid_50 will get hit. It is constructed and sampled when interface_category is not AXI_WRITE_ONLY and num_outstanding_xact is not -1 & trans_axi_num_outstanding_xacts_with_multiple_same_arid_enable set to 1.

Coverpoints:

read_outstanding_same_id: Captures the same id values programmed in svt_axi_port_configuration :: cov_multi_same_ids
num_outstanding_read : Captures number of outstanding read transactions with a matching ARID values to the one programmed in svt_axi_port_configuration :: cov_multi_same_ids.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], cov_multi_same_ids[0] = ARID1, cov_multi_same_ids[1] = ARID2, cov_multi_same_ids[1] = ARID3 and outstanding transactions have the following IDs: ARID1 ARID2 ARID1 ARID4 ARID3 ARID1 ARID3 ARID5 ARID2. The bins of read_outstanding_same_id hit will be read_same_arid_1,read_same_arid_2 and read_same_arid_3, bins of cross_same_id_with_num_outstanding_xacts hit will be read_same_arid_1 with read_outstanding_xacts_3,read_same_arid_2 with read_outstanding_xacts_2, read_same_arid_3 with read_outstanding_xacts_1 as there are 3 outstanding transactions matching with ARID1, 2 outstanding transactions with ARID2 and 1 outstanding transaction with ARID3.

Cross Coverpoints :

cross_same_id_with_num_outstanding_xacts: Crosses coverpoints read_outstanding_same_id and num_outstanding_read

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_multiple_same_awid

write_outstanding_same_id:write_same_awid
num_outstanding_write:write_outstanding_xacts

cross_same_id_with_num_outstanding_xacts

Covergroup: trans_axi_num_outstanding_xacts_with_multiple_same_awid

This covergroup captures the number of outstanding write transactions with same AWID values which is in progress, if master is programmed with multiple same ids. For Example : If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], then the master will have three different ids AWID1, AWID2 and AWID3.This covergroup will cross all the 3 ids with svt_axi_port_configuration :: num_outstanding_xact. If number of outstanding transactions are 50 with AWID1,then bins write_same_awid_1, write_outstanding_xacts_with_same_awid_1 to write_outstanding_xacts_with_same_awid_50 will get hit. It is constructed and sampled when trans_axi_num_outstanding_xacts_with_multiple_same_awid_enable set to 1 & num_outstanding_xacts is not -1.

Coverpoints:

write_outstanding_same_id: Captures the same id values programmed in svt_axi_port_configuration :: cov_multi_same_ids
num_outstanding_write : Captures number of outstanding write transactions with a matching AWID values to the one programmed in svt_axi_port_configuration :: cov_multi_same_ids.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], cov_multi_same_ids[0] = AWID1, cov_multi_same_ids[1] = AWID2, cov_multi_same_ids[1] = AWID3 and outstanding transactions have the following IDs: AWID1 AWID2 AWID1 AWID4 AWID3 AWID1 AWID3 AWID5 AWID2. The bins of write_outstanding_same_id hit will be write_same_awid_1,write_same_awid_2 and write_same_awid_3, bins of cross_same_id_with_num_outstanding_xacts hit will be write_same_awid_1 with write_outstanding_xacts_3,write_same_awid_2 with write_outstanding_xacts_2, write_same_awid_3 with write_outstanding_xacts_1 as there are 3 outstanding transactions matching with AWID1, 2 outstanding transactions with AWID2 and 1 outstanding transaction with AWID3.

Cross Coverpoints :

cross_same_id_with_num_outstanding_xacts: Crosses Coverpoints write_outstanding_same_id, num_outstanding_write .

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_same_arid

read_outstanding_xacts_with_same_arid

read_outstanding_xacts_with_same_arid:read_outstanding_xacts_with_same_arid

Covergroup: trans_axi_num_outstanding_xacts_with_same_arid

It is constructed and sampled when interface_ category is not AXI_WRITE_ONLY and trans_axi_num_outstanding_xacts_with_same_arid_enable set to 1 & num_outstanding_xact is not -1.

Coverpoints:

read_outstanding_xacts_with_same_arid: Captures the number of outstanding read transactions with a matching ARID value to the one programmed in svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If outstanding transactions have the following IDs: ARID1 ARID1 ARID3 ARID1 ARID3 ARID2 and svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts is programmed to ARID1. The bins hit will be 1,2 and 3 as there are 3 outstanding transactions matching with ARID1.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_axi_num_outstanding_xacts_with_same_awid

write_outstanding_xacts_with_same_awid

write_outstanding_xacts_with_same_awid:write_outstanding_xacts_with_same_awid

Covergroup: trans_axi_num_outstanding_xacts_with_same_awid

It is constructed and sampled when interface_category is not AXI_READ_ONLY and trans_axi_num_outstanding_xacts_with_same_awid_enable set to 1 & num_outstanding_xacts is not -1.

Coverpoints:

write_outstanding_xacts_with_same_awid: Captures the number of outstanding write transactions with a matching AWID value to the one programmed in svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If outstanding transactions have the following IDs: AWID1 AWID1 AWID3 AWID1 AWID3 AWID2 and svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts is programmed to AWID1. The bins hit will be 1, 2 and 3 as there are 3 outstanding transactions matching with AWID1.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_cross_axi_outstanding_xact

total_outstanding_xact:total_outstanding_xact
outstanding_write_xact:write_outstanding_xact
outstanding_read_xact:read_outstanding_xact

This covergroup captures attributes for total outstanding xact , outstanding write xact and outstanding read xact. It is constructed when trans_cross_axi_outstanding_xact_enable is set to 1.

Covergroup: trans_cross_axi_outstanding_xact

Coverpoints:

total_outstanding_xact : Captures total number of outstanding(read/write) transactions
outstanding_write_xact : Captures number of outstanding write transactions
outstanding_read_xact : Captures number of outstanding read transactions

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_master_ace_barrier_response_with_outstanding_xacts

ace_completed_barrier_type

ace_completed_barrier_type:outstanding_xacts_during_memory_barrier, outstanding_xacts_during_sync_barrier

Covergroup: trans_master_ace_barrier_response_with_outstanding_xacts

It is constructed and sampled when system_ace_barrier_response_with_outstanding_xacts_enable ,barrier_enable and system_monitor_enable set to 1.

system_ace_barrier_response_with_outstanding_xacts_enable Coverpoints:

ace_completed_barrier_type: This is covered when there are outstanding transactions in the queue of a master when the response to a barrier is received. There are multiple ways in which an interconnect can handle barriers. Some interconnects may send response to a barrier only after all outstanding transactions are complete. Others may forward the barrier downstream and wait for the response of the downstream barrier before responding to the original barrier. In such a case there could be outstanding transactions in the queue of the master when a barrier response is received. This coverpoint covers the latter behaviour.
One or more ACE/ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.3

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_master_num_outstanding_dvm_syncs

num_outstanding_dvm_sync_xacts

num_outstanding_dvm_sync_xacts:outstanding_dvm_syncs_less_than_256, outstanding_dvm_syncs_equals_256

Covergroup: trans_master_num_outstanding_dvm_syncs

This covergroup captures outstanding dvm based snoop transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

num_outstanding_dvm_sync_xacts: Captures number of outstanding dvm sync snoop transactions. Note that a master is allowed to send only one outstanding DVM sync transaction (ie, a DVM sync transaction to which a DVM complete is not yet received). Therefore a maximum of 256 outstanding DVM sync snoop transactions is possible only in a system with atleast 257 masters capable of sending DVM transactions.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C12.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_non_barrier_xact_after_256_outstanding_barrier_xact

non_barrier_after_256_outstanding_barrier_xact

non_barrier_after_256_outstanding_barrier_xact:write_xact_after_256_outstanding_barrier_xact

Covergroup: trans_non_barrier_xact_after_256_outstanding_barrier_xact

This Covergroup captures barrier outstanding transaction. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_non_barrier_xact_after_256_outstanding_barrier_xact_enable & barrier enable set to 1.

Coverpoints:

non_barrier_after_256_outstanding_barrier_xact: Captures if active transactions on write channel occur after 256 barrier outstanding transactions are accepted by slave component

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_outstanding_read_with_same_id_to_different_slaves

axi_outstanding_read_with_same_id_to_different_slaves

axi_outstanding_read_with_same_id_to_different_slaves:outstanding_with_same_id_to_different_slaves

Covergroup: trans_outstanding_read_with_same_id_to_different_slaves

This Covergroup captures outstanding read request having same id for different slaves. This covergroup is constructed for all master interface types except AXI4_STREAM and only if the number of slaves in the system (svt_axi_system_configuration :: num_slaves) is greater than 1 and trans_outstanding_read_with_same_id_to_different_slaves_enable set to 1.

Coverpoints:

axi_outstanding_read_with_same_id_to_different_slaves: This is covered when:
- A master issues two outstanding read transactions with the same ID
- These read transactions are targeted to two different slaves

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_OUTSTANDING_XACT_FLOW

trans_outstanding_write_with_same_id_to_different_slaves

axi_outstanding_write_with_same_id_to_different_slaves

axi_outstanding_write_with_same_id_to_different_slaves:outstanding_with_same_id_to_different_slaves

Covergroup: trans_outstanding_write_with_same_id_to_different_slaves

This Covergroup captures outstanding write request having same id for different slaves. This covergroup is constructed for all master interface types and only if the number of slaves in the system (svt_axi_system_configuration :: num_slaves) is greater than 1 and trans_outstanding_read_with_same_id_to_different_slaves_enable set to 1.

Coverpoints:

axi_outstanding_read_with_same_id_to_different_slaves: This is covered when:
- A master issues two outstanding write transactions with the same ID
- These write transactions are targeted to two different slaves

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_INTERLEAVING_DEPTH

trans_cross_axi_write_interleaving_depth

write_data_interleave

write_data_interleave:write_data_interleave_depth

This covergroup captures attributes for write data interleave depth. It is constructed when interface type is set to AXI3 .

Covergroup: trans_cross_axi_write_interleaving_depth

Coverpoints:

write_data_interleave : Captures write data interleave depth

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITERESP_XACT_FLOW

trans_cross_ace_awsnoop_bresp

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
bresp:okay_resp, exokay_resp, slverr_resp, decerr_resp
slave_port_id:slave_id

awsnoop_bresp

Covergroup: trans_cross_ace_awsnoop_bresp

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITERESP_XACT_FLOW

trans_cross_exclusive_writenosnoop_domain_type

coherent_write_xact_type:coherent_writenosnoop_xact
bresp:exokay_resp
domain_type:domain_non_shareable, domain_system_shareable

awsnoop_awdomain_bresp

Covergroup : trans_cross_exclusive_writenosnoop_domain_type

This Covergroup captures coherant writenosnoop_xact_type,write_resp and domain_type for write transaction. It is constructed and sampled when trans_cross_exclusive_writenosnoop_domain_type_enable and exclusive_access_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent writenosnoop transaction
bresp : Captures exokay write response
domain_type : Captures NONSHAREABLE & SYSTEMSHAREABLE domain types

Cross coverpoints:

awsnoop_awdomain_bresp : Crosses cover points coherent_write_xact_type, domain_type and bresp

The EXOKAY response is permitted for WriteNoSnoop with domain innershareable & outershareable. Rest all other bins are ignored.

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITECACHE_XACT_FLOW

trans_cross_ace_awsnoop_awcache

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable, write_through_no_allocate, write_through_read_allocate, write_through_write_allocate, write_through_read_and_write_allocate, write_back_no_allocate, write_back_read_allocate, write_back_write_allocate, write_back_read_and_write_allocate
slave_port_id:slave_id

awsnoop_awcache

Covergroup: trans_cross_ace_awsnoop_awcache

This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITECACHE_XACT_FLOW

trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty
final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_sharedclean

awsnoop_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate

This Covergroup captures coherant read xact_type ,initial and final cacheline state for write transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_READ_ONLY & trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate_enable set to 1 & update_cache_for_non_coherent_xacts set to 0.

Coverpoints:

coherent_write_xact_type : Captures coherent Write transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states

Cross coverpoints:

awsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITECACHE_XACT_FLOW

trans_cross_ace_awsnoop_update_cache_cacheinitialstate_cachefinalstate

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty
final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_sharedclean

awsnoop_update_cache_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_awsnoop_update_cache_cacheinitialstate_cachefinalstate

Coverpoints:

coherent_write_xact_type : Captures coherent Write transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states

Cross coverpoints:

awsnoop_update_cache_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITEDOMAIN_XACT_FLOW

trans_cross_ace_awsnoop_awdomain

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable
slave_port_id:slave_id

awsnoop_awdomain

Covergroup : trans_cross_ace_awsnoop_awdomain

This Covergroup captures coherant write xact_type,domain and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type

Cross coverpoints:

awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_ace_concurrent_overlapping_arsnoop_acsnoop

coherent_read_xact_type:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact
snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_overlapping_arsnoop_acsnoop

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_read_xact_type:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on read channel of master . This excludes READNOSNOOP,DVMMESSAGE,DVMCOMPLETE,READBARRIER transactions The bins in this covergroup will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address Two ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_ace_concurrent_overlapping_arsnoop_acsnoop_one_ace_acelite

coherent_read_xact_type:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact
snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_overlapping_arsnoop_acsnoop_one_ace_acelite

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_read_xact_type:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on read channel of master . This excludes READNOSNOOP,DVMMESSAGE,DVMCOMPLETE,READBARRIER transactions The bins in this covergroup will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address Atleast one ACE and one ACE_LITE master needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_axi_snoop

ACVALID_to_ACREADY_Delay:acvalid_to_acready_delay_min, acvalid_to_acready_delay_mid, acvalid_to_acready_delay_max
ACVALID_to_CRVALID_Delay:acvalid_to_crvalid_delay_min, acvalid_to_crvalid_delay_mid, acvalid_to_crvalid_delay_max
CRVALID_to_CRREADY_Delay:crvalid_to_crready_delay_min, crvalid_to_crready_delay_mid, crvalid_to_crready_delay_max
ACVALID_to_prev_ACVALID_Delay:acvalid_to_prev_acvalid_delay_min, acvalid_to_prev_acvalid_delay_mid, acvalid_to_prev_acvalid_delay_max
ACVALID_before_ACREADY:acvalid_before_acready
ACREADY_before_ACVALID:acready_before_acvalid
CRVALID_before_CRREADY:crvalid_before_crready
CRREADY_before_CRVALID:crready_before_crvalid

Covergroup: trans_axi_snoop

This Covergroup captures delay scenarios between valid and ready signal for snoop address and snoop data. It is constructed when trans_axi_snoop_enable is set to 1 and interface type is AXI_ACE or ACE_LITE.

Coverpoints:

ACVALID_to_ACREADY_Delay: Captures min, mid and max range of delays between signals acvalid and acready
ACVALID_to_CRVALID_Delay: Captures min, mid and max range of delays between signals acvalid and crvalid
CRVALID_to_CRREADY_Delay: Captures min, mid and max range of delays between signals crvalid and crready
ACVALID_to_prev_ACVALID_Delay: Captures min, mid and max range of delays between current and previous acvalid signals
ACVALID_before_ACREADY: Captures if ACVALID signal comes before ACREADY signal
ACREADY_before_ACVALID: Captures if ACREADY signal comes before ACVALID signal
CRVALID_before_CRREADY: Captures if CRVALID signal comes before CRREADY signal
CRREADY_before_CRVALID: Captures if CRREADY signal comes before CRVALID signal

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_axi_snoop_data_phase

CDVALID_to_prev_CDVALID_Delay:cdvalid_to_prev_cdvalid_delay_min, cdvalid_to_prev_cdvalid_delay_mid, cdvalid_to_prev_cdvalid_delay_max
CDVALID_to_CDREADY_Delay:cdvalid_to_cdready_delay_min, cdvalid_to_cdready_delay_mid, cdvalid_to_cdready_delay_max
CDVALID_before_CDREADY:cdvalid_before_cdready
CDREADY_before_CDVALID:cdready_before_cdvalid

Covergroup: trans_axi_snoop_data_phase

This Covergroup captures valid to ready delay scenario for snoop channel. It is constructed when trans_axi_snoop_enable is set to 1.

Coverpoints:

CDVALID_to_prev_CDVALID_Delay
CDVALID_to_CDREADY_Delay
CDVALID_before_CDREADY: Captures if CDVALID signal comes before CDREADY signal
CDREADY_before_CDVALID: Captures if CDREADY signal comes before CDVALID signal

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_cross_ace_acsnoop_acaddr

snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
snoop_addr:addr_range_min, addr_range_mid, addr_range_max

acsnoop_acaddr

Covergroup: trans_cross_ace_acsnoop_acaddr

This Covergroup captures snoop xact type and address. It is constructed when trans_cross_ace_acsnoop_acaddr_enable is asserted.

Coverpoints:

snoop_xact_type: Captures Snoop transaction
snoop_addr: Captures Snoop address

Cross coverpoints:

acsnoop_acaddr : Crosses cover points snoop_xact_type and snoop_addr

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_cross_ace_acsnoop_acaddr_one_ace_acelite

snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
snoop_addr:addr_range_min, addr_range_mid, addr_range_max

acsnoop_acaddr

Covergroup: trans_cross_ace_acsnoop_acaddr_one_ace_acelite

This Covergroup captures snoop xact type and address. It is constructed when trans_cross_ace_acsnoop_acaddr_enable is asserted. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system.

Coverpoints:

snoop_xact_type: Captures Snoop transaction
snoop_addr: Captures Snoop address

Cross coverpoints:

acsnoop_acaddr : Crosses cover points snoop_xact_type and snoop_addr

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_cross_ace_acsnoop_acprot

snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
snoop_prot:data_secure_normal, data_non_secure_normal

acsnoop_acprot

Covergroup: trans_cross_ace_acsnoop_acprot

This Covergroup captures snoop xact type and protection signal It is constructed when trans_cross_ace_acsnoop_acprot_enable is asserted.

Coverpoints:

snoop_xact_type: Captures Snoop transaction
snoop_prot: Captures Snoop protection type

Cross coverpoints:

acsnoop_acprot : Crosses cover points snoop_xact_type and snoop_prot

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_cross_ace_acsnoop_acprot_one_ace_acelite

snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
snoop_prot:data_secure_normal, data_non_secure_normal

acsnoop_acprot

Covergroup: trans_cross_ace_acsnoop_acprot_one_ace_lite

This Covergroup captures snoop xact type and protection signal. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when trans_cross_ace_acsnoop_acprot_enable is asserted.

Coverpoints:

snoop_xact_type: Captures Snoop transaction
snoop_prot: Captures Snoop protection type

Cross coverpoints:

acsnoop_acprot : Crosses cover points snoop_xact_type and snoop_prot

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_cross_ace_awsnoop_awbar

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization

awsnoop_awbar

Covergroup: trans_cross_ace_awsnoop_awbar

This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awbar_enable and barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier

Cross coverpoints:

awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_readunique_snoop_resp_datatransfer_with_clean_cacheline

snoop_resp_datatransfer_with_clean_cacheline

snoop_resp_datatransfer_with_clean_cacheline:snoop_no_datatransfer, snoop_with_datatransfer

Covergroup: trans_master_readunique_snoop_resp_datatransfer_with_clean_cacheline

This Covergroup captures snoop rersponse for readunique data transfer. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE .

Coverpoints:

snoop_resp_datatransfer_with_clean_cacheline: Captures whether data was transferred for READUNIQUE snoop when the cache was in a clean state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.3.3

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr

snoop_xact_type

snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact

Covergroup: trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr

This Covergroup captures snoop responses with data transfer when a WRITEUNIQUE or WRITELINEUNIQUE to the same address is in progress. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE .

Coverpoints:

snoop_xact_type: Captures snoop transactions other than DVM transactions and MAKEINVALID. MAKEINVALID transactions are not captured because it is recommended that MAKEINVALID does not transfer data.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr_one_ace_acelite

snoop_xact_type

snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact

Covergroup: trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr_one_ace_acelite

This Covergroup captures snoop responses with data transfer when a WRITEUNIQUE or WRITELINEUNIQUE to the same address is in progress, when only one ACE master and one or more ACE_LITE masters present in the system. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE .

Coverpoints:

snoop_xact_type: Captures snoop transactions READONCE,CLEANSHARED,CLEANINVALID. Other transactions are not captured because ACE_LITE master cant fire READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict

memory_update_excluding_writeevict:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeback_xact, coherent_writeclean_xact, coherent_evict_xact
snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

trans_cross_memory_update_snoop_xact_to_same_address

Covergroup: trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict

This Covergroup captures read transaction for for same address snooped to master. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_READ_ONLY.

Coverpoints:

memory_update_excluding_writeevict: Captures WRITEBACK,WRITECLEAN,EVICT,WRITEUNIQUE and WRITELINEUNIQUE transactions to the same address as a snoop. WRITENOSNOOP transactions to non overlapping addresses are captured because WRITENOSNOOP is issued to non-shareable region and another master may not access the same address as that of a WRITENOSNOOP through a snoop.
snoop_xact_type: Captures snoop transactions other than DVM transactions
Cross Coverpoints :
trans_cross_memory_update_snoop_xact_to_same_address: Crosses memory_update_excluding_writeevict and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict_one_ace_acelite

memory_update_excluding_writeevict:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeback_xact, coherent_writeclean_xact, coherent_evict_xact
snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

trans_cross_memory_update_snoop_xact_to_same_address

Covergroup: trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict_one_ace_acelite

This Covergroup captures write transaction for memory update and snoop based dvm unset type. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_READ_ONLY. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system.

Coverpoints:

memory_update_excluding_writeevict: Captures WRITEBACK,WRITECLEAN,EVICT,WRITEUNIQUE and WRITELINEUNIQUE transactions to the same address as a snoop. WRITENOSNOOP transactions to non overlapping addresses are captured because WRITENOSNOOP is issued to non-shareable region and another master may not access the same address as that of a WRITENOSNOOP through a snoop.
snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions
Cross Coverpoints :
trans_cross_memory_update_snoop_xact_to_same_address: Crosses memory_update_excluding_writeevict and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_snoop_to_same_addr_as_writeevict

write_evict_xact:coherent_writeevict_xact
snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

trans_cross_writeevict_snoop_xact_to_same_address

Covergroup: trans_master_snoop_to_same_addr_as_writeevict

This Covergroup captures write transaction for same address as snoop and snoop transaction except dvm based. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE writeevict_enable set to 1. Coverpoints:

write_evict_xact: Captures WRITEEVICT transactions to the same address as a snoop.
snoop_xact_type: Captures snoop transactions other than DVM transactions

Cross Coverpoints :

trans_cross_writeevict_snoop_xact_to_same_address: Crosses write_evict_xact and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_snoop_to_same_addr_as_writeevict_one_ace_acelite

write_evict_xact:coherent_writeevict_xact
snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

trans_cross_writeevict_snoop_xact_to_same_address

Covergroup: trans_master_snoop_to_same_addr_as_writeevict_one_ace_acelite

This Covergroup captures write evict and snoop xact transaction. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE writeevict_enable set to 1. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system.

Coverpoints:

write_evict_xact: Captures WRITEEVICT transactions to the same address as a snoop.
snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions

Cross Coverpoints :

trans_cross_writeevict_snoop_xact_to_same_address: Crosses write_evict_xact and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOP_XACT_FLOW

trans_master_snoop_to_same_address_as_read_xact

read_xact_to_same_address_as_snoop

read_xact_to_same_address_as_snoop:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact

Covergroup: trans_master_snoop_to_same_address_as_read_xact

This Covergroup captures read transaction for for same address snooped to master. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_WRITE_ONLY.

Coverpoints:

read_xact_to_same_address_as_snoop: Captures read transactions to the same address as a snoop to the master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp

coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact
snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact
snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp The bins in covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp is applicable only for ACE Masters .The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that * generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port :Coverpoint of cresp.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite

coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact
snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact
snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with non overlapping address The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite is applicable only for ACE Masters .The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite needs at least one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Coverpoint of cresp.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled

coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact
snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact
snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled is applicable only for ACE Masters.The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled needs at least one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : coverpoint of cresp. Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled

coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writeevict_xact
snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact
snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled is applicable only for ACE Masters. The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled needs atleast one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master. This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Coverpoint of cresp.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled

coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact
snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact
snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enable

The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled is applicable only for ACE Masters .The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that * generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port :

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled

coherent_write_xact_type_gen_snoop:coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writeevict_xact
snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact
snoop_crresp_on_ace_port:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

ace_concurrent_overlap_snoop_xact

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled

The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled is applicable only for ACE Masters .The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that * generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port :

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_cross_ace_acsnoop_crresp

snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
snoop_crresp:cresp_x0000, cresp_x1000, cresp_x0001, cresp_x1001, cresp_x0101, cresp_x1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

acsnoop_crresp
acsnoop_crresp_wasunique

Covergroup: trans_cross_ace_acsnoop_crresp

This Covergroup captures snoop xact_type, rresp_type(unique and notunique) . It is constructed when trans_cross_ace_acsnoop_crresp_enable is set to 1.

Coverpoints:

snoop_xact_type: Captures Snoop transaction
snoop_crresp: Captures Snoop response type

Cross coverpoints:

acsnoop_crresp : Crosses cover points snoop_xact_type and snoop_crresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_cross_ace_acsnoop_crresp_one_ace_acelite

snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
snoop_crresp:cresp_x0000, cresp_x1000, cresp_x0001, cresp_x1001, cresp_x0101, cresp_x1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique

acsnoop_crresp
acsnoop_crresp_wasunique

Covergroup: trans_cross_ace_acsnoop_crresp_one_ace_acelite

This Covergroup captures snoop xact_type, rresp_type(unique and notunique) . This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when trans_cross_ace_acsnoop_crresp_enable is set to 1.

Coverpoints:

snoop_xact_type: Captures Snoop transaction
snoop_crresp: Captures Snoop response type

Cross coverpoints:

acsnoop_crresp : Crosses cover points snoop_xact_type and snoop_crresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_master_ace_coherent_and_ace_snoop_response_association

coh_xact_from_ace:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, writeunique_coherent, writelineunique_coherent
snoop_crresp_from_ace:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique
ace_init_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state
ace_final_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state
snoop_xact_on_ace_master:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

coh_xact_ace_snp_resp_ace_init_final_cache_state

Covergroup: trans_master_ace_coherent_and_ace_snoop_response_association

Covergroup for all coherent transactions generated from ACE master and the correponding Snoop transactions on ACE-Masters and snoop response from ACE-Masters for these snoop transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there are two ACE master s in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_coherent_and_ace_snoop_response_association_enable to 1.

Coverpoints:

coh_xact_from_ace: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE Master
snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE master resulted in this snoop transaction and snoop response and subsequently hit bins of coverpoint cmds_from_ace. System Monitor provides this information to Port Monitor.
snoop_xact_on_ace_master: This coverpoint has bins corresponding to each of the valid snoop transaction type on ACE master
snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique)
ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master.
ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master.

Cross Coverpoints:

coh_xact_ace_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace, snoop_xact_on_ace_master,snp_crresp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace

ace_coh_and_snp_association

ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readonce_coherent_to_readclean_snoop, readonce_coherent_to_readnotshareddirty_snoop, readonce_coherent_to_readshared_snoop, readonce_coherent_to_readunique_snoop, readonce_coherent_to_cleaninvalid_snoop, readonce_coherent_to_cleanshared_snoop, readclean_coherent_to_readclean_snoop, readclean_coherent_to_readnotshareddirty_snoop, readclean_coherent_to_readshared_snoop, readclean_coherent_to_readunique_snoop, readclean_coherent_to_cleaninvalid_snoop, readnotshareddirty_coherent_to_readclean_snoop, readnotshareddirty_coherent_to_readnotshareddirty_snoop, readnotshareddirty_coherent_to_readshared_snoop, readnotshareddirty_coherent_to_readunique_snoop, readnotshareddirty_coherent_to_cleaninvalid_snoop, readshared_coherent_to_readclean_snoop, readshared_coherent_to_readnotshareddirty_snoop, readshared_coherent_to_readshared_snoop, readshared_coherent_to_readunique_snoop, readshared_coherent_to_cleaninvalid_snoop, readunique_coherent_to_readunique_snoop, readunique_coherent_to_cleaninvalid_snoop, cleanunique_coherent_to_readunique_snoop, cleanunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_readunique_snoop, makeunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_makeinvalid_snoop, cleanshared_coherent_to_readunique_snoop, cleanshared_coherent_to_cleaninvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_readunique_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_readunique_snoop, makeinvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_readunique_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_readunique_snoop, writelineunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop

Covergroup: system_ace_coherent_and_snoop_association_recommended_and_optional_ace

This Covergroup captures optional snoop transactions to snooped masters when coherant transaction is received from initiating master. It is constructed when interface_type is AXI_ACE and system_ace_coherent_and_snoop_association_enable set to 1.

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended and optional snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace_lite

ace_coh_and_snp_association

ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readonce_coherent_to_readclean_snoop, readonce_coherent_to_readnotshareddirty_snoop, readonce_coherent_to_readshared_snoop, readonce_coherent_to_readunique_snoop, readonce_coherent_to_cleaninvalid_snoop, readonce_coherent_to_cleanshared_snoop, cleanshared_coherent_to_readunique_snoop, cleanshared_coherent_to_cleaninvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_readunique_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_readunique_snoop, makeinvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_readunique_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_readunique_snoop, writelineunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop

Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace_lite

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended and optional snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id

coh_xact_t1_ace_lite:writeunique_coherent, writelineunique_coherent
coh_xact_t2_ace_lite:writeunique_coherent, writelineunique_coherent
snoop_crresp_0_t1:cresp_0, cresp_1
snoop_crresp_0_t2:cresp_0, cresp_1
coh_xact_id:ace_lite_xact_id

coh_xact_ace_lite_xacts_ace_snp_resp_specific_id

Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id

Covergroup for back to back combination of CLEANINVALID and MAKEINVALID coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id_enable to 1.

Coverpoints:

coh_xact_t1_ace_lite: This coverpoint has bins corresponding to first transaction of a back to back transactions from an ACE-Lite Master
coh_xact_t2_ace_lite: This coverpoint has bins corresponding to second transaction of a back to back transactions from an ACE-Lite Master
snoop_crresp_0_t1 & snoop_crresp_0_t2: This coverpoint has bins for all possible values of CRRESP[0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master.

Cross Coverpoints:

coh_xact_ace_lite_xacts_ace_snp_resp_specific_id: This is the cross-coverage between coh_xact_t1_ace_lite, snoop_crresp_0_t1, coh_xact_t2_ace_lite, snoop_crresp_0_t2, coh_xact_id.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id

coh_xact_from_ace_lite:readonce_coherent, cleanshared_coherent, cleaninvalid_coherent, makeinvalid_coherent, writeunique_coherent, writelineunique_coherent
snoop_crresp_from_ace:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique
ace_init_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state
ace_final_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state

coh_xact_ace_lite_snp_resp_ace_init_final_cache_state

Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id

Covergroup for all coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be sampled only when transaction is having configured specific id. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id_enable set to 1.

Coverpoints:

coh_xact_from_ace_lite: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE-Lite Master
snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE-Lite master resulted in this snoop response and subsequently hit bins of coverpoint cmds_from_ace_lite. System Monitor provides this information to Port Monitor.
snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique)
ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master.
ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master.

Cross Coverpoints:

coh_xact_ace_lite_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace_lite, snp_resp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_SNOOPRESP_XACT_FLOW

trans_master_snoop_resp_during_wu_wlu_to_same_addr

snoop_crresp:cresp_x0000, cresp_x1000, cresp_x0001, cresp_x1001
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique
awunique_val:is_not_unique, is_unique

snoop_resp_awunique

Covergroup: trans_master_snoop_resp_during_wu_wlu_to_same_addr

This Covergroup captures snoop response type,WasUnique bit ,awunique value and snoop response with awunique value. It is constructed and sampled when interface_type is AXI_ACE and interface_category is not AXI_READ_ONLY.

Coverpoints:

snoop_crresp: Captures snoop response values
snoop_crresp_wu: Captures value of WasUnique bit in snoop response
awunique_val: Captures the value of signal AWUNIQUE for WRITEUNIQUE and WRITELINEUNIQUE transactions

Cross Coverpoints:

snoop_resp_awunique: Cross of snoop_crresp, snoop_crresp_wu and awunique_val

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITEDOMAINBARRIER_XACT_FLOW

trans_cross_ace_awdomain_awbarrier_memory_sync

coherent_write_xact_type:coherent_writebarrier_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable

awdomain_awbarrier_memory_sync

Covergroup: trans_cross_ace_awdomain_awbarrier_memory_sync

This Covergroup captures barrier_type and domain_type for write transaction. It is constructed and sampled when trans_cross_ace_awdomain_awbarrier_memory_sync_enable

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier
domain_type : Captures domain type

Cross coverpoints:

awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type MEMORY_BARRIER & SYNC_BARRIER with awdomain

As barrier types are memory & sync therefore, ignoring bins intersect with NORMAL_ACCESS_RESPECT_BARRIER & NORMAL_ACCESS_IGNORE_BARRIER and ignoring all other non-writebarrier bins.

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITEDOMAINBARRIER_XACT_FLOW

trans_cross_ace_awdomain_awbarrier_respect_ignore

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable

awdomain_awbarrier_respect_ignore

Covergroup : trans_cross_ace_awdomain_awbarrier_respect_ignore

This Covergroup captures coherant write xact_type and barrier_type for write transaction. It is constructed and sampled when trans_cross_ace_awdomain_awbarrier_respect_ignore_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures non write barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with awdomain

As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are WRITEBARRIER with Memory & Sync

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READCACHE_XACT_FLOW

trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty
final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_uniquedirty, final_state_sharedclean, final_state_shareddirty

arsnoop_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate

This Covergroup captures coherant read xact_type ,initial and final cacheline state for read transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_WRITE_ONLY & trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_enable is set 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_read_xact_type initial_cache_line_state and final_cache_line_state

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READCACHE_XACT_FLOW

trans_cross_ace_arsnoop_update_cache_cacheinitialstate_cachefinalstate

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty
final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_uniquedirty, final_state_sharedclean, final_state_shareddirty

arsnoop_update_cache_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_arsnoop_update_cache_cacheinitialstate_cachefinalstate

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_read_xact_type initial_cache_line_state and final_cache_line_state

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READRESP_XACT_FLOW

trans_cross_ace_ardvmmessage_ardvmresp

ardvm_message_type:message_tlb_invalidate, message_branch_predictor_invalidate, message_physical_instruction_cache_invalidate, message_virtual_instruction_cache_invalidate, message_synchronization, message_hint
ardvm_resp:message_accept, message_reject

ardvmmessage_ardvmresp

Covergroup: trans_cross_ace_ardvmmessage_ardvmresp

This Covergroup captures coherant read xact_type and response type for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_ardvmmessage_ardvmresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1

Coverpoints:

ardvm_message_type : Captures DVM message on araddr[14:12]
ardvm_resp : Capture DVM response on rresp [4:0], accept = 4'b0000 and reject = 4'b0010

Cross coverpoints:

ardvmmessage_ardvmresp : Crosses coverpoints ardvm_message_type and ardvm_resp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READRESP_XACT_FLOW

trans_cross_ace_arsnoop_coh_rresp

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
coh_rresp:coherent_rresp_shared_clean, coherent_rresp_shared_dirty, coherent_rresp_unique_clean, coherent_rresp_unique_dirty
slave_port_id:slave_id

arsnoop_coh_rresp

Covergroup: trans_cross_ace_arsnoop_coh_rresp

This Covergroup captures coherant read xact_type,response type and slave_port_id for read transaction. It is constructed and sampled when interface type is not ACE_LITE and AXI_WRITE_ONLY. and trans_cross_ace_arsnoop_coh_rresp_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
coh_rresp : Captures read coherent response

Cross coverpoints:

arsnoop_coh_rresp : Crosses cover points coherent_read_xact_type and coh_rresp

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_ORDERING_XACT_FLOW

trans_master_back_to_back_write_ordering

xact_back_to_back_write_ordering

xact_back_to_back_write_ordering:back_to_back_write_with_same_id

Covergroup: trans_master_back_to_back_write_ordering

This Covergroup captures back to back write transactions for same id. It is constructed when port_kind is AXI_MASTER and interface_type is not AXI4_STREAM & interface_category is not AXI_READ_ONLY.

Coverpoints:

xact_back_to_back_write_ordering: Captures if back-to-back write transactions with the same id is observed

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_ORDERING_XACT_FLOW

trans_master_write_after_read_ordering

xact_write_after_read_ordering

xact_write_after_read_ordering:write_after_read_with_write_completing_first, write_after_read_with_read_completing_first

Covergroup: trans_master_write_after_read_ordering

This Covergroup captures write transaction after read happens. It is constructed when port_kind is AXI_MASTER and interface_type is not AXI4_STREAM & interface_category is AXI_READ_WRITE.

Coverpoints:

xact_write_after_read_ordering: Captures the order of completion of a write transaction issued after a read

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_ORDERING_XACT_FLOW

trans_xact_ordering_after_barrier

axi_xact_ordering_after_barrier

axi_xact_ordering_after_barrier:read_xact_overtake_barrier_response, read_xact_fallbehind_barrier_response, write_xact_overtake_barrier_response, write_xact_fallbehind_barrier_response

Covergroup: trans_xact_ordering_after_barrier

This Covergroup captures read & write transaction ordering for barrier response scenarios. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_ordering_after_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_ordering_after_barrier: This is covered when a master issues transactions between issuing a barrier transaction on the address channel and receiving the read and write barrier responses.
- Such transactions have no ordering guarantee with respect to the barrier. On the address channel, these transactions are permitted to remain after the barrier transaction or they are permitted to overtake the barrier transaction.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_NARROW_TRANSFER

trans_cross_axi_read_narrow_transfer_arlen_araddr

read_xact_type:read_xact
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f

axi_read_narrow_transfer_arlen_araddr

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr

This Covergroup captures transfer size and address offset for read narrow transfer. It is constrcuted and sampled when trans_cross_axi_read_narrow_transfer_arlen_araddr_enable is asserted.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_NARROW_TRANSFER

trans_cross_axi_write_narrow_transfer_awlen_awaddr

write_xact_type:write_xact
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f

axi_write_narrow_transfer_awlen_awaddr

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer It is constructed and sampled when trans_cross_axi_write_narrow_transfer_awlen_awaddr_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_READ_UNALIGNED_TRANSFER

trans_cross_axi_read_unaligned_transfer

read_xact_type:read_xact
burst_type:fixed_burst, incr_burst, wrap_burst
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte

axi_read_unaligned_transfer

Covergroup: trans_cross_axi_read_unaligned_transfer

This Covergroup captures burst_type,burst_length, transfer size and address offset for read unaligned transfer. It is constructed and sampled when trans_cross_axi_read_unaligned_transfer_enable.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_WRITE_UNALIGNED_TRANSFER

trans_cross_axi_write_unaligned_transfer

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
addr_offset:offset_0, offset_1, offset_2, offset_3, offset_4, offset_5, offset_6, offset_7, offset_8, offset_9, offset_a, offset_b, offset_c, offset_d, offset_e, offset_f, offset_10, offset_11, offset_12, offset_13, offset_14, offset_15, offset_16, offset_17, offset_18, offset_19, offset_1a, offset_1b, offset_1c, offset_1d, offset_1e, offset_1f, offset_20, offset_21, offset_22, offset_23, offset_24, offset_25, offset_26, offset_27, offset_28, offset_29, offset_2a, offset_2b, offset_2c, offset_2d, offset_2e, offset_2f, offset_30, offset_31, offset_32, offset_33, offset_34, offset_35, offset_36, offset_37, offset_38, offset_39, offset_3a, offset_3b, offset_3c, offset_3d, offset_3e, offset_3f, offset_40, offset_41, offset_42, offset_43, offset_44, offset_45, offset_46, offset_47, offset_48, offset_49, offset_4a, offset_4b, offset_4c, offset_4d, offset_4e, offset_4f, offset_50, offset_51, offset_52, offset_53, offset_54, offset_55, offset_56, offset_57, offset_58, offset_59, offset_5a, offset_5b, offset_5c, offset_5d, offset_5e, offset_5f, offset_60, offset_61, offset_62, offset_63, offset_64, offset_65, offset_66, offset_67, offset_68, offset_69, offset_6a, offset_6b, offset_6c, offset_6d, offset_6e, offset_6f, offset_70, offset_71, offset_72, offset_73, offset_74, offset_75, offset_76, offset_77, offset_78, offset_79, offset_7a, offset_7b, offset_7c, offset_7d, offset_7e, offset_7f
transfer_size:xfer_size_1byte, xfer_size_2byte, xfer_size_4byte, xfer_size_8byte, xfer_size_16byte, xfer_size_32byte, xfer_size_64byte, xfer_size_128byte, xfer_size_256byte, xfer_size_512byte

axi_write_unaligned_transfer

Covergroup: trans_cross_axi_write_unaligned_transfer

This Covergrpoup captures following signals for unaligned write transfer. It is constructed and sampled when trans_cross_axi_write_unaligned_transfer_enable is asserted. Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_DIRTYDATA_XACT_FLOW

trans_master_ace_cross_cache_line_dirty_data_write

ace_cross_cache_line_dirty_data_write

ace_cross_cache_line_dirty_data_write:readonce_cross_cache_line_dirty_data_write, writeunique_cross_cache_line_dirty_data_write

Covergroup: trans_master_ace_cross_cache_line_dirty_data_write

This is a system-level covergroup which works by enabling sys_cfg field system_which captures dirty data for write cache line. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE ,interface_category is AXI_READ_WRITE and system_ace_cross_cache_line_dirty_data_write_enable set to 1.

Coverpoints:

ace_cross_cache_line_dirty_data_write: This is covered under the following conditions:
- The interconnect may need to snoop multiple cachelines for a WRITEUNIQUE or READONCE transaction because it spans multiple cache lines
- Atleast two of these snoop transactions return dirty data
- The interconnect writes the dirty data of the snoop transactions to slave
  One or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_DIRTYDATA_XACT_FLOW

trans_master_ace_dirty_data_write

ace_dirty_data_write

ace_dirty_data_write:readonce_dirty_data_write, readclean_dirty_data_write, readnotshreaddirty_dirty_data_write, cleaninvalid_dirty_data_write, cleanshared_dirty_data_write, cleanunique_dirty_data_write, writeunique_dirty_data_write

Covergroup: trans_master_ace_dirty_data_write

This is a system-level covergroup which works by enabling sys_cfg field system_ace_dirty_data_write_enable. It is constructed and sampled when interface_type is AXI_ACE,interface_category is AXI_READ_WRITE and system_ace_dirty_data_write_enable set to 1.

Coverpoints:

master_xact_of_ic_dirty_data_write: This is covered when the interconnect issues a write to the slave because dirty data was returned by one of the snoop responses and that dirty data could not be returned to the master that initiated the original transaction
Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_DIRTYDATA_XACT_FLOW

trans_master_ace_dirty_data_write_one_ace_acelite

ace_dirty_data_write

ace_dirty_data_write:readonce_dirty_data_write, cleaninvalid_dirty_data_write, cleanshared_dirty_data_write, writeunique_dirty_data_write

Covergroup: trans_master_ace_dirty_data_write_one_ace_acelite

This is a system-level covergroup which works by enabling sys_cfg field system_ace_dirty_data_write_enable. It is constructed and sampled when interface_type is ACE_LITE ,interface_category is AXI_READ_WRITE and system_ace_dirty_data_write_enable set to 1.

Coverpoints:

master_xact_of_ic_dirty_data_write: This is covered when the interconnect issues a write to the slave because dirty data was returned by one of the snoop responses and that dirty data could not be returned to the master that initiated the original transaction
One ACE and one or more ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_DIRTYDATA_XACT_FLOW

trans_master_ace_snoop_and_memory_returns_data

ace_snoop_and_memory_data_timing:snoop_data_before_memory_data, snoop_data_along_with_memory_data, snoop_data_after_memory_data, snoop_returns_data_and_memory_not_returns_data
ace_snoop_and_memory_returns_data_xact_type:readonce_snoop_and_memory_returns_data, readclean_snoop_and_memory_returns_data, readnotshreaddirty_snoop_and_memory_returns_data, readunique_snoop_and_memory_returns_data, readshared_snoop_and_memory_returns_data

snoop_memory_timing_and_xact_cross

Covergroup: trans_master_ace_snoop_and_memory_returns_data

It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_snoop_and_memory_returns_data_enable set to 1.

Coverpoints:

ace_snoop_and_memory_read_timing: This cover point covers possible relative timings of snoop generation by the interconnect with respect to receiving speculative read data by the interconnect and bin snoop_returns_data_and_memory_not_returns_data covers if a transaction is found with snoop data transfer and without associated slave transaction. The various timings covered are:
- snoop issued before the first read data beat is received through speculative read transaction
- snoop issued after the last beat of read data is received through speculative read transaction
- snoop issued while the read data is being received through speculative read transaction
ace_snoop_and_memory_returns_data_xact_type: Covers the various coherent transaction types for which speculative read was issued. The transaction types covered are READONCE, READCLEAN READNOSHAREDDIRTY, READUNIQUE and READSHARED transactions
At least two ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_ace_coherent_and_snoop_association_recommended_ace

ace_coh_and_snp_association

ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readclean_coherent_to_readclean_snoop, readnotshareddirty_coherent_to_readnotshareddirty_snoop, readshared_coherent_to_readshared_snoop, readunique_coherent_to_readunique_snoop, cleanunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_makeinvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop

Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_ace

This Covergroup captures scenari when master issues coherant transaction , interconnect recommends snooop based transaction to snooped masters. It is constructed and sampled when interface _type is AXI_ACE and system_ace_coherent_and_snoop_association_enable set to 1.

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_ace_coherent_and_snoop_association_recommended_ace_lite

ace_coh_and_snp_association

ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop

Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_ace_lite

This Covergroup captures scenario when master issues coherant transaction , interconnect recommends snooop based transaction to snooped masters. It is constructed and sampled when interface _type is ACE_LITE .

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_ace_concurrent_overlapping_coherent_xacts

coherent_xact_on_ace_master_port:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_writeunique_xact, coherent_writelineunique_xact
coherent_xact_on_other_ace_master_port_in_system:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_writeunique_xact, coherent_writelineunique_xact

ace_concurrent_overlapping

Covergroup: trans_master_ace_concurrent_overlapping_coherent_xacts

The covergroup trans_master_ace_concurrent_overlapping_coherent_xacts covers coherent transactions initiated from different ACE masters concurrently on the same address. The covergroup needs atlease two ACE masters to be present in the system. It is constructed and sampled when interface_type is AXI_ACE and system_ace_concurrent_overlapping_coherent_xacts_enable set to 1. Coverpoints:

coherent_xact_on_ace_master_port: This coverpoint covers svt_axi_transaction :: coherent_xact_type transaction . All coherent transactions capable of generating snoop are bins of this coverpoint .
coherent_xact_on_other_ace_master_port_in_system : This coverpoint covers svt_axi_transaction :: coherent_xact_type transactions . All coherent transactions capable of generating snoop are bins of this coverpoint .

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_ace_concurrent_readunique_cleanunique

ace_concurrent_readunique_cleanunique

ace_concurrent_readunique_cleanunique:readunique_readunique, readunique_cleanunique, cleanunique_cleannique

Covergroup: trans_master_ace_concurrent_readunique_cleanunique

This Covergroup captures scenario for ACE master initiating simultanous ReadUnique or CleanUnique transactions. It is consstructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_concurrent_readunique_cleanunique_enable set to 1.

Coverpoints:

ace_concurrent_readunique_cleanunique: This is covered when multiple ACE masters concurrently(that are simultaneously active) initiate ReadUnique or CleanUnique transactions.
Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_ace_lite_coherent_and_ace_snoop_response_association

coh_xact_from_ace_lite:readonce_coherent, cleanshared_coherent, cleaninvalid_coherent, makeinvalid_coherent, writeunique_coherent, writelineunique_coherent
snoop_crresp_from_ace:cresp_0000, cresp_1000, cresp_0001, cresp_1001, cresp_0101, cresp_1101
snoop_crresp_wu:cresp_wasunique, cresp_wasnotunique
ace_init_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state
ace_final_cache_state:invalid_cache_state, uniqueclean_cache_state, sharedclean_cache_state, uniquedirty_cache_state, shareddirty_cache_state
associate_snoop_xact_for_coh_xact_from_acelite_master:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact

coh_xact_ace_lite_snp_resp_ace_init_final_cache_state

Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association

Covergroup for all coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_enable set to 1.

Coverpoints:

coh_xact_from_ace_lite: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE-Lite Master
snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE-Lite master resulted in this snoop response and subsequently hit bins of coverpoint cmds_from_ace_lite. System Monitor provides this information to Port Monitor.
associate_snoop_xact_for_coh_xact_from_acelite_master: This coverpoint has bins corresponding to valid snoop transactions issued to ACE master for coherent xacts from ACE-Lite Master
snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique)
ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master.
ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master.

Cross Coverpoints:

coh_xact_ace_lite_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace_lite,associate_snoop_xact_for_coh_xact_from_acelite_master, snp_resp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_ace_no_cached_copy_overlapping_coherent_xact

ace_no_cached_copy_overlap_coh_xact

ace_no_cached_copy_overlap_coh_xact:overlap_readonce_readonce, overlap_writeunique_writeunique, overlap_writelineunique_writelineunique

Covergroup: trans_master_ace_no_cached_copy_overlapping_coherent_xact

This Covergroup captures no cached copy for overlapping coherant transaction. It is constructed and sampled when interface_type is AXI_ACE and system_ace_no_cached_copy_overlapping_coherent_xact_enable set to 1.

Coverpoints:

no_cached_copy_overlap_coh_xact: This coverpoint has following bins
overlap_readonce_readonce: This bin gets hit when two or more masters issue readonce coherent transactions to overlapping cacheline simultaneously.
overlap_writeunique_writeunique: This bin gets hit when two or more masters issue writeunique coherent transactions to overlapping cacheline simultaneously.
overlap_writelineunique_writelineunique: This bin gets hit when two or more masters issue writelineunique coherent transactions to overlapping cacheline simultaneously.

Two or more ACE / ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_ace_store_overlapping_coherent_xact

ace_store_overlap_coh_xact

ace_store_overlap_coh_xact:overlap_readunique_readunique, overlap_cleanunique_cleanunique, overlap_makeunique_makeunique

Covergroup: trans_master_ace_store_overlapping_coherent_xact

This Covergroup captures overlapped coherant transaction for readunique and cleanunique . It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_store_overlapping_coherent_xact_enable set to 1.

Coverpoints:

store_overlap_coh_xact: This cover point has follwoing bins
overlap_readunique_readunique: This bin gets hit when two or more masters issue readunique coherent transactions to overlapping cacheline simultaneously.
overlap_cleanunique_cleanunique: This bin gets hit when two or more masters issue cleanunique coherent transactions to overlapping cacheline simultaneously.
overlap_makeunique_makeunique: This bin gets hit when two or more masters issue makeunique coherent transactions to overlapping cacheline simultaneously.

Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C4.10

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_coherent_unmatched_excl_access

unmatched_excl_access

unmatched_excl_access:unmatched_excl_store_access, unmatched_excl_load_access

Covergroup: trans_master_coherent_unmatched_excl_access

This Covergroup captures coherant transactions for exclusive access. It is constructed when interface_type is AXI_ACE and exclusive_access_enable set to 1.

Coverpoints:

unmatched_excl_access: Captures exclusive load accesses which did not have a corresponding exclusive store access and exclusive store accesses which did not have a corresponding exclusive load access. The unmatched_excl_load_access is hit when a second exclusive load access to the same ID is received before an exclusive store to that ID. The unmatched_excl_store_access is hit when there is no prior exclusive load to an exclusive store (CLEANUNIQUE) transaction.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C9.6

AXI_PORT_MON_XACT_FLOW

AXI_PORT_MON_COHERANT_XACT_FLOW

trans_master_concurrent_coherent_exclusive_access

num_coherent_exl_access

num_coherent_exl_access:one_thread, more_than_one_thread

Covergroup: trans_master_concurrent_coherent_exclusive_access

This Covergroup captures coherant transactions for exclusive access. It is constructed when interface_type is AXI_ACE and exclusive_access_enable set to 1.

Coverpoints:

num_coherent_exl_access: Number of concurrent coherent exclusive accesses on different IDs

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C9.6

Covergroup

Coverpoints

Bins

Cross Coverage

Description

signal_state_acaddr

acaddr_min_mid_max

acaddr_min_mid_max:acaddr_range_min, acaddr_range_mid, acaddr_range_max

State covergroups for ACE snoop channel protocol signals

signal_state_awaddr

awaddr_min_mid_max

awaddr_min_mid_max:awaddr_range_min, awaddr_range_mid, awaddr_range_max

State covergroups for common protocol signals among AXI3, AXI4, AXI4_Lite, ACE

signal_state_awlen

awlen_min_mid_max

awlen_min_mid_max:awlen_range_min, awlen_range_mid, awlen_range_max

State covergroups for common protocol signals among AXI3, AXI4, ACE

signal_state_awregion

awregion_min_mid_max

awregion_min_mid_max:awregion_range_min, awregion_range_mid, awregion_range_max

State covergroups for AXI4 and additional ACE read/write channel protocol signals

signal_state_tdata

tdata_min_mid_max

tdata_min_mid_max:tdata_range_min, tdata_range_mid, tdata_range_max

State coverage for STREAM protocol signals

signal_state_wid

wid_min_mid_max

wid_min_mid_max:wid_range_min, wid_range_mid, wid_range_max

State covergroups for AXI3 protocol signals

system_ace_barrier_response_with_outstanding_xacts

ace_completed_barrier_type

ace_completed_barrier_type:outstanding_xacts_during_memory_barrier, outstanding_xacts_during_sync_barrier

Covergroup: system_ace_barrier_response_with_outstanding_xacts

Coverpoints:

ace_completed_barrier_type: This is covered when there are outstanding transactions in the queue of a master when the response to a barrier is received. There are multiple ways in which an interconnect can handle barriers. Some interconnects may send response to a barrier only after all outstanding transactions are complete. Others may forward the barrier downstream and wait for the response of the downstream barrier before responding to the original barrier. In such a case there could be outstanding transactions in the queue of the master when a barrier response is received. This coverpoint covers the latter behaviour.
One or more ACE/ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.3

system_ace_coherent_and_snoop_association_recommended

ace_coh_and_snp_association

ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readclean_coherent_to_readclean_snoop, readnotshareddirty_coherent_to_readnotshareddirty_snoop, readshared_coherent_to_readshared_snoop, readunique_coherent_to_readunique_snoop, cleanunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_makeinvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop

Covergroup: system_ace_coherent_and_snoop_association_recommended

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

system_ace_coherent_and_snoop_association_recommended_and_optional

ace_coh_and_snp_association

ace_coh_and_snp_association:readonce_coherent_to_readonce_snoop, readonce_coherent_to_readclean_snoop, readonce_coherent_to_readnotshareddirty_snoop, readonce_coherent_to_readshared_snoop, readonce_coherent_to_readunique_snoop, readonce_coherent_to_cleaninvalid_snoop, readonce_coherent_to_cleanshared_snoop, readclean_coherent_to_readclean_snoop, readclean_coherent_to_readnotshareddirty_snoop, readclean_coherent_to_readshared_snoop, readclean_coherent_to_readunique_snoop, readclean_coherent_to_cleaninvalid_snoop, readnotshareddirty_coherent_to_readclean_snoop, readnotshareddirty_coherent_to_readnotshareddirty_snoop, readnotshareddirty_coherent_to_readshared_snoop, readnotshareddirty_coherent_to_readunique_snoop, readnotshareddirty_coherent_to_cleaninvalid_snoop, readshared_coherent_to_readclean_snoop, readshared_coherent_to_readnotshareddirty_snoop, readshared_coherent_to_readshared_snoop, readshared_coherent_to_readunique_snoop, readshared_coherent_to_cleaninvalid_snoop, readunique_coherent_to_readunique_snoop, readunique_coherent_to_cleaninvalid_snoop, cleanunique_coherent_to_readunique_snoop, cleanunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_readunique_snoop, makeunique_coherent_to_cleaninvalid_snoop, makeunique_coherent_to_makeinvalid_snoop, cleanshared_coherent_to_readunique_snoop, cleanshared_coherent_to_cleaninvalid_snoop, cleanshared_coherent_to_cleanshared_snoop, cleaninvalid_coherent_to_readunique_snoop, cleaninvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_readunique_snoop, makeinvalid_coherent_to_cleaninvalid_snoop, makeinvalid_coherent_to_makeinvalid_snoop, writeunique_coherent_to_readunique_snoop, writeunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_readunique_snoop, writelineunique_coherent_to_cleaninvalid_snoop, writelineunique_coherent_to_makeinvalid_snoop

Covergroup: system_ace_coherent_and_snoop_association_recommended_and_optional

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended and optional snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

system_ace_concurrent_overlapping_coherent_xacts

coherent_xact_on_ace_master_port:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_writeunique_xact, coherent_writelineunique_xact
coherent_xact_on_other_ace_master_port_in_system:coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_writeunique_xact, coherent_writelineunique_xact

ace_concurrent_overlapping

Covergroup: system_ace_concurrent_overlapping_coherent_xacts The covergroup system_ace_concurrent_overlapping_coherent_xacts covers coherent transactions initiated from different ACE masters concurrently on the same address. The covergroup needs atlease two ACE masters to be present in the system. Coverpoints:

coherent_xact_on_ace_master_port: This coverpoint covers svt_axi_transaction :: coherent_xact_type transaction . All coherent transactions capable of generating snoop are bins of this coverpoint .
coherent_xact_on_other_ace_master_port_in_system : This coverpoint covers svt_axi_transaction :: coherent_xact_type transactions . All coherent transactions capable of generating snoop are bins of this coverpoint .

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

system_ace_concurrent_readunique_cleanunique

ace_concurrent_readunique_cleanunique

ace_concurrent_readunique_cleanunique:readunique_readunique, readunique_cleanunique, cleanunique_cleannique

Covergroup: system_ace_concurrent_readunique_cleanunique

Coverpoints:

ace_concurrent_readunique_cleanunique: This is covered when multiple ACE masters concurrently(that are simultaneously active) initiate ReadUnique or CleanUnique transactions.
Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

system_ace_cross_cache_line_dirty_data_write

ace_cross_cache_line_dirty_data_write:readonce_cross_cache_line_dirty_data_write, writeunique_cross_cache_line_dirty_data_write
ace_snoop_returns_data:only_one_snoop_returns_data
wstrb_of_dirty_data:partial_cacheline_wstrb, full_cacheline_wstrb

Covergroup: system_ace_cross_cache_line_dirty_data_write

Coverpoints:

ace_snoop_returns_data : This is covered only when one snoop returns a dirty data.
wstrb_of_dirty_data : This will indicate whether the wstrb value of the dirty data is full cacheline or partial cacheline.
ace_cross_cache_line_dirty_data_write: This is covered under the following conditions:
- The interconnect may need to snoop multiple cachelines for a WRITEUNIQUE or READONCE transaction because it spans multiple cache lines.
- Atleast one or more snoop transactions return dirty data.
- The interconnect writes the dirty data of the snoop transactions to slave. One or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

system_ace_dirty_data_write

ace_dirty_data_write:readonce_dirty_data_write, readclean_dirty_data_write, readnotshreaddirty_dirty_data_write, cleaninvalid_dirty_data_write, cleanshared_dirty_data_write, cleanunique_dirty_data_write, writeunique_dirty_data_write
ace_snoop_returns_data:only_one_snoop_returns_data

Covergroup: system_ace_dirty_data_write

Coverpoints:

master_xact_of_ic_dirty_data_write: This is covered when the interconnect issues a write to the slave because dirty data was returned by one of the snoop responses and that dirty data could not be returned to the master that initiated the original transaction
ace_snoop_returns_data : This is covered only when one snoop returns a dirty data. One or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

system_ace_no_cached_copy_overlapping_coherent_xact

ace_no_cached_copy_overlap_coh_xact

ace_no_cached_copy_overlap_coh_xact:overlap_readonce_readonce, overlap_writeunique_writeunique, overlap_writelineunique_writelineunique

Covergroup: system_ace_no_cached_copy_overlapping_coherent_xact

Coverpoints:

no_cached_copy_overlap_coh_xact: This coverpoint has following bins
overlap_readonce_readonce: This bin gets hit when two or more masters issue readonce coherent transactions to overlapping cacheline simultaneously.
overlap_writeunique_writeunique: This bin gets hit when two or more masters issue writeunique coherent transactions to overlapping cacheline simultaneously.
overlap_writelineunique_writelineunique: This bin gets hit when two or more masters issue writelineunique coherent transactions to overlapping cacheline simultaneously.

Two or more ACE / ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

system_ace_snoop_and_memory_returns_data

ace_snoop_and_memory_data_timing:snoop_data_before_memory_data, snoop_data_along_with_memory_data, snoop_data_after_memory_data, snoop_returns_data_and_memory_not_returns_data
ace_snoop_and_memory_returns_data_xact_type:readonce_snoop_and_memory_returns_data, readclean_snoop_and_memory_returns_data, readnotshreaddirty_snoop_and_memory_returns_data, readunique_snoop_and_memory_returns_data, readshared_snoop_and_memory_returns_data

snoop_memory_timing_and_xact_cross

Covergroup: system_ace_snoop_and_memory_returns_data

Coverpoints:

ace_snoop_and_memory_read_timing: This cover point covers possible relative timings of snoop generation by the interconnect with respect to receiving speculative read data by the interconnect and bin snoop_returns_data_and_memory_not_returns_data covers if a transaction is found with snoop data transfer and without associated slave transaction. The various timings covered are:
- snoop issued before the first read data beat is received through speculative read transaction
- snoop issued after the last beat of read data is received through speculative read transaction
- snoop issued while the read data is being received through speculative read transaction
ace_snoop_and_memory_returns_data_xact_type: Covers the various coherent transaction types for which speculative read was issued. The transaction types covered are READONCE, READCLEAN READNOSHAREDDIRTY, READUNIQUE and READSHARED transactions
At least two ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1

system_ace_store_overlapping_coherent_xact

ace_store_overlap_coh_xact

ace_store_overlap_coh_xact:overlap_readunique_readunique, overlap_cleanunique_cleanunique, overlap_makeunique_makeunique

Covergroup: system_ace_store_overlapping_coherent_xact

Coverpoints:

store_overlap_coh_xact: This cover point has follwoing bins
overlap_readunique_readunique: This bin gets hit when two or more masters issue readunique coherent transactions to overlapping cacheline simultaneously.
overlap_cleanunique_cleanunique: This bin gets hit when two or more masters issue cleanunique coherent transactions to overlapping cacheline simultaneously.
overlap_makeunique_makeunique: This bin gets hit when two or more masters issue makeunique coherent transactions to overlapping cacheline simultaneously.

Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C4.10

system_ace_valid_read_channel_valid_overlap

arvalid:arvalid_val
arready_val_0:arready_0
acvalid_val_0:acvalid_0
acready:acready_val_1, acready_val_0

overlap_arvalid_arready_acvalid_acready_corss

Covergroup: system_ace_valid_read_channel_valid_overlap

This covergroup is cross coverage of read address and snoop channel whenever ARVALID is 1, ARREADY is 0, read outstanding is reached, ACVALID=0 and ACREADY=1

Coverpoints:

arvalid : Captures ARVALID ==1
arready_val_0 : Captures ARREADY == 0
acvalid_val_0 : Captures ACVALID =0
acready : Captures ACREADY=1

Cross coverpoints:

overlap_arvalid_arready_acvalid_acready_corss : Crosses coverpoints arvalid arready_val_0 acvalid_val_0 acready

system_ace_valid_write_channel_valid_overlap

awvalid:awvalid_val
awready_val_0:awready_0
acvalid_val_0:acvalid_0
acready:acready_val_1, acready_val_0

overlap_awvalid_awready_acvalid_acready_corss

Covergroup: system_ace_valid_write_channel_valid_overlap

This covergroup is cross coverage of write address and snoop channel whenever AWVALID is 1, AWREADY is 0, read outstanding is reached, ACVALID=0 and ACREADY=1

Coverpoints:

awvalid : Captures AWVALID ==1
awready_val_0 : Captures AWREADY == 0
acvalid_val_0 : Captures ACVALID =0
acready : Captures ACREADY=1

Cross coverpoints:

overlap_awvalid_awready_acvalid_acready_corss : Crosses coverpoints awvalid awready_val_0 acvalid_val_0 acready

system_ace_write_during_speculative_fetch

ace_write_during_speculative_fetch

ace_write_during_speculative_fetch:overlapping_write_during_readonce, overlapping_write_during_readclean, overlapping_write_during_readnotshareddirty, overlapping_write_during_readunique, overlapping_write_during_readshared

Covergroup: system_ace_write_during_speculative_fetch

Coverpoints:

ace_write_during_speculative_fetch: This cover point covers the following condition: A master issues a read transaction. This results in interconnect generating snoop transactions towards other masters within the domain. The interconnect also generates speculative read transaction for this location. Speculative transaction returns data while the snoop transactions do not return data. The snoop transactions may not return data, either because there is no entry in the snooped masters' caches or a WRITEBACK/WRITECLEAN of dirty data is in progress. The interconnect now detects that a write transaction (the WRITEBACK/WRITECLEAN which is in progress) is received for the same address for which it did a speculative fetch. In such situation, interconnect performs another read from main memory, as originally received data from speculative read is now stale
At least two ACE master needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1

system_ace_xacts_with_high_priority_from_other_master_during_barrier

ace_xacts_with_high_priority_from_other_master_during_barrier

ace_xacts_with_high_priority_from_other_master_during_barrier:xacts_from_other_master_during_barrier

Covergroup: system_ace_xacts_with_high_priority_from_other_master_during_barrier

Coverpoints:

ace_xacts_with_high_priority_from_other_master_during_barrier: This cover point covers the following condition: When the interconnect receives barrier from a master, then all other transactions launched by other masters in that domain may be stalled. This cover point covers condition where master issues transactions with non-zero QOS value. Then another master issues a barrier transaction within the same domain.
Two or more ACE/ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.1

system_axi_master_to_slave_access

axi_master_to_slave_access

axi_master_to_slave_access:master_to_slave_pair_id

Covergroup: system_axi_master_to_slave_access

Coverpoints:

provides coverage for master to slave accessibility. It tries to measure whether each axi master read from or write into every connected axi slaves in the system or not. This is captured as a unique master-slave access pair-id i.e. each master and slave pair is given an unique id represented as an individual coverage bin. Following example describes how this pair-id can be decoded to which {master, slave} pair it belongs to, is given below.
Example: system configuration:: num_masters = 3, num_slaves = 2
Total possible unique values of master_slave_pair_id {0..5}
master_id = INT(master_slave_pair_id / num_slaves) [integer quotient]
slave_id = (master_slave_pair_id % num_slaves)
If coverage report shows id as 3 then master_id = INT(3/2) = 1, slave_id = (3%2) = 1
So, the master-slave access pair, this particular bin has covered, is {master-1, slave-1}
master_to_slave_pair_id: Captures each master to slave access pair id value Ignore Bins : depending on the nature of system, user may not be interested in some master-slave pair accesses. User can do this in following two ways:
Example: system configuration:: num_masters = 3, num_slaves = 2
Total possible unique values of master_slave_pair_id {0..5}
Master-Slave pairs to be ignored are {1,3,4}
User can do this in following two ways:
- VIP Built-in IGNORE_BIN define: VIP provides following "define" macro
  User can just define following callback hook to include the master-slave pair id values which should be ignored.
  `define IGNORE_BINS_CG_system_axi_master_to_slave_access_CP_master_to_slave_pair_id ignore_bins = {1,[3:4]};
  NOTE: ignore bin name is completely user defined, VIP doesn't have any restriction for this.
- user can override the covergroup by extending the callback class and re-defining this covergroup
- user can disable this covergroup and define their own covergroup extending this coverage callback class

system_axi_master_to_slave_access_range

axi_master_to_slave_access

axi_master_to_slave_access:master_to_slave_pair_id_0, master_to_slave_pair_id_1, master_to_slave_pair_id_2, master_to_slave_pair_id_3, master_to_slave_pair_id_4, master_to_slave_pair_id_5, master_to_slave_pair_id_6

Covergroup: system_axi_master_to_slave_access_range

Coverpoints:

provides coverage for master to slave accessibility. It tries to measure whether each axi master read from or write into every connected axi slaves in the system or not. This is captured as a unique master-slave access pair-id i.e. each master and slave pair is given an unique id represented as an individual coverage bin. Following example describes how this pair-id can be decoded to which {master, slave} pair it belongs to, is given below.
(num_master*num_slave)/6 should not be equal to zero are needed for this covergroup
Example: system configuration:: num_masters = 3, num_slaves = 2
Total possible unique values of master_slave_pair_id {0..5}
master_id = INT(master_slave_pair_id / num_slaves) [integer quotient]
slave_id = (master_slave_pair_id % num_slaves)
If coverage report shows id as 3 then master_id = INT(3/2) = 1, slave_id = (3%2) = 1
So, the master-slave access pair, this particular bin has covered, is {master-1, slave-1}
master_to_slave_pair_id: Captures each master to slave access pair id value Ignore Bins : depending on the nature of system, user may not be interested in some master-slave pair accesses. User can do this in following two ways:
Example: system configuration:: num_masters = 3, num_slaves = 2
Total possible unique values of master_slave_pair_id {0..5}
Master-Slave pairs to be ignored are {1,3,4}
User can do this in following two ways:
- VIP Built-in IGNORE_BIN define: VIP provides following "define" macro
  User can just define following callback hook to include the master-slave pair id values which should be ignored.
  `define IGNORE_BINS_CG_system_axi_master_to_slave_access_CP_master_to_slave_pair_id ignore_bins = {1,[3:4]};
  NOTE: ignore bin name is completely user defined, VIP doesn't have any restriction for this.
- user can override the covergroup by extending the callback class and re-defining this covergroup
- user can disable this covergroup and define their own covergroup extending this coverage callback class

trans_ace_barrier_pair_sequence

barrier_pair_sequence

barrier_pair_sequence:barrier_pair_rd_after_wr_seq, barrier_pair_wr_after_rd_seq, barrier_pair_simultaneous_rd_wr_seq

Coverage group for covering the order of read and write barrier transactions within a barrier pair
Bins:
barrier_pair_rd_after_wr_seq - Read barrier transaction occurs after write barrier transaction
barrier_pair_wr_after_rd_seq - Write barrier transaction occurs after read barrier transaction
barrier_pair_simultaneous_rd_wr_seq - Read barrier and write barrier transactions occurs at same clock This covergroup is applicable only for svt_axi_port_configuration :: axi_interface_type set to AXI_ACE/ACE_LITE.

trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate

snoop_xact_type:snoop_readonce_xact, snoop_readshared_xact, snoop_readclean_xact, snoop_readnotshareddirty_xact, snoop_readunique_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty
final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_uniquedirty, final_state_sharedclean, final_state_shareddirty

acsnoop_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate

This Covergroup captures snoop_xact_type, snoop initial and final cache line state for snoop based transaction. It is constructed when interface_type is not ACE_LITE and trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate_enable set to 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

acsnoop_cacheinitialstate_cachefinalstate : Crosses cover points snoop_xact_type initial_cache_line_state and final_cache_line_state

trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate_one_ace_acelite

snoop_xact_type:snoop_readonce_xact, snoop_cleanshared_xact, snoop_cleaninvalid_xact, snoop_makeinvalid_xact, snoop_dvmcomplete_xact, snoop_dvmmessage_xact
initial_cache_line_state:initial_state_invalid, initial_state_uniqueclean, initial_state_uniquedirty, initial_state_sharedclean, initial_state_shareddirty
final_cache_line_state:final_state_invalid, final_state_uniqueclean, final_state_uniquedirty, final_state_sharedclean, final_state_shareddirty

acsnoop_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate

This Covergroup captures snoop_xact_type, snoop initial and final cache line state for snoop based transaction. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when interface_type is not ACE_LITE and trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate_enable set to 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

acsnoop_cacheinitialstate_cachefinalstate : Crosses cover points snoop_xact_type initial_cache_line_state and final_cache_line_state

trans_cross_ace_ardomain_arbarrier_memory_sync

coherent_read_xact_type:coherent_readbarrier_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable

ardomain_arbarrier_memory_sync

Covergroup: trans_cross_ace_ardomain_arbarrier_memory_sync

This Covergroup captures barrier_type and domain_type for read transaction. It is constructed and sampled when trans_cross_ace_ardomain_arbarrier_memory_sync_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
barrier_type : Captures read barrier
domain_type : Captures domain type

Cross coverpoints:

arbarrier_ardomain : Crosses cover points read transaction of certain barrier_type MEMORY_BARRIER & SYNC_BARRIER with ardomain As barrier types are memory & sync therefore, ignoring bins intersect with NORMAL_ACCESS_RESPECT_BARRIER & NORMAL_ACCESS_IGNORE_BARRIER and ignoring all other non-readbarrier bins.

trans_cross_ace_ardomain_arbarrier_respect_ignore

coherent_read_xact_type:coherent_readnosnoop_xact, coherent_readonce_xact, coherent_readshared_xact, coherent_readclean_xact, coherent_readnotshareddirty_xact, coherent_readunique_xact, coherent_cleanunique_xact, coherent_makeunique_xact, coherent_cleanshared_xact, coherent_cleaninvalid_xact, coherent_makeinvalid_xact, coherent_dvmcomplete_xact, coherent_dvmmessage_xact, coherent_readbarrier_xact
barrier_type:barrier_normal_respect, barrier_memory, barrier_normal_ignore, barrier_synchronization
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable

ardomain_arbarrier_respect_ignore

Covergroup: trans_cross_ace_ardomain_arbarrier_respect_ignore

This Covergroup captures barrier_type and domain_type for read transaction. It is constructed and sampled when trans_cross_ace_ardomain_arbarrier_respect_ignore_enable & barrier_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
barrier_type : Captures non read barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

arbarrier_ardomain : Crosses cover points read transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with ardomain

As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are READBARRIER with Memory & Sync

trans_cross_ace_awsnoop_awdomain_awcache

coherent_write_xact_type:coherent_writenosnoop_xact, coherent_writeunique_xact, coherent_writelineunique_xact, coherent_writeclean_xact, coherent_writeback_xact, coherent_evict_xact, coherent_writebarrier_xact, coherent_writeevict_xact
domain_type:domain_non_shareable, domain_inner_shareable, domain_outer_shareable, domain_system_shareable
cache_type:device_non_bufferable, device_bufferable, normal_non_cacheable_non_bufferable, normal_non_cacheable_bufferable, write_through_no_allocate, write_through_read_allocate, write_through_write_allocate, write_through_read_and_write_allocate, write_back_no_allocate, write_back_read_allocate, write_back_write_allocate, write_back_read_and_write_allocate

awsnoop_awdomain_awcache

Covergroup: trans_cross_ace_awsnoop_awdomain_awcache

This Covergroup captures coherant write xact_type,domain and cache type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_awcache_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awdomain_awcache : Crosses cover points coherent_write_xact_type and domain_type and cache_type

trans_cross_ace_dvm_firstpart_secondpart_addr_range_32

araddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
araddr_dvm_firsrpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
araddr_dvm_secondpart_32:dvm_araddr_secondpart_range_1, dvm_araddr_secondpart_range_2, dvm_araddr_secondpart_range_3

dvm_firstpart_secondpart_addr_range_32

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_32

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_secondpart_32 : Captures SecondPart of DVM of width32

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_32 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_secondpart_32

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb47to16

acdvm_message_type:message_tlb_invalidate
acdvm_hypervisor_type:all_guest_os, hypervisor_and_all_guest_os, hypervisor, el
acdvm_security_type:no_secure, secure, secure_and_no_secure
acdvm_addr_mode_bits:invl_all_guestOS_stage1_invl_only, invl_all_guestOS_stage1_stage2, invl_by_va_guestOS, invl_by_va_guestOS_leaf_entry_only, invl_by_asid_guestOS, invl_by_asid_va_guestOS, invl_by_asid_va_guestOS_leaf_entry_only, invl_by_ipa_guestOS, invl_by_ipa_guestOS_leaf_entry_only
acaddr_dvm_firstpart_va_or_vmid:dvm_araddr_bits_31to24_range_1, dvm_araddr_bits_31to24_range_2, dvm_araddr_bits_31to24_range_3, dvm_araddr_bits_31to24_range_4
acaddr_dvm_firstpart_va_or_asid:dvm_araddr_bits_23to16_range_1, dvm_araddr_bits_23to16_range_2, dvm_araddr_bits_23to16_range_3, dvm_araddr_bits_23to16_range_4
acaddr_dvm_msb47to32_firstpart:dvm_araddr_firstpart_range_1, dvm_araddr_firstpart_range_2, dvm_araddr_firstpart_range_3

dvm_snoop_tlbinvl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb47to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

trans_cross_axi3_awburst_awlen_awaddr_awsize

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi3_awburst_awlen_awaddr_awsize

Covergroup: trans_cross_axi3_awburst_awlen_awaddr_awsize

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi3_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

trans_cross_axi3_awburst_awlen_awcache

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
cache_type:non_cacheable_non_bufferable, bufferable_or_modifiable_only, cacheable_but_no_alloc, cacheable_bufferable_but_no_alloc, cacheable_write_through_allocate_on_read_only, cacheable_write_back_allocate_on_read_only, cacheable_write_through_allocate_on_write_only, cacheable_write_back_allocate_on_write_only, cacheable_write_through_allocate_on_both_read_write, cacheable_write_back_allocate_on_both_read_write

axi3_awburst_awlen_awcache

Covergroup: trans_cross_axi3_awburst_awlen_awcache

This covergroup describes about burst_type,burst_length and cache signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi3_awburst_awlen_awcache: Crosses cover points write_xact_type, burst_type, burst_length, cache_type

trans_cross_axi3_awburst_awlen_awlock

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
atomic_type:normal, exclusive, locked

axi3_awburst_awlen_awlock

Covergroup: trans_cross_axi3_awburst_awlen_awlock

This covergroup describes about burst_type,burst_length and lock signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi3_awburst_awlen_awlock: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

trans_cross_axi3_awburst_awlen_awprot

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

axi3_awburst_awlen_awprot

Covergroup: trans_cross_axi3_awburst_awlen_awprot

This covergroup describes about burst_type,burst_length and protection signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi3_awburst_awlen_awprot: Crosses cover points write_xact_type, burst_type, burst_length, prot_type

trans_cross_axi3_awburst_awlen_awsize

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi3_awburst_awlen_awsize

Covergroup: trans_cross_axi3_awburst_awlen_awsize

This covergroup describes for burst_type,burst_length and burst_size for write transfer. It is constructed when interface type is AXI3 and trans_cross_axi_awburst_awlen_awsize_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi3_awburst_awlen_awsize: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

trans_cross_axi4_awburst_awlen_awaddr_awsize

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
addr:addr_range_min, addr_range_mid, addr_range_max
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi4_awburst_awlen_awaddr_awsize

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

trans_cross_axi4_awburst_awlen_awcache

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
cache_type:non_cacheable_non_bufferable, bufferable_or_modifiable_only, cacheable_but_no_alloc, cacheable_bufferable_but_no_alloc, cacheable_write_through_allocate_on_read_only, cacheable_write_back_allocate_on_read_only, cacheable_write_through_allocate_on_write_only, cacheable_write_back_allocate_on_write_only, cacheable_write_through_allocate_on_both_read_write, cacheable_write_back_allocate_on_both_read_write

axi4_awburst_awlen_awcache

Covergroup: trans_cross_axi4_awburst_awlen_awcache

This covergroup describes about burst_type,burst_length and cache signal for write transfer. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi4_awburst_awlen_awcache: Crosses cover points write_xact_type, burst_type, burst_length, cache_type

trans_cross_axi4_awburst_awlen_awlock

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
atomic_type:normal, exclusive, locked

axi4_awburst_awlen_awlock

Covergroup: trans_cross_axi4_awburst_awlen_awlock

This covergroup describes about burst_type,burst_length and lock signal for write transfer. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi4_awburst_awlen_awsize: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

trans_cross_axi4_awburst_awlen_awprot

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
prot_type:data_secure_normal, data_secure_privileged, data_non_secure_normal, data_non_secure_privileged, instruction_secure_normal, instruction_secure_privileged, instruction_non_secure_normal, instruction_non_secure_privileged

axi4_awburst_awlen_awprot

Covergroup: trans_cross_axi4_awburst_awlen_awprot

This covergroup describes about burst_type,burst_length and protection signal for write transfer. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi4_awburst_awlen_awprot: Crosses cover points write_xact_type, burst_type, burst_length, prot_type

trans_cross_axi4_awburst_awlen_awsize

write_xact_type:write_xact
burst_type:fixed_burst, incr_burst, wrap_burst
burst_length:burst_length
burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit

axi4_awburst_awlen_awsize

Covergroup: trans_cross_axi4_awburst_awlen_awsize

This covergroup describes for burst_type,burst_length and burst_size for write transfer. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_awburst_awlen_awsize_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awsize: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

trans_cross_axi4_stream_interleaving_depth

axi4_stream_data_interleave

axi4_stream_data_interleave:axi4_stream_data_interleave_size

Covergroup: trans_cross_axi4_stream_interleaving_depth

This covergroup describes about interleave depth size for axi_stream tb. It is constructed when interface type is AXI_STREAM

Coverpoints:

axi4_stream_interleave : Captures axi4 stream data interleave depth

trans_cross_axi_ooo_read_response_depth

ooo_read_response:ooo_depth
ooo_read_response_depth:ooo_depth

Covergroup: trans_cross_axi_ooo_read_response_depth

This covergroup describes It is constructed when trans_cross_axi_ooo_read_response_depth_enable is asserted. Coverpoints:

ooo_read_response: Captures out-of-order read response
ooo_read_response_depth: Captures out-of-order read response depth
- out-of-order response depth is determined by the position of the transaction in outstanding queue for which response is being returned. Ex: if outstanding queue has 5 entries and response is received for 4th transaction (i.e. entry[3]) then depth will be determined as "3" because, response for the first or head-of-ooo-queue transaction is not considered as out-of-order.
- User has option to modify each coverpoints through following defines.
  - VIP Built-in IGNORE_BIN define: VIP provides following "define" macro
    
    _CG_ provides covergroup name and _CP_ provides coverpoint name. By default these are defined empty. User can just define above macros to ignore certain bin values or ignore all bins and define entirely customized set of bins. NOTE: ignore bin name is completely user defined, VIP doesn't have any restriction fo this.
  - user can override the covergroup by extending the callback class and re-defining this covergroup
  - user can disable this covergroup and define their own covergroup extending this coverage callback class

trans_cross_axi_ooo_write_response_depth

ooo_write_response:ooo_depth
ooo_write_response_depth:ooo_depth

Covergroup: trans_cross_axi_ooo_write_response_depth

Coverpoints:

ooo_write_response : Captures out-of-order write response
ooo_write_response_depth : Captures out-of-order write response depth
- out-of-order response depth is determined by the position of the transaction in outstanding queue for which response is being returned. Ex: if outstanding queue has 5 entries and response is received for 4th transaction (i.e. entry[3]) then depth will be determined as "3" because, response for the first or head-of-ooo-queue transaction is not considered as out-of-order.
- User has option to modify each coverpoints through following defines.
  - VIP Built-in IGNORE_BIN define: VIP provides following "define" macro
    
    _CG_ provides covergroup name and _CP_ provides coverpoint name. By default these are defined empty. User can just define above macros to ignore certain bin values or ignore all bins and define entirely customized set of bins. NOTE: ignore bin name is completely user defined, VIP doesn't have any restriction fo this.
  - user can override the covergroup by extending the callback class and re-defining this covergroup
  - user can disable this covergroup and define their own covergroup extending this coverage callback class

trans_cross_axi_read_interleaving_depth

read_data_interleave

read_data_interleave:read_data_interleave_size

Covergroup: trans_cross_axi_read_interleaving_depth

This covergroup describes about interleave depth size for read transfer. It is constructed when trans_cross_axi_read_interleaving_depth_enable is asserted. The number of bins get hit is equal to the number of active read transactions that were interleaved.

Coverpoints:

read_data_interleave : Captures read data interleave depth

trans_cross_axi_write_strobes

write_xact_type:write_xact
wstrb:wstrb_all_ones_8, wstrb_all_ones_16, wstrb_all_ones_32, wstrb_all_ones_64, wstrb_all_ones_128, wstrb_all_ones_256, wstrb_all_ones_512, wstrb_all_ones_1024, wstrb_all_ones_2048, wstrb_all_ones_4096, wstrb_all_zeroes_8, wstrb_all_zeroes_16, wstrb_all_zeroes_32, wstrb_all_zeroes_64, wstrb_all_zeroes_128, wstrb_all_zeroes_256, wstrb_all_zeroes_512, wstrb_all_zeroes_1024, wstrb_all_zeroes_2048, wstrb_all_zeroes_4096, wstrb_all_one_zero_data_width_16, wstrb_all_zero_one_data_width_16, wstrb_all_one_zero_data_width_32, wstrb_all_zero_one_data_width_32, wstrb_all_one_zero_data_width_64, wstrb_all_zero_one_data_width_64, wstrb_all_one_zero_data_width_128, wstrb_all_zero_one_data_width_128, wstrb_all_one_zero_data_width_256, wstrb_all_zero_one_data_width_256, wstrb_all_one_zero_data_width_512, wstrb_all_zero_one_data_width_512, wstrb_all_one_zero_data_width_1024, wstrb_all_zero_one_data_width_1024, wstrb_all_one_zero_data_width_2048, wstrb_all_zero_one_data_width_2048, wstrb_all_one_zero_data_width_4096, wstrb_all_zero_one_data_width_4096

axi_write_strobes

Covergroup: trans_cross_axi_write_strobes

This covergroup captures strobe values for write transfer. It is constructed and sampled when trans_cross_axi_write_strobes_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
wstrb: Captures write strobe values

Cross coverpoints:

axi_write_strobes: Crosses cover points write_xact_type,wstrb

trans_cross_master_to_slave_path_access_axi3

all_slaves:slvs_b
slaves_excluding_register_space:slvs_no_cfg_b
write_xact_type:write_xact
read_xact_type:read_xact
axi_ex_xact_type:exclusive_type
atomic_type:normal, locked
burst_type:fixed_burst, incr_burst, wrap_burst
axi_burst_size:burst_size_8bit, burst_size_16bit, burst_size_32bit, burst_size_64bit, burst_size_128bit, burst_size_256bit, burst_size_512bit, burst_size_1024bit, burst_size_2048bit, burst_size_4096bit
cache_type:non_cacheable_non_bufferable, bufferable_or_modifiable_only, cacheable_but_no_alloc, cacheable_bufferable_but_no_alloc, cacheable_write_through_allocate_on_read_only, cacheable_write_back_allocate_on_read_only, cacheable_write_through_allocate_on_write_only, cacheable_write_back_allocate_on_write_only, cacheable_write_through_allocate_on_both_read_write, cacheable_write_back_allocate_on_both_read_write
burst_length:burst_length
axi_response_type:axi_okay_response, axi_exokay_response, axi_slverr_response, axi_decerr_response, axi_exokay_fail_response
axi_address_aligned:axi_8bit_aligned_address, axi_16bit_aligned_address, axi_32bit_aligned_address, axi_64bit_aligned_address, axi_128bit_aligned_address, axi_256bit_aligned_address

cache_len_1_all_okay
cache_len_reduced_all_okay
cache_len_reduced_ignore_response
cache_all_okay_fixed
cache_all_slverr_fixed
cache_ignore_resp_fixed
cache_all_okay_fixed_unaligned
cache_ignore_resp_fixed_unaligned
master_to_slave_all_okay
master_to_slave_ignore_response
master_to_slave_decerr_len_1
master_to_slave_slverr_len_1
master_to_slave_decerr
master_to_slave_slverr
master_to_all_slave_ignore_response
cross_xact_type_len_1_wstrb
cross_xact_type_len_2_wstrb
cross_xact_type_len_3_wstrb
cross_xact_type_len_4_wstrb
cross_xact_type_len_16_wstrb
cross_aligned_unaligned_addr_asize
cross_aligned_unaligned_addr_asize_ignore_resp
master_to_slave_x_wr_okay_addr_align
master_to_slave_x_wr_fail_addr_align
master_to_slave_x_wr_decerr
master_to_slave_x_wr_slverr
master_to_slave_x_wr_okay_wstrb
master_to_slave_x_wr_fail_wstrb

This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI3 and trans_cross_master_to_slave_path_access_axi3_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_axi3

Coverpoints:

all_slaves : Captures all participating path cov slaves
slaves_excluding_register_space : Captures all non axi/ace register address space slaves
coherent_read_xact_type: Captures readonce coherent read transaction
coherent_write_xact_type: Captures coherent write transaction

Cross coverpoints:

cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type
cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

trans_lock_followed_by_excl_sequence

lock_followed_by_excl_sequence

lock_followed_by_excl_sequence:lock_followed_by_excl_seq

Coverage group for covering locked transaction followed by exclusive transaction
This will be covered when a locked read transaction followed by a exclusive read transaction is fired. Applicable only when axi_interface_type is AXI3. Bins:
lock_followed_by_excl_seq - lock transaction followed by exclusive transaction

trans_master_barrier_id_reuse_for_non_barrier

num_barrier_id_reuse_for_non_barrier

num_barrier_id_reuse_for_non_barrier:barrier_id_reuse

Covergroup: trans_master_barrier_id_reuse_for_non_barrier

This Covergroup captures number of ID used for barrier transaction and it is reused as normal type. It is constructed when interface_type is AXI_ACE and barrier_enable set to 1.

Coverpoints:

num_barrier_id_reuse_for_non_barrier: Captures the number of times that the ID used for barrier transaction is reused for a normal transaction

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4

trans_xact_domain_after_innershareable_barrier

axi_xact_domain_after_innershareable_barrier

axi_xact_domain_after_innershareable_barrier:innershareable_read_barrier_followed_by_nonshareable_read_xact, innershareable_read_barrier_followed_by_outershareable_read_xact, innershareable_read_barrier_followed_by_systemshareable_read_xact, innershareable_write_barrier_followed_by_nonshareable_write_xact, innershareable_write_barrier_followed_by_outershareable_write_xact, innershareable_write_barrier_followed_by_systemshareable_write_xact

Covergroup: trans_xact_domain_after_innershareable_barrier

This Covergroup captures innershareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_innershareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_innershareable_barrier: This is covered when:
- Master initiates inner-shareable transaction followed by inner-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with none/outer/system domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

trans_xact_domain_after_nonshareable_barrier

axi_xact_domain_after_nonshareable_barrier

axi_xact_domain_after_nonshareable_barrier:nonshareable_read_barrier_followed_by_innershareable_read_xact, nonshareable_read_barrier_followed_by_outershareable_read_xact, nonshareable_read_barrier_followed_by_systemshareable_read_xact, nonshareable_write_barrier_followed_by_innershareable_write_xact, nonshareable_write_barrier_followed_by_outershareable_write_xact, nonshareable_write_barrier_followed_by_systemshareable_write_xact

Covergroup: trans_xact_domain_after_nonshareable_barrier

This Covergroup captures nonshareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_nonshareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_nonshareable_barrier: This is covered when:
- Master initiates non-shareable transaction followed by non-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with inner/outer/system domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

trans_xact_domain_after_outershareable_barrier

axi_xact_domain_after_outershareable_barrier

axi_xact_domain_after_outershareable_barrier:outershareable_read_barrier_followed_by_nonshareable_read_xact, outershareable_read_barrier_followed_by_innershareable_read_xact, outershareable_read_barrier_followed_by_systemshareable_read_xact, outershareable_write_barrier_followed_by_nonshareable_write_xact, outershareable_write_barrier_followed_by_innershareable_write_xact, outershareable_write_barrier_followed_by_systemshareable_write_xact

Covergroup: trans_xact_domain_after_outershareable_barrier

This Covergroup captures outershareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_outershareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_outershareable_barrier: This is covered when:
- Master initiates outer-shareable transaction followed by outer-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with none/inner/system domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

trans_xact_domain_after_systemshareable_barrier

axi_xact_domain_after_systemshareable_barrier

axi_xact_domain_after_systemshareable_barrier:systemshareable_read_barrier_followed_by_nonshareable_read_xact, systemshareable_read_barrier_followed_by_innershareable_read_xact, systemshareable_read_barrier_followed_by_outershareable_read_xact, systemshareable_write_barrier_followed_by_nonshareable_write_xact, systemshareable_write_barrier_followed_by_innershareable_write_xact, systemshareable_write_barrier_followed_by_outershareable_write_xact

Covergroup: trans_xact_domain_after_systemshareable_barrier

This Covergroup captures systemshareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_systemshareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_aftershareable_barrier: This is covered when:
- Master initiates system-shareable transaction followed by outer-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with inner/outer/systemnone domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

Covergroup	Coverpoints	Bins
signal_state_acprot	acprot	acprot:svt_axi_data_secure_normal, svt_axi_data_secure_privileged, svt_axi_data_non_secure_normal, svt_axi_data_non_secure_privileged, svt_axi_instruction_secure_normal, svt_axi_instruction_secure_privileged, svt_axi_instruction_non_secure_normal, svt_axi_instruction_non_secure_privileged
signal_state_acsnoop	acsnoop	acsnoop:svt_axi_snoop_transaction_type_readonce, svt_axi_snoop_transaction_type_readshared, svt_axi_snoop_transaction_type_readclean, svt_axi_snoop_transaction_type_readnotshareddirty, svt_axi_snoop_transaction_type_readunique, svt_axi_snoop_transaction_type_cleanshared, svt_axi_snoop_transaction_type_cleaninvalid, svt_axi_snoop_transaction_type_makeinvalid, svt_axi_snoop_transaction_type_dvmcomplete, svt_axi_snoop_transaction_type_dvmmessage
signal_state_araddr	araddr_min_mid_max	araddr_min_mid_max:araddr_range_min, araddr_range_mid, araddr_range_max
signal_state_arbar	arbar	arbar:svt_axi_barrier_type_na_respbar, svt_axi_barrier_type_membar, svt_axi_barrier_type_na_ignbar, svt_axi_barrier_type_syncbar
signal_state_arburst	arburst	arburst:svt_axi_transaction_burst_fixed, svt_axi_transaction_burst_incr, svt_axi_transaction_burst_wrap
signal_state_arcache	arcache	arcache:svt_axi_3_non_cacheable_non_bufferable, svt_axi_3_bufferable_or_modifiable_only, svt_axi_3_cacheable_but_no_alloc, svt_axi_3_cacheable_bufferable_but_no_alloc, svt_axi_3_cacheable_wr_thru_alloc_on_rd_only, svt_axi_3_cacheable_wr_back_alloc_on_rd_only, svt_axi_3_cacheable_wr_thru_alloc_on_wr_only, svt_axi_3_cacheable_wr_back_alloc_on_wr_only, svt_axi_3_cacheable_wr_thru_alloc_on_both_rd_wr, svt_axi_3_cacheable_wr_back_alloc_on_both_rd_wr
signal_state_arcache_axi4	arcache	arcache:svt_axi_4_arcache_device_non_bufferable, svt_axi_4_arcache_device_bufferable, svt_axi_4_arcache_normal_non_cachable_non_bufferable, svt_axi_4_arcache_normal_non_cachable_bufferable, svt_axi_4_arcache_write_through_no_allocate, svt_axi_4_arcache_write_through_read_allocate, svt_axi_4_arcache_write_through_write_allocate, svt_axi_4_arcache_write_through_read_and_write_allocate, svt_axi_4_arcache_write_back_no_allocate, svt_axi_4_arcache_write_back_read_allocate, svt_axi_4_arcache_write_back_write_allocate, svt_axi_4_arcache_write_back_read_and_write_allocate
signal_state_ardomain	ardomain	ardomain:svt_axi_domain_type_nonshareable, svt_axi_domain_type_innershareable, svt_axi_domain_type_outershareable, svt_axi_domain_type_systemshareable
signal_state_arid	arid_min_mid_max	arid_min_mid_max:arid_range_min, arid_range_mid, arid_range_max
signal_state_arlen	arlen_min_mid_max	arlen_min_mid_max:arlen_range_min, arlen_range_mid, arlen_range_max
signal_state_arlock	arlock	arlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive, svt_axi_transaction_locked
signal_state_arlock_axi4	arlock	arlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive
signal_state_arprot	arprot	arprot:svt_axi_data_secure_normal, svt_axi_data_secure_privileged, svt_axi_data_non_secure_normal, svt_axi_data_non_secure_privileged, svt_axi_instruction_secure_normal, svt_axi_instruction_secure_privileged, svt_axi_instruction_non_secure_normal, svt_axi_instruction_non_secure_privileged
signal_state_arqos	arqos_min_mid_max	arqos_min_mid_max:arqos_range_min, arqos_range_mid, arqos_range_max
signal_state_arregion	arregion_min_mid_max	arregion_min_mid_max:arregion_range_min, arregion_range_mid, arregion_range_max
signal_state_arsize	arsize	arsize:svt_axi_transaction_burst_size_8, svt_axi_transaction_burst_size_16, svt_axi_transaction_burst_size_32, svt_axi_transaction_burst_size_64, svt_axi_transaction_burst_size_128, svt_axi_transaction_burst_size_256, svt_axi_transaction_burst_size_512, svt_axi_transaction_burst_size_1024
signal_state_arsnoop	arsnoop	arsnoop:arsnoop_zero, arsnoop_one, arsnoop_two, arsnoop_three, arsnoop_seven, arsnoop_eight, arsnoop_nine, arsnoop_eleven, arsnoop_twelve, arsnoop_thirteen, arsnoop_fourteen, arsnoop_fifteen
signal_state_aruser	aruser_min_mid_max	aruser_min_mid_max:aruser_range_min, aruser_range_mid, aruser_range_max
signal_state_awbar	awbar	awbar:svt_axi_barrier_type_na_respbar, svt_axi_barrier_type_membar, svt_axi_barrier_type_na_ignbar, svt_axi_barrier_type_syncbar
signal_state_awburst	awburst	awburst:svt_axi_transaction_burst_fixed, svt_axi_transaction_burst_incr, svt_axi_transaction_burst_wrap
signal_state_awcache	awcache	awcache:svt_axi_3_non_cacheable_non_bufferable, svt_axi_3_bufferable_or_modifiable_only, svt_axi_3_cacheable_but_no_alloc, svt_axi_3_cacheable_bufferable_but_no_alloc, svt_axi_3_cacheable_wr_thru_alloc_on_rd_only, svt_axi_3_cacheable_wr_back_alloc_on_rd_only, svt_axi_3_cacheable_wr_thru_alloc_on_wr_only, svt_axi_3_cacheable_wr_back_alloc_on_wr_only, svt_axi_3_cacheable_wr_thru_alloc_on_both_rd_wr, svt_axi_3_cacheable_wr_back_alloc_on_both_rd_wr
signal_state_awcache_axi4	awcache	awcache:svt_axi_4_awcache_device_non_bufferable, svt_axi_4_awcache_device_bufferable, svt_axi_4_awcache_normal_non_cachable_non_bufferable, svt_axi_4_awcache_normal_non_cachable_bufferable, svt_axi_4_awcache_write_through_no_allocate, svt_axi_4_awcache_write_through_read_allocate, svt_axi_4_awcache_write_through_write_allocate, svt_axi_4_awcache_write_through_read_and_write_allocate, svt_axi_4_awcache_write_back_no_allocate, svt_axi_4_awcache_write_back_read_allocate, svt_axi_4_awcache_write_back_write_allocate, svt_axi_4_awcache_write_back_read_and_write_allocate
signal_state_awdomain	awdomain	awdomain:svt_axi_domain_type_nonshareable, svt_axi_domain_type_innershareable, svt_axi_domain_type_outershareable, svt_axi_domain_type_systemshareable
signal_state_awid	awid_min_mid_max	awid_min_mid_max:awid_range_min, awid_range_mid, awid_range_max
signal_state_awlock	awlock	awlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive, svt_axi_transaction_locked
signal_state_awlock_axi4	awlock	awlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive
signal_state_awprot	awprot	awprot:svt_axi_data_secure_normal, svt_axi_data_secure_privileged, svt_axi_data_non_secure_normal, svt_axi_data_non_secure_privileged, svt_axi_instruction_secure_normal, svt_axi_instruction_secure_privileged, svt_axi_instruction_non_secure_normal, svt_axi_instruction_non_secure_privileged
signal_state_awqos	awqos_min_mid_max	awqos_min_mid_max:awqos_range_min, awqos_range_mid, awqos_range_max
signal_state_awsize	awsize	awsize:svt_axi_transaction_burst_size_8, svt_axi_transaction_burst_size_16, svt_axi_transaction_burst_size_32, svt_axi_transaction_burst_size_64, svt_axi_transaction_burst_size_128, svt_axi_transaction_burst_size_256, svt_axi_transaction_burst_size_512, svt_axi_transaction_burst_size_1024
signal_state_awsnoop	awsnoop	awsnoop:awsnoop_zero, awsnoop_one, awsnoop_two, awsnoop_three, awsnoop_four, awsnoop_five
signal_state_awuser	awuser_min_mid_max	awuser_min_mid_max:awuser_range_min, awuser_range_mid, awuser_range_max
signal_state_bid	bid_min_mid_max	bid_min_mid_max:bid_range_min, bid_range_mid, bid_range_max
signal_state_bresp	bresp	bresp:svt_axi_okay_response, svt_axi_exokay_response, svt_axi_slverr_response, svt_axi_decerr_response
signal_state_buser	buser_min_mid_max	buser_min_mid_max:buser_range_min, buser_range_mid, buser_range_max
signal_state_cddata	cddata_min_mid_max	cddata_min_mid_max:cddata_range_min, cddata_range_mid, cddata_range_max
signal_state_crresp	crresp	crresp:crresp_zero, crresp_one, crresp_two, crresp_three, crresp_five, crresp_seven, crresp_eight, crresp_nine, crrsep_ten, crresp_eleven, crresp_thirteen, crresp_fifteen, crresp_sixteen, crresp_seventeen, crresp_eighteen, crresp_nineteen, crresp_twentyone, crresp_twentythree, crresp_twentyfour, crresp_twentyfive, crresp_twentysix, crresp_twentyseven, crresp_twentynine, crresp_thirtyone
signal_state_rdata	rdata_min_mid_max	rdata_min_mid_max:rdata_range_min, rdata_range_mid, rdata_range_max
signal_state_rid	rid_min_mid_max	rid_min_mid_max:rid_range_min, rid_range_mid, rid_range_max
signal_state_rresp	rresp	rresp:svt_axi_okay_response, svt_axi_exokay_response, svt_axi_slverr_response, svt_axi_decerr_response
signal_state_rresp_ace	rresp	rresp:svt_axi_coherent_resp_type_unique_clean, svt_axi_coherent_resp_type_unique_dirty, svt_axi_coherent_resp_type_shared_clean, svt_axi_coherent_resp_type_shared_dirty
signal_state_ruser	ruser_min_mid_max	ruser_min_mid_max:ruser_range_min, ruser_range_mid, ruser_range_max
signal_state_tdest	tdest_min_mid_max	tdest_min_mid_max:tdest_range_min, tdest_range_mid, tdest_range_max
signal_state_tid	tid_min_mid_max	tid_min_mid_max:tid_range_min, tid_range_mid, tid_range_max
signal_state_tkeep	tkeep_min_mid_max	tkeep_min_mid_max:tkeep_range_min, tkeep_range_mid, tkeep_range_max
signal_state_tstrb	tstrb_min_mid_max	tstrb_min_mid_max:tstrb_range_min, tstrb_range_mid, tstrb_range_max
signal_state_tuser	tuser_min_mid_max	tuser_min_mid_max:tuser_range_min, tuser_range_mid, tuser_range_max
signal_state_wdata	wdata_min_mid_max	wdata_min_mid_max:wdata_range_min, wdata_range_mid, wdata_range_max
signal_state_wstrb	wstrb_min_mid_max	wstrb_min_mid_max:wstrb_range_min, wstrb_range_mid, wstrb_range_max
signal_state_wuser	wuser_min_mid_max	wuser_min_mid_max:wuser_range_min, wuser_range_mid, wuser_range_max
system_interleaved_ace_concurrent_outstanding_same_id	interleaved_ace_concurrent_outstanding_same_id	interleaved_ace_concurrent_outstanding_same_id:concurrent_outstanding_same_id_group_id
toggle_cov	signal_index	signal_index:toggle_bit_0to1, toggle_bit_1to0

Covergroup

Coverpoints

Bins

signal_state_acprot

acprot

acprot:svt_axi_data_secure_normal, svt_axi_data_secure_privileged, svt_axi_data_non_secure_normal, svt_axi_data_non_secure_privileged, svt_axi_instruction_secure_normal, svt_axi_instruction_secure_privileged, svt_axi_instruction_non_secure_normal, svt_axi_instruction_non_secure_privileged

signal_state_acsnoop

acsnoop

acsnoop:svt_axi_snoop_transaction_type_readonce, svt_axi_snoop_transaction_type_readshared, svt_axi_snoop_transaction_type_readclean, svt_axi_snoop_transaction_type_readnotshareddirty, svt_axi_snoop_transaction_type_readunique, svt_axi_snoop_transaction_type_cleanshared, svt_axi_snoop_transaction_type_cleaninvalid, svt_axi_snoop_transaction_type_makeinvalid, svt_axi_snoop_transaction_type_dvmcomplete, svt_axi_snoop_transaction_type_dvmmessage

signal_state_araddr

araddr_min_mid_max

araddr_min_mid_max:araddr_range_min, araddr_range_mid, araddr_range_max

signal_state_arbar

arbar

arbar:svt_axi_barrier_type_na_respbar, svt_axi_barrier_type_membar, svt_axi_barrier_type_na_ignbar, svt_axi_barrier_type_syncbar

signal_state_arburst

arburst

arburst:svt_axi_transaction_burst_fixed, svt_axi_transaction_burst_incr, svt_axi_transaction_burst_wrap

signal_state_arcache

arcache

arcache:svt_axi_3_non_cacheable_non_bufferable, svt_axi_3_bufferable_or_modifiable_only, svt_axi_3_cacheable_but_no_alloc, svt_axi_3_cacheable_bufferable_but_no_alloc, svt_axi_3_cacheable_wr_thru_alloc_on_rd_only, svt_axi_3_cacheable_wr_back_alloc_on_rd_only, svt_axi_3_cacheable_wr_thru_alloc_on_wr_only, svt_axi_3_cacheable_wr_back_alloc_on_wr_only, svt_axi_3_cacheable_wr_thru_alloc_on_both_rd_wr, svt_axi_3_cacheable_wr_back_alloc_on_both_rd_wr

signal_state_arcache_axi4

arcache

arcache:svt_axi_4_arcache_device_non_bufferable, svt_axi_4_arcache_device_bufferable, svt_axi_4_arcache_normal_non_cachable_non_bufferable, svt_axi_4_arcache_normal_non_cachable_bufferable, svt_axi_4_arcache_write_through_no_allocate, svt_axi_4_arcache_write_through_read_allocate, svt_axi_4_arcache_write_through_write_allocate, svt_axi_4_arcache_write_through_read_and_write_allocate, svt_axi_4_arcache_write_back_no_allocate, svt_axi_4_arcache_write_back_read_allocate, svt_axi_4_arcache_write_back_write_allocate, svt_axi_4_arcache_write_back_read_and_write_allocate

signal_state_ardomain

ardomain

ardomain:svt_axi_domain_type_nonshareable, svt_axi_domain_type_innershareable, svt_axi_domain_type_outershareable, svt_axi_domain_type_systemshareable

signal_state_arid

arid_min_mid_max

arid_min_mid_max:arid_range_min, arid_range_mid, arid_range_max

signal_state_arlen

arlen_min_mid_max

arlen_min_mid_max:arlen_range_min, arlen_range_mid, arlen_range_max

signal_state_arlock

arlock

arlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive, svt_axi_transaction_locked

signal_state_arlock_axi4

arlock

arlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive

signal_state_arprot

arprot

arprot:svt_axi_data_secure_normal, svt_axi_data_secure_privileged, svt_axi_data_non_secure_normal, svt_axi_data_non_secure_privileged, svt_axi_instruction_secure_normal, svt_axi_instruction_secure_privileged, svt_axi_instruction_non_secure_normal, svt_axi_instruction_non_secure_privileged

signal_state_arqos

arqos_min_mid_max

arqos_min_mid_max:arqos_range_min, arqos_range_mid, arqos_range_max

signal_state_arregion

arregion_min_mid_max

arregion_min_mid_max:arregion_range_min, arregion_range_mid, arregion_range_max

signal_state_arsize

arsize

arsize:svt_axi_transaction_burst_size_8, svt_axi_transaction_burst_size_16, svt_axi_transaction_burst_size_32, svt_axi_transaction_burst_size_64, svt_axi_transaction_burst_size_128, svt_axi_transaction_burst_size_256, svt_axi_transaction_burst_size_512, svt_axi_transaction_burst_size_1024

signal_state_arsnoop

arsnoop

arsnoop:arsnoop_zero, arsnoop_one, arsnoop_two, arsnoop_three, arsnoop_seven, arsnoop_eight, arsnoop_nine, arsnoop_eleven, arsnoop_twelve, arsnoop_thirteen, arsnoop_fourteen, arsnoop_fifteen

signal_state_aruser

aruser_min_mid_max

aruser_min_mid_max:aruser_range_min, aruser_range_mid, aruser_range_max

signal_state_awbar

awbar

awbar:svt_axi_barrier_type_na_respbar, svt_axi_barrier_type_membar, svt_axi_barrier_type_na_ignbar, svt_axi_barrier_type_syncbar

signal_state_awburst

awburst

awburst:svt_axi_transaction_burst_fixed, svt_axi_transaction_burst_incr, svt_axi_transaction_burst_wrap

signal_state_awcache

awcache

awcache:svt_axi_3_non_cacheable_non_bufferable, svt_axi_3_bufferable_or_modifiable_only, svt_axi_3_cacheable_but_no_alloc, svt_axi_3_cacheable_bufferable_but_no_alloc, svt_axi_3_cacheable_wr_thru_alloc_on_rd_only, svt_axi_3_cacheable_wr_back_alloc_on_rd_only, svt_axi_3_cacheable_wr_thru_alloc_on_wr_only, svt_axi_3_cacheable_wr_back_alloc_on_wr_only, svt_axi_3_cacheable_wr_thru_alloc_on_both_rd_wr, svt_axi_3_cacheable_wr_back_alloc_on_both_rd_wr

signal_state_awcache_axi4

awcache

awcache:svt_axi_4_awcache_device_non_bufferable, svt_axi_4_awcache_device_bufferable, svt_axi_4_awcache_normal_non_cachable_non_bufferable, svt_axi_4_awcache_normal_non_cachable_bufferable, svt_axi_4_awcache_write_through_no_allocate, svt_axi_4_awcache_write_through_read_allocate, svt_axi_4_awcache_write_through_write_allocate, svt_axi_4_awcache_write_through_read_and_write_allocate, svt_axi_4_awcache_write_back_no_allocate, svt_axi_4_awcache_write_back_read_allocate, svt_axi_4_awcache_write_back_write_allocate, svt_axi_4_awcache_write_back_read_and_write_allocate

signal_state_awdomain

awdomain

awdomain:svt_axi_domain_type_nonshareable, svt_axi_domain_type_innershareable, svt_axi_domain_type_outershareable, svt_axi_domain_type_systemshareable

signal_state_awid

awid_min_mid_max

awid_min_mid_max:awid_range_min, awid_range_mid, awid_range_max

signal_state_awlock

awlock

awlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive, svt_axi_transaction_locked

signal_state_awlock_axi4

awlock

awlock:svt_axi_transaction_normal, svt_axi_transaction_exclusive

signal_state_awprot

awprot

awprot:svt_axi_data_secure_normal, svt_axi_data_secure_privileged, svt_axi_data_non_secure_normal, svt_axi_data_non_secure_privileged, svt_axi_instruction_secure_normal, svt_axi_instruction_secure_privileged, svt_axi_instruction_non_secure_normal, svt_axi_instruction_non_secure_privileged

signal_state_awqos

awqos_min_mid_max

awqos_min_mid_max:awqos_range_min, awqos_range_mid, awqos_range_max

signal_state_awsize

awsize

awsize:svt_axi_transaction_burst_size_8, svt_axi_transaction_burst_size_16, svt_axi_transaction_burst_size_32, svt_axi_transaction_burst_size_64, svt_axi_transaction_burst_size_128, svt_axi_transaction_burst_size_256, svt_axi_transaction_burst_size_512, svt_axi_transaction_burst_size_1024

signal_state_awsnoop

awsnoop

awsnoop:awsnoop_zero, awsnoop_one, awsnoop_two, awsnoop_three, awsnoop_four, awsnoop_five

signal_state_awuser

awuser_min_mid_max

awuser_min_mid_max:awuser_range_min, awuser_range_mid, awuser_range_max

signal_state_bid

bid_min_mid_max

bid_min_mid_max:bid_range_min, bid_range_mid, bid_range_max

signal_state_bresp

bresp

bresp:svt_axi_okay_response, svt_axi_exokay_response, svt_axi_slverr_response, svt_axi_decerr_response

signal_state_buser

buser_min_mid_max

buser_min_mid_max:buser_range_min, buser_range_mid, buser_range_max

signal_state_cddata

cddata_min_mid_max

cddata_min_mid_max:cddata_range_min, cddata_range_mid, cddata_range_max

signal_state_crresp

crresp

crresp:crresp_zero, crresp_one, crresp_two, crresp_three, crresp_five, crresp_seven, crresp_eight, crresp_nine, crrsep_ten, crresp_eleven, crresp_thirteen, crresp_fifteen, crresp_sixteen, crresp_seventeen, crresp_eighteen, crresp_nineteen, crresp_twentyone, crresp_twentythree, crresp_twentyfour, crresp_twentyfive, crresp_twentysix, crresp_twentyseven, crresp_twentynine, crresp_thirtyone

signal_state_rdata

rdata_min_mid_max

rdata_min_mid_max:rdata_range_min, rdata_range_mid, rdata_range_max

signal_state_rid

rid_min_mid_max

rid_min_mid_max:rid_range_min, rid_range_mid, rid_range_max

signal_state_rresp

rresp

rresp:svt_axi_okay_response, svt_axi_exokay_response, svt_axi_slverr_response, svt_axi_decerr_response

signal_state_rresp_ace

rresp

rresp:svt_axi_coherent_resp_type_unique_clean, svt_axi_coherent_resp_type_unique_dirty, svt_axi_coherent_resp_type_shared_clean, svt_axi_coherent_resp_type_shared_dirty

signal_state_ruser