How to download VIP smartsearch?
DESIGNWARE_HOMEto required designware home location where VIP Smartsearch should be downloaded.
vip_smartsearch_<version>.runfile.
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
How to install VIP Smartsearch?
Please refer to the fileVIP_Smartsearch_installation_and_usage_guide.pdfin
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>for installation steps.
Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.Inheritance diagram for class svt_axi_transaction:
This is the base transaction type which contains all the physical attributes of the transaction like address, data, burst type, burst length, etc. It also provides the timing information of the transaction to the master & slave transactors, that is, delays for valid and ready signals with respect to some reference events.
The svt_axi_transaction also contains a handle to configuration object of type svt_axi_port_configuration , which provides the configuration of the port on which this transaction would be applied. The port configuration is used during randomizing the transaction.
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Generates an SVT pattern object to represent the properties which are to be written to FSDB. The pattern is customized to contain only the fields necessary for the application and tranaction type.
Note: As a performance enhancement, property values in the pattern are pre-populated when the pattern is created. This allows the FSDB writer infrastructure to skip the get_prop_val_via_pattern step.
Return values - An svt_pattern instance containing entries to be written to FSDB | ||||||||||
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This method is used to delate object_type for bus_activity when bus _activity ends on the bus . This methid is used by pa writer class in generating XML/FSDB
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Simple utility used to convert 'bit [1023:0]' property value representation into its equivalent string property value representation. Extended to support decoding of enum values.
prop_name - The name of the property being encoded. prop_val_string - The string describing the value to be encoded. prop_val - The bit vector encoding of prop_val_string. typ - Optional field type used to help in the encode effort.
Return values - The enum value corresponding to the desc. | ||||||
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This method allocates a pattern containing svt_pattern_data instances for all of the primitive data fields in the object. The name is set to the corresponding field name, the value is set to 0.
Return values - An svt_pattern instance containing entries for all of the data fields. | ||||||||||
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Extend the copy method to take care of the transaction fields and cleanup the exception xact pointers.
rhs - Source object to be copied. | ||||||||||||||
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Does a basic validation of this transaction object
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Simple utility used to convert string property value representation into its equivalent 'bit [1023:0]' property value representation. Extended to support encoding of enum values.
prop_name - The name of the property being encoded. prop_val_string - The string describing the value to be encoded. prop_val - The bit vector encoding of prop_val_string. typ - Optional field type used to help in the encode effort.
Return values - The enum value corresponding to the desc. | ||||||
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Method that returns the associative cache set index for the current transaction. Applicable only in case of coherent transactions, when svt_axi_port_configuration :: num_associative_cache_ways is set to 2. By default, it returns addr[("Num cache set index bits"-1):"Num byte offset bits"]. If the associative cache set index must be computed differently, this method must be overriden in an extended transaction class by the users. |
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Method to obtain the associative cache tag for the current transaction. Applicable only in case of coherent transactions, when svt_axi_port_configuration :: num_associative_cache_ways is set to 2. By default, it returns the tagged address itself as the associative cache tag. If the associative cache tag must be computed differently, this method must be overriden in an extended transaction class by the users. |
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Returns the address and lanes corresponding to the beat number
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Returns the address and lanes corresponding to the beat number
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Gets the beat number corresponding to an address
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returns burst size aligned address
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Gets the number of beats of data/resp to be sent.
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Gets the burst_size of a transaction.
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Gets the burst_type of a transaction.
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Returns the total number of bytes transferred in this transaction or beat number svt_axi_port_configuration :: get_byte_count_from_wstrb_enable set to 0, the byte count is calculated using burst_length and burst_size based on beat_num - Indicates the beat number for which the byte count is to be calculated. If set to -1, the total number of bytes for the entire transaction is calculated. If svt_axi_port_configuration :: get_byte_count_from_wstrb_enable is set to 1, the byte count is calculated using wstrb based on beat_num - Indicates the beat number for which the byte count is to be calculated. If set to -1, the total number of bytes for the entire transaction is calculated. Return values - The total number of bytes transferred in this transaction or beat number |
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Returns the byte lanes on which data is driven for a given data width
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Gets the current byte lane based on the current data beat, address and burst size
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Decodes the given snoop value(ARSNOOP/ACSNOOP) and returns the transaction type. This function can be used for the read address channel and the snoop address channel. snoop_val - The value on ARSNOOP/ACSNOOP |
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Decodes the given snoop value(AWSNOOP) and returns the transaction type. This function can be used for the write address channel. snoop_val - The value on AWSNOOP |
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Returns the encoding for ARSNOOP based on the transaction type Return values - The encoded value of ARSNOOP |
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Returns the encoding for AWSNOOP based on the transaction type Return values - The encoded value of AWSNOOP |
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Returns the encoding for AWSNOOP/ARSNOOP/ACSNOOP based on the transaction type Return values - The encoded value of AWSNOOP/ARSNOOP/ACSNOOP |
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Gets the maximum byte address which is addressed by this transaction
convert_to_global_addr - Indicates if the min and max address of this transaction must be translated to a global address before checking for overlap use_tagged_addr - Indicates whether a tagged address is provided convert_to_slave_addr - Indicates whether the address should be converted to a slave address requester_name - Name of the master component from which the transaction originated Return values - Maximum byte address addressed by this transaction |
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Returns the class name for the object used for logging.
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Gets the minimum byte address which is addressed by this transaction
convert_to_global_addr - Indicates if the min and max address of this transaction must be translated to a global address before checking for overlap use_tagged_addr - Indicates whether a tagged address is provided convert_to_slave_addr - Indicates whether the address should be converted to a slave address requester_name - Name of the master component from which the transaction originated Return values - Minimum byte address addressed by this transaction |
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This method returns PA object which contains the PA header information for XML or FSDB.
uid - Optional string indicating the unique identification value for object. If not provided uses the 'get_uid' method to retrieve the value. typ - Optional string indicating the 'type' of the object. If not provided uses the type name for the class. parent_uid - Optional string indicating the UID of the object's parent. If not provided the method assumes there is no parent. channel - Optional string indicating an object channel. If not provided the method assumes there is no channel.
Return values - The requested object block description. | ||||||||||||
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Ensures that only valid lanes have poison asserted. In wysisyg format the constraints leave data[] and poison[] open. This function is called in post_randomize to make sure that poison[] is asserted only for valid lanes
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HDL Support: For read access to public data members of this class.
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Returns the channel on which a transaction will be transmitted Return values - The channel (READ/WRITE) on which this transaction will be transmitted. |
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This method is used in setting the unique identification id for the objects of bus activity This method returns a string which holds uid of bus activity object This is used by pa writer class in generating XML/FSDB
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returns lowest address of the transaction. For WRAP type of transaction it indicates starting address after transaction statisfies WRAP condition and wraps over to include lower addresses
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Returns the index (of data or wstrb fields) corresponding to the wrap boundary
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Ensures that only valid lanes have wstrb asserted. In wysisyg format the constraints leave data[] and wstrb[] open. This function is called in post_randomize to make sure that wstrb is asserted only for valid lanes
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Returns 1 if the specified error_kind is there in transaction, else returns 0
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returns 1 if status of all relevant phases of current transaction are assigned as ABORTED
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Checks if the transaction crosses the 4kb boundary
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Checks if the given address range overlaps with the address range of this transaction
min_addr - The minimum address of the address range be checked max_addr - The maximum address of the address range be checked convert_to_global_addr - Indicates if the min and max address of this transaction must be translated to a global address before checking for overlap use_tagged_addr - Indicates whether a tagged address is provided convert_to_slave_addr - Indicates whether the address should be converted to a slave address requester_name - Name of the master component from which the transaction originated Return values - Returns 1 if there is an address overlap, else returns 0. |
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Returns 1 if current transaction is allocate transaction
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Indicates if this transaction is applicable for updates in the FIFO rate control model Return values - Returns 1 if applicable, else returns 0 |
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Returns 1 if current transaction is cacheable transaction
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Determines if this transaction is a CMO transaction on Read channel
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Determines if this transaction is a CMO transaction
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Checks if the coherent transaction is DVM Sync
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Returns 1 if current transaction is of device_type
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Returns 1 if current transaction is DVM transaction
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Calculates whether the transaction is partial or full cacheline access. returns 1, if transaction is full cacheline access. returns 0, if it is a partial cacheline access.
cacheline_size - indicates the value of the master cache line size |
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Determines if this transaction is a PCMO transaction on write channel
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returns 1 if current transaction is configured as secure access physical addr range
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Indicates whether the current transaction is supported in CHI System monitor
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returns 1 if transaction status fields are ABORTED, or it is dropped; otherwise returns 0
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returns 1 if transaction status shows ended otherwise 0
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Limits the data to what can be transmitted if the address is unaligned. If the address is unaligned, we need to take care that data[0] and wstrb[0] are consistent with what can actually be driven on the bus. For example, for a 64 bit bus, if the address is 0x7, data can be sent only on 1 byte for the first beat. For a FIXED burst the address is same for all beats, so this operation needs to be done for all beats. For other bursts, only the first address can be unaligned, other beats are aligned addresses data_only - (Optional: default = 0) If this bit is set the operation is done only for data. beat_num - (Optional: default = -1) Applicable for a FIXED burst. When set to -1, masking is done for all beats, otherwise it is done only for the selected beat. |
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Ensures that valid x,z,0,1 all four state datas are calculated with respect to data_mask values. This function is called under SVT_MEM_LOGIC_DATA macro define only, to make sure while masking valid x and z state data also considered towards masked data.
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CONSTUCTOR: Create a new transaction instance, passing the appropriate argument values to the parent class.
name - Instance name of the transaction | ||||||||
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Returns the data in the data_to_pack[] field as a byte stream based on the burst_type. The assumption is that either data[] or cache_write_data[] fields of this class have been passed as arguments to data_to_pack[] field. In the case of WRAP bursts the data is returned such that packed_data[0] corresponds to the data for the wrap boundary. In the case of INCR bursts, the data as passed in data_to_pack[] is directly packed to packed_data[]. data_to_pack - Data to be packed packed_data - [] Output byte stream with packed data |
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Returns the data_user in the data_to_pack[] field as a byte stream based on the burst_type. The assumption is that data_user[] has been passed as arguments to data_to_pack[] field. In the case of WRAP bursts the data_user is returned such that packed_data[0] corresponds to the data for the wrap boundary. In the case of INCR bursts, the data_user as passed in data_to_pack[] is directly packed to packed_data[]. data_to_pack - Data to be packed packed_data - [] Output byte stream with packed data |
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Returns the poison in the poison_to_pack[] field as a byte stream based on the burst_type. The assumption is that either poison[] or cache_write_poison[] fields of this class have been passed as arguments to data_to_pack5[] field. In the case of WRAP bursts the data is returned such that packed_poison[0] corresponds to the poison for the wrap boundary. In the case of INCR bursts, the poison as passed in poison_to_pack[] is directly packed to packed_poison[]. poison_to_pack - poison to be packed packed_poison - [] Output byte stream with packed poison |
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Returns the wstrb in the wstrb_to_pack[] field as a byte stream based on the burst_type. In the case of WRAP bursts the wstrb is returned such that packed_wstrb[0] corresponds to the wstrb for the wrap boundary. In the case of INCR bursts, the wstrb as passed in wstrb_to_pack[] is directly packed to packed_wstrb[]. wstrb_to_pack - wstrb to be packed packed_wstrb - [] Output byte stream with packed wstrb |
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Generates an SVT pattern object to represent the properties which are to be written to FSDB when the PA channel is RADDR, RDATA, WADDR, WDATA, or WRESP.
Return values - An svt_pattern instance containing entries to be written to FSDB |
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Generates an SVT pattern object to represent the properties which are to be written to FSDB when a full tranaction is to be recorded. Note that not all properties are written. Instead, only properties needed for debug are added.
Return values - An svt_pattern instance containing entries to be written to FSDB |
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Populates the partial data and byteen provided into data and byteen that is used to write into a full cacheline
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Generates an SVT pattern object to represent the properties which are to be written to FSDB when the pa_format_type is set to FSDB_PERF_ANALYSIS.
Return values - An svt_pattern instance containing entries to be written to FSDB |
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Generates an SVT pattern object to represent the properties which are to be written to FSDB when the PA channel is "STREAM DATA".
Return values - An svt_pattern instance containing entries to be written to FSDB |
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post_randomize does the following 1) Aligns the address to no of Bytes for Exclusive Accesses
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pre_randomize does the following 1) Tests the validity of the configuration 2) calculate the log_2 of master configs data_width
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Returns a string (with no line feeds) that reports the essential contents of the packet generally necessary to uniquely identify that packet.
prefix - (Optional: default = "") The string given in this argument becomes the first item listed in the value returned. It is intended to be used to identify the transactor (or other source) that requested this string. This argument should be limited to 8 characters or less (to accommodate the fixed column widths in the returned string). If more than 8 characters are supplied, only the first 8 characters are used. hdr_only - (Optional: default = 0) If this argument is supplied, and is '1', the function returns a 3-line table header string, which indicates which packet data appears in the subsequent columns. If this argument is '1', the prefix argument becomes the column label for the first header column (still subject to the 8 character limit). | ||||
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Method to turn reasonable constraints on/off as a block.
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Unsets the suspend_master_xact property
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Sets the configuration property
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mark end of transaction
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This method is used to set object_type for bus_activity when bus_activity is getting started on the bus . This method is used by pa writer class in generating XML/FSDB
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HDL Support: For write access to public data members of this class.
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Sets the suspend_master_xact property
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Extend the svt_post_do_all_do_copy method to cleanup the exception xact pointers.
to - Destination class for the copy operation | ||||
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Unpacks the data in data_to_unpack[] into utemp_datanpacked_data. For an INCR burst, the data is directly unpacked into unpacked_data For a WRAP burst, the data is unpacked such that unpacked_data[0] corresponds to the starting address. The assumption here is that data_to_unpack[] has a byte stream whose data starts from the address corresponding to the wrap boundary data_to_unpack - The data to unpack. unpacked_data - The unpacked data. |
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Unpacks the data_user in data_to_unpack[] into utemp_datanpacked_data. For an INCR burst, the data_user is directly unpacked into unpacked_data For a WRAP burst, the data_user is unpacked such that unpacked_data[0] corresponds to the starting address. The assumption here is that data_to_unpack[] has a byte stream whose data_user starts from the address corresponding to the wrap boundary data_to_unpack - The data to unpack. unpacked_data - The unpacked data. |
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Unpacks the poison in poison_to_unpack[] into unpacked_poison. For an INCR burst, the poison is directly unpacked into unpacked_poison For a WRAP burst, the poison is unpacked such that unpacked_poison[0] corresponds to the starting address. The assumption here is that poison_to_unpack[] has a byte stream whose poison starts from the address corresponding to the wrap boundary poison_to_unpack - The poison to unpack. unpacked_poison - The unpacked poison. |
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Unpacks the wstrb in wstrb_to_unpack[] into unpacked_wstrb. For an INCR burst, the wstrb is directly unpacked into unpacked_wstrb For a WRAP burst, the wstrb is unpacked such that unpacked_wstrb[0] corresponds to the starting address. The assumption here is that wstrb_to_unpack[] has a byte stream whose wstrb starts from the address corresponding to the wrap boundary wstrb_to_unpack - The wstrb to unpack. unpacked_wstrb - The unpacked wstrb. |
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waits for addr phase to end
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waits for data phase to end
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waits for transaction to end
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waits for write resp phase to end
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waits for slave transaction to update the memory
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Represents the status of the read/write acknowledge sent via RACK/WACK for ACE interface. RACK/WACK is asserted for a single cycle. Following are the possible status types:
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The variable represents AWADDR when xact_type is WRITE and ARADDR when xact_type is READ. The maximum width of this signal is controlled through macro SVT_AXI_MAX_ADDR_WIDTH. Default value of this macro is 64. To change the maximum width of this variable, user can change the value of this macro. Define the new value for the macro in file svt_axi_user_defines.svi, and then specify this file to be compiled by the simulator. Also, specify +define+SVT_AXI_INCLUDE_USER_DEFINES on the simulator compilation command line. Please consult User Guide for additional information, and consult VIP example for usage demonstration. The SVT_AXI_MAX_ADDR_WIDTH macro is only used to control the maximum width of the signal. The actual width used by VIP is controlled by configuration parameter svt_axi_port_configuration :: addr_width. |
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This variable stores the timing information for address ready on read and write transactions. The simulation clock cycle number when the address valid and ready both are asserted i.e. handshake happens, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for address ready on read and write transactions. The simulation time number when the address valid and ready both are asserted i.e. handshake happens, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This members applies to AWREADY signal delay for write transactions, and ARREADY signal delay for read transactions.
If configuration parameter svt_axi_port_configuration :: default_awready or svt_axi_port_configuration :: default_arready is FALSE, this member defines the AWREADY or ARREADY signal delay in number of clock cycles. The reference event used for this delay is reference_event_for_addr_ready_delay. If configuration parameter svt_axi_port_configuration :: default_awready or svt_axi_port_configuration :: default_arready is TRUE, this member defines the number of clock cycles for which AWREADY or ARREADY signal should be deasserted after each handshake, before pulling it up again to its default value. Applicable for ACTIVE SLAVE only. |
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Represents the current status of the read or write address. Following are the possible status types.
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The variable holds the value for signals AWUSER/ARUSER. Applicable for all interface types. Enabled through port configuration parameters svt_axi_port_configuration :: aruser_enable and svt_axi_port_configuration :: awuser_enable.
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This variable stores the cycle information for address valid on read and write transactions. The simulation clock cycle number when the address valid is asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for address valid on read and write transactions. The simulation time when the address valid is asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable defines the number of cycles the AWVALID or ARVALID signal is delayed. The reference event for this delay is reference_event_for_addr_valid_delay. Applicable for ACTIVE MASTER only.
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This variable stores the cycle information for address wakeup of read or write transaction. The simulation clock cycle number when the address wakeup is asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for address wakeup of read or write transaction. The simulation time when the address wakeup is asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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Indicates that the data as given in cache_write_data [] in this transaction needs to be allocated in the cache. Applicable only when transaction type is READUNIQUE or CLEANUNIQUE. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE.
Applicable for ACTIVE MASTER only. |
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The variable represents ARVMIDEXT when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE with svt_axi_system_configuration :: DVMV8_1 or above. The maximum width of this signal is controlled through macro SVT_AXI_MAX_VMIDEXT_WIDTH. Default value of this macro is 4 based on DVMv8.1 architecture recomendation.
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if this bit is set to '0' then AWAKEUP signal will be asserted before ARVALID or AWVALID with respect to awakeup_assert_delay. if this bit is set to '1' then AWAKEUP signal will be asserted after ARVALID or AWVALID with respect to awakeup_assert_delay. Applicable for ACTIVE MASTER only.
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This member points to a barrier pair transaction associated to this current transaction. When associated_barrier_xact is null, it indicates that this current transaction is not a post-barrier transaction. When associated_barrier_xact is non-null, this current transaction will wait for responses from the barrier transactions in associated_barrier_xact, before it can be transmitted.
associated_barrier_xact can be set in the callback svt_axi_master_callback :: associate_xact_to_barrier_pair. In this callback, user can associate this transaction with a barrier transaction pair. Please refer to User Guide for more details on usage of this member. |
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When this bit is set by user, it indicates that this transaction is a post-barrier transaction and that it needs to wait for responses from the barrier transaction pair indicated in associated_barrier_xact. associated_barrier_xact can be set in the callback svt_axi_master_callback :: associate_xact_to_barrier_pair. In this callback, user can associate this transaction with a barrier transaction pair.
Please refer to User Guide for more description. |
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Represents the set index in the associative cache that contains the cacheline corresponding to the transaction address. Applicable only in case of coherent, cacheable transactions initiated from active ACE master VIP with an n-way associative cache (svt_axi_port_configuration :: num_associative_cache_ways > 0). Will be automatically populated by the active ACE master driver before the request is driven out on the interface and is a read-only field for users. In case of coherent transactions that allocate the cache, the value of this field is determined by the API "get_associative_cache_set_index". For all other coherent non-allocating transactions, the value of this field is determined by the properties of the corresponding cacheline. Default value: -1. |
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Represents the Tag value of the associative cache entry that contains the cacheline corresponding to the transaction address. Applicable only in case of coherent, cacheable transactions initiated from active ACE master VIP with an n-way associative cache (svt_axi_port_configuration :: num_associative_cache_ways > 0). Will be automatically populated by the active ACE master driver before the request is driven out on the interface and is a read-only field for users. In case of coherent transactions that allocate the cache, the value of this field is determined by the API "get_associative_tag". For all other coherent non-allocating transactions, the value of this field is determined by the properties of the corresponding cacheline. Default value: 0. |
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Represents the way number within the associative cache set that contains the cacheline corresponding to the transaction address. Applicable only in case of coherent, cacheable transactions initiated from active ACE master VIP with an n-way associative cache (svt_axi_port_configuration :: num_associative_cache_ways > 0). Will be automatically populated by the active ACE master driver before the request is driven out on the interface and is a read-only field for users. Default value: -1. |
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Represents the atomic access of a transaction. The variable holds the value for AWLOCK/ARLOCK. Following are the possible atomic types:
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Defines the delay in number of cycles for AWAKEUP signal assertion before or after ARVALID or AWVALID signal. Applicable for ACTIVE MASTER only
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Defines the delay in number of cycles for AWAKEUP signal deassertion after ARVALID-ARREADY or AWVALID-AWREADY signal handshake. Applicable for ACTIVE MASTER only.
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This variable represents barrier transaction type. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE.
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If configuration parameter svt_axi_port_configuration :: default_bready is FALSE, this member defines the BREADY signal delay in number of clock cycles. The reference event for this delay is reference_event_for_bready_delay.
If configuration parameter svt_axi_port_configuration :: default_bready is TRUE, this member defines the number of clock cycles for which BREADY signal should be deasserted after each handshake, before pulling it up again to its default value. Applicable for ACTIVE MASTER only. |
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This variable specifies the response for write transaction. The variable holds the value for BRESP. Following are the possible response types:
MASTER ACTIVE MODE: Will Store the write response received from the slave. SLAVE ACTIVE MODE: The write response programmed by the user. PASSIVE MODE - MASTER/SLAVE: Stores the write response seen on the bus. |
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The variable represents the actual length of the burst. For eg. burst_length = 1 means a burst of length 1.
If svt_axi_port_configuration :: axi_interface_type is AXI3, burst length of 1 to 16 is supported. If svt_axi_port_configuration :: axi_interface_type is AXI4, burst length of 1 to 256 is supported. |
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Represents the burst size of a transaction . The variable holds the value for AWSIZE/ARSIZE.
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Represents the burst type of a transaction. The burst type holds the value for AWBURST/ARBURST. Following are the possible burst types:
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Defines the BVALID delay in terms of number of clock cycles. The reference event for this delay is reference_event_for_bvalid_delay.
Applicable for ACTIVE SLAVE only. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE. Users who need to bypass lookup of cache to determine valid initial cache line states can set this property to 1. In order to randomize this property to 1, the user must switch off svt_axi_master_transaction :: reasonable_bypass_cache_lookup constraint. Setting this property will enable transactions to be sent out even if the initial cache state does not meet requirements set by ACE protocol. Please note that coherency is not guaranteed when this property is set
Applicable for ACTIVE MASTER only. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE.
Indicates if update of cache must be bypassed for this transaction. A typical use model is to set this bit in pre_cache_update callback of the driver based on response received in the transaction. For example, if the response received is SLVERR, user may not want the driver to update the cache. When using this property, it is the user's responsibility that system coherency is not lost, since cache will not be updated. Applicable for ACTIVE MASTER only. |
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Represents the cache support of a transaction. The variable holds the value for AWCACHE/ARCACHE.
Following values are supported in AXI3 mode:
Following values for ARCACHE are supported in AXI4 mode:
Following values for AWCACHE are supported in AXI4 mode:
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE.
Represents data that needs to be stored to the cache if the allocate_in_cache bit is set for a READUNIQUE/CLEANUNIQUE transaction or if the transaction is MAKEUNIQUE. Applicable to masters in active mode. Refer section 3.6 of ACE specification. Writes in ACE are performed by removing all other copies of the cache line so that the master that is performing the write has a unique copy at the time of writing. Depending on whether a paritial or full update of a cache line is required a transaction such as READUNIQUE,MAKEUNIQUE or CLEANUNIQUE is sent. Some of these transactions such as READUNIQUE will return data (either from memory or the cache of some other master) and this will be available in the data[] field of this class. Other transactions such as MAKEUNIQUE and CLEANUNIQUE will not return any data. For a READUNIQUE transaction, if the allocate_in_cache bit is not set, the data available in data[] is written in cache. If the allocate_in_cache bit is set the data available in this variable is written to cache. Note however, that this variable is overwritten by the data that is received in data[] prior to writing in the cache. This is done because READUNIQUE is used for partial update of a cacheline when a master does not have a copy of the cacheline. So a user can actually populate this variable after a copy of this cacheline is received and not at the time of randomization. For a CLEANUNIQUE transaction, if the allocate_in_cache bit is set, the data in this variable is written to cache. For a MAKEUNIQUE transaction, the data in this variable is always written into the cache. Updating this variable is normally done in the pre_cache_update callback issued by the master driver after all the responses are received but prior to the RACK signal being driven. An important aspect of this variable is that this data is not driven on the physical bus. Applicable for ACTIVE MASTER only. |
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If set, the driver checks if this transaction accesses a location addressed by a previous transaction from this port or from some other master. If there are any such previous transactions, this transaction is blocked until all those transactions complete. Also, the driver does not pull any more transactions until this transaction is unblocked. If not set, this transaction is not checked for access to a location which was previously accessed by another transaction. When svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM then setting of this attribute to 1 is not applicable, VIP will override it to 0. Applicable only when svt_axi_system_configuration :: overlap_addr_access_control_enable is set
Applicable for ACTIVE MASTER only |
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This variable represents the shareable coherent transaction types. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE.
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Array for the coherent read responses. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE.
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This is a counter which is incremented for every beat. Useful when user would try to access the transaction class to know its current state. This represents the beat number for which the status is reflected in member data_status.
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Multibit array for different usages.
If cust_xact_flow[0] is set to '1', indicate that transaction should be drived immediately on the interface. This is aplicable only for AXI4 STREAM transactions. cust_xact_flow[31:1] bits are for future use. |
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MASTER in active mode:
For write transactions this variable specifies write data to be driven on the WDATA bus. SLAVE in active mode: For read transactions this variable specifies read data to be driven on the RDATA bus. PASSIVE MODE: This variable stores the write or read data as seen on WDATA or RDATA bus.
APPLICABLE IN ALL MODES: If svt_axi_port_configuration :: wysiwyg_enable is set to 0 (default), the data must be stored right-justified by the user. The model will drive the data on the correct lanes. If svt_axi_port_configuration :: wysiwyg_enable is set to 1, the data is transmitted as programmed by user and is reported as seen on bus. No right-justification is used in this case. |
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Indicates that data will start before address for write transactions. In data_before_addr scenario (i.e., when data_before_addr = '1'), addr and data channel related delay considerations are: 1) For programming address_channel related delay: awvalid_delay and reference_event_for_addr_valid_delay are used. (for more information, look for the description of these variables). reference_event_for_addr_valid_delay should be set FIRST_WVALID_DATA_BEFORE_ADDR. In data_before_addr scenarios reference_event_for_addr_delay should be set very carefully to FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR as this may cause potential deadlock scenarios in SLAVE DUT where slave DUT waits for awvalid signal before driving wready signal. 2) For programming data_channel related delay: wvalid_delay[] and reference_event_for_first_wvalid_delay & reference_event_for_next_wvalid_delay are used. (for more information, look for the description of these variables). For wvalid_delay[0] - reference_event_for_first_wvalid_delay For remaining indices of wvalid_delay - reference_event_for_next_wvalid_delay In data_before_addr scenario, reference_event_for_first_wvalid_delay must be PREV_WRITE_DATA_HANDSHAKE, otherwise it will cause failure. .
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Represents the status of the read or write data transfer. Following are the possible status types.
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The variable holds the value for signals WUSER/RUSER. Applicable for all interface types. Enabled through port configuration parameters svt_axi_port_configuration :: wuser_enable and svt_axi_port_configuration :: ruser_enable.
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This variable represents the data check parity bit's with respect to valid data. It consists of a bit for each 8 data byte in the transaction data. Each bit of parity check data is calculated from every 8bit of data. Applicable when svt_axi_port_configuration :: check_type is set to ODD_PARITY_BYTE_DATA or ODD_PARITY_BYTE_ALL.
Active Master.
Active Slave.
Passive components.
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This variable stores the timing information for the data channnel blocking ratio. The blocking cycle for a beat is defined as the number of cycles that valid was asserted, but corresponding ready was not asserted. This ratio is derived from data_valid_assertion_cycle and data_ready_assertion_cycle, calculated as sum of data ready blocking cycles divided by sum of data valid assertion cycles. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for data ready on read and write transactions. The simulation clock cycle number when the data valid and ready both are asserted, is captured in this member. This variable is also applicable for AXI4_STREAM protocol and it will hold tready assertion cycle. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for data ready on read and write transactions. The simulation time when the data valid and ready both are asserted, is captured in this member. This variable is also applicable for AXI4_STREAM protocol and it will hold tready assertion time. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the cycle information for data valid on read and write transactions. The simulation clock cycle number when the data valid is asserted, is captured in this member. This variable is also applicable for AXI4_STREAM protocol and it will hold tvalid assertion cycle. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for data valid on read and write transactions. The simulation time when the data valid is asserted, is captured in this member. This variable is also applicable for AXI4_STREAM protocol and it will hold tvalid assertion time. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable represents the shareability domain of coherent transactions. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE.
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE. Defines the delay between reception of DVM Sync and transmission of DVM Complete. Delay for master component in terms of number of clock cycles for generating DVM Complete transaction after receiving a DVM Sync transaction.
Applicable for ACTIVE MASTER only. |
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Indicates the value of the source master which will be propogated in the ID field of the master and the corresponding slave transaction. Applicable for users who want to correlate master transactions to slave transactions in the system monitor. This parameter is applicable when svt_axi_port_configuration :: source_master_id_xmit_to_slaves_type is set to DYNAMIC_SOURCE_MASTER_ID_XMIT_TO_SLAVES. This property must be set by the user in a system monitor callback issued at the start of a transaction
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This variable controls enabling of interleaving for the current transaction. In case of AXI4_STREAM interface type for active master, setting this variable to 1 is applicable only when svt_axi_port_configuration :: stream_interleave_depth is greater than 1. Example: svt_axi_port_configuration :: read_data_reordering_depth = 2 Requirement: Unless all beats of transaction 1 are sent out, the beats of 2nd transactions should not be sent. Solution: Program the enable_interleave = 0 for both the transaction 1. |
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Represents the status of coherent exclusive access. Following are the possible status types:
A combination of excl_access_status and excl_mon_status can be used to determine the reason for failure of exclusive store. Please refer to the User Guide for more description. |
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Represents the status of master exclusive monitor, which indicates the cause of failure for a coherent exclusive store. It is valid only for exclusive store transaction, that is, CleanUnique. For all other transactions it is set to EXCL_MON_INVALID by default. Following are the possible status types:
A combination of excl_access_status and excl_mon_status can be used to determine the reason for failure of exclusive store. Please refer to the User Guide for more description. |
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This variable represents the final cache line data. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE. The final cache line data of a transaction is the data of the the line just before the transaction ended.
Applicable for ACTIVE MASTER only. |
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This variable represents the final cache line state. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE. The final cache line state of a transaction is the state of the the line just before the transaction ended. This variable is updated by the VIP, and is a read-only variable. User is not expected or supposed to modify this variable.
Applicable for ACTIVE MASTER only. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE. Indicates if the cache line state needs to be forced to an invalid state even if that is not the recommended state, since it is permissible for a cache line which is in a clean state to be held in the invalid state. Valid only when: svt_axi_port_configuration :: cache_line_state_change_type is set to LEGAL_WITHOUT_SNOOP_FILTER_CACHE_LINE_STATE_CHANGE.
Applicable for ACTIVE MASTER only. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE. Indicates if the cache line state needs to be forced to a shared state even if the actual state of the line is unique, since it is permissible for a cache line which is in the unique state to be held in the shared state. Valid only when: svt_axi_port_configuration :: cache_line_state_change_type is set to LEGAL_WITH_SNOOP_FILTER_CACHE_LINE_STATE_CHANGE or LEGAL_WITHOUT_SNOOP_FILTER_CACHE_LINE_STATE_CHANGE.
Applicable for ACTIVE MASTER only. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE. Forces transactions which are not constrained to be of cacheline size by protocol to be of cacheline size. Currently applicable only to READONCE, WRITEUNIQUE, WRITENOSNOOP and READNOSNOOP transactions. Applicable to WRITENOSNOOP and READNOSNOOP only when svt_axi_port_configuration :: update_cache_for_non_coherent_xacts is set and svt_axi_port_configuration :: axi_interface_type is AXI_ACE. If this bit is set, READONCE and WRITEUNIQUE transactions will be forced to cache line size transactions. This has a dependency on svt_axi_port_configuration :: force_xact_to_cache_line_size_interface_type.
Applicable for ACTIVE MASTER only. |
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The variable holds the value of AWID/WID/BID/ARID/RID signals. The maximum width of this signal is controlled through macro SVT_AXI_MAX_ID_WIDTH. Default value of this macro is 8. To change the maximum width of this variable, user can change the value of this macro. Define the new value for the macro in file svt_axi_user_defines.svi, and then specify this file to be compiled by the simulator. Also, specify +define+SVT_AXI_INCLUDE_USER_DEFINES on the simulator compilation command line. Please consult User Guide for additional information, and consult VIP example for usage demonstration. The SVT_AXI_MAX_ID_WIDTH macro is only used to control the maximum width of the signal. The actual width used by VIP is controlled by configuration parameter svt_axi_port_configuration :: id_width. |
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Applicable when svt_axi_port_configuration :: toggle_ready_signals_during_idle_period is set. Applicable for slave VIP.
Indicates the number of cycles for which awready and arready should be high and low when the corresponding address channel is idle, that is, when AWVALID/ARVALID is low. This property helps to toggle the AWREADY/ARREADY signal during the idle period between the assertion of AWVALID/ARVALID signal of this transaction and the next transaction. This value may be assigned during randomization of the transaction object in the slave sequence. Values provided in even numbered indices indicate the number of clocks for which the ready signal must be driven low and the values in odd numbered indices indicate the number of clocks for which it must driven high. Values in this variable are applicable only until the corresponding valid is asserted. When AWVALID/ARVALID is observed on the interface, this delay is no longer applicable and the delay specified in addr_ready_delay is applied before asserting AWREADY/ARREADY. Note that toggling AWREADY/ARREADY during the idle period may lead to situations where the AWREADY/ARREADY signal is already asserted when the corresponding valid is sampled, even though the value of svt_axi_port_configuration :: default_awready or svt_axi_port_configuration :: default_arready is low. Similarly, AWREADY/ARREADY may be low when the corresponding valid is sampled, even though the value of svt_axi_port_configuration :: default_awready or svt_axi_port_configuration :: default_arready is high. In both these cases, addr_ready_delay is not applicable. The size of this array can be set to any value greater than 0, based on the number of times the user would like the signal to toggle during idle period. |
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Applicable when svt_axi_port_configuration :: toggle_ready_signals_during_idle_period is set. Applicable for master VIP.
Indicates the number of cycles for which BREADY should be high and low when the write response channel is idle, that is, when BVALID is low. This property helps to toggle the BREADY signal during the idle period between the assertion of BVALID signal. The value for this property may be set when the transaction is randomized at the master or in a callback such as svt_axi_port_monitor_callback :: write_resp_phase_started. Values provided in even numbered indices indicate the number of clocks for which the ready signal must be driven low and the values in odd numbered indices indicate the number of clocks for which it must driven high. Values in this variable are applicable only until BVALID is asserted. When BVALID is observed on the interface, this delay is no longer applicable. The delay specified in bready_delay is applied before this attribute is applied. Note that toggling BREADY during the idle period may lead to situations where the BREADY signal is already asserted when BVALID is sampled, even though the value of svt_axi_port_configuration :: default_bready is low. Similarly, BREADY may be low when the corresponding valid is sampled, even though the value of svt_axi_port_configuration :: default_bready is high. In both these cases, bready_delay is not applicable. The size of this array can be set to any value greater than 0, based on the number of times the user would like the signal to toggle during idle period. |
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This variable stores the timing information for wakeup of idle read or write channel. The simulation time when the wakeup is asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for wakeup of idle read or write channel. The simulation time when the wakeup is deasserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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Applicable when svt_axi_port_configuration :: toggle_ready_signals_during_idle_period is set. Applicable for master VIP.
Indicates the number of cycles for which RREADY should be high and low when the read data channel is idle, that is, when RVALID is low. This property helps to toggle the RREADY signal during the idle period between the assertion of RVALID signal. Values provided in even numbered indices indicate the number of clocks for which the ready signal must be driven low and the values in odd numbered indices indicate the number of clocks for which it must driven high. Note that the values provided in this variable are applied for all read data beats. If the user requires a different set of delays during the idle period for each beat, the user must use the read_data_phase_started callback to change the values of this property for the corresponding beat. Once changed, the values will be applicable for all subsequent beats of the transaction unless it is is changed for a subsequent beat. Values in this variable are applicable only until RVALID is asserted. When RVALID is observed on the interface, this delay is no longer applicable. The delay specified in rready_delay [] is applied before this property is used. Note that toggling RREADY during the idle period may lead to situations where the RREADY signal is already asserted when the RVALID is sampled, even though the value of svt_axi_port_configuration :: default_rready is low. Similarly, RREADY may be low when the corresponding valid is sampled, even though the value of svt_axi_port_configuration :: default_rready is high. In both these cases, rready_delay [] is not applicable. The size of this array can be set to any value greater than 0, based on the number of times the user would like the signal to toggle during idle period. |
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Applicable when svt_axi_port_configuration :: toggle_last_signals_during_idle_period is set. Applicable for AXI4 stream master VIP.
This is a bit vector array attribute with one element size equal to 16 and array size equal to the packet size i.e stream_burst_length. The value of an individual element of the array contains all the TLAST values to be driven during the idle period before the corresponding transfer. Value of 0 indicates the TLAST signal must be driven low and the value of 1 indicates the signal must be driven high. idle_tlast_value is valid only during TVALID is low. When TVALID is high, idle_tlast_value is not applicable. Consider the following example. idle_tlast_value[0] = 16’b0000 0000 1010 1010 Here, 16 = 16. idle_tlast_value[0] represents all the TLAST values to be driven before the first transfer of the packet. If tvalid_delay[0] = 5, there will be 5 clock cycles before the TVALID is asserted. Here, the valid values of idle_tlast_value[0] will be idle_tlast_value[0][4:0] = 5’b01010 and TLAST will be driven to LOW -> HIGH -> LOW -> HIGH-> LOW before TVALID assertion for the first transfer. |
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Applicable when svt_axi_port_configuration :: toggle_ready_signals_during_idle_period is set. Applicable for slave VIP.
Indicates the number of cycles for which wready should be high and low when the write data channel is idle, that is, when WVALID is low. This property helps to toggle the WREADY signal during the idle period between the assertion of WVALID signal. Values provided in even numbered indices indicate the number of clocks for which the ready signal must be driven low and the values in odd numbered indices indicate the number of clocks for which it must driven high. Note that the values provided in this variable are applied for all write data beats. If the user requires a different set of delays during the idle period for each beat, the user must use the write_data_phase_started callback to change the values of this property for the corresponding beat. Once changed, the values will be applicable for all subsequent beats of the transactions unless it is is changed for a subsequent beat. Values in this variable are applicable only until WVALID is asserted. When WVALID is observed on the interface, this delay is no longer applicable and the delay specified in wready_delay [] is applied before asserting WREADY. Note that toggling WREADY during the idle period may lead to situations where the WREADY signal is already asserted when the WVALID is sampled, even though the value of svt_axi_port_configuration :: default_wready is low. Similarly, WREADY may be low when the corresponding valid is sampled, even though the value of svt_axi_port_configuration :: default_wready is high. In both these cases, wready_delay [] is not applicable. The size of this array can be set to any value greater than 0, based on the number of times the user would like the signal to toggle during idle period. |
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This variable represents the initial cache line state. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE. The initial cache line state of a transaction that is driven on the READ channel is populated just after the reception of the first beat of the response of a transaction. The initial cache line state of a transaction that is driven on the WRITE channel is populated just before the transaction is started. This variable is updated by the VIP, and is a read-only variable. User is not expected or supposed to modify this variable.
Applicable for ACTIVE MASTER only. |
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Represents the various interleave pattern for a read and write transaction. The interleave_pattern gives flexibility to program interleave blocks with different patterns as mentioned below.
A Block is group of beats within a transaction. EQUAL_BLOCK : Drives equal distribution of blocks provided by equal_block_length variable. RANDOM_BLOCK : Drives the blocks programmed in random_interleave_array Please note that currently interleaving based on EQUAL_BLOCK is not supported. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE.
Indicates if the transaction is auto generated by the VIP. Transactions are auto-generated when: 1. The cache is full and an entry needs to be evicted from the cache. 2. User supplies a cache maintenance transaction and the protocol requires that the cache line is first written into memory before sending the cache maintenance transaction. This is a read-only member, which VIP uses to indicate whether the transaction is auto generated. It should not be modified by the user. Applicable for ACTIVE MASTER only. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE.
Indicates if the transaction ended because the requested data was already available in the cache. This bit is set by the master, no action is taken if the user sets this bit. A transaction with this bit set was not sent out on the bus and therefore other components in the testbench will not detect this transaction. Applicable for ACTIVE MASTER only. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE.
Indicates if a coherent transaction was dropped because the start state of the corresponding cache line is not as expected before transmitting the transaction. The expected start states for each of the transaction types are given in section 5 of the ACE specification. Applicable for ACTIVE MASTER only. |
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This variable indicate whether the data check parity error is detected in the transaction. This bit is set to 1, if parity error is deducted in a transaction. By default this is set to 0. Applicable when svt_axi_port_configuration :: check_type is set to ODD_PARITY_BYTE_DATA or ODD_PARITY_BYTE_ALL.
Active Master.
Active Slave.
Passive components.
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This variable represents the data check parity error bit's with respect to valid data, Each bit of parity check data is calculated from every 8bit of data with 1bit if datachk. By default all bits are set to 'b1, if any parity error is detected then that particular bit is set to 0. Applicable when svt_axi_port_configuration :: check_type is set to ODD_PARITY_BYTE_DATA or ODD_PARITY_BYTE_ALL. Active Master.
Active Slave.
Passive components.
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A bit that must be set by the user to indicate that this transaction will be sent to the slave driver from the slave sequencer through the delayed_response_request_port of the slave driver. If the transaction is randomized before putting it into the delayed_response_request_port of the slave driver, then this bit must be set by the user. This bit must not be set for a transaction that is sent on the seq_item_port.
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Indicates if the current data beat of a read transaction has rlast asserted.This is a sticky bit in that it remains set to 1 after the last data beat.
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Indicates if the current data beat of a write transaction has wlast asserted. This is useful when data is received before addr and it is required to determine the last beat. This is a sticky bit in that it remains set to 1 after the last data beat.
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE.
Indicates if the transaction is a result of a speculative read operation. A speculative read is defined as a read of a cache line that a master already holds in its cache. This is a read-only member, which VIP uses to indicate whether the transaction is a speculative read. Modifying the value of this member will not have any effect. Applicable for ACTIVE MASTER only. |
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Represents the value of AWUNIQUE signal driven/sampled on the interface. Applicable when svt_axi_port_configuration :: awunique_enable is set. AWUNIQUE is asserted as per table C3-9 of section C3.1.4 on AWUNIQUE signal. The value in the randomized transaction may be overridden by the driver as per protocol requirements. For transactions where AWUNIQUE may be asserted or deasserted, the randomized value is driven.
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE and svt_axi_port_configuration :: snoop_response_data_transfer_mode is set to SNOOP_RESP_DATA_TRANSFER_USING_WB_WC.
Indicates if this transaction is a WRITEBACK/WRITECLEAN auto-generated transaction which was generated to transfer snoop data. When svt_axi_port_configuration :: snoop_response_data_transfer_mode is set to SNOOP_RESP_DATA_TRANSFER_USING_WB_WC, snoop data from a dirty line is transferred using a WRITEBACK/WRITECLEAN transaction instead of the snoop data channel. All transactions which have this variable set will also have is_auto_generated set. |
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Weight used to control distribution of longer bursts within transaction generation.
This controls the distribution of the length of the bursts using burst_length field |
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Weight used to control distribution of long delays within transaction generation.
This controls the distribution of delays for the 'delay' fields (e.g., delays for asserting the ready signals). |
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Represents the maximum byte address of this transaction. If tagging is enabled, this will be the maximum tagged address .
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When this bit is set , it indicates that this transaction has updated the AXI Slave memory with write data and other properties.
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Represents the minimum byte address of this transaction. If tagging is enabled, this will be the minimum tagged address .
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Variable that holds the object_id of this transaction
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Variables used in generating XML/FSDB for pa writer
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Indicates that this master transaction is a partial write transaction and this transaction will be split by the interconnect into a full Read transaction followed by partial Write transaction to the corresponding slave. Applicable for users who want to correlate master transactions to slave transactions in the system monitor. This parameter is applicable when svt_axi_port_configuration :: partial_write_to_slave_read_and_write_association_enable is set to This property must be set by the user in a system monitor callback issued at the start of a transaction
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Represents the phase type. Following are the possible transaction types:
Please note that WRITE and READ transaction type is valid for svt_axi_port_configuration :: axi_interface_type is AXI3/AXI4/AXI4_LITE |
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MASTER in active mode:
For write transactions this variable specifies write data to be driven on the WDATA bus. SLAVE in active mode: For read transactions this variable specifies read data to be driven on the RDATA bus. PASSIVE MODE: This variable stores the write or read data as seen on WDATA or RDATA bus. |
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The variable holds the value for signals WUSER/RUSER as they are driven on the bus Applicable for all interface types. Enabled through port configuration parameters svt_axi_port_configuration :: wuser_enable and svt_axi_port_configuration :: ruser_enable.
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MASTER in active mode:
For write transactions this variable specifies wstrb to be driven on the WSTRB bus. SLAVE in active mode: This variable stores the WSTRB as seen on WSTRB bus. PASSIVE MODE: This variable stores the WSTRB as seen on WSTRB bus. |
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This field defines the Poison. This field is applicable for write data, read data. It consists of a bit for each 8 data byte in the transaction data, which when set indicates that set of corresponding 8 data bytes have been previously been corrupted. Applicable when svt_axi_port_configuration :: poison_enable is set to 1. If svt_axi_port_configuration :: wysiwyg_enable is set to 0 (default).
Active Slave.
Passive components.
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The port configuration corresponding to this transaction
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Represents port ID. Not currently supported.
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This variable represents the prefinal cache line state. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE or ACE_LITE. The prefinal cache line state of a transaction is the state of the cache just before cache is updated . This variable is updated by the VIP, and is a read-only variable. User is not expected or supposed to modify this variable.
Applicable for ACTIVE MASTER only. |
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Represents the protection support of a transaction. The variable holds the value for AWPROT/ARPROT. The conventions of the enumeration are:
For the above conventions, following are the possible protection types:
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The variable holds the value for AWQOS/ARQOS
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE. Defines the RACK delay in terms of number of clock cycles. The reference event for this delay is reference_event_for_rack_delay.
Applicable for ACTIVE MASTER only. |
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When the interleave_pattern is set to RANDOM_BLOCK, the user would program this array with blocks. There are default constraints, which the user can override and set their own block patterns. In case of AXI4_STREAM interface type for active master, programming this array is applicable only when svt_axi_port_configuration :: stream_interleave_depth is greater than 1. |
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Defines reference event for AWREADY or ARREADY delay.
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Defines a reference event from which the AWVALID or ARVALID delay should start. Following are the different reference events:
PREV_ADDR_VALID: Reference event is the previous AWVALID or ARVALID signal PREV_ADDR_HANDSHAKE: Reference event is previous read or write Address handshake FIRST_WVALID_DATA_BEFORE_ADDR: This is used when data_before_addr bit is set. The reference event for address valid to occur is the first wvalid of the current transaction. FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR: This is used when data_before_addr bit is set. The reference event for address valid to occur is the first data handshake of the current transaction. PREV_LAST_DATA_HANDSHAKE: Reference event is previous read or write last data handshake to Address valid assertion. Reasonable constraint on reference_event_for_addr_delay in data_before_addr scenarios is added in svt_axi_transaction class to constraint the value of reference_event_for_addr_delay not to take FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR. User may swicth off the constraint reasonable_reference_event_for_addr_delay by setting rand_mode to 0 incase they want reasonable_reference_event_for_addr_delay to take FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR. In data_before_addr scenarios reference_event_for_addr_delay should be set very carefully to FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR as this may cause potential deadlock scenarios in ACE SLAVE DUT where slave DUT waits for awvalid signal before driving wready signal. |
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Defines a reference event for BREADY delay.
BVALID: Reference event is assertion of BVALID signal |
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Defines a reference event for BVALID delay.
LAST_DATA_HANDSHAKE: Reference event for BVALID delay is completion of handshake for last write data. ADDR_HANDSHAKE: Reference event for BVALID delay is completion of handshake for address phase. |
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Defines the reference events to delay the first rvalid signal. The delay must be programmed in rvalid_delay[0]. Following are the different events under this category:
READ_ADDR_VALID: Reference event for first RVALID is assertion of ARVALID signal READ_ADDR_HANDSHAKE: Reference event for first RVALID is completion of read address handshake |
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Defines the reference events to delay the first wvalid signal. The delay must be programmed in wvalid_delay[0]. Following are the different events under this category:
WRITE_ADDR_VALID: Reference event for first WVALID is assertion of AWVALID signal WRITE_ADDR_HANDSHAKE: This event is applicable when write data is transmitted after write address, that is, when data_before_addr is set to 0. This reference event specifies the write address handshake. PREV_WRITE_DATA_HANDSHAKE: This event is applicable when write data is transmitted before write address, that is, when data_before_addr is set to 1. This reference event specifies the previous write data handshake. |
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Defines the reference events to delay the RVALID signals from second beat onwards. Following are the different events under this category:
PREV_RVALID : Reference event to delay RVALID is assertion of previous rvalid. The delay timer starts as soon as previous valid signal is asserted. If previous data handshake does not complete before timer expires, the current transfer waits for the previous handshake to complete, and then immediately asserts rvalid. PREV_READ_HANDSHAKE : Reference event to delay RVALID is completion of previous read data handshake. |
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Defines the reference events for WVALID delay from second beat onwards. Following are the different events under this category:
PREV_WVALID: Reference event for WVALID delay is assertion of previous wvalid. The delay timer starts as soon as previous valid signal is asserted. If previous data handshake does not complete before timer expires, the current transfer waits for the previous handshake to complete, and then immediately asserts wvalid. PREV_WRITE_HANDSHAKE: Reference event for WVALID delay is completion of previous data handshake. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE.
Defines the reference event from which the RACK delay should start.
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Defines the reference event for RREADY delay.
RVALID: Reference event for RREADY is assertion of RVALID signal MANUAL_RREADY: (Not supported currently) This event allows the user to generate RREADY patterns, in cycles, as follows: 1. The reference event for this delay is the beginning of the Address handshake. 2. The rready_delay[0] represents the following a. A value > 0 is the no. of cycles default rready signal is driven b. A value < 0 is the no. of cycles default rready signal is driven after toggling 3. The remaining rready_delay element represents no. of cycles to drive rready Example 1: For eg. RREADY pattern (cycles) = 1110011 and default_rready = 1 data_delay[0] = 3 Three cycles high (driving default_rready value) data_delay[1] = 2 Two cycles low (toggled previous RREADY value) data_delay[2] = 2 Two cycles high (toggled previous RREADY value) For eg. cycle pattern RREADY = 0001100 and default_rready = 1 data_delay[0] = -3 Three cycles low (toggled default_rready value) data_delay[1] = 2 Two cycles high (toggled previous RREADY value) data_delay[2] = 2 Two cycles low (toggled previous RREADY value) |
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Defines the reference events for TVALID delay from second beat onwards. Following are the different events under this category:
PREV_TVALID: In this case, assertion of previous tvalid signal is considered as the reference event for TVALID delay. The delay timer starts as soon as previous tvalid signal is asserted. If previous tvalid-tready handshake does not complete before timer expires, the current transfer waits for the previous handshake to complete, and then immediately asserts tvalid. PREV_TVALID_TREADY_HANDSHAKE: Reference event for TVALID delay is completion of previous tvalid-tready handshake. |
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE.
Defines the reference event from which the WACK delay should start.
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Defines the reference events for WREADY delay.
WVALID: Reference event for WREADY is assertion of WVALID signal. MANUAL_WREADY: (Not supported currently) This event allows the user to generate WREADY patterns, in cycles, as follows : 1. The reference event for this delay is the beginning of the Address handshake. 2. The wready_delay[0] represents the following a. A value > 0 is the no. of cycles default wready signal is driven b. A value < 0 is the no. of cycles default wready signal is driven after toggling 3. The remaining wready_delay element represents no. of cycles to drive wready Example 1: For eg. WREADY pattern (cycles) = 1110011 and default_wready = 1 data_delay[0] = 3 Three cycles high (driving default_wready value) data_delay[1] = 2 Two cycles low (toggled previous WREADY value) data_delay[2] = 2 Two cycles high (toggled previous WREADY value) For eg. cycle pattern WREADY = 0001100 and default_wready = 1 data_delay[0] = -3 Three cycles low (toggled default_wready value) data_delay[1] = 2 Two cycles high (toggled previous WREADY value) data_delay[2] = 2 Two cycles low (toggled previous WREADY value) |
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The variable holds the value for AWREGION/ARREGION
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Sets the reordering priority of the current transaction within the set of transactions that are allowed access to read data channel based on svt_axi_port_configuration :: read_data_reordering_depth.
This member is applicable only when svt_axi_port_configuration :: reordering_algorithm is svt_axi_port_configuration :: PRIORITIZED. This value indicates the priority of sending the response to current transaction compared to remaining transactions within the depth indicated by svt_axi_port_configuration :: read_data_reordering_depth for read transactions or by svt_axi_port_configuration :: write_resp_reordering_depth for write transactions. Note that the value of this attribute should be within the following range: [1:svt_axi_port_configuration :: read_data_reordering_depth] for read transactions and [1:svt_axi_port_configuration :: write_resp_reordering_depth] for write transactions. If svt_axi_port_configuration :: reordering_priority_high_value is set to ‘1’ then, the transactions with highest value for this attribute will get higher priority. If svt_axi_port_configuration :: reordering_priority_high_value is set to ‘0’ then, the transactions with least value for this attribute will get higher priority. If there are more than one transactions with same priority, those transaction will be processed in the same order as they are received. Applicable for ACTIVE SLAVE only. |
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The variable holds the value for signal BUSER. Applicable for all interface types. Enabled through port configuration parameter svt_axi_port_configuration :: buser_enable.
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If configuration parameter svt_axi_port_configuration :: default_rready is FALSE, this member defines the RREADY signal delay in number of clock cycles. The reference event for this delay is reference_event_for_rready_delay
If configuration parameter svt_axi_port_configuration :: default_rready is TRUE, this member defines the number of clock cycles for which RREADY signal should be deasserted after each handshake, before pulling it up again to its default value. Applicable for ACTIVE MASTER only. |
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This array variable specifies the response for read transaction. The array holds the value for RRESP. Following are the possible response types:
MASTER ACTIVE MODE: Will Store the read responses received from the slave. SLAVE ACTIVE MODE: The read responses programmed by the user. PASSIVE MODE - MASTER/SLAVE: Stores the read responses seen on the bus. |
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Defines RVALID delay, in terms of number of clock cycles. The reference event for this delay is:
Applicable for ACTIVE SLAVE only. |
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Weight used to control distribution of short bursts within transaction generation.
This controls the distribution of the length of the bursts using burst_length field |
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Weight used to control distribution of short delays within transaction generation.
This controls the distribution of delays for the 'delay' fields (e.g., delays for asserting the ready signals). |
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Defines the burst length of a AXI4 Stream Packet. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM.
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A bit that indicates that the testbench would like to suspend arready signal for a READ transaction until this bit is reset. This is applicable only when svt_axi_port_configuration :: default_arready is set to 0 svt_axi_transaction :: addr_ready_delay won't be applicable when this bit is set to 1
Applicable for ACTIVE SLAVE only. |
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A bit that indicates that the testbench would like to suspend awready signal for a WRITE transaction until this bit is reset. This is applicable only when svt_axi_port_configuration :: default_awready is set to 0 svt_axi_transaction :: addr_ready_delay won't be applicable when this bit is set to 1
Applicable for ACTIVE SLAVE only. |
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Indicates that data will start before address for write transactions, even though data_before_addr is set to 0. This is useful when awvalid is suspended for write transaction and respective transaction data is driven before resuming the suspended awvalid signal.
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A bit array that indicates that the testbench would like to suspend write data beats and keep all beats suspended for a WRITE transaction until this bit is reset.
Applicable with svt_axi_port_configuration :: explicit_write_suspension_enable and for ACTIVE AXI4 MASTER only. |
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A bit that indicates that the testbench would like to suspend response/data for a READ/WRITE/COHERENT transaction until this bit is reset. This bit is usually set by the testbench when it needs to provide response information to the driver (the slave driver expects the response information in 0 time), but the data to respond with is not yet known. The testbench can set this bit and put this transaction back into the input channel of the slave. The transaction's response/data will not be sent until this bit is reset. Once the data is available, the testbench can populate response fields and reset this bit, upon which the slave driver will send the response/data of this transaction.
Applicable for ACTIVE SLAVE only. |
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A bit array that indicates that the testbench would like to suspend read data beats and keep all beats suspended for a READ transaction until this bit is reset. This bit array is usually set by the testbench when it needs to provide response information to the driver (the slave driver expects the response information in 0 time), but the data to respond with is not yet known. With this bit array, read interleaving and out of order responses can be specified. Note that suspend_response is prioritized to this bit array.
Applicable with svt_axi_port_configuration :: suspend_response_per_read_beat_enable and for ACTIVE SLAVE only. |
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A bit that indicates that the testbench would like to suspend wready signal for a WRITE transaction until this bit is reset. This is applicable only when svt_axi_port_configuration :: default_wready is set to 0 svt_axi_transaction :: wready_delay won't be applicable when this bit is set to 1
Applicable for ACTIVE SLAVE only. |
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A bit that indicates that the testbench would like to suspend the write addr phase until this bit is reset.
Applicable with svt_axi_port_configuration :: explicit_write_suspension_enable and for ACTIVE AXI4 MASTER only. |
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Used to drive TDATA signals. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM.
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TDEST provides routing information for the data stream. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM.
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The variable holds the value of TID signal. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM.
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TKEEP is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM.
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Represents the total byte count of this transaction. .
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If configuration parameter svt_axi_port_configuration :: default_tready is FALSE, this member defines the TREADY signal delay in number of clock cycles. The reference event for this delay is reference_event_for_tready_delay.
Please note that reference_event_for_tready_delay is not supported currently. Absolute value of tready_delay is considered for delay calculation with respect to tvalid signal. If configuration parameter svt_axi_port_configuration :: default_tready is TRUE, this member defines the number of clock cycles for which TREADY signal should be deasserted after each handshake, before pulling it up again to its default value. When the configuration parameter svt_axi_port_configuration :: toggle_ready_signals_during_idle_period is set to 1 then this attribute is inapplicable and the configuration attributes tready_assert_min_delay, tready_assert_max_delay, tready_deassert_min_delay and tready_deassert_max_delay are used to toggle the tready signal during the idle period. Applicable for ACTIVE SLAVE only. |
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Used to drive TSTRB signal. The strobes are right aligned and the model will drive strobes on appropriate lanes. The model also takes care of the endianness while driving tstrb. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM.
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TUSER is user defined sideband information that can be transmitted alongside the data stream. Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI4_STREAM.
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Defines the delay in number of clock cycles for TVALID signal. The reference event for this delay is: reference_event_for_tvalid_delay
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Applicable when svt_axi_port_configuration :: axi_interface_type is set to AXI_ACE. Defines the WACK delay in terms of number of clock cycles. The reference event for this delay is reference_event_for_wack_delay.
Applicable for ACTIVE MASTER only. |
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If configuration parameter svt_axi_port_configuration :: default_wready is FALSE, this member defines the WREADY signal delay in number of clock cycles. The reference event for this delay is reference_event_for_wready_delay.
If configuration parameter svt_axi_port_configuration :: default_wready is TRUE, this member defines the number of clock cycles for which WREADY signal should be deasserted after each handshake, before pulling it up again to its default value. Applicable for ACTIVE SLAVE only. |
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This variable stores the cycle information for response ready on a write transaction. The simulation clock cycle number when the write response valid and ready both are asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for response ready on write transactions. The simulation time when the response valid and ready both are asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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Represents the status of the write response transfer. Following are the possible status types.
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This variable stores the cycle information for response valid on a write transaction. The simulation clock cycle number when the write response valid is asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the timing information for response valid on write transactions. The simulation time when the response valid is asserted, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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Array of Write strobes. If svt_axi_port_configuration :: wysiwyg_enable is set to 0 (default), the wstrb must be stored right-justified by the user. The model will drive these strobes on the correct lanes. If svt_axi_port_configuration :: wysiwyg_enable is set to 1, the wstrb is transmitted as programmed by user and is reported as seen on bus. No right-justification is used in this case.
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Defines the delay in number of cycles for WVALID signal. The reference event for this delay is:
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The simulation time when the master or slave driver receives the transaction from the sequencer, is captured in this member. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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This variable stores the transaction consumed at driver timing information. The transaction consumed at driver time to begin time delay is calculated as the difference between begin_time and xact_consumed_by_driver_time. This information can be used for doing performance analysis. VIP updates the value of this member variable, user does not need to program this variable.
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Represents the transaction type. Following are the possible transaction types:
Please note that WRITE and READ transaction type is valid for svt_axi_port_configuration :: axi_interface_type is AXI3/AXI4/AXI4_LITE and COHERENT transaction type is valid for svt_axi_port_configuration :: axi_interface_type is AXI_ACE. |
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Weight used to control distribution of burst length to 1 within transaction generation.
This controls the distribution of the length of the bursts using burst_length field |
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Weight used to control distribution of zero delay within transaction generation.
This controls the distribution of delays for the 'delay' fields (e.g., delays for asserting the ready signals). |
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constraint ace_valid_ranges {
} // ace_valid_ranges |
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constraint axi3_4_valid_ranges {
if (port_cfg.axi_interface_type == svt_axi_port_configuration::AXI3) burst_length <= 16; else burst_length <= 256; if(port_cfg.ace_version == svt_axi_port_configuration::ACE_VERSION_1_0 && xact_type == COHERENT) { !(coherent_xact_type inside{CLEANSHAREDPERSIST,READONCECLEANINVALID,READONCEMAKEINVALID});} } // axi3_4_valid_ranges |
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constraint axi4_stream_valid_ranges {
if (port_cfg.axi_port_kind == svt_axi_port_configuration::AXI_MASTER) { if (port_cfg.axi_interface_type == svt_axi_port_configuration::AXI4_STREAM) { if (!port_cfg.tid_enable) { tid == 0; } else { tid inside {[0 : ((1 << port_cfg.tid_width) -1)]}; } if (!port_cfg.tdest_enable) { tdest == 0; } else { tdest inside {[0 : ((1 << port_cfg.tdest_width) -1)]}; } if (!port_cfg.tlast_enable) { stream_burst_length == 1; } if(tdata_size_from_parent > 0) { stream_burst_length == tdata_size_from_parent; } } //AXI4_STREAM } //AXI_MASTER } // axi4_stream_valid_ranges |
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constraint disable_constraint_first_wvalid_reference_event {
reference_event_for_first_wvalid_delay dist { WRITE_ADDR_VALID:=50000, WRITE_ADDR_HANDSHAKE:=1, PREV_WRITE_DATA_HANDSHAKE:=50000 }; } |
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constraint reasonable_cust_xact_flow {
soft cust_xact_flow == 0; } |
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constraint reasonable_no_interleaving {
if (port_cfg.axi_port_kind == svt_axi_port_configuration::AXI_SLAVE && port_cfg.prioritized_reordering_type == svt_axi_port_configuration::XACT_ADDR_HANDSHAKE_TO_RSP_DAT_VALID_DELAY) { enable_interleave == 0; start_new_interleave == 0; equal_block_length == 0; } } |
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constraint reasonable_reference_event_for_addr_delay {
if(data_before_addr){ reference_event_for_addr_valid_delay inside {FIRST_WVALID_DATA_BEFORE_ADDR};} } |
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constraint reasonable_reference_event_for_addr_ready_delay {
reference_event_for_addr_ready_delay inside {ADDR_VALID}; } |
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Re-organised constraint blocks based on interface type. This will make it easy to turn-off the constraints based on interface type. It can result in significant run-time improvement.
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constraint wdata_optimistic_flow_valid_ranges {
if(port_cfg.wdata_optimistic_flow_control_enable && port_cfg.axi_port_kind == svt_axi_port_configuration::AXI_MASTER && xact_type == WRITE) { data_before_addr == 0; } } |