Main Page
Classes
Macros
Coverage
Sequences
Globals
Index
?
simple
reg expr
SVT
UVM
uvm_analysis_port Class Reference
Inheritance diagram for class uvm_analysis_port:
uvm_analysis_port
Node0
uvm_port_base
Node1
uvm_analysis_port
Node0->Node1
Node2
svt_debug_opts_analysis_imp_port
Node1->Node2
Node3
svt_debug_opts_analysis_port
Node1->Node3
List of all members.
Public Member Functions
virtual function string
get_type_name
( )
function void
new
( string name,
uvm_component
parent )
function void
write
( input T t )
Class Parameters
type
T
= int;
Member Function Documentation
virtual function string
uvm_analysis_port::
get_type_name
( )
Superseded functions
uvm_port_base
::
get_type_name
function void
uvm_analysis_port::
new
( string
name
,
uvm_component
parent
)
Superseding functions
svt_debug_opts_analysis_port
::
new
function void
uvm_analysis_port::
write
( input T
t
)
Class Parameters Documentation
type attribute
uvm_analysis_port::
T
= int
07 August 2024, Copyright © 2024 Synopsys, Inc.