AMBA SVT UVM Documentation - Interfaces Reference

Product	Interface Group	Interfaces
amba_svt	Default Group	svt_axi_master_if
svt_axi_lp_if
svt_axi_slave_if
svt_axi_if
svt_ahb_master_if
svt_ahb_slave_if
svt_ahb_if	svt_ahb_slave_if, svt_ahb_master_if
svt_apb_slave_if
svt_apb_if	svt_apb_slave_if
CHI Request Node interface. This is a sub-interface of svt_chi_if.	svt_chi_rn_if
CHI Slave Node interface. This is a sub-interface of svt_chi_if.	svt_chi_sn_if
CHI IC Request Node interface. This is a sub-interface of svt_chi_if.	svt_chi_ic_rn_if
CHI IC Slave Node interface. This is a sub-interface of svt_chi_if.	svt_chi_ic_sn_if
Top Level interface for CHI VIP	svt_chi_if	svt_chi_ic_sn_if, svt_chi_sn_if, svt_chi_ic_rn_if, svt_chi_rn_if

interface svt_axi_lp_if () General description: The low power interface svt_axi_lp_if defines the AXI low power signals appropriate for a single port, along with the modports needed for the monitor VIP.

Modports

Clocking blocks

interface svt_axi_slave_if

(

input logic common_aclk

)

General description:

The slave interface svt_axi_slave_if defines the AXI signals appropriate for a single port, along with the modports needed for the AXI slave and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Clock signal description:

Signal Name	Signal Description
aclk	If all AXI interfaces in the system are expected to run on a different clock, user can use the aclk signal in the port interfaces. Set the configuration parameter svt_axi_system_configuration :: common_clock_mode to 0. In this case, connect the aclk signal in each port interface to the appropriate port specific clock in the testbench.

Debug port description:
In active and passive mode, the VIP assigns a unique number to each transaction. This number is also displayed in the messages issued by the VIP. The debug port reflects this unique transaction number. This makes it easy to fnd a particular transaction on the waveforms, by looking at the debug port signals. For example, if messages mentions that there is a error on transaction #100, used can jump to value #100 on debug port signals, to find the transaction. A seperate debug port is provided for each AXI channel, so that you can jump to the address phase, data phase or response phase of a given transaction, for example transaction #100.

Signal Name	Signal Description
read_addr_xact_num	Transaction number on read address channel. Used in active mode.
read_data_xact_num	Transaction number on read data channel. Used in active mode.
read_data_xfer_id	Data transfer number on read data channel. Used in active mode.
write_addr_xact_num	Transaction number on write address channel. Used in active mode.
write_data_xact_num	Transaction number on write data channel. Used in active mode.
write_data_xfer_id	Data transfer number on write data channel. Used in active mode.
write_resp_xact_num	Transaction number on write response channel. Used in active mode.
snoop_addr_xact_num	Transaction number on snoop address channel. Used in active mode.
snoop_data_xact_num	Transaction number on snoop data channel. Used in active mode.
snoop_data_xfer_id	Data transfer number on snoop data channel. Used in active mode.
snoop_resp_xact_num	Transaction number on snoop response channel. Used in active mode.
mon_read_addr_xact_num	Transaction number on read address channel. Used in passive mode.
mon_read_data_xact_num	Transaction number on read data channel. Used in passive mode.
mon_read_data_xfer_id	Data transfer number on read data channel. Used in passive mode.
mon_write_addr_xact_num	Transaction number on write address channel. Used in passive mode.
mon_write_data_xact_num	Transaction number on write data channel. Used in passive mode.
mon_write_data_xfer_id	Data transfer number on write data channel. Used in passive mode.
mon_write_resp_xact_num	Transaction number on write response channel. Used in passive mode.
mon_snoop_addr_xact_num	Transaction number on snoop address channel. Used in passive mode.
mon_snoop_data_xact_num	Transaction number on snoop data channel. Used in passive mode.
mon_snoop_data_xfer_id	Data transfer number on snoop data channel. Used in passive mode.
mon_snoop_resp_xact_num	Transaction number on snoop response channel. Used in passive mode.

AXI signal description:
This sub-interface supports signals for AXI3, AXI4, ACE and AXI4 Stream protocols. The names of the signals match the names specified in the AXI specification. Please refer to the AXI specification for specific description of any of the signals.

Modports

Clocking blocks

Functions

interface svt_axi_if ()

General description:

AXI VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_axi_if is defined. The top level interface contains an array of master & slave interfaces. By default, 16 master and 16 slave interfaces are defined in the top level interface. Currently, the maximum master and slave interfaces supported is 450. The number of master and slave interfaces in top level interface can be controlled using macros SVT_AXI_MAX_NUM_MASTERS_{0..450} and SVT_AXI_MAX_NUM_SLAVES_{0..450} respectively. For example, if you want to use 8 master interfaces and 10 slave interfaces, you can define following macros when compiling the VIP:

SVT_AXI_MAX_NUM_MASTERS_8

SVT_AXI_MAX_NUM_SLAVES_10
Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces:

Interface Name	Interface Description
svt_axi_master_if	Master Interface used by master VIP component
svt_axi_slave_if	Slave Interface used by slave VIP component

Clock signal description:

Signal Name

Signal Description

common_aclk

If all AXI interfaces in the system are expected to run on a common clock, user can use the common clock mode. Common clock mode can be selected by setting configuration parameter svt_axi_system_configuration :: common_clock_mode to 1. This is the default mode of operation. When common clock mode is used, connect common_aclk signal to the top level clock signal in the testbench. Pleae note that if you are using the Interconnect VIP component, you are required to always connect common_aclk signalto a clock in the testbench, as Interconnect VIP component internally uses this clock for its operation.

aclk

This signal belongs to the master and slave sub-interfaces. If all AXI interfaces in the system are expected to run on a different clock, user can use the aclk signal in the port interfaces. Set the configuration parameter svt_axi_system_configuration :: common_clock_mode to 0. In this case, connect the aclk signal in each port interface to the appropriate port specific clock in the testbench.

Clock connection examples:

Usage with common clock:
assign axi_if.common_aclk = SystemClock;

Usage with port specific clock:
assign axi_if.master_if[0].aclk = master_clk;
assign axi_if.slave_if[0].aclk = slave_clk;

Interface signal connections:

If master VIP is active, then connect DUT slave port signals to master interface:
assign axi_if.master_if[0].awvalid = DUT_slave_intf.awvalid;

If master VIP is passive, then connect DUT master port signals to master interface:
assign axi_if.master_if[0].awvalid = DUT_master_intf.awvalid;

If slave VIP is active, then connect DUT master port signals to slave interface:
assign axi_if.slave_if[0].awready = DUT_master_intf.awready;

If slave VIP is passive, then connect DUT slave port signals to slave interface:
assign axi_if.slave_if[0].awready = DUT_slave_intf.awready;

Functions

interface svt_chi_rn_if ( input logic clk, input logic resetn ) General description: The RN interface svt_chi_rn_if defines the CHI signals appropriate for a fully coherent Request Node, along with the modports needed for the CHI RN and monitor VIP. RN interface is a sub-interface to the top level interface svt_chi_if. Clock signal description: Clock signal is obtained in this RN interface through interface port list. User provides this signal from the testbench to the top level interface svt_chi_if through interface port list. The top level interface then passes this signal down to the RN sub-interface. Debug port description: The CHI VIP drives the object number of the transaction corresponding to a flit on the debug ports. The CHI VIP drives the current l-credit count corresponding to each virtual channel on the debug ports. curr_req_lcrd_count : Current TX REQ VC l-credit count, will be driven whenever there is a change in TX REQ VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_txrsp_lcrd_count : Current TX RSP VC l-credit count, will be driven whenever there is a change in TX RSP VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_txdat_lcrd_count : Current TX DAT VC l-credit count, will be driven whenever there is a change in TX DAT VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_snp_lcrd_count : Current RX SNP VC l-credit count, will be driven whenever there is a change in RX SNP VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_snp_vc_flit_buffer_size curr_rxrsp_lcrd_count : Current RX RSP VC l-credit count, will be driven whenever there is a change in RX RSP VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_rsp_vc_flit_buffer_size curr_rxdat_lcrd_count : Current RX DAT VC l-credit count, will be driven whenever there is a change in RX DAT VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size CHI signal description: This sub-interface supports signals for the CHI protocol. The names of the signals match the names specified in the CHI specification. Please refer to the CHI specification for specific description of any of the signals.

Ports
bit	is_active
logic	TXSACTIVE
logic	RXSACTIVE
logic	TXLINKACTIVEREQ
logic	TXLINKACTIVEACK
logic	RXLINKACTIVEREQ
logic	RXLINKACTIVEACK
logic	SYSCOREQ
logic	SYSCOACK
logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0]	TXREQFLITPEND
logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0]	TXREQFLITV
logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0]	TXREQFLIT
logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0]	TXREQLCRDV
logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0]	RXRSPFLITPEND
logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0]	RXRSPFLITV
logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0]	RXRSPFLIT
logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0]	RXRSPLCRDV
logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0]	RXDATFLITPEND
logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0]	RXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	RXDATFLIT
logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0]	RXDATLCRDV
logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0]	RXSNPFLITPEND
logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0]	RXSNPFLITV
logic [SVT_CHI_MAX_SNP_FLIT_WIDTH-1:0]	RXSNPFLIT
logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0]	RXSNPLCRDV
logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0]	TXRSPFLITPEND
logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0]	TXRSPFLITV
logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0]	TXRSPFLIT
logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0]	TXRSPLCRDV
logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0]	TXDATFLITPEND
logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0]	TXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	TXDATFLIT
logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0]	TXDATLCRDV
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	req_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	rx_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	rx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_req_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_req_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_txrsp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_txdat_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_snp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_rxrsp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_rxdat_lcrd_count
string	full_name

Modports
modport rn_modport ( input resetn, clocking rn_cb ) Modport used to connect the VIP HN to CHI interface signals.

modport monitor_modport ( input resetn, clocking monitor_cb ) Modport used to connect the VIP Monitor to CHI interface signals.

modport rn_async_modport ( output TXSACTIVE, input RXSACTIVE, output TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, output RXLINKACTIVEACK, output SYSCOREQ, input SYSCOACK, output TXREQFLITPEND, output TXREQFLITV, output TXREQFLIT, input TXREQLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, output RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, output RXDATLCRDV, input RXSNPFLITPEND, input RXSNPFLITV, input RXSNPFLIT, output RXSNPLCRDV, output TXRSPFLITPEND, output TXRSPFLITV, output TXRSPFLIT, input TXRSPLCRDV, output TXDATFLITPEND, output TXDATFLITV, output TXDATFLIT, input TXDATLCRDV ) Asynchronous modport suitable for SV RN Bind interface.

modport monitor_async_modport ( input TXSACTIVE, input RXSACTIVE, input TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, input RXLINKACTIVEACK, input SYSCOREQ, input SYSCOACK, input TXREQFLITPEND, input TXREQFLITV, input TXREQFLIT, input TXREQLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, input RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, input RXDATLCRDV, input RXSNPFLITPEND, input RXSNPFLITV, input RXSNPFLIT, input RXSNPLCRDV, input TXRSPFLITPEND, input TXRSPFLITV, input TXRSPFLIT, input TXRSPLCRDV, input TXDATFLITPEND, input TXDATFLITV, input TXDATFLIT, input TXDATLCRDV ) Asynchronous monitor modport suitable for SV RN Bind interface connection in Passive mode. MTI and NC reported compile errors with synchronous monitor modport. This was required to resolve the above issue.

modport debug_modport ( output req_obj_num, output rx_rsp_obj_num, output rx_dat_obj_num, output tx_rsp_obj_num, output tx_dat_obj_num, output snp_req_obj_num, output snp_dat_obj_num, output snp_rsp_obj_num, output curr_req_lcrd_count, output curr_txrsp_lcrd_count, output curr_txdat_lcrd_count, output curr_snp_lcrd_count, output curr_rxrsp_lcrd_count, output curr_rxdat_lcrd_count ) Debug Modport

Clocking blocks
clocking rn_cb @ ( posedge clk ) default input #0.1 output #0.1 output TXSACTIVE, input RXSACTIVE, output TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, output RXLINKACTIVEACK, output SYSCOREQ, input SYSCOACK, output TXREQFLITPEND, output TXREQFLITV, output TXREQFLIT, input TXREQLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, output RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, output RXDATLCRDV, input RXSNPFLITPEND, input RXSNPFLITV, input RXSNPFLIT, output RXSNPLCRDV, output TXRSPFLITPEND, output TXRSPFLITV, output TXRSPFLIT, input TXRSPLCRDV, output TXDATFLITPEND, output TXDATFLITV, output TXDATFLIT, input TXDATLCRDV Clocking block that defines VIP CHI RN Interface signal synchronization and directionality.

clocking monitor_cb @ ( posedge clk ) default input #0.1 output #0.1 input TXSACTIVE, input RXSACTIVE, input TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, input RXLINKACTIVEACK, input SYSCOREQ, input SYSCOACK, input TXREQFLITPEND, input TXREQFLITV, input TXREQFLIT, input TXREQLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, input RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, input RXDATLCRDV, input RXSNPFLITPEND, input RXSNPFLITV, input RXSNPFLIT, input RXSNPLCRDV, input TXRSPFLITPEND, input TXRSPFLITV, input TXRSPFLIT, input TXRSPLCRDV, input TXDATFLITPEND, input TXDATFLITV, input TXDATFLIT, input TXDATLCRDV Clocking block that defines VIP CHI RN Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_chi_sn_if ( input logic clk, input logic resetn ) General description: The SN interface svt_chi_sn_if defines the CHI signals appropriate for a fully coherent Slave Node, along with the modports needed for the CHI SN and monitor VIP. SN interface is a sub-interface to the top level interface svt_chi_if. Clock signal description: Clock signal is obtained in this SN interface through interface port list. User provides this signal from the testbench to the top level interface svt_chi_if through interface port list. The top level interface then passes this signal down to the SN sub-interface. Debug port description: The CHI VIP drives the object number of the transaction corresponding to a flit on the debug ports. The CHI VIP drives the current l-credit count corresponding to each virtual channel on the debug ports. curr_txrsp_lcrd_count : Current TX RSP VC l-credit count, will be driven whenever there is a change in TX RSP VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_txdat_lcrd_count : Current TX DAT VC l-credit count, will be driven whenever there is a change in TX DAT VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_req_lcrd_count : Current RX REQ VC l-credit count, will be driven whenever there is a change in RX REQ VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_req_vc_flit_buffer_size curr_rxdat_lcrd_count : Current RX DAT VC l-credit count, will be driven whenever there is a change in RX DAT VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size CHI signal description: This sub-interface supports signals for the CHI protocol. The names of the signals match the names specified in the CHI specification. Please refer to the CHI specification for specific description of any of the signals.

Ports
bit	is_active
logic	TXSACTIVE
logic	RXSACTIVE
logic	TXLINKACTIVEREQ
logic	TXLINKACTIVEACK
logic	RXLINKACTIVEREQ
logic	RXLINKACTIVEACK
logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0]	RXREQFLITPEND
logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0]	RXREQFLITV
logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0]	RXREQFLIT
logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0]	RXREQLCRDV
logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0]	TXRSPFLITPEND
logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0]	TXRSPFLITV
logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0]	TXRSPFLIT
logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0]	TXRSPLCRDV
logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0]	TXDATFLITPEND
logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0]	TXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	TXDATFLIT
logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0]	TXDATLCRDV
logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0]	RXDATFLITPEND
logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0]	RXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	RXDATFLIT
logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0]	RXDATLCRDV
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	req_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	rx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_txdat_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_txrsp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_req_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_rxdat_lcrd_count
string	full_name

Modports
modport sn_modport ( input resetn, clocking sn_cb ) Modport used to connect the VIP HN to CHI interface signals.

modport monitor_modport ( input resetn, clocking monitor_cb ) Modport used to connect the VIP Monitor to CHI interface signals.

modport sn_async_modport ( output TXSACTIVE, input RXSACTIVE, output TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, output RXLINKACTIVEACK, input RXREQFLITPEND, input RXREQFLITV, input RXREQFLIT, output RXREQLCRDV, output TXRSPFLITPEND, output TXRSPFLITV, output TXRSPFLIT, input TXRSPLCRDV, output TXDATFLITPEND, output TXDATFLITV, output TXDATFLIT, input TXDATLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, output RXDATLCRDV ) Asynchronous modport suitable for SV SN Bind interface.

modport monitor_async_modport ( input TXSACTIVE, input RXSACTIVE, input TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, input RXLINKACTIVEACK, input RXREQFLITPEND, input RXREQFLITV, input RXREQFLIT, input RXREQLCRDV, input TXRSPFLITPEND, input TXRSPFLITV, input TXRSPFLIT, input TXRSPLCRDV, input TXDATFLITPEND, input TXDATFLITV, input TXDATFLIT, input TXDATLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, input RXDATLCRDV ) Asynchronous monitor modport suitable for SV SN Bind interface connection in Passive mode. MTI and NC reported compile errors with synchronous monitor modport. This was required to resolve the above issue.

modport debug_modport ( output req_obj_num, output rx_dat_obj_num, output tx_rsp_obj_num, output tx_dat_obj_num, output curr_req_lcrd_count, output curr_txdat_lcrd_count, output curr_txrsp_lcrd_count, output curr_rxdat_lcrd_count ) Debug Modport

Clocking blocks
clocking sn_cb @ ( posedge clk ) default input #0.1 output #0.1 output TXSACTIVE, input RXSACTIVE, output TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, output RXLINKACTIVEACK, input RXREQFLITPEND, input RXREQFLITV, input RXREQFLIT, output RXREQLCRDV, output TXRSPFLITPEND, output TXRSPFLITV, output TXRSPFLIT, input TXRSPLCRDV, output TXDATFLITPEND, output TXDATFLITV, output TXDATFLIT, input TXDATLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, output RXDATLCRDV Clocking block that defines VIP CHI SN Interface signal synchronization and directionality.

clocking monitor_cb @ ( posedge clk ) default input #0.1 output #0.1 input TXSACTIVE, input RXSACTIVE, input TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, input RXLINKACTIVEACK, input RXREQFLITPEND, input RXREQFLITV, input RXREQFLIT, input RXREQLCRDV, input TXRSPFLITPEND, input TXRSPFLITV, input TXRSPFLIT, input TXRSPLCRDV, input TXDATFLITPEND, input TXDATFLITV, input TXDATFLIT, input TXDATLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, input RXDATLCRDV Clocking block that defines VIP CHI SN Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_chi_ic_rn_if ( input logic clk, input logic resetn ) General description: The RN interface svt_chi_ic_rn_if defines the CHI signals appropriate for an interconnect node that connects to a fully coherent Request Node, along with the modports needed for the CHI Interconnect and monitor VIP. IC RN interface is a sub-interface to the top level interface svt_chi_if. Clock signal description: Clock signal is obtained in this IC RN interface through interface port list. User provides this signal from the testbench to the top level interface svt_chi_if through interface port list. The top level interface then passes this signal down to the RN sub-interface. Debug port description: The CHI VIP drives the object number of the transaction corresponding to a flit on the debug ports. The CHI VIP drives the current l-credit count corresponding to each virtual channel on the debug ports. curr_snp_lcrd_count : Current TX SNP VC l-credit count, will be driven whenever there is a change in TX SNP VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_txrsp_lcrd_count : Current TX RSP VC l-credit count, will be driven whenever there is a change in TX RSP VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_txdat_lcrd_count : Current TX DAT VC l-credit count, will be driven whenever there is a change in TX DAT VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_req_lcrd_count : Current RX REQ VC l-credit count, will be driven whenever there is a change in RX REQ VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_req_vc_flit_buffer_size curr_rxrsp_lcrd_count : Current RX RSP VC l-credit count, will be driven whenever there is a change in RX RSP VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_rsp_vc_flit_buffer_size curr_rxdat_lcrd_count : Current RX DAT VC l-credit count, will be driven whenever there is a change in RX DAT VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size CHI signal description: This sub-interface supports signals for the CHI protocol. The names of the signals match the names specified in the CHI specification. Please refer to the CHI specification for specific description of any of the signals.

Ports
bit	is_active
logic	RXSACTIVE
logic	TXSACTIVE
logic	RXLINKACTIVEREQ
logic	RXLINKACTIVEACK
logic	TXLINKACTIVEREQ
logic	TXLINKACTIVEACK
logic	SYSCOREQ
logic	SYSCOACK
logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0]	RXREQFLITPEND
logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0]	RXREQFLITV
logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0]	RXREQFLIT
logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0]	RXREQLCRDV
logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0]	TXRSPFLITPEND
logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0]	TXRSPFLITV
logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0]	TXRSPFLIT
logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0]	TXRSPLCRDV
logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0]	TXDATFLITPEND
logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0]	TXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	TXDATFLIT
logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0]	TXDATLCRDV
logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0]	TXSNPFLITPEND
logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0]	TXSNPFLITV
logic [SVT_CHI_MAX_SNP_FLIT_WIDTH-1:0]	TXSNPFLIT
logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0]	TXSNPLCRDV
logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0]	RXRSPFLITPEND
logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0]	RXRSPFLITV
logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0]	RXRSPFLIT
logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0]	RXRSPLCRDV
logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0]	RXDATFLITPEND
logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0]	RXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	RXDATFLIT
logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0]	RXDATLCRDV
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	req_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	rx_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	rx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_req_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_snp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_txrsp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_txdat_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_req_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_rxrsp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_rxdat_lcrd_count
string	full_name

Modports
modport ic_rn_modport ( input resetn, clocking sn_cb ) Modport used to connect the VIP HN to CHI interface signals.

modport monitor_modport ( input resetn, clocking monitor_cb ) Modport used to connect the VIP Monitor to CHI interface signals.

modport debug_modport ( output req_obj_num, output rx_rsp_obj_num, output rx_dat_obj_num, output tx_rsp_obj_num, output tx_dat_obj_num, output snp_req_obj_num, output snp_dat_obj_num, output snp_rsp_obj_num, output curr_req_lcrd_count, output curr_txrsp_lcrd_count, output curr_txdat_lcrd_count, output curr_snp_lcrd_count, output curr_rxrsp_lcrd_count, output curr_rxdat_lcrd_count ) Debug Modport

Clocking blocks
clocking sn_cb @ ( posedge clk ) default input #0.1 output #0.1 input RXSACTIVE, output TXSACTIVE, input RXLINKACTIVEREQ, output RXLINKACTIVEACK, output TXLINKACTIVEREQ, input TXLINKACTIVEACK, input SYSCOREQ, output SYSCOACK, input RXREQFLITPEND, input RXREQFLITV, input RXREQFLIT, output RXREQLCRDV, output TXRSPFLITPEND, output TXRSPFLITV, output TXRSPFLIT, input TXRSPLCRDV, output TXDATFLITPEND, output TXDATFLITV, output TXDATFLIT, input TXDATLCRDV, output TXSNPFLITPEND, output TXSNPFLITV, output TXSNPFLIT, input TXSNPLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, output RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, output RXDATLCRDV Clocking block that defines VIP CHI RN Interface signal synchronization and directionality.

clocking monitor_cb @ ( posedge clk ) default input #0.1 output #0.1 input TXSACTIVE, input RXSACTIVE, input TXLINKACTIVEREQ, input TXLINKACTIVEACK, input RXLINKACTIVEREQ, input RXLINKACTIVEACK, input SYSCOREQ, input SYSCOACK, input RXREQFLITPEND, input RXREQFLITV, input RXREQFLIT, input RXREQLCRDV, input TXRSPFLITPEND, input TXRSPFLITV, input TXRSPFLIT, input TXRSPLCRDV, input TXDATFLITPEND, input TXDATFLITV, input TXDATFLIT, input TXDATLCRDV, input TXSNPFLITPEND, input TXSNPFLITV, input TXSNPFLIT, input TXSNPLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, input RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, input RXDATLCRDV Clocking block that defines VIP CHI RN Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_chi_ic_sn_if ( input logic clk, input logic resetn ) General description: The SN interface svt_chi_ic_sn_if defines the CHI signals appropriate for a node in the interconnect that connects to a fully coherent Slave Node, along with the modports needed for the Interconnect and monitor VIP. IC SN interface is a sub-interface to the top level interface svt_chi_if. Clock signal description: Clock signal is obtained in this IC SN interface through interface port list. User provides this signal from the testbench to the top level interface svt_chi_if through interface port list. The top level interface then passes this signal down to the SN sub-interface. Debug port description: The CHI VIP drives the object number of the transaction corresponding to a flit on the debug ports. The CHI VIP drives the current l-credit count corresponding to each virtual channel on the debug ports. curr_req_lcrd_count : Current TX REQ VC l-credit count, will be driven whenever there is a change in TX REQ VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_txdat_lcrd_count : Current TX DAT VC l-credit count, will be driven whenever there is a change in TX DAT VC l-credit count On power up or reset will be driven to default l-credit count value zero curr_rxrsp_lcrd_count : Current RX RSP VC l-credit count, will be driven whenever there is a change in RX RSP VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_rsp_vc_flit_buffer_size curr_rxdat_lcrd_count : Current RX DAT VC l-credit count, will be driven whenever there is a change in RX DAT VC l-credit count On power up or reset will be driven to default l-credit count value svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size CHI signal description: This sub-interface supports signals for the CHI protocol. The names of the signals match the names specified in the CHI specification. Please refer to the CHI specification for specific description of any of the signals.

Ports
bit	is_active
logic	TXSACTIVE
logic	RXSACTIVE
logic	RXLINKACTIVEREQ
logic	RXLINKACTIVEACK
logic	TXLINKACTIVEREQ
logic	TXLINKACTIVEACK
logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0]	TXREQFLITPEND
logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0]	TXREQFLITV
logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0]	TXREQFLIT
logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0]	TXREQLCRDV
logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0]	RXRSPFLITPEND
logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0]	RXRSPFLITV
logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0]	RXRSPFLIT
logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0]	RXRSPLCRDV
logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0]	RXDATFLITPEND
logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0]	RXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	RXDATFLIT
logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0]	RXDATLCRDV
logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0]	TXDATFLITPEND
logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0]	TXDATFLITV
logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0]	TXDATFLIT
logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0]	TXDATLCRDV
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	req_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	rx_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	rx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	tx_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_req_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_dat_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	snp_rsp_obj_num
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_req_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_txdat_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_rxrsp_lcrd_count
logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0]	curr_rxdat_lcrd_count
string	full_name

Modports
modport ic_sn_modport ( input resetn, clocking rn_cb ) Modport used to connect the VIP HN to CHI interface signals.

modport monitor_modport ( input resetn, clocking monitor_cb ) Modport used to connect the VIP Monitor to CHI interface signals.

modport debug_modport ( output req_obj_num, output rx_rsp_obj_num, output rx_dat_obj_num, output tx_rsp_obj_num, output tx_dat_obj_num, output snp_req_obj_num, output snp_dat_obj_num, output snp_rsp_obj_num, output curr_req_lcrd_count, output curr_txdat_lcrd_count, output curr_rxrsp_lcrd_count, output curr_rxdat_lcrd_count ) Debug Modport

Clocking blocks
clocking rn_cb @ ( posedge clk ) default input #0.1 output #0.1 output TXSACTIVE, input RXSACTIVE, input RXLINKACTIVEREQ, output RXLINKACTIVEACK, output TXLINKACTIVEREQ, input TXLINKACTIVEACK, output TXREQFLITPEND, output TXREQFLITV, output TXREQFLIT, input TXREQLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, output RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, output RXDATLCRDV, output TXDATFLITPEND, output TXDATFLITV, output TXDATFLIT, input TXDATLCRDV Clocking block that defines VIP CHI SN Interface signal synchronization and directionality.

clocking monitor_cb @ ( posedge clk ) default input #0.1 output #0.1 input RXSACTIVE, input TXSACTIVE, input RXLINKACTIVEREQ, input RXLINKACTIVEACK, input TXLINKACTIVEREQ, input TXLINKACTIVEACK, input TXREQFLITPEND, input TXREQFLITV, input TXREQFLIT, input TXREQLCRDV, input RXRSPFLITPEND, input RXRSPFLITV, input RXRSPFLIT, input RXRSPLCRDV, input RXDATFLITPEND, input RXDATFLITV, input RXDATFLIT, input RXDATLCRDV, input TXDATFLITPEND, input TXDATFLITV, input TXDATFLIT, input TXDATLCRDV Clocking block that defines VIP CHI SN Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_chi_if

(

input logic clk,
input logic resetn

)

General description:

CHI VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_chi_if is defined. The top level interface contains an array of RN & SN interfaces. By default, 16 RN and 16 SN interfaces are defined in the top level interface. Currently, the maximum RN and SN interfaces supported is 512 and 128 respectively. The number of RN and SN interfaces in top level interface can be controlled using macros the SVT_CHI_MAX_NUM_RNS_{0..512} and SVT_CHI_MAX_NUM_SNS_{0..128} respectively. For example, if you want to use 8 RN interfaces and 10 SN interfaces, you can define following macros when compiling the VIP:

SVT_CHI_MAX_NUM_RNS_8

SVT_CHI_MAX_NUM_SNS_10
Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces:

Interface Name	Interface Description
svt_chi_rn_if	RN Interface used by RN VIP component contained within the CHI System component
svt_chi_sn_if	Sn Interface used by sn VIP component contained within the CHI System component

Clock signal description:

Common clock mode - Default usage:
- Clock signal 'clk' is provided to the svt_chi_if through interface port list.
- This clock signal is then passed down to the sub-interfaces for RN, SN.
Multi clock mode - Usage with port specific clock:
- This feature is enabled by defining the following compile time macro `SVT_CHI_ENABLE_MULTI_CLOCK
- An array of clocks meant for the each RN [(16-1):0] is supplied through interface port rn_clk[(16-1):0]. The RN sub-interface for a given index 'i' rn_if[i], ic_rn_if[i] is supplied with rn_clk[i].
- An array of clocks meant for the each SN [(16-1):0] is supplied through interface port sn_clk[(16-1):0]. The SN sub-interface for a given index 'i' sn_if[i], ic_sn_if[i] is supplied with sn_clk[i].

Reset signal description:

Common reset mode - Default usage:
- Reset signal 'resetn' is provided to the svt_chi_if through interface port list.
- This rest signal is then passed down to the sub-interfaces for RN, SN.
Multi reset mode - Usage with port specific reset:
- This feature is enabled by defining the following compile time macro `SVT_CHI_ENABLE_MULTI_RESET
- An array of resetn signals meant for the each RN [(16-1):0] is supplied through interface port rn_resetn[(16-1):0]. The RN sub-interface for a given index 'i' rn_if[i], ic_rn_if[i] is supplied with rn_resetn[i].
- An array of resetn signals meant for the each SN [(16-1):0] is supplied through interface port sn_resetn[(16-1):0]. The SN sub-interface for a given index 'i' sn_if[i], ic_sn_if[i] is supplied with sn_resetn[i].

Following is the interface definition:

interface svt_chi_if (
`ifndef SVT_CHI_ENABLE_MULTI_CLOCK
input logic clk,
`else
input logic rn_clk[(`SVT_CHI_MAX_NUM_RNS-1):0],
input logic sn_clk[(`SVT_CHI_MAX_NUM_SNS-1):0],
`endif
`ifndef SVT_CHI_ENABLE_MULTI_RESET
input logic resetn
`else
input logic rn_resetn[(`SVT_CHI_MAX_NUM_RNS-1):0],
input logic sn_resetn[(`SVT_CHI_MAX_NUM_SNS-1):0]
`endif
);

Sub-interfaces

svt_chi_rn_if

rn_if

svt_chi_ic_rn_if

ic_rn_if

svt_chi_sn_if

sn_if

svt_chi_ic_sn_if

ic_sn_if

Ports

string

full_name

Functions

void function

set_enable_signal_log ()

string function

get_full_name ()

interface svt_ahb_master_if ( input logic common_hclk, input logic common_hresetn, input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hrdata_bus, input logic hready_bus, input logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] hresp_bus, input logic [(SVT_AHB_MAX_DATA_USER_WIDTH-1):0] hrdata_huser_bus ) General description: The master interface svt_ahb_master_if defines the AHB signals appropriate for a single port, along with the modports needed for the AHB master and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Ports
bit	is_active
logic	hclk
logic	hresetn
logic	hgrant
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hrdata
logic	hready
logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]	hresp
logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]	haddr
logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]	hburst
logic	hbusreq
logic	hlock
logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]	hprot
logic	hnonsec
logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]	hsize
logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]	htrans
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hwdata
logic	hwrite
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	addr_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	data_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	xact_beat_num
logic [SVT_AHB_MAX_USER_WIDTH-1:0]	control_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hwdata_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hrdata_huser
string	full_name

Modports
modport svt_ahb_master_modport ( input internal_hresetn, clocking ahb_master_cb ) Modport used to connect the VIP Master to AHB interface signals.

modport svt_ahb_bus_modport ( input haddr, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hsize, input htrans, input hwdata, input hwrite, input control_huser, input hwdata_huser, output hgrant, clocking ahb_bus_cb ) Modport used to connect the VIP Bus to AHB master interface signals. The asynchronous signals are required for multiplexing functionality.

modport svt_ahb_monitor_modport ( input internal_hresetn, clocking ahb_monitor_cb ) Modport used to connect the VIP Monitor to AHB interface signals.

modport svt_ahb_master_async_modport ( input hgrant, input hrdata, input hready, input hresp, input hrdata_huser, output haddr, output hburst, output hbusreq, output hlock, output hprot, output hnonsec, output hsize, output htrans, output hwdata, output hwrite, output control_huser, output hwdata_huser, input is_active ) Asynchronous modport suitable for SV Master Bind interface

modport svt_ahb_debug_modport ( output addr_phase_xact_num, output data_phase_xact_num, output xact_beat_num ) Modport used to connect the VIP Debug Port.

Clocking blocks
clocking ahb_master_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input hrdata, input hready, input hgrant, input hresp, input hrdata_huser, output haddr, output hburst, output hbusreq, output hlock, output hprot, output hnonsec, output hsize, output htrans, output hwdata, output hwrite, output control_huser, output hwdata_huser Clocking block that defines VIP AHB Master Interface signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge common_hclk ) default input #0.01 output #0.01 input haddr, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hsize, input htrans, input hwdata, input hwrite, input control_huser, input hwdata_huser, output hgrant Clocking block that defines VIP AHB Bus-Master Interface signal synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input hgrant, input hrdata, input hready, input hresp, input haddr, input hburst, input hbusreq, input hlock, input hprot, input hnonsec, input hsize, input htrans, input hwdata, input hwrite, input control_huser, input hwdata_huser, input hrdata_huser Clocking block that defines the AHB Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_ahb_slave_if ( input logic common_hclk, input logic common_hresetn, input logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] haddr_bus, input logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] hburst_bus, input logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] hmaster_bus, input logic hmastlock_bus, input logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] hprot_bus, input logic hnonsec_bus, input logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] hsize_bus, input logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] htrans_bus, input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hwdata_bus, input logic hwrite_bus, input logic hready_bus, input logic [SVT_AHB_MAX_USER_WIDTH-1:0] control_huser_bus, input logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] hwdata_huser_bus ) General description: The slave interface svt_ahb_slave_if defines the AHB signals appropriate for a single port, along with the modports needed for the AHB slave and monitor VIP. Debug signals and a debug modport are also defined. The debug port provides useful information for debugging.

Ports
bit	is_active
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hrdata
logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]	hresp
logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]	haddr
logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]	hburst
logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]	hprot
logic	hnonsec
logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]	hsize
logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]	htrans
logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]	hwdata
logic	hwrite
logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]	hmaster
logic	hmastlock
logic [(SVT_AHB_MAX_HSEL_WIDTH-1):0]	hsel
logic	hready_in
logic	hready
logic [(SVT_AHB_MAX_NUM_MASTERS-1):0]	hsplit
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	addr_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	data_phase_xact_num
logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]	xact_beat_num
logic [SVT_AHB_MAX_USER_WIDTH-1:0]	control_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hwdata_huser
logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]	hrdata_huser
string	full_name

Modports
modport svt_ahb_slave_modport ( input internal_hresetn, clocking ahb_slave_cb ) Modport used to connect the VIP Slave to AHB interface signals.

modport svt_ahb_bus_modport ( input hrdata, input hready, input hresp, input hsplit, input hrdata_huser, output hsel, clocking ahb_bus_cb ) Modport used to connect the VIP Bus to AHB master interface signals. Asynchronous signals are required for multiplexing functionality

modport svt_ahb_monitor_modport ( input internal_hresetn, clocking ahb_monitor_cb ) Modport used to connect the VIP Monitor to AHB interface signals.

modport svt_ahb_slave_async_modport ( input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hsel, input hsize, input htrans, input hwdata, input hwrite, input hready_in, input control_huser, input hwdata_huser, output hrdata, output hready, output hresp, output hsplit, output hrdata_huser, input is_active ) Asynchronous modport suitable for SV Slave Bind interface

modport svt_ahb_debug_modport ( output addr_phase_xact_num, output data_phase_xact_num, output xact_beat_num ) Modport used to connect the VIP Debug Port.

Clocking blocks
clocking ahb_slave_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hsel, input hsize, input htrans, input hwdata, input hwrite, input hready_in, input control_huser, input hwdata_huser, output hrdata, output hready, output hresp, output hsplit, output hrdata_huser Clocking block that defines the VIP AHB Bus-Slave Interface signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge common_hclk ) default input #0.01 output #0.01 input hrdata, input hready, input hresp, input hsplit, input hrdata_huser, output hsel Clocking block that defines the VIP AHB slave Interface signal synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge internal_hclk ) default input #0.01 output #0.01 input internal_hresetn, input haddr, input hburst, input hmaster, input hmastlock, input hprot, input hnonsec, input hsel, input hsize, input htrans, input hwdata, input hwrite, input hrdata, input hready, input hready_in, input hresp, input hsplit, input control_huser, input hwdata_huser, input hrdata_huser Clocking block that defines the AHB Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_ahb_if ()

General description:

AHB VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_ahb_if is defined. The top level interface contains reset signal for the bus, and an array of master & slave interfaces. The top level interface can be used for connecting the master & slave components to the AHB Bus. By default, 16 master and 16 slave interfaces are defined in the top level interface. Currently, the maximum number of master and slave interfaces supported is 128. The number of master and slave interfaces in top level interface can be controlled using macros SVT_AHB_MAX_NUM_MASTERS_{0..128} and SVT_AHB_MAX_NUM_SLAVES_{0..128} respectively. For example, if you want to use 8 master interfaces and 10 slave interfaces, you can define following macros when compiling the VIP:

SVT_AHB_MAX_NUM_MASTERS_8

SVT_AHB_MAX_NUM_SLAVES_10
Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces:

Interface Name	Interface Description
svt_ahb_master_if	Master Interface used by master VIP component
svt_ahb_slave_if	Slave Interface used by slave VIP component

Clock signal description:

Signal Name	Signal Description
hclk	This clock signal belongs to the top level AHB Interface. User is expected to connect clock signal in testbench to this hclk signal in the top level interface. This clock is used by all the AHB master and slave VIP components.

Clock connection examples:
assign ahb_if.hclk = SystemClock;

Reset signal description:

Signal Name	Signal Description
hresetn	This reset signal belongs to the top level AHB Interface. User is expected to connect reset signal in testbench to this hclk signal in the top level interface. This reset is used by all the AHB master and slave VIP components.

Reset connection examples:
assign ahb_if.hresetn = SystemResetn;

Sub-interfaces

svt_ahb_master_if

master_if

svt_ahb_slave_if

slave_if

Ports

logic

hclk

logic

hresetn

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]

hrdata_bus

logic

hready_bus

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0]

hresp_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]

hrdata_huser_bus

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0]

haddr_bus

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0]

hburst_bus

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0]

hprot_bus

logic

hnonsec_bus

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0]

hsize_bus

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0]

htrans_bus

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0]

hwdata_bus

logic

hwrite_bus

logic [SVT_AHB_MAX_USER_WIDTH-1:0]

control_huser_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0]

hwdata_huser_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

hmaster_bus

logic

hmastlock_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

curr_hmaster

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0]

prev_hmaster

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]

curr_sel_slave

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0]

prev_sel_slave

logic [SVT_AHB_MAX_NUM_MASTERS-1:0]

hsplit_bus

string

full_name

Modports

modport svt_ahb_bus_modport

(

input hresetn,
output hrdata_bus,
output hready_bus,
output hresp_bus,
output haddr_bus,
output hburst_bus,
output hprot_bus,
output hnonsec_bus,
output hsize_bus,
output htrans_bus,
output hwdata_bus,
output hwrite_bus,
output control_huser_bus,
output hmaster_bus,
output hmastlock_bus,
output hwdata_huser_bus,
output hrdata_huser_bus,
clocking ahb_bus_reset_cb,
clocking ahb_bus_cb

)

Modport used to connect the reset signal to VIP AHB Bus The signals corresponding to following need to be asynchronous

The address, control, write data from granted master to all slaves
The response, read data from selected slave to all masters

modport svt_ahb_monitor_modport

(

input hresetn,
input hrdata_bus,
input hready_bus,
input hresp_bus,
input haddr_bus,
input hburst_bus,
input hprot_bus,
input hnonsec_bus,
input hsize_bus,
input htrans_bus,
input hwdata_bus,
input hwrite_bus,
input control_huser_bus,
input hmaster_bus,
input hmastlock_bus,
input hwdata_huser_bus,
input hrdata_huser_bus,
clocking ahb_bus_reset_cb,
clocking ahb_monitor_cb

)

Monitor modport for the bus signals. The Modport includes the clocking blocks for synchronous sampling. It also includes the signals directly for asynnchronous sampling wherever it is required.

modport svt_ahb_debug_modport

(

output curr_hmaster,
output prev_hmaster,
output curr_sel_slave,
output prev_sel_slave,
output hsplit_bus

)

Debug modport

Clocking blocks

clocking ahb_bus_reset_cb @ ( posedge hclk )
default input #0.01 output #0.01

input hresetn

Clocking block that defines the VIP AHB Bus Interface reset signal synchronization and directionality.

clocking ahb_bus_cb @ ( posedge hclk )
default input #0.01 output #0.01

output hmaster_bus,
output hmastlock_bus

Clocking block that defines the VIP AHB Bus Interface bus to all slaves signals synchronization and directionality.

clocking ahb_monitor_cb @ ( posedge hclk )
default input #0.01 output #0.01

input hrdata_bus,
input hready_bus,
input hresp_bus,
input haddr_bus,
input hburst_bus,
input hprot_bus,
input hnonsec_bus,
input hsize_bus,
input htrans_bus,
input hwdata_bus,
input hwrite_bus,
input control_huser_bus,
input hmaster_bus,
input hmastlock_bus,
input hwdata_huser_bus,
input hrdata_huser_bus

Clocking block that defines the VIP AHB Bus Interface bus to all slaves signals synchronization and directionality.

Functions

virtual AHB_MASTER_IF function

get_master_if (int idx)

void function

set_enable_signal_log ()

string function

get_full_name ()

interface svt_apb_slave_if () APB Slave Interface provides the SystemVerilog interface which can be used to connect the Slave VIP to a DUT. A top level interface svt_apb_if is defined. The top level interface contains the system level pins and an array of slave interfaces.

Ports
bit	is_active
logic	pclk
logic	presetn
logic	psel
logic	penable
logic	pwrite
logic [(SVT_APB_MAX_ADDR_WIDTH-1):0]	paddr
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	pwdata
logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0]	pstrb
logic [2:0]	pprot
logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0]	control_puser
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	prdata
logic	pready
logic	pslverr
logic [31:0]	xact_id
logic [31:0]	mon_xact_id
string	full_name

Modports
modport svt_apb_slave_modport ( clocking apb_slave_cb ) Modport used to connect the VIP Slave to APB interface signals.

modport svt_apb_monitor_modport ( input presetn, clocking apb_monitor_cb ) Modport used to connect the VIP Monitor to APB interface signals.

modport svt_apb_debug_modport ( output xact_id, output mon_xact_id ) Modport used to connect the VIP Debug Port.

modport svt_apb_slave_async_modport ( input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, output prdata, output pready, output pslverr ) Asynchronous modport suitable for SV Slave Bind interface

Clocking blocks
clocking apb_slave_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pstrb, input pprot, input control_puser, output prdata, output pready, output pslverr Clocking block that defines VIP APB Slave Interface signal synchronization and directionality.

clocking apb_monitor_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB System Monitor Interface signal synchronization and directionality.

Functions
void function	set_enable_signal_log ()
string function	get_full_name ()

interface svt_apb_if () APB VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_apb_if is defined. The top level interface contains the system level pins and an array of slave interfaces. By default, 16 slave interfaces are defined in the top level interface. Currently, the maximum number of slave interfaces supported is 128. The number of slave interfaces in top level interface can be controlled using macro SVT_APB_MAX_NUM_SLAVES_{0..128}. For example, if you want to use 20 slave interfaces, you can define following macro when compiling the VIP: SVT_APB_MAX_NUM_SLAVES_20 Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

Sub-interfaces
svt_apb_slave_if	slave_if

Ports
bit	is_active
bit	disable_x_check_of_presetn
bit	disable_x_check_of_pclk
logic	pclk
logic	presetn
logic [(SVT_APB_MAX_NUM_SLAVES-1):0]	psel
logic	penable
logic	pwrite
logic [(SVT_APB_MAX_ADDR_WIDTH-1):0]	paddr
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	pwdata
logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0]	pstrb
logic [2:0]	pprot
logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0]	control_puser
logic [(SVT_APB_MAX_DATA_WIDTH-1):0]	prdata
logic	pready
logic	pslverr
logic [31:0]	xact_id
logic [31:0]	mon_xact_id
string	full_name

Modports
modport svt_apb_master_modport ( input presetn, clocking apb_master_cb ) Modport used to connect the VIP Master to APB interface signals.

modport svt_apb_monitor_modport ( input presetn, clocking apb_monitor_cb ) Modport used to connect the VIP Monitor to APB interface signals.

modport svt_apb_debug_modport ( output xact_id, output mon_xact_id ) Modport used to connect the VIP Debug Port.

modport svt_apb_master_async_modport ( input presetn, output psel, output penable, output pwrite, output paddr, output pwdata, output pstrb, output pprot, output control_puser, input prdata, input pready, input pslverr ) Asynchronous modport suitable for SV Master Bind interface

Clocking blocks
clocking apb_master_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, output psel, output penable, output pwrite, output paddr, output pwdata, output pstrb, output pprot, output control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB Master Interface signal synchronization and directionality.

clocking apb_monitor_cb @ ( posedge pclk ) default input #0.01 output #0.01 input presetn, input psel, input penable, input pwrite, input paddr, input pwdata, input pstrb, input pprot, input control_puser, input prdata, input pready, input pslverr Clocking block that defines VIP APB System Monitor Interface signal synchronization and directionality.

Functions
virtual APB_SLAVE_IF function	get_slave_if (int idx)
void function	set_enable_signal_log ()
string function	get_full_name ()

function void
svt_chi_rn_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_chi_rn_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_chi_rn_if signal
input logic clk

interface svt_chi_rn_if signal
input logic resetn

bit attribute
svt_chi_rn_if::is_active

logic attribute
svt_chi_rn_if::TXSACTIVE

logic attribute
svt_chi_rn_if::RXSACTIVE

logic attribute
svt_chi_rn_if::TXLINKACTIVEREQ

logic attribute
svt_chi_rn_if::TXLINKACTIVEACK

logic attribute
svt_chi_rn_if::RXLINKACTIVEREQ

logic attribute
svt_chi_rn_if::RXLINKACTIVEACK

logic attribute
svt_chi_rn_if::SYSCOREQ

logic attribute
svt_chi_rn_if::SYSCOACK

logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0] attribute
svt_chi_rn_if::TXREQFLITPEND

logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0] attribute
svt_chi_rn_if::TXREQFLITV

logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0] attribute
svt_chi_rn_if::TXREQFLIT

logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0] attribute
svt_chi_rn_if::TXREQLCRDV

logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0] attribute
svt_chi_rn_if::RXRSPFLITPEND

logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0] attribute
svt_chi_rn_if::RXRSPFLITV

logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0] attribute
svt_chi_rn_if::RXRSPFLIT

logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0] attribute
svt_chi_rn_if::RXRSPLCRDV

logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_rn_if::RXDATFLITPEND

logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_rn_if::RXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_rn_if::RXDATFLIT

logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_rn_if::RXDATLCRDV

logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0] attribute
svt_chi_rn_if::RXSNPFLITPEND

logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0] attribute
svt_chi_rn_if::RXSNPFLITV

logic [SVT_CHI_MAX_SNP_FLIT_WIDTH-1:0] attribute
svt_chi_rn_if::RXSNPFLIT

logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0] attribute
svt_chi_rn_if::RXSNPLCRDV

logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_rn_if::TXRSPFLITPEND

logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_rn_if::TXRSPFLITV

logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0] attribute
svt_chi_rn_if::TXRSPFLIT

logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_rn_if::TXRSPLCRDV

logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_rn_if::TXDATFLITPEND

logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_rn_if::TXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_rn_if::TXDATFLIT

logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_rn_if::TXDATLCRDV

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::req_obj_num

Object number of the transaction currently observed on REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::rx_rsp_obj_num

Object number of the transaction currently observed on RX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::rx_dat_obj_num

Object number of the transaction currently observed on RX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::tx_rsp_obj_num

Object number of the transaction currently observed on TX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::tx_dat_obj_num

Object number of the transaction currently observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::snp_req_obj_num

Object number of the transaction currently observed on SNP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::snp_dat_obj_num

Object number of the transaction currently observed on TX DAT VC, if it corresponds to a snoop transaction

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::snp_rsp_obj_num

Object number of the transaction currently observed on TX RSP VC, if it corresponds to a snoop transaction

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::curr_req_lcrd_count

Current L-credit count observed on TX REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::curr_txrsp_lcrd_count

Current L-credit count observed on TX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::curr_txdat_lcrd_count

Current L-credit count observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::curr_snp_lcrd_count

Current L-credit count observed on RX SNP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::curr_rxrsp_lcrd_count

Current L-credit count observed on RX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_rn_if::curr_rxdat_lcrd_count

Current L-credit count observed on RX DAT VC

string attribute
svt_chi_rn_if::full_name

Full path to this interface or module instance

function void
svt_chi_sn_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_chi_sn_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_chi_sn_if signal
input logic clk

interface svt_chi_sn_if signal
input logic resetn

bit attribute
svt_chi_sn_if::is_active

logic attribute
svt_chi_sn_if::TXSACTIVE

logic attribute
svt_chi_sn_if::RXSACTIVE

logic attribute
svt_chi_sn_if::TXLINKACTIVEREQ

logic attribute
svt_chi_sn_if::TXLINKACTIVEACK

logic attribute
svt_chi_sn_if::RXLINKACTIVEREQ

logic attribute
svt_chi_sn_if::RXLINKACTIVEACK

logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0] attribute
svt_chi_sn_if::RXREQFLITPEND

logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0] attribute
svt_chi_sn_if::RXREQFLITV

logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0] attribute
svt_chi_sn_if::RXREQFLIT

logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0] attribute
svt_chi_sn_if::RXREQLCRDV

logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_sn_if::TXRSPFLITPEND

logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_sn_if::TXRSPFLITV

logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0] attribute
svt_chi_sn_if::TXRSPFLIT

logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_sn_if::TXRSPLCRDV

logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_sn_if::TXDATFLITPEND

logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_sn_if::TXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_sn_if::TXDATFLIT

logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_sn_if::TXDATLCRDV

logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_sn_if::RXDATFLITPEND

logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_sn_if::RXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_sn_if::RXDATFLIT

logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_sn_if::RXDATLCRDV

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::req_obj_num

Object number of the transaction currently observed on REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::rx_dat_obj_num

Object number of the transaction currently observed on RX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::tx_rsp_obj_num

Object number of the transaction currently observed on TX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::tx_dat_obj_num

Object number of the transaction currently observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::curr_txdat_lcrd_count

Current L-credit count observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::curr_txrsp_lcrd_count

Current L-credit count observed on TX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::curr_req_lcrd_count

Current L-credit count observed on RX REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_sn_if::curr_rxdat_lcrd_count

Current L-credit count observed on RX DAT VC

string attribute
svt_chi_sn_if::full_name

Full path to this interface or module instance

function void
svt_chi_ic_rn_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_chi_ic_rn_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_chi_ic_rn_if signal
input logic clk

interface svt_chi_ic_rn_if signal
input logic resetn

bit attribute
svt_chi_ic_rn_if::is_active

logic attribute
svt_chi_ic_rn_if::RXSACTIVE

logic attribute
svt_chi_ic_rn_if::TXSACTIVE

logic attribute
svt_chi_ic_rn_if::RXLINKACTIVEREQ

logic attribute
svt_chi_ic_rn_if::RXLINKACTIVEACK

logic attribute
svt_chi_ic_rn_if::TXLINKACTIVEREQ

logic attribute
svt_chi_ic_rn_if::TXLINKACTIVEACK

logic attribute
svt_chi_ic_rn_if::SYSCOREQ

logic attribute
svt_chi_ic_rn_if::SYSCOACK

logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXREQFLITPEND

logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXREQFLITV

logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0] attribute
svt_chi_ic_rn_if::RXREQFLIT

logic [(SVT_CHI_RN_MAX_TXREQ_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXREQLCRDV

logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXRSPFLITPEND

logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXRSPFLITV

logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0] attribute
svt_chi_ic_rn_if::TXRSPFLIT

logic [(SVT_CHI_RN_MAX_RXRSP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXRSPLCRDV

logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXDATFLITPEND

logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_ic_rn_if::TXDATFLIT

logic [(SVT_CHI_RN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXDATLCRDV

logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXSNPFLITPEND

logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXSNPFLITV

logic [SVT_CHI_MAX_SNP_FLIT_WIDTH-1:0] attribute
svt_chi_ic_rn_if::TXSNPFLIT

logic [(SVT_CHI_RN_MAX_RXSNP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::TXSNPLCRDV

logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXRSPFLITPEND

logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXRSPFLITV

logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0] attribute
svt_chi_ic_rn_if::RXRSPFLIT

logic [(SVT_CHI_RN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXRSPLCRDV

logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXDATFLITPEND

logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_ic_rn_if::RXDATFLIT

logic [(SVT_CHI_RN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_ic_rn_if::RXDATLCRDV

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::req_obj_num

Object number of the transaction currently observed on REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::rx_rsp_obj_num

Object number of the transaction currently observed on RX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::rx_dat_obj_num

Object number of the transaction currently observed on RX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::tx_rsp_obj_num

Object number of the transaction currently observed on TX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::tx_dat_obj_num

Object number of the transaction currently observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::snp_req_obj_num

Object number of the transaction currently observed on SNP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::snp_dat_obj_num

Object number of the transaction currently observed on TX DAT VC, if it corresponds to a snoop transaction

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::snp_rsp_obj_num

Object number of the transaction currently observed on TX RSP VC, if it corresponds to a snoop transaction

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::curr_snp_lcrd_count

Current L-credit count observed on TX SNP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::curr_txrsp_lcrd_count

Current L-credit count observed on TX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::curr_txdat_lcrd_count

Current L-credit count observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::curr_req_lcrd_count

Current L-credit count observed on RX REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::curr_rxrsp_lcrd_count

Current L-credit count observed on RX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_rn_if::curr_rxdat_lcrd_count

Current L-credit count observed on RX DAT VC

string attribute
svt_chi_ic_rn_if::full_name

Full path to this interface or module instance

function void
svt_chi_ic_sn_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_chi_ic_sn_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_chi_ic_sn_if signal
input logic clk

interface svt_chi_ic_sn_if signal
input logic resetn

bit attribute
svt_chi_ic_sn_if::is_active

logic attribute
svt_chi_ic_sn_if::TXSACTIVE

logic attribute
svt_chi_ic_sn_if::RXSACTIVE

logic attribute
svt_chi_ic_sn_if::RXLINKACTIVEREQ

logic attribute
svt_chi_ic_sn_if::RXLINKACTIVEACK

logic attribute
svt_chi_ic_sn_if::TXLINKACTIVEREQ

logic attribute
svt_chi_ic_sn_if::TXLINKACTIVEACK

logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::TXREQFLITPEND

logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::TXREQFLITV

logic [SVT_CHI_MAX_REQ_FLIT_WIDTH-1:0] attribute
svt_chi_ic_sn_if::TXREQFLIT

logic [(SVT_CHI_SN_MAX_RXREQ_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::TXREQLCRDV

logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::RXRSPFLITPEND

logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::RXRSPFLITV

logic [SVT_CHI_MAX_RSP_FLIT_WIDTH-1:0] attribute
svt_chi_ic_sn_if::RXRSPFLIT

logic [(SVT_CHI_SN_MAX_TXRSP_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::RXRSPLCRDV

logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::RXDATFLITPEND

logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::RXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_ic_sn_if::RXDATFLIT

logic [(SVT_CHI_SN_MAX_TXDAT_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::RXDATLCRDV

logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::TXDATFLITPEND

logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::TXDATFLITV

logic [SVT_CHI_MAX_DAT_FLIT_WIDTH-1:0] attribute
svt_chi_ic_sn_if::TXDATFLIT

logic [(SVT_CHI_SN_MAX_RXDAT_CHANNELS-1):0] attribute
svt_chi_ic_sn_if::TXDATLCRDV

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::req_obj_num

Object number of the transaction currently observed on REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::rx_rsp_obj_num

Object number of the transaction currently observed on RX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::rx_dat_obj_num

Object number of the transaction currently observed on RX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::tx_rsp_obj_num

Object number of the transaction currently observed on TX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::tx_dat_obj_num

Object number of the transaction currently observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::snp_req_obj_num

Object number of the transaction currently observed on SNP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::snp_dat_obj_num

Object number of the transaction currently observed on TX DAT VC, if it corresponds to a snoop transaction

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::snp_rsp_obj_num

Object number of the transaction currently observed on TX RSP VC, if it corresponds to a snoop transaction

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::curr_req_lcrd_count

Current L-credit count observed on TX REQ VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::curr_txdat_lcrd_count

Current L-credit count observed on TX DAT VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::curr_rxrsp_lcrd_count

Current L-credit count observed on RX RSP VC

logic [(SVT_CHI_DEBUG_PORT_WIDTH-1):0] attribute
svt_chi_ic_sn_if::curr_rxdat_lcrd_count

Current L-credit count observed on RX DAT VC

string attribute
svt_chi_ic_sn_if::full_name

Full path to this interface or module instance

function void
svt_chi_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_chi_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_chi_if signal
input logic clk

interface svt_chi_if signal
input logic resetn

svt_chi_rn_if attribute
svt_chi_if::rn_if

svt_chi_ic_rn_if attribute
svt_chi_if::ic_rn_if

svt_chi_sn_if attribute
svt_chi_if::sn_if

svt_chi_ic_sn_if attribute
svt_chi_if::ic_sn_if

string attribute
svt_chi_if::full_name

Full path to this interface or module instance

function void
svt_ahb_master_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_ahb_master_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_ahb_master_if signal
input logic common_hclk

interface svt_ahb_master_if signal
input logic common_hresetn

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hrdata_bus

interface svt_ahb_master_if signal
input logic hready_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] hresp_bus

interface svt_ahb_master_if signal
input logic [(SVT_AHB_MAX_DATA_USER_WIDTH-1):0] hrdata_huser_bus

bit attribute
svt_ahb_master_if::is_active = 1

logic attribute
svt_ahb_master_if::hclk

User clock In multiple clock mode, user is expected to drive this signal

logic attribute
svt_ahb_master_if::hresetn

User reset In multiple reset mode, user is expected to drive this signal

logic attribute
svt_ahb_master_if::hgrant

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_master_if::hrdata

logic attribute
svt_ahb_master_if::hready

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hresp

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] attribute
svt_ahb_master_if::haddr

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hburst

logic attribute
svt_ahb_master_if::hbusreq

logic attribute
svt_ahb_master_if::hlock

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hprot

logic attribute
svt_ahb_master_if::hnonsec

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::hsize

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::htrans

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_master_if::hwdata

logic attribute
svt_ahb_master_if::hwrite

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::addr_phase_xact_num

Debug port signals

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::data_phase_xact_num

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_master_if::xact_beat_num

logic [SVT_AHB_MAX_USER_WIDTH-1:0] attribute
svt_ahb_master_if::control_huser

AHB sideband signals

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_master_if::hwdata_huser

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_master_if::hrdata_huser

string attribute
svt_ahb_master_if::full_name

Full path to this interface or module instance

function void
svt_ahb_slave_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_ahb_slave_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

interface svt_ahb_slave_if signal
input logic common_hclk

interface svt_ahb_slave_if signal
input logic common_hresetn

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] haddr_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] hburst_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] hmaster_bus

interface svt_ahb_slave_if signal
input logic hmastlock_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] hprot_bus

interface svt_ahb_slave_if signal
input logic hnonsec_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] hsize_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] htrans_bus

interface svt_ahb_slave_if signal
input logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] hwdata_bus

interface svt_ahb_slave_if signal
input logic hwrite_bus

interface svt_ahb_slave_if signal
input logic hready_bus

interface svt_ahb_slave_if signal
input logic [SVT_AHB_MAX_USER_WIDTH-1:0] control_huser_bus

interface svt_ahb_slave_if signal
input logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] hwdata_huser_bus

bit attribute
svt_ahb_slave_if::is_active = 1

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_slave_if::hrdata

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hresp

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] attribute
svt_ahb_slave_if::haddr

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hburst

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hprot

logic attribute
svt_ahb_slave_if::hnonsec

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hsize

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::htrans

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_slave_if::hwdata

logic attribute
svt_ahb_slave_if::hwrite

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::hmaster

logic attribute
svt_ahb_slave_if::hmastlock

logic [(SVT_AHB_MAX_HSEL_WIDTH-1):0] attribute
svt_ahb_slave_if::hsel

logic attribute
svt_ahb_slave_if::hready_in

logic attribute
svt_ahb_slave_if::hready

logic [(SVT_AHB_MAX_NUM_MASTERS-1):0] attribute
svt_ahb_slave_if::hsplit

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::addr_phase_xact_num

Debug port signals

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::data_phase_xact_num

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_slave_if::xact_beat_num

logic [SVT_AHB_MAX_USER_WIDTH-1:0] attribute
svt_ahb_slave_if::control_huser

AHB sideband signals

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_slave_if::hwdata_huser

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_slave_if::hrdata_huser

string attribute
svt_ahb_slave_if::full_name

Full path to this interface or module instance

function virtual AHB_MASTER_IF
svt_ahb_if::get_master_if

( int idx )

function void
svt_ahb_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_ahb_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

logic attribute
svt_ahb_if::hclk

logic attribute
svt_ahb_if::hresetn

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_if::hrdata_bus

Bus: Slave to Master Mux signals

logic attribute
svt_ahb_if::hready_bus

logic [(SVT_AHB_HRESP_PORT_WIDTH-1):0] attribute
svt_ahb_if::hresp_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_if::hrdata_huser_bus

logic [(SVT_AHB_MAX_ADDR_WIDTH-1):0] attribute
svt_ahb_if::haddr_bus

Bus: Master to Slave Mux signals

logic [(SVT_AHB_HBURST_PORT_WIDTH-1):0] attribute
svt_ahb_if::hburst_bus

logic [(SVT_AHB_HPROT_PORT_WIDTH-1):0] attribute
svt_ahb_if::hprot_bus

logic attribute
svt_ahb_if::hnonsec_bus

logic [(SVT_AHB_HSIZE_PORT_WIDTH-1):0] attribute
svt_ahb_if::hsize_bus

logic [(SVT_AHB_HTRANS_PORT_WIDTH-1):0] attribute
svt_ahb_if::htrans_bus

logic [(SVT_AHB_MAX_DATA_WIDTH-1):0] attribute
svt_ahb_if::hwdata_bus

logic attribute
svt_ahb_if::hwrite_bus

logic [SVT_AHB_MAX_USER_WIDTH-1:0] attribute
svt_ahb_if::control_huser_bus

logic [SVT_AHB_MAX_DATA_USER_WIDTH-1:0] attribute
svt_ahb_if::hwdata_huser_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_if::hmaster_bus

Bus: Following signals from bus to slave are common, generated by bus

logic attribute
svt_ahb_if::hmastlock_bus

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_if::curr_hmaster

Debug port signals

logic [(SVT_AHB_HMASTER_PORT_WIDTH-1):0] attribute
svt_ahb_if::prev_hmaster

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_if::curr_sel_slave

logic [(SVT_AHB_DEBUG_PORT_WIDTH-1):0] attribute
svt_ahb_if::prev_sel_slave

logic [SVT_AHB_MAX_NUM_MASTERS-1:0] attribute
svt_ahb_if::hsplit_bus

svt_ahb_master_if attribute
svt_ahb_if::master_if

svt_ahb_slave_if attribute
svt_ahb_if::slave_if

string attribute
svt_ahb_if::full_name

Full path to this interface or module instance

function void
svt_apb_slave_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_apb_slave_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

bit attribute
svt_apb_slave_if::is_active = 1

logic attribute
svt_apb_slave_if::pclk

logic attribute
svt_apb_slave_if::presetn

logic attribute
svt_apb_slave_if::psel

logic attribute
svt_apb_slave_if::penable

logic attribute
svt_apb_slave_if::pwrite

logic [(SVT_APB_MAX_ADDR_WIDTH-1):0] attribute
svt_apb_slave_if::paddr

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_slave_if::pwdata

logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0] attribute
svt_apb_slave_if::pstrb

logic [2:0] attribute
svt_apb_slave_if::pprot

logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0] attribute
svt_apb_slave_if::control_puser

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_slave_if::prdata

logic attribute
svt_apb_slave_if::pready

logic attribute
svt_apb_slave_if::pslverr

logic [31:0] attribute
svt_apb_slave_if::xact_id

Debug Signals for master driver

logic [31:0] attribute
svt_apb_slave_if::mon_xact_id

Debug Signals for master monitor

string attribute
svt_apb_slave_if::full_name

Full path to this interface or module instance

function virtual APB_SLAVE_IF
svt_apb_if::get_slave_if

( int idx )

function void
svt_apb_if::set_enable_signal_log

( )

support for signal logging.

function string
svt_apb_if::get_full_name

( )

Simple method for getting the full path for an interface or module.

svt_apb_slave_if attribute
svt_apb_if::slave_if

bit attribute
svt_apb_if::is_active = 1

bit attribute
svt_apb_if::disable_x_check_of_presetn = 0

bit attribute
svt_apb_if::disable_x_check_of_pclk = 0

logic attribute
svt_apb_if::pclk

logic attribute
svt_apb_if::presetn

logic [(SVT_APB_MAX_NUM_SLAVES-1):0] attribute
svt_apb_if::psel

logic attribute
svt_apb_if::penable

logic attribute
svt_apb_if::pwrite

logic [(SVT_APB_MAX_ADDR_WIDTH-1):0] attribute
svt_apb_if::paddr

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_if::pwdata

logic [((SVT_APB_MAX_DATA_WIDTH/8)-1):0] attribute
svt_apb_if::pstrb

logic [2:0] attribute
svt_apb_if::pprot

logic [(SVT_APB_MAX_CONTROL_PUSER_WIDTH-1):0] attribute
svt_apb_if::control_puser

logic [(SVT_APB_MAX_DATA_WIDTH-1):0] attribute
svt_apb_if::prdata[SVT_APB_MAX_NUM_SLAVES-1:0]

logic attribute
svt_apb_if::pready[SVT_APB_MAX_NUM_SLAVES-1:0]

logic attribute
svt_apb_if::pslverr[SVT_APB_MAX_NUM_SLAVES-1:0]

logic [31:0] attribute
svt_apb_if::xact_id

Debug Signals for master driver

logic [31:0] attribute
svt_apb_if::mon_xact_id

Debug Signals for master monitor

string attribute
svt_apb_if::full_name

Full path to this interface or module instance

VIP Smartsearch

AMBA SVT UVM Documentation - Interfaces Reference

Interface Definition Documentation