☛ NOTE: Based on the AMBA Progressive Terminology updates, you must interpret the term Master as Manager, and Slave as Subordinate in the VIP documentation and messages.

Introduction
This is the Class Reference Manual of Synopsys AXI SVT VIP.

The AXI SVT User Guide is installed at:

• Synopsys AXI Verification IP UVM User Manual (PDF)

The AMBA VIP Release Notes are installed at:

• Synopsys AMBA VIP Release Notes (PDF)

The AXI SVT Basic Example QuickStart is installed at:

• AXI SVT Basic Example QuickStart (HTML)

The AXI SVT Verification Plan is installed in $DESIGNWARE_HOME/vip/svt/amba_svt/latest/doc/VerificationPlans. The README file is installed at $DESIGNWARE_HOME/vip/svt/amba_svt/latest/doc/VerificationPlans/AMBA4/README

The Synopsys VIP for AXI is a suite of advanced verification components and data objects based on SystemVerilog UVM-compliant technology. This on-line help contains information about the classes, functions, and member variables. It shows class hierarchy and contents and it provides links you can use to navigate to more details. Below is the summary of the components and the user interface of the Synopsys AXI VIP.

AXI VIP Components

• svt_axi_master_agent Defines an agent for the AXI Master component. The master agent encapsulates master sequencer, master driver, and port monitor. The master agent can be configured to operate in active mode and passive mode.
• svt_axi_slave_agent Defines an agent for the AXI Slave component. The slave agent encapsulates slave sequencer, slave driver, and port monitor. The slave agent can be configured to operate in active mode and passive mode. Slave memory is represented by class svt_mem . Slave memory is instantiated in slave agent. In passive mode, the slave agent keeps the memory updated based on the observed data on the bus. This enables the system-level checks in the passive mode. In active mode, the slave memory is updated by the slave sequence. Refer to slave sequence svt_axi_slave_base_sequence in file $DESIGNWARE_HOME/vip/svt/amba_svt/latest/axi_slave_agent_svt/sverilog/src/vcs/svt_axi_slave_sequence_collection.svp. A reference to the slave memory instantiated in the slave agent is provided in the slave sequence. Using the API of this slave memory, you can read or write into the slave memory through this base sequence, or sequence extended from this base sequence.
• svt_axi_interconnect_env Defines an Interconnect Env component. The Interconnect Env routes the AXI transactions between multiple masters and slaves. The Interconnect Env contains configurable number of master & slave ports. The Interconnect Env routes the transactions from masters to slaves based on address map.
• svt_axi_system_monitor The system monitor observes transactions across the ports of a single interconnect and performs checks between the transactions of these ports. For the list of system checks supported by the system monitor, please click on the "Protocol Checks" tab in this class reference documentation.
• svt_axi_system_env Defines a System ENV for the AXI SVT suite. The AXI System ENV encapsulates the master agents, slave agents, Interconnect Env, system monitor, system sequencer and the system configuration. The number of master and slave agents is configured based on the system configuration provided by the user. The user can specify whether Interconnect Env is required in the System Env, using the system configuration.

AXI VIP User Interface

Configuration Objects:
Configuration data objects convey the system level and port level testbench configuration. The configuration data objects contain built-in constraints, which come into effect when the configuration objects are randomized. If the configuration needs to be changed later, it can be done through reconfigure() method of the master, slave, interconnect or system components. The AXI VIP defines following configuration classes:

• svt_axi_system_configuration System configuration
• svt_axi_port_configuration Port configuration
• svt_axi_interconnect_configuration Interconnect configuration

Transaction Objects:
Transaction objects, which are extended from the uvm_transaction base class, define a unit of AXI protocol information that is passed across the bus. The attributes of transaction objects are public and are accessed directly for setting and getting values. Most transaction attributes can be randomized. The transaction object can represent the desired activity to be simulated on the bus, or the actual bus activity that was monitored. AXI VIP defines following transaction classes:

• svt_axi_transaction (AXI Base transaction)
• svt_axi_master_transaction (AXI Master transaction)
• svt_axi_slave_transaction (AXI Slave transaction)
• svt_axi_snoop_transaction (AXI ACE Snoop Base transaction)
• svt_axi_master_snoop_transaction (AXI ACE Snoop Master transaction)
• svt_axi_ic_master_transaction (AXI transaction on Interconnect Master port, which is connected to a Slave component; Not supported in this release. In current release, port monitor within Interconnect Master Agent provides object of type svt_axi_master_transaction instead of svt_axi_ic_master_transaction)
• svt_axi_ic_slave_transaction (AXI transaction on Interconnect Slave port, which is connected to a Master component)
• svt_axi_ic_snoop_transaction (AXI ACE Snoop transaction on Interconnect Slave port, which is connected to a Master component)
• svt_axi_system_transaction (AXI system transaction)
• svt_amba_pv_extension (TLM 2.0 Generic Payload extension class)

Analysis port:
The port monitor in the Master & Slave agents provides an analysis port. At the end of the transaction, the port monitor within the Master & Slave agents provides the completed svt_axi_master_transaction & svt_axi_slave_transaction object respectively, from its analysis port.
The Port Monitor in the Interconnect Master Agent and Interconnect Slave agent also provides an analysis port. At the end of the transaction on the interconnect ports, the port monitor within the Interconnect Master Agent and Interconnect Slave agent provides the completed svt_axi_ic_master_transaction and svt_axi_ic_slave_transaction object respectively, from its analysis port.
The analysis port used by port monitor within Master agent, Slave agent, Interconnect Master Agent and Interconnect Slave agent is:

• svt_monitor :: item_observed_port

The port monitor in the Master & Slave agents provides an analysis port to provide pre-completion transaction object. The port monitor within the Master & Slave agents will provide svt_axi_master_transaction & svt_axi_slave_transaction object respectively into this new analysis port just after new_transaction_started callback is issued.
The analysis port used by port monitor within Master agent, Slave agent is:

• svt_axi_port_monitor :: item_started_port

The port monitor in the Master agent provides an analysis port to provide completed snoop transaction object. The port monitor within the Master agent will provide svt_axi_snoop_transaction object into this new analysis port at the end of the Snoop transaction.
The analysis port used by port monitor within Master agent is:

• svt_axi_port_monitor :: snoop_item_observed_port

Callbacks:
Callbacks are an access mechanism that enable the insertion of user-defined code and allow access to objects for scoreboarding and functional coverage. Each master and slave component is associated with a callback class that contains a set of callback methods. AXI VIP provides following callbacks classes:

• svt_axi_master_callback (Master callback class)
• svt_axi_slave_callback (Slave callback class)
• svt_axi_port_monitor_callback (Port monitor callback class)
• svt_axi_system_monitor_callback (System monitor callback class)
• svt_axi_interconnect_callback (Interconnect callback class)

Interfaces and modports:
SystemVerilog models signal connections using interfaces and modports. Interfaces define the set of signals which make up a port connection. Modports define collection of signals for a given port, the direction of the signals, and the clock with respect to which these signals are driven and sampled. AXI VIP provides below interfaces:

• svt_axi_if (Top level interface, which contains an array of master & slave port sub-interfaces)
• svt_axi_master_if (sub-interface for master ports)
• svt_axi_slave_if (sub-interface for slave ports)

The port sub-interface provides below modports to connect VIP to the DUT:

• svt_axi_slave_modport (Modport used to connect master VIP component to slave DUT port)
• svt_axi_master_modport (Modport used to connect slave VIP component to master DUT port)
• svt_axi_debug_modport (Modport used to access the debug port signals)

Functional Coverage:
The Synopsys AXI Verification IP provides default transaction coverage. The coverage is shaped based on the configuration. AXI VIP provides below coverage callback classes:

• svt_axi_port_monitor_def_cov_data_callback

The coverage data callback class defines default data and event information that are used to implement the coverage groups. The coverage data callback class is extended from callback class svt_axi_port_monitor_callback . This class itself does not contain any cover groups.

• svt_axi_port_monitor_def_cov_callback

This class is extended from the coverage data callback class. This class includes default cover groups.

Protocol Checks:
For a complete list of protocol checks supported by the AXI VIP, please click on the "Protocol Checks" tab in this class reference documentation. The guidelines to use Protocol Checks tab are defined below:

• "Group" filter: This captures the grouping of the checks based on the interface type. This filter can be used to select a specific interface type.
  For a specific interface select all the groups that have required interface.
  Eg: For ACE5_LiteDVM interface type related checks - Select all groups with ACE5_LiteDVM.
  Eg: The group "AXI3 Onwards" will have all the AXI/ACE interfaces starting from AXI3.
• "Subgroup" filter: This captures the sub-grouping of the checks based on the feature. This filter can be used to select a specific feature category.
  Eg: For Signal level checks - Select subgroups Signal Validity/Signal Stability.
  Eg: For a particular Feature like MTE - Select subgroups as below
  • MTE: Signal Stability -> Have all MTE signal level stability checks.
  • MTE: Signal Validity -> Have all MTE signal level validity checks.
  • MTE -> Feature specific checks.
• Reference: This column field captures the reference of the check with Specification Name,Specification Version, Section ID, Section Name.
  
  • For the features that are available up to AXI-H.c specification, references are from AXI-H.c specification.
  • For the features that are introduced in AXI-J specification, references are from AXI-J specification.
  • For the features that are introduced in AXI-K specification, references are from AXI-K specification.
  • In a future release, these all references will be updated to point to AXI-K specification, as applicable.

AXI sequence collection:
The AXI VIP provides a collection of AXI master & slave sequences. These sequences can be registered with the master & slave sequencers within the master & slave agents respectively, to generate different types of AXI scenarios.

For a complete list of Sequences supported by the AXI VIP, please click on the "Sequences" tab in this class reference documentation.

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13 August 2024, Copyright © 2024 Synopsys, Inc.