VIP Smartsearch

X
  • VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.

  • How to download VIP smartsearch?

    1. Get VIP Smartsearch (Available as a seperate run file).
    2. Set environment variable 
      DESIGNWARE_HOME
      to required designware home location where VIP Smartsearch should be downloaded.
    3. Run 
      vip_smartsearch_<version>.run
      file.
      VIP Smartsearch will be downloaded to the location 
      $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

  • How to install VIP Smartsearch?

    Please refer to the file 
    VIP_Smartsearch_installation_and_usage_guide.pdf
    in 
    $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
    for installation steps.

  • Customer Support

    For more details about VIP smartsearch tool, contact support_center@synopsys.com.
    Mention your queries along with below details and send email to above email id.
    Product: Verification IP
    Sub Product: <vip_title>
    Tool: VIP Smartsearch
13 August 2024, Copyright © 2024 Synopsys, Inc.

DTI SVT UVM Documentation - Interfaces Reference

Interfaces for DTI SVT UVM Documentation: Show All Interfaces

Product Interface Group Interfaces Sub-interfaces
amba_svt Top Level interface for DTI VIP components within AMBA VIP. svt_dti_agent_if
Default Group svt_dti_port_if svt_dti_agent_if, svt_axi_slave_if, svt_axi_master_if
svt_dti_if

Interface Definition Documentation

 interface svt_dti_agent_if
(
input logic common_clk,
input logic common_resetn
)
General description:

DTI VIP provides the SystemVerilog interface which can be used to connect the VIP to the DUT. A top level interface svt_dti_if is defined. The top level interface contains an array of dti_if interfaces. By default, 6 dti interfaces are defined in the top level interface. Currently, the maximum dti tx and dt rx interfaces supported is 6. The number of dti interfaces in top level interface can be controlled using macros SVT_DTI_MAX_NUM_MASTERS_{0..5} and SVT_DTI_MAX_NUM_SLAVES_{0..5} respectively. For example, if you want to use 8 master interfaces and 10 slave interfaces, you can define following macros when compiling the VIP:

  • SVT_DTI_MAX_NUM_MASTERS_8
  • SVT_DTI_MAX_NUM_SLAVES_10
    Please refer to User Guide section Overriding System Constants on how to provide these macro definitions to VIP.

    Sub-interfaces:

    Interface Name Interface Description
    svt_dti_master_if Master Interface used by master VIP component
    svt_dti_slave_if Slave Interface used by slave VIP component

    Clock signal description:

    Signal Name Signal Description
    common_aclk If all DTI interfaces in the system are expected to run on a common clock, user can use the common clock mode. Common clock mode can be selected by setting configuration parameter svt_dti_system_configuration :: common_clock_mode to 1. This is the default mode of operation. When common clock mode is used, connect common_aclk signal to the top level clock signal in the testbench. Pleae note that if you are using the Interconnect VIP component, you are required to always connect common_aclk signal to a clock in the testbench, as Interconnect VIP component internally uses this clock for its operation.
    aclk This signal belongs to the master and slave sub-interfaces. If all DTI interfaces in the system are expected to run on a different clock, user can use the aclk signal in the port interfaces. Set the configuration parameter svt_dti_system_configuration :: common_clock_mode to 0. In this case, connect the aclk signal in each port interface to the appropriate port specific clock in the testbench.

    Clock connection examples:

  • Usage with common clock:
    assign dti_if[0].common_aclk = SystemClock;

  • Usage with port specific clock:
    assign dti_if.dti_master_if[0].tx_if.aclk = master_clk;
    assign dti_if.dti_slave_if[0].rx_if.aclk = slave_clk;

    Interface signal connections:

  • If master VIP is active, then connect DUT slave port signals to master interface:
    assign dti_if.dti_master_if[0].tx_if.tvalid = DUT_slave_intf.rx_if[0].tvalid;
    assign dti_if.dti_master_if[0].rx_if.tvalid = DUT_slave_intf.tx_if[0].tvalid;

  • If master VIP is passive, then connect DUT master port signals to master interface:
    assign dti_if.dti_master_if[0].tx_if.tvalid = DUT_master_intf.tx_if[0].twvalid;
    assign dti_if.dti_master_if[0].rx_if.tvalid = DUT_master_intf.rx_if[0].twvalid;

  • If slave VIP is active, then connect DUT master port signals to slave interface:
    assign dti_if.dti_slave_if[0].tx_if.tready = DUT_master_intf.rx_if[0].tready; assign dti_if.dti_slave_if[0].rx_if.tready = DUT_master_intf.tx_if[0].tready;

  • If slave VIP is passive, then connect DUT slave port signals to slave interface:
    assign dti_if.dti_slave_if[0].tx_if.tready = DUT_slave_intf.tx_if[0].tready; assign dti_if.dti_slave_if[0].rx_if.tready = DUT_slave_intf.rx_if[0].tready; .
    • Ports
    logic
    clk
     
    logic
    resetn
     
    logic
    internal_clk
     
    logic
    internal_resetn
     
    logic
    clock_enable
     
    logic
    common_clk_mode
     
    logic
    common_reset_mode
     

     interface svt_dti_agent_if signal
     input  logic common_clk

     interface svt_dti_agent_if signal
     input  logic common_resetn

     logic  attribute
     svt_dti_agent_if::clk

     logic  attribute
     svt_dti_agent_if::resetn

     logic  attribute
     svt_dti_agent_if::internal_clk

     logic  attribute
     svt_dti_agent_if::internal_resetn

     logic  attribute
     svt_dti_agent_if::clock_enable = 1

     logic  attribute
     svt_dti_agent_if::common_clk_mode = 1

     logic  attribute
     svt_dti_agent_if::common_reset_mode = 1

    13 August 2024, Copyright © 2024 Synopsys, Inc.