How to download VIP smartsearch?
DESIGNWARE_HOMEto required designware home location where VIP Smartsearch should be downloaded.
vip_smartsearch_<version>.runfile.
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
How to install VIP Smartsearch?
Please refer to the fileVIP_Smartsearch_installation_and_usage_guide.pdfin
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>for installation steps.
Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.Macros defined for DTI SVT UVM Documentation:
AMBA User Modifiable Macros
AMBA User Non-Modifiable Macros
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6
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1
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interconnect_env
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16
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256
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1
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1
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1
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1
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2
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2
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4
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4
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3
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5
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4
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3
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2
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2
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2
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4
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8
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16
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4
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(xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT || xact.coherent_xact_type == svt_axi_transaction::WRITEBACK || xact.coherent_xact_type == svt_axi_transaction::READONCE ) ) |
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(xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE || `ifdef SVT_ACE5_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH || xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH || `endif xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE || xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE || xact.coherent_xact_type == svt_axi_transaction::READUNIQUE || xact.coherent_xact_type == svt_axi_transaction::READCLEAN || xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY || xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED || xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID|| xact.coherent_xact_type == svt_axi_transaction::READONCE ) ) |
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((xact.coherent_xact_type == svt_axi_master_transaction::READUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::CLEANUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::CLEANINVALID)|| (xact.coherent_xact_type == svt_axi_master_transaction::WRITEUNIQUE) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::MAKEINVALID)|| (xact.coherent_xact_type == svt_axi_master_transaction::MAKEUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::WRITELINEUNIQUE) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHARED) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHAREDPERSIST) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READONCECLEANINVALID) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READONCEMAKEINVALID) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READCLEAN)|| (xact.coherent_xact_type == svt_axi_master_transaction::READSHARED)|| (xact.coherent_xact_type == svt_axi_master_transaction::READNOTSHAREDDIRTY) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READCLEAN)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READSHARED)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READNOTSHAREDDIRTY) ) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCE) && (snoop.snoop_xact_type != svt_axi_snoop_transaction::MAKEINVALID) ) |
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2
| |
if define SVT_AXI_LOCK_WIDTH=1, also define SVT_AXI_LOCK_WIDTH_AS_ONE due to compilation warnings
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0.01
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0.01
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16
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|
|
10
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|
|
|
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6
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|
|
6
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|
|
8
|
|
|
4
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|
|
|
|
4
|
|
|
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64
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|
|
128
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|
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64
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6
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|
|
6
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|
|
8
|
|
|
4
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|
|
16
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|
|
4
|
|
|
10
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|
|
32
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|
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64
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10
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|
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16
|
|
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|
|
10
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|
|
16
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|
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8
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|
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1024
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250
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8
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|
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16
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|
|
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16
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|
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16
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16
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|
|
8
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|
|
8
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|
|
16
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|
|
1
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|
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32
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20
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9
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|
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4
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1024
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4
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128
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10
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128
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16
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4
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8
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1000
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8192
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64
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64
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256
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1
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2
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(4*CEIL(SVT_AXI_MAX_DATA_WIDTH,128))
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16
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4
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128
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4
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8
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16
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16
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8
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16
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4
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16
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1
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1000
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8192
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8
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16
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0
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0
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3
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0
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0
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0
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3
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0
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1
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0
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0.01
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0.01
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256
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((SVT_AXI_MAX_DATA_WIDTH/8)> 8)?(8):(SVT_AXI_MAX_DATA_WIDTH/8)
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4
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ACE_VERSION_1_0
| |
Default value of port configuration attribute ace_version. User can change this value to ACE_VERSION_2_0 to use ACE5 features, along with defining compile time macro SVT_ACE5_ENABLE.
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AXI3
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3
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4
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10
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10
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10
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4
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4
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3
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0.01
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0.01
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5
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11
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1
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1
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1
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1
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3
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2
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3
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3
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1
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1
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1
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3
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3
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1
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1
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3
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3
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1
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1
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3
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3
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3
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3
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3
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1
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1
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1
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3
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3
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1
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1
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3
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3
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3
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3
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3
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1
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1
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12
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100000
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16
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256
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2
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2
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4
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4
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3
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5
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4
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3
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2
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4
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8
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16
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2
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0.01
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0.01
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4
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|
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4
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10
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4
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16
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128
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4
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|
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8
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|
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8
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|
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0.01
|
|
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0.01
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256
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|
3
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|
|
4
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|
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4
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4
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3
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0.01
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0.01
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0
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|
|
svt_axi_slave_agent
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((dividend / divisor) + ((dividend % divisor) != 0)) |
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|
|
`define var``_``val |
|
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`ifdef SVT_UVM_TECHNOLOGY reporter `elsif SVT_OVM_TECHNOLOGY reporter `else log `endif |
|
|
32
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1
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|
|
2
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|
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0
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|
|
3
|
|
|
2
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|
|
3
|
|
|
2
|
|
|
2
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|
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1
|
|
|
0
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|
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1
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|
|
0
|
|
|
2
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|
|
128
|
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|
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|
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|
|
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
2
|
|
|
15
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|
|
7
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|
|
11
|
|
|
14
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|
|
6
|
|
|
10
|
|
|
0
|
|
|
1
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
11
|
|
|
15
|
|
|
15
|
|
|
11
|
|
|
10
|
|
|
14
|
|
|
14
|
|
|
10
|
|
|
1
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
7
|
|
|
7
|
|
|
15
|
|
|
15
|
|
|
6
|
|
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6
|
|
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14
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|
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14
|
|
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|
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|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) ADDR('h%0x) SECURE('h%0h) RESP('h%0x)} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.port_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.snoop_xact_type.name:"null"), ((xact != null)?xact.snoop_addr:0), ((xact != null)?!xact.snoop_prot[1]:0), ((xact != null)?{xact.get_crresp_value()}:0)) |
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0
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|
|
( ( (sys_cfg.use_recommended_coherent_to_snoop_map == 1) && (SVT_AXI_RECOMMENDED_SNOOP_XACT(xact,snoop)) ) || ( (sys_cfg.use_recommended_coherent_to_snoop_map == 0) && (xact.get_xact_type() == svt_axi_master_transaction::COHERENT) && ( (SVT_AXI_LEGAL_SNOOP_MAPPING(xact,snoop)) ) ) ) |
|
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1
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|
|
4
|
|
|
2
|
|
|
0
|
|
|
1
|
|
|
3
|
|
|
17
|
|
|
8
|
|
|
9
|
|
|
10
|
|
|
11
|
|
|
12
|
|
|
13
|
|
|
14
|
|
|
15
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
5
|
|
|
6
|
|
|
7
|
|
|
16
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
13
|
|
|
|
3'b000
|
|
|
3'b101
|
|
|
3'b100
|
|
|
3'b111
|
|
|
3'b110
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
3
|
|
|
2
|
|
|
2
|
|
|
0
|
|
|
1
|
|
|
(xact_type == COHERENT) && ( (coherent_xact_type == READNOSNOOP) || (coherent_xact_type == READONCE) || (coherent_xact_type == READONCECLEANINVALID) || (coherent_xact_type == READONCEMAKEINVALID) || (coherent_xact_type == READSHARED) || (coherent_xact_type == READCLEAN) || (coherent_xact_type == READNOTSHAREDDIRTY) || (coherent_xact_type == READUNIQUE) || (coherent_xact_type == CLEANUNIQUE) || (coherent_xact_type == MAKEUNIQUE) || (coherent_xact_type == CLEANSHARED) || (coherent_xact_type == CLEANINVALID) || (coherent_xact_type == MAKEINVALID) || (coherent_xact_type == DVMCOMPLETE) || (coherent_xact_type == DVMMESSAGE) || (coherent_xact_type == READBARRIER) || (coherent_xact_type == CLEANSHAREDPERSIST) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER) ) |
|
|
2
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
9
|
|
|
8
|
|
|
30
|
|
|
6
|
|
|
31
|
|
|
11
|
|
|
12
|
|
|
19
|
|
|
10
|
|
|
7
|
|
|
35
|
|
|
13
|
|
|
3
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
2
|
|
|
5
|
|
|
25
|
|
|
26
|
|
|
27
|
|
|
18
|
|
|
20
|
|
|
17
|
|
|
34
|
|
|
21
|
|
|
33
|
|
|
16
|
|
|
14
|
|
|
37
|
|
|
32
|
|
|
15
|
|
|
24
|
|
|
23
|
|
|
36
|
|
|
(xact_type == COHERENT) && ( (coherent_xact_type == WRITENOSNOOP) || (coherent_xact_type == WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (coherent_xact_type == WRITEUNIQUEPTLSTASH) || (coherent_xact_type == WRITEUNIQUEFULLSTASH) || (coherent_xact_type == STASHONCEUNIQUE) || (coherent_xact_type == STASHONCESHARED) || (coherent_xact_type == STASHTRANSLATION) || (coherent_xact_type == CMO) || (coherent_xact_type == WRITEPTLCMO) || (coherent_xact_type == WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (coherent_xact_type == WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (coherent_xact_type == PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (coherent_xact_type == WRITEZERO) || `endif `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (coherent_xact_type == WRITENOSNPFULL) || `endif `endif (coherent_xact_type == WRITELINEUNIQUE) || (coherent_xact_type == WRITEBACK) || (coherent_xact_type == WRITECLEAN) || (coherent_xact_type == WRITEBARRIER) || (coherent_xact_type == WRITEEVICT) || (coherent_xact_type == EVICT) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || `endif (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) || (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT) || (xact.coherent_xact_type == svt_axi_transaction::EVICT) ) |
|
|
0
|
|
|
3'b010
|
|
|
3'b011
|
|
|
3'b000
|
|
|
3'b001
|
|
|
'b11
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
3
|
|
|
14
|
|
|
13
|
|
|
12
|
|
|
11
|
|
|
10
|
|
|
9
|
|
|
8
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
(((cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI3 || cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI4)&& (xact.get_xact_type() != svt_axi_transaction::IDLE)) || ((cfg.get_axi_interface_type() == svt_axi_port_configuration::ACE_LITE || cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI_ACE) && `ifdef SVT_ACE5_ENABLE (xact.get_xact_type() == svt_axi_transaction::ATOMIC) || `endif (xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP || `ifdef SVT_ACE5_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO || xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEZERO || `endif `endif xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP ) ) ) ) |
|
|
'b01
|
|
|
|
|
17
|
|
|
1
|
|
|
11
|
|
|
10
|
|
|
8
|
|
|
9
|
|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::ENDED) `else xact.get_end_realtime() `endif |
|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::STARTED) `else xact.get_begin_realtime() `endif |
|
|
svt_axi_ic_modport
|
|
|
svt_axi_ic_modport
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
5
|
|
|
3
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
4
|
|
|
5
|
|
|
2
|
|
|
3
|
|
|
3'b110
|
|
|
3'b111
|
|
|
3'b100
|
|
|
3'b101
|
|
|
4
|
|
|
5
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
12
|
|
|
(obj.get_xact_type() == svt_axi_transaction::DATA_STREAM) |
|
|
((obj.xact_type == svt_axi_transaction::READ) || ((obj.xact_type == svt_axi_transaction::COHERENT) && ((obj.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (obj.coherent_xact_type == svt_axi_transaction::READONCE) || (obj.coherent_xact_type == svt_axi_transaction::READSHARED) || (obj.coherent_xact_type == svt_axi_transaction::READCLEAN) || (obj.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (obj.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (obj.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (obj.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (obj.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (obj.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (obj.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (obj.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (obj.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (obj.coherent_xact_type == svt_axi_transaction::READBARRIER ) ) ) ) |
|
|
((obj.xact_type == svt_axi_transaction::WRITE) || ((obj.xact_type == svt_axi_transaction::COHERENT) && ((obj.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (obj.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (obj.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || `endif (obj.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (obj.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (obj.coherent_xact_type == svt_axi_transaction::WRITEEVICT) || (obj.coherent_xact_type == svt_axi_transaction::EVICT) || (obj.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) ) ) `ifdef SVT_ACE5_ENABLE || ((obj.xact_type == svt_axi_transaction::ATOMIC) && ((obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_ADD) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_CLR) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_EOR) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SET) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SMAX) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SMIN) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_UMAX) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_UMIN) ) ) `endif ) |
|
|
1
|
|
|
2
|
|
|
2
|
|
|
3
|
|
|
3
|
|
|
1'b0
|
|
|
0
|
|
|
svt_axi_master_if
|
|
|
0
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
0
|
|
|
6
|
|
|
1
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
4
|
|
|
3
|
|
|
5
|
|
|
svt_axi_master_transaction_scenario
|
|
|
svt_axi_master_transaction
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
|
|
0
|
|
|
1
|
|
|
16
|
|
|
16
|
|
|
1
|
|
|
5
|
|
|
$sformatf("{OBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) COHERENT_XACT_TYPE(%0s) ID('h%0x) SECURE('d%0d) ADDR('h%0x) } ", ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.coherent_xact_type.name:"null"), ((xact != null)?xact.id:0), ((xact != null)?!xact.prot_type[1]:0), ((xact != null)?xact.addr:0)) |
|
|
1'b1
|
|
|
0
|
|
|
2
|
|
|
0
|
|
|
7
|
|
|
6
|
|
|
5
|
|
|
4
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
64
|
|
|
'b00
|
|
|
1
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) %0s PORT_NAME(%0s) TYPE(%0s)%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s}", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf("AUTO_GENERATED_XACT('b%0b)",xact.is_auto_generated)):""):""), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null && xact.xact_type == svt_axi_transaction::WRITE)?($sformatf(" WLAST('b%0b)",xact.is_last_write_data_beat)):""), ((xact != null) && (xact.xact_type == svt_axi_transaction::READ)?($sformatf(" RLAST('b%0b)",xact.is_last_read_data_beat)):""), ((xact != null && xact.get_transmitted_channel() == svt_axi_transaction::WRITE)?($sformatf(" DATA_BEFORE_ADDR('b%0b)",xact.data_before_addr)):""), ((xact != null)?((xact.xact_type == svt_axi_transaction::COHERENT)?{$sformatf(" COHERENT_XACT_TYPE(%0s)",xact.coherent_xact_type.name)}:""):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TID('h%0x)",xact.tid)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TDEST('h%0x)",xact.tdest)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" ID('h%0x)",xact.id)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" PROT_TYPE(%0s)",xact.prot_type.name)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" ADDR('h%0x)",xact.addr)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" BURST(%0s)",xact.burst_type.name)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" SIZE(%0s)",xact.burst_size.name)):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" LENGTH('d%0d)",xact.burst_length)):($sformatf(" LENGTH('d%0d)",xact.stream_burst_length))):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" CACHE_TYPE('d%0d)",xact.cache_type)):"")) |
|
|
3
|
|
|
4
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
'b100
|
|
|
|
|
$sformatf("%0s('d%0d) : {TYPE(%0s) ID('h%0x) ADDR('h%0x)}", SVT_DATA_UTIL_ARG_TO_STRING(function_name), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.id:0), ((xact != null)?xact.addr:0)) |
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) %0s PORT_NAME(%0s) TYPE(%0s)%0s%0s LENGTH('h%0h)%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf("AUTO_GENERATED_XACT('b%0b)",xact.is_auto_generated)):""):""), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" BURST(%0s)",xact.burst_type.name)):""):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" SIZE(%0s)",xact.burst_size.name)):""):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?xact.burst_length:xact.stream_burst_length):0), ((xact != null && xact.xact_type == svt_axi_transaction::WRITE)?($sformatf(" WLAST('b%0b)",xact.is_last_write_data_beat)):""), ((xact != null) && (xact.xact_type == svt_axi_transaction::READ)?($sformatf(" RLAST('b%0b)",xact.is_last_read_data_beat)):""), ((xact != null && xact.get_transmitted_channel() == svt_axi_transaction::WRITE)?($sformatf(" DATA_BEFORE_ADDR('b%0b)",xact.data_before_addr)):""), ((xact != null)?((xact.xact_type == svt_axi_transaction::COHERENT)?{$sformatf(" COHERENT_XACT_TYPE(%0s)",xact.coherent_xact_type.name)}:""):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" ID('h%0x)",xact.id)):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" SECURE('h%0h)",!xact.prot_type[1])):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" ADDR('h%0x)",xact.addr)):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" CACHE_TYPE('h%0h)",xact.cache_type)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TID('h%0x)",xact.tid)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TDEST('h%0x)",xact.tdest)):""), ((xact != null)?(xact.atomic_type==svt_axi_transaction::EXCLUSIVE)?" EXCL":"":""), ((xact != null)?((xact.get_begin_time()==-1)?"":($sformatf(" START_TIME(%0t)",xact.get_begin_realtime()))):""), ((xact != null)?((xact.get_end_time()==-1)?"":($sformatf(" END_TIME(%0t)",xact.get_end_realtime()))):"")) |
|
|
0
|
|
|
1
|
|
|
2
|
|
|
0
|
|
|
0
|
|
|
1
|
|
|
3
|
|
|
5
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
( (xact.get_xact_type() == svt_axi_master_transaction::COHERENT) && ( ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::WRITEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHARED) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHAREDPERSIST) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCECLEANINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCEMAKEINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::MAKEINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READCLEAN) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READCLEAN) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READNOTSHAREDDIRTY) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READNOTSHAREDDIRTY) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READSHARED) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::MAKEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::WRITELINEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) ) ) |
|
|
2
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
2
|
|
|
`define var``_``val |
|
|
0
|
|
|
3
|
|
|
1
|
|
|
svt_axi_slave_if
|
|
|
1
|
|
|
0
|
|
|
6
|
|
|
0
|
|
|
5
|
|
|
3
|
|
|
2
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
svt_axi_slave_transaction_scenario_gen_callbacks
|
|
|
svt_axi_slave_transaction_scenario_gen
|
|
|
svt_axi_slave_transaction_scenario
|
|
|
svt_axi_slave_transaction
|
|
|
4
|
|
|
'b10
|
|
|
16
|
|
|
1
|
|
|
2
|
|
|
4
|
|
|
8
|
|
|
0
|
|
|
1
|
|
|
5
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
9
|
|
|
8
|
|
|
14
|
|
|
15
|
|
|
13
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
7
|
|
|
|
|
128
|
|
|
16
|
|
|
512
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) BURST_LENGTH('d%0d) TID('h%0x) TDEST('h%0x)%0s%0s} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), (((xact != null) && (xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.stream_burst_length:0), ((xact != null)?xact.tid:0), ((xact != null)?xact.tdest:0), ((xact != null)?((xact.get_begin_time()==-1)?"":($sformatf(" START_TIME(%0t)",xact.get_begin_realtime()))):""), ((xact != null)?((xact.get_end_time()==-1)?"":($sformatf(" END_TIME(%0t)",xact.get_end_realtime()))):"")) |
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
3
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
7
|
|
|
4
|
|
|
1
|
|
|
8
|
|
|
5
|
|
|
2
|
|
|
9
|
|
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6
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3
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0
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2
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4
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7
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6
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1
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0
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2
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0
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0
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4
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3
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2
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1
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5
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3
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2
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0
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6
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1
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'b101
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3
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4
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2
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0
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5
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1
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'b111
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1
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1
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7
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1
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|
`define SVT_AXI_VALID_MASTER_IDX_0 |
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`define SVT_AXI_VALID_SLAVE_IDX_0 |
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10
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12
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14
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15
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2,4,8,16
|
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0
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1
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2
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0
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0
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1
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16
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0
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3
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2
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5
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17
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4
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7
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6
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9
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18
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11
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10
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13
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19
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12
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15
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14
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8
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2
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0
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1
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1
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( ( ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) || (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE) ) && (this_xact.is_coherent_xact_dropped == 1) ) || ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) && ( (this_xact.ack_status == svt_axi_transaction::ACCEPT) || (this_xact.ack_status == svt_axi_transaction::ABORTED) ) ) || ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (SVT_AXI_IS_TRANSMITTED_CHANNEL_WRITE(this_xact)) && ( ( (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) || (this_xact.write_resp_status == svt_axi_transaction::ABORTED) ) ) ) || `ifdef SVT_ACE5_ENABLE ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (`SVT_AXI_IS_TRANSMITTED_CHANNEL_READ_WRITE(this_xact)) && ( ( (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) || (this_xact.write_resp_status == svt_axi_transaction::ABORTED) || (this_xact.atomic_read_data_status == svt_axi_transaction::ACCEPT) || (this_xact.atomic_read_data_status == svt_axi_transaction::ABORTED) ) ) ) || `endif ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (SVT_AXI_IS_TRANSMITTED_CHANNEL_READ(this_xact)) && ( ( (this_xact.data_status == svt_axi_transaction::ACCEPT) || (this_xact.data_status == svt_axi_transaction::ABORTED) ) ) ) ) |
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1
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2
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1
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3
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((1<<SVT_AXI_MAX_BURST_LENGTH_WIDTH)-1)
|
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|
17
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17
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|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::ENDED) `else xact.get_end_realtime() `endif |
|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::STARTED) `else xact.get_begin_realtime() `endif |
|
|
1
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|
16
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|
16
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|
|
1
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$sformatf("{%0s KIND(%0s) %0s CHAN(%0s) %0s %0s %0s %0s %0s %0s %0s %0s %0s %0s MSG(%0s) STS(%0s)}", ((xact != null)? ($sformatf("OBJECT_NUM('d%0d)",xact.object_id)):"OBJECT_NUM(-1)"), ((xact != null)?xact.port_cfg.dti_port_kind.name():""), ((xact != null)? ($sformatf("PORT_ID('d%0d)",xact.port_cfg.port_id)):""), ((xact != null)?xact.channel_type.name():""), ((xact != null)? ($sformatf("ID('h%0h)",xact.id)):""), ((xact != null && xact.message_type==0)?($sformatf("PROTOCOL_VERSION('h%0h)",xact.protocol_version)):""), ((xact != null)? ($sformatf("DTI_VERSION(%0s)",xact.port_cfg.dti_version)):""), ((xact != null && (xact.message_type==3 ||xact.message_type==16))? ($sformatf("BYPASS('h%0h)",xact.bypass)):""), ((xact != null && (xact.message_type==1 ||xact.message_type==14))? ($sformatf("OAS('h%0h)",xact.output_address_size)):""), ((xact != null && (xact.message_type==2))? ($sformatf("SEC_SID('h%0h)",xact.secure_stream_id)):""), ((xact != null && (xact.message_type==2 && xact.port_cfg.dti_version==2))? ($sformatf("MMUV('h%0h)",xact.mmuv)):""), ((xact != null && (xact.message_type==2 && xact.port_cfg.dti_version==1))? ($sformatf("FLOW('%0s)",xact.flow)):""), ((xact != null && (xact.message_type.name()=="DTI_TBU_REG_RDATA"))? ($sformatf("DATA(%0s)",xact.get_data_string())):""), ((xact != null && (xact.message_type.name()=="DTI_TBU_REG_READ"))? ($sformatf("DATA(%0s)",xact.get_data_string())):""), ((xact != null)?xact.message_type.name():""), ((xact != null)?xact.xact_status.name():"")) |
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`define var``_``val |
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( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h00|| xact.operation == 9'h10|| xact.operation ==9'h18|| xact.operation == 9'h20|| xact.operation == 9'h30|| xact.operation ==9'h38 )) || ((xact.port_cfg.dti_version != svt_dti_port_configuration::DTI3_0 && xact.port_cfg.dti_version != svt_dti_port_configuration::DTI4_0) && ( xact.operation == 8'h00|| xact.operation == 8'h10|| xact.operation ==8'h18|| xact.operation == 8'h20|| xact.operation == 8'h30|| xact.operation ==8'h38 )) ) ) |
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( xact.operation == 9'h100|| xact.operation == 9'h110|| xact.operation ==9'h118 ) |
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( xact.operation == 9'h104|| xact.operation == 9'h105 ) |
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( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'h40|| xact.operation == 8'h41 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'h40|| xact.operation == 8'h41|| xact.operation == 8'h82|| xact.operation == 8'h85|| xact.operation == 8'h90|| xact.operation == 8'h95|| xact.operation == 8'hC0|| xact.operation == 8'hC9|| xact.operation == 8'hC1|| xact.operation == 8'hC8 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h80|| xact.operation == 9'h81|| xact.operation == 9'h88|| xact.operation == 9'h89|| xact.operation == 9'hA0|| xact.operation == 9'hB2|| xact.operation == 9'hB0|| xact.operation == 9'hB1|| xact.operation == 9'hB8|| xact.operation == 9'hB9|| xact.operation == 9'hB5|| xact.operation == 9'hE0|| xact.operation == 9'hE1|| xact.operation == 9'hE8|| xact.operation == 9'hE9|| xact.operation == 9'h40|| xact.operation == 9'h41|| xact.operation == 9'h82|| xact.operation == 9'h85|| xact.operation == 9'h90|| xact.operation == 9'h95|| xact.operation == 9'hC0|| xact.operation == 9'hC9|| xact.operation == 9'hC1|| xact.operation == 9'hC8 ) ) ) ) |
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( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h47|| xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) ) |
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$sformatf("{OBJECT_NUM('d%0d) PORT_ID('d%0d) TYPE(%0s) TID('h%0x) TDATA('h%0x) TDEST('h%0x) } ", ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.tid:0), ((xact != null)?xact.tdata[0]:0), ((xact != null)?xact.tdest:0)) |
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( xact.operation == 8'h31 || xact.operation==8'h33 ||xact.operation==8'h39 ) |
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( xact.operation == 8'h31 || xact.operation==8'h33 || xact.operation==8'h39 ) |
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( xact.operation==8'h39 ) |
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( xact.operation == 8'h31 || xact.operation==8'h33 || xact.operation==8'h39 ) |
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`define SVT_DTI_VALID_MASTER_IDX_0 |
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`define SVT_DTI_VALID_SLAVE_IDX_0 |
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( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation==8'h88||xact.operation==8'h89|| xact.operation==8'hB8||xact.operation==8'hB9|| xact.operation==8'hE8||xact.operation==8'hE9 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0) && ( xact.operation==8'h88||xact.operation==8'h89|| xact.operation==8'hB8||xact.operation==8'hB9|| xact.operation==8'hE8||xact.operation==8'hE9|| xact.operation==8'h88||xact.operation==8'h89|| xact.operation==8'hC8||xact.operation==8'hC9 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation==9'h88||xact.operation==9'h89|| xact.operation==9'hB8||xact.operation==9'hB9|| xact.operation==9'hE8||xact.operation==9'hE9|| xact.operation==9'h88||xact.operation==9'h89|| xact.operation==9'hC8||xact.operation==9'hC9|| xact.operation==9'h198||xact.operation==9'h199|| xact.operation==9'h1C8||xact.operation==9'h1C9 ) ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h100 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h104 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h105 ) ) ) |
|
|
( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'h41 ) ) || (( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0)&& ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40|| xact.operation == 8'h82|| xact.operation == 8'h85|| xact.operation == 8'h90|| xact.operation == 8'h95|| xact.operation == 8'hC0|| xact.operation == 8'hC1|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'hB9|| xact.operation == 8'hE8|| xact.operation == 8'h41|| xact.operation == 8'hC8|| xact.operation == 8'hC9 ) ) || (( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0)&& ( xact.operation == 9'h80|| xact.operation == 9'h81|| xact.operation == 9'hA0|| xact.operation == 9'hB2|| xact.operation == 9'hB0|| xact.operation == 9'hB1|| xact.operation == 9'hB5|| xact.operation == 9'hE0|| xact.operation == 9'hE1|| xact.operation == 9'h40|| xact.operation == 9'h82|| xact.operation == 9'h85|| xact.operation == 9'h90|| xact.operation == 9'h95|| xact.operation == 9'hC0|| xact.operation == 9'hC1|| xact.operation == 9'h88|| xact.operation == 9'h89|| xact.operation == 9'hB8|| xact.operation == 9'hB9|| xact.operation == 9'hE8|| xact.operation == 9'hE9|| xact.operation == 9'hB9|| xact.operation == 9'hE8|| xact.operation == 9'h41|| xact.operation == 9'hC8|| xact.operation == 9'hC9|| xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) ) |
|
|
( ( (xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h80 || xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40 ) ) || ( (xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40|| xact.operation == 8'h82|| xact.operation == 8'h85|| xact.operation == 8'h90|| xact.operation == 8'h95|| xact.operation == 8'hC0|| xact.operation == 8'hC1 ) ) || ( ( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 ||xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h80|| xact.operation == 9'h81|| xact.operation == 9'hA0|| xact.operation == 9'hB2|| xact.operation == 9'hB0|| xact.operation == 9'hB1|| xact.operation == 9'hB5|| xact.operation == 9'hE0|| xact.operation == 9'hE1|| xact.operation == 9'h40|| xact.operation == 9'h82|| xact.operation == 9'h85|| xact.operation == 9'h90|| xact.operation == 9'h95|| xact.operation == 9'hC0|| xact.operation == 9'hC1|| xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && (xact.operation ==8'hB2 ||xact.operation==8'hB0 ||xact.operation==8'hB1||xact.operation==8'hB8 ||xact.operation==8'hB9||xact.operation==8'hB5 ||xact.operation==8'h10||xact.operation==8'h30 )) || ( ( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0) && (xact.operation == 8'hB2||xact.operation==8'hB0 ||xact.operation==8'hB1||xact.operation==8'hB8 ||xact.operation==8'hB9||xact.operation==8'hB5 ||xact.operation==8'h10||xact.operation==8'h30 ||xact.operation==8'h81||xact.operation==8'h82 ||xact.operation==8'h85||xact.operation==8'h88 ||xact.operation==8'h89||xact.operation==8'h90 ||xact.operation==8'h95 )) || ( ( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && (xact.operation == 9'hB2||xact.operation==9'hB0 ||xact.operation==9'hB1||xact.operation==9'hB8 ||xact.operation==9'hB9||xact.operation==9'hB5 ||xact.operation==9'h10||xact.operation==9'h30 ||xact.operation==9'h81||xact.operation==9'h82 ||xact.operation==9'h85||xact.operation==9'h88 ||xact.operation==9'h89||xact.operation==9'h90 ||xact.operation==9'h95 ||xact.operation==9'h190||xact.operation==9'h191 ||xact.operation==9'h192||xact.operation==9'h195 ||xact.operation==9'h198||xact.operation==9'h199 ||xact.operation==9'h110 )) ) |
|
|
( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation ==8'h81 || xact.operation==8'h85 || xact.operation ==8'h89 || xact.operation==8'h95 || xact.operation ==8'hB1 || xact.operation==8'hB9 || xact.operation ==8'hB5 || xact.operation==8'hC9 || xact.operation ==8'hC1 || xact.operation==8'hE1 || xact.operation ==8'hE9 || xact.operation==8'h41 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0 ) && ( xact.operation ==9'h81 || xact.operation==9'h85 || xact.operation ==9'h89 || xact.operation==9'h95 || xact.operation ==9'hB1 || xact.operation==9'hB9 || xact.operation ==9'hB5 || xact.operation==9'hC9 || xact.operation ==9'hC1 || xact.operation==9'hE1 || xact.operation ==9'hE9 || xact.operation==9'h41 || xact.operation ==9'h191 || xact.operation==9'h195 || xact.operation ==9'h199 || xact.operation==9'h1C1 || xact.operation==9'h1C9 ) ) ) ) |
|
|
( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h38 || xact.operation==9'h30 || xact.operation == 9'h18 || xact.operation==9'h10 )) || ((xact.port_cfg.dti_version != svt_dti_port_configuration::DTI3_0 && xact.port_cfg.dti_version != svt_dti_port_configuration::DTI4_0) && ( xact.operation == 8'h38 || xact.operation==8'h30 || xact.operation == 8'h18 || xact.operation==8'h10 )) ) ) |
|
|
( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h18|| xact.operation==9'h38 )) || ((xact.port_cfg.dti_version != svt_dti_port_configuration::DTI3_0 && xact.port_cfg.dti_version != svt_dti_port_configuration::DTI4_0) && ( xact.operation ==8'h18|| xact.operation==8'h38 )) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h198 || xact.operation==9'h199 || xact.operation ==9'h1C8 || xact.operation==9'h1C9 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h118 || xact.operation ==9'h110 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation==9'h118 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h47 || xact.operation ==9'h191 || xact.operation ==9'h195 || xact.operation ==9'h199 || xact.operation ==9'h1C1 || xact.operation ==9'h1C9 || xact.operation ==9'h100 || xact.operation ==9'h105 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h190 || xact.operation==9'h191 || xact.operation ==9'h192 || xact.operation==9'h195 || xact.operation ==9'h198 || xact.operation==9'h199 ) ) ) |
|
|
( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h81|| xact.operation == 8'h89|| xact.operation == 8'hB1|| xact.operation == 8'hB9|| xact.operation == 8'hE1|| xact.operation == 8'hE9|| xact.operation == 8'h41|| xact.operation == 8'hB5 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation == 8'h81|| xact.operation == 8'h89|| xact.operation == 8'hB1|| xact.operation == 8'hB9|| xact.operation == 8'hE1|| xact.operation == 8'hE9|| xact.operation == 8'h41|| xact.operation == 8'hB5|| xact.operation == 8'h85|| xact.operation == 8'h95|| xact.operation == 8'hC9|| xact.operation == 8'hC1 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0 ) && ( xact.operation == 9'h81|| xact.operation == 9'h89|| xact.operation == 9'hB1|| xact.operation == 9'hB9|| xact.operation == 9'hE1|| xact.operation == 9'hE9|| xact.operation == 9'h41|| xact.operation == 9'hB5|| xact.operation == 9'h85|| xact.operation == 9'h95|| xact.operation == 9'hC9|| xact.operation == 9'hC1|| xact.operation == 9'h47|| xact.operation == 9'h191||xact.operation == 9'h199|| xact.operation == 9'h1C1|| xact.operation == 9'h1C9|| xact.operation == 9'h195 ) ) ) ) |
|
|
( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation ==8'hB2 || xact.operation==8'hB0 || xact.operation ==8'hB1 || xact.operation==8'hB8 || xact.operation ==8'hB9 || xact.operation==8'hB5 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation ==8'hB2 || xact.operation==8'hB0 || xact.operation ==8'hB1 || xact.operation==8'hB8 || xact.operation ==8'hB9 || xact.operation==8'hB5 || xact.operation ==8'h81 || xact.operation==8'h82 || xact.operation ==8'h85 || xact.operation==8'h88 || xact.operation ==8'h89 || xact.operation==8'h90 || xact.operation ==8'h95 ) ) || (( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'hB2 || xact.operation==9'hB0 || xact.operation ==9'hB1 || xact.operation==9'hB8 || xact.operation ==9'hB9 || xact.operation==9'hB5 || xact.operation ==9'h81 || xact.operation==9'h82 || xact.operation ==9'h85 || xact.operation==9'h88 || xact.operation ==9'h89 || xact.operation==9'h90 || xact.operation ==9'h95|| xact.operation ==9'h190 || xact.operation==9'h191 || xact.operation ==9'h192 || xact.operation==9'h195 || xact.operation ==9'h198 || xact.operation==9'h199 ) ) ) ) |
|
|
2,4,8,16
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
`ifdef SVT_UVM_TECHNOLOGY uvm_object_utils(obj) `elsif SVT_OVM_TECHNOLOGY `ovm_object_utils(obj) `endif |
AMBA User Modifiable Macros
AMBA User Non-Modifiable Macros
|
|
|
|
|
|
|
|
|
|
|
|
6
|
|
|
1
|
|
|
interconnect_env
|
|
|
16
|
|
|
256
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
|
|
2
|
|
|
2
|
|
|
4
|
|
|
|
|
4
|
|
|
|
|
|
|
3
|
|
|
5
|
|
|
4
|
|
|
3
|
|
|
2
|
|
|
|
|
|
|
2
|
|
|
2
|
|
|
4
|
|
|
8
|
|
|
16
|
|
|
4
|
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT || xact.coherent_xact_type == svt_axi_transaction::WRITEBACK || xact.coherent_xact_type == svt_axi_transaction::READONCE ) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE || `ifdef SVT_ACE5_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH || xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH || `endif xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE || xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE || xact.coherent_xact_type == svt_axi_transaction::READUNIQUE || xact.coherent_xact_type == svt_axi_transaction::READCLEAN || xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY || xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED || xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID|| xact.coherent_xact_type == svt_axi_transaction::READONCE ) ) |
|
|
((xact.coherent_xact_type == svt_axi_master_transaction::READUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::CLEANUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::CLEANINVALID)|| (xact.coherent_xact_type == svt_axi_master_transaction::WRITEUNIQUE) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::MAKEINVALID)|| (xact.coherent_xact_type == svt_axi_master_transaction::MAKEUNIQUE)|| (xact.coherent_xact_type == svt_axi_master_transaction::WRITELINEUNIQUE) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHARED) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHAREDPERSIST) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READONCECLEANINVALID) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READONCEMAKEINVALID) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) ) || ( ((xact.coherent_xact_type == svt_axi_master_transaction::READCLEAN)|| (xact.coherent_xact_type == svt_axi_master_transaction::READSHARED)|| (xact.coherent_xact_type == svt_axi_master_transaction::READNOTSHAREDDIRTY) ) && ((snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READCLEAN)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READSHARED)|| (snoop.snoop_xact_type == svt_axi_snoop_transaction::READNOTSHAREDDIRTY) ) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCE) && (snoop.snoop_xact_type != svt_axi_snoop_transaction::MAKEINVALID) ) |
|
|
2
| |
if define SVT_AXI_LOCK_WIDTH=1, also define SVT_AXI_LOCK_WIDTH_AS_ONE due to compilation warnings
|
|
|
0.01
|
|
|
0.01
|
|
|
16
|
|
|
10
|
|
|
|
|
6
|
|
|
6
|
|
|
8
|
|
|
4
|
|
|
|
|
4
|
|
|
|
|
64
|
|
|
128
|
|
|
64
|
|
|
6
|
|
|
6
|
|
|
8
|
|
|
4
|
|
|
16
|
|
|
4
|
|
|
10
|
|
|
32
|
|
|
64
|
|
|
10
|
|
|
16
|
|
|
|
|
10
|
|
|
16
|
|
|
8
|
|
|
1024
|
|
|
250
|
|
|
8
|
|
|
|
|
16
|
|
|
|
|
16
|
|
|
|
|
16
|
|
|
|
|
16
|
|
|
8
|
|
|
8
|
|
|
16
|
|
|
1
|
|
|
32
|
|
|
20
|
|
|
9
|
|
|
4
|
|
|
1024
|
|
|
4
|
|
|
128
|
|
|
10
|
|
|
128
|
|
|
|
|
|
|
|
|
|
|
16
|
|
|
4
|
|
|
8
|
|
|
1000
|
|
|
8192
|
|
|
|
|
|
|
64
|
|
|
64
|
|
|
256
|
|
|
1
|
|
|
2
|
|
|
(4*CEIL(SVT_AXI_MAX_DATA_WIDTH,128))
|
|
|
16
|
|
|
|
|
|
|
4
|
|
|
128
|
|
|
4
|
|
|
8
|
|
|
16
|
|
|
16
|
|
|
8
|
|
|
16
|
|
|
4
|
|
|
16
|
|
|
1
|
|
|
|
|
1000
|
|
|
8192
|
|
|
|
|
8
|
|
|
|
|
16
|
|
|
0
|
|
|
0
|
|
|
3
|
|
|
0
|
|
|
0
|
|
|
0
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
0
|
|
|
0.01
|
|
|
0.01
|
|
|
256
|
|
|
((SVT_AXI_MAX_DATA_WIDTH/8)> 8)?(8):(SVT_AXI_MAX_DATA_WIDTH/8)
|
|
|
4
|
|
|
ACE_VERSION_1_0
| |
Default value of port configuration attribute ace_version. User can change this value to ACE_VERSION_2_0 to use ACE5 features, along with defining compile time macro SVT_ACE5_ENABLE.
|
|
|
AXI3
|
|
|
3
|
|
|
4
|
|
|
10
|
|
|
10
|
|
|
10
|
|
|
4
|
|
|
4
|
|
|
3
|
|
|
0.01
|
|
|
0.01
|
|
|
5
|
|
|
11
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
2
|
|
|
|
|
3
|
|
|
3
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
3
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
3
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
3
|
|
|
3
|
|
|
3
|
|
|
3
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
3
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
3
|
|
|
3
|
|
|
3
|
|
|
3
|
|
|
1
|
|
|
1
|
|
|
|
|
12
|
|
|
|
|
100000
|
|
|
|
|
16
|
|
|
256
|
|
|
2
|
|
|
2
|
|
|
4
|
|
|
|
|
4
|
|
|
|
|
|
|
3
|
|
|
5
|
|
|
4
|
|
|
3
|
|
|
2
|
|
|
4
|
|
|
8
|
|
|
16
|
|
|
2
|
|
|
0.01
|
|
|
0.01
|
|
|
4
|
|
|
4
|
|
|
10
|
|
|
4
|
|
|
16
|
|
|
|
|
128
|
|
|
4
|
|
|
8
|
|
|
8
|
|
|
0.01
|
|
|
0.01
|
|
|
256
|
|
|
3
|
|
|
4
|
|
|
4
|
|
|
4
|
|
|
3
|
|
|
0.01
|
|
|
0.01
|
|
|
|
|
|
|
0
|
|
|
|
|
svt_axi_slave_agent
|
|
|
((dividend / divisor) + ((dividend % divisor) != 0)) |
|
|
|
|
`define var``_``val |
|
|
`ifdef SVT_UVM_TECHNOLOGY reporter `elsif SVT_OVM_TECHNOLOGY reporter `else log `endif |
|
|
32
|
|
|
1
|
|
|
2
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
3
|
|
|
2
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
128
|
|
|
|
|
|
|
|
|
|
|
1
|
|
|
1
|
|
|
3
|
|
|
2
|
|
|
15
|
|
|
7
|
|
|
11
|
|
|
14
|
|
|
6
|
|
|
10
|
|
|
0
|
|
|
1
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
11
|
|
|
15
|
|
|
15
|
|
|
11
|
|
|
10
|
|
|
14
|
|
|
14
|
|
|
10
|
|
|
1
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
7
|
|
|
7
|
|
|
15
|
|
|
15
|
|
|
6
|
|
|
6
|
|
|
14
|
|
|
14
|
|
|
|
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) ADDR('h%0x) SECURE('h%0h) RESP('h%0x)} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.port_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.snoop_xact_type.name:"null"), ((xact != null)?xact.snoop_addr:0), ((xact != null)?!xact.snoop_prot[1]:0), ((xact != null)?{xact.get_crresp_value()}:0)) |
|
|
0
|
|
|
( ( (sys_cfg.use_recommended_coherent_to_snoop_map == 1) && (SVT_AXI_RECOMMENDED_SNOOP_XACT(xact,snoop)) ) || ( (sys_cfg.use_recommended_coherent_to_snoop_map == 0) && (xact.get_xact_type() == svt_axi_master_transaction::COHERENT) && ( (SVT_AXI_LEGAL_SNOOP_MAPPING(xact,snoop)) ) ) ) |
|
|
1
|
|
|
4
|
|
|
2
|
|
|
0
|
|
|
1
|
|
|
3
|
|
|
17
|
|
|
8
|
|
|
9
|
|
|
10
|
|
|
11
|
|
|
12
|
|
|
13
|
|
|
14
|
|
|
15
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
5
|
|
|
6
|
|
|
7
|
|
|
16
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
13
|
|
|
|
3'b000
|
|
|
3'b101
|
|
|
3'b100
|
|
|
3'b111
|
|
|
3'b110
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
3
|
|
|
2
|
|
|
2
|
|
|
0
|
|
|
1
|
|
|
(xact_type == COHERENT) && ( (coherent_xact_type == READNOSNOOP) || (coherent_xact_type == READONCE) || (coherent_xact_type == READONCECLEANINVALID) || (coherent_xact_type == READONCEMAKEINVALID) || (coherent_xact_type == READSHARED) || (coherent_xact_type == READCLEAN) || (coherent_xact_type == READNOTSHAREDDIRTY) || (coherent_xact_type == READUNIQUE) || (coherent_xact_type == CLEANUNIQUE) || (coherent_xact_type == MAKEUNIQUE) || (coherent_xact_type == CLEANSHARED) || (coherent_xact_type == CLEANINVALID) || (coherent_xact_type == MAKEINVALID) || (coherent_xact_type == DVMCOMPLETE) || (coherent_xact_type == DVMMESSAGE) || (coherent_xact_type == READBARRIER) || (coherent_xact_type == CLEANSHAREDPERSIST) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER) ) |
|
|
2
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
9
|
|
|
8
|
|
|
30
|
|
|
6
|
|
|
31
|
|
|
11
|
|
|
12
|
|
|
19
|
|
|
10
|
|
|
7
|
|
|
35
|
|
|
13
|
|
|
3
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
2
|
|
|
5
|
|
|
25
|
|
|
26
|
|
|
27
|
|
|
18
|
|
|
20
|
|
|
17
|
|
|
34
|
|
|
21
|
|
|
33
|
|
|
16
|
|
|
14
|
|
|
37
|
|
|
32
|
|
|
15
|
|
|
24
|
|
|
23
|
|
|
36
|
|
|
(xact_type == COHERENT) && ( (coherent_xact_type == WRITENOSNOOP) || (coherent_xact_type == WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (coherent_xact_type == WRITEUNIQUEPTLSTASH) || (coherent_xact_type == WRITEUNIQUEFULLSTASH) || (coherent_xact_type == STASHONCEUNIQUE) || (coherent_xact_type == STASHONCESHARED) || (coherent_xact_type == STASHTRANSLATION) || (coherent_xact_type == CMO) || (coherent_xact_type == WRITEPTLCMO) || (coherent_xact_type == WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (coherent_xact_type == WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (coherent_xact_type == PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (coherent_xact_type == WRITEZERO) || `endif `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (coherent_xact_type == WRITENOSNPFULL) || `endif `endif (coherent_xact_type == WRITELINEUNIQUE) || (coherent_xact_type == WRITEBACK) || (coherent_xact_type == WRITECLEAN) || (coherent_xact_type == WRITEBARRIER) || (coherent_xact_type == WRITEEVICT) || (coherent_xact_type == EVICT) ) |
|
|
(xact.get_xact_type() == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || `endif (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) || (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT) || (xact.coherent_xact_type == svt_axi_transaction::EVICT) ) |
|
|
0
|
|
|
3'b010
|
|
|
3'b011
|
|
|
3'b000
|
|
|
3'b001
|
|
|
'b11
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
3
|
|
|
14
|
|
|
13
|
|
|
12
|
|
|
11
|
|
|
10
|
|
|
9
|
|
|
8
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
(((cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI3 || cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI4)&& (xact.get_xact_type() != svt_axi_transaction::IDLE)) || ((cfg.get_axi_interface_type() == svt_axi_port_configuration::ACE_LITE || cfg.get_axi_interface_type() == svt_axi_port_configuration::AXI_ACE) && `ifdef SVT_ACE5_ENABLE (xact.get_xact_type() == svt_axi_transaction::ATOMIC) || `endif (xact.get_xact_type() == svt_axi_transaction::COHERENT && (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP || `ifdef SVT_ACE5_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO || xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE xact.coherent_xact_type == svt_axi_transaction::WRITEZERO || `endif `endif xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP ) ) ) ) |
|
|
'b01
|
|
|
|
|
17
|
|
|
1
|
|
|
11
|
|
|
10
|
|
|
8
|
|
|
9
|
|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::ENDED) `else xact.get_end_realtime() `endif |
|
|
`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::STARTED) `else xact.get_begin_realtime() `endif |
|
|
svt_axi_ic_modport
|
|
|
svt_axi_ic_modport
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
5
|
|
|
3
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
4
|
|
|
5
|
|
|
2
|
|
|
3
|
|
|
3'b110
|
|
|
3'b111
|
|
|
3'b100
|
|
|
3'b101
|
|
|
4
|
|
|
5
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
12
|
|
|
(obj.get_xact_type() == svt_axi_transaction::DATA_STREAM) |
|
|
((obj.xact_type == svt_axi_transaction::READ) || ((obj.xact_type == svt_axi_transaction::COHERENT) && ((obj.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (obj.coherent_xact_type == svt_axi_transaction::READONCE) || (obj.coherent_xact_type == svt_axi_transaction::READSHARED) || (obj.coherent_xact_type == svt_axi_transaction::READCLEAN) || (obj.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (obj.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (obj.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (obj.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (obj.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (obj.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (obj.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (obj.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (obj.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (obj.coherent_xact_type == svt_axi_transaction::READBARRIER ) ) ) ) |
|
|
((obj.xact_type == svt_axi_transaction::WRITE) || ((obj.xact_type == svt_axi_transaction::COHERENT) && ((obj.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || `ifdef SVT_ACE5_ENABLE (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (obj.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (obj.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (obj.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || `endif (obj.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || (obj.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (obj.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (obj.coherent_xact_type == svt_axi_transaction::WRITEEVICT) || (obj.coherent_xact_type == svt_axi_transaction::EVICT) || (obj.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) ) ) `ifdef SVT_ACE5_ENABLE || ((obj.xact_type == svt_axi_transaction::ATOMIC) && ((obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_ADD) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_CLR) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_EOR) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SET) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SMAX) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_SMIN) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_UMAX) || (obj.atomic_xact_op_type == svt_axi_transaction::ATOMICSTORE_UMIN) ) ) `endif ) |
|
|
1
|
|
|
2
|
|
|
2
|
|
|
3
|
|
|
3
|
|
|
1'b0
|
|
|
0
|
|
|
svt_axi_master_if
|
|
|
0
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
0
|
|
|
6
|
|
|
1
|
|
|
0
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
4
|
|
|
3
|
|
|
5
|
|
|
svt_axi_master_transaction_scenario
|
|
|
svt_axi_master_transaction
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
|
|
0
|
|
|
1
|
|
|
16
|
|
|
16
|
|
|
1
|
|
|
5
|
|
|
$sformatf("{OBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) COHERENT_XACT_TYPE(%0s) ID('h%0x) SECURE('d%0d) ADDR('h%0x) } ", ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.coherent_xact_type.name:"null"), ((xact != null)?xact.id:0), ((xact != null)?!xact.prot_type[1]:0), ((xact != null)?xact.addr:0)) |
|
|
1'b1
|
|
|
0
|
|
|
2
|
|
|
0
|
|
|
7
|
|
|
6
|
|
|
5
|
|
|
4
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
64
|
|
|
'b00
|
|
|
1
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) %0s PORT_NAME(%0s) TYPE(%0s)%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s}", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf("AUTO_GENERATED_XACT('b%0b)",xact.is_auto_generated)):""):""), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null && xact.xact_type == svt_axi_transaction::WRITE)?($sformatf(" WLAST('b%0b)",xact.is_last_write_data_beat)):""), ((xact != null) && (xact.xact_type == svt_axi_transaction::READ)?($sformatf(" RLAST('b%0b)",xact.is_last_read_data_beat)):""), ((xact != null && xact.get_transmitted_channel() == svt_axi_transaction::WRITE)?($sformatf(" DATA_BEFORE_ADDR('b%0b)",xact.data_before_addr)):""), ((xact != null)?((xact.xact_type == svt_axi_transaction::COHERENT)?{$sformatf(" COHERENT_XACT_TYPE(%0s)",xact.coherent_xact_type.name)}:""):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TID('h%0x)",xact.tid)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TDEST('h%0x)",xact.tdest)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" ID('h%0x)",xact.id)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" PROT_TYPE(%0s)",xact.prot_type.name)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" ADDR('h%0x)",xact.addr)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" BURST(%0s)",xact.burst_type.name)):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" SIZE(%0s)",xact.burst_size.name)):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" LENGTH('d%0d)",xact.burst_length)):($sformatf(" LENGTH('d%0d)",xact.stream_burst_length))):""), ((xact != null && xact.xact_type.name != "DATA_STREAM")?($sformatf(" CACHE_TYPE('d%0d)",xact.cache_type)):"")) |
|
|
3
|
|
|
4
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
'b100
|
|
|
|
|
$sformatf("%0s('d%0d) : {TYPE(%0s) ID('h%0x) ADDR('h%0x)}", SVT_DATA_UTIL_ARG_TO_STRING(function_name), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.id:0), ((xact != null)?xact.addr:0)) |
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) %0s PORT_NAME(%0s) TYPE(%0s)%0s%0s LENGTH('h%0h)%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s%0s} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf("AUTO_GENERATED_XACT('b%0b)",xact.is_auto_generated)):""):""), (((xact != null)&&(xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" BURST(%0s)",xact.burst_type.name)):""):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?($sformatf(" SIZE(%0s)",xact.burst_size.name)):""):""), ((xact != null)?((xact.xact_type.name!="DATA_STREAM")?xact.burst_length:xact.stream_burst_length):0), ((xact != null && xact.xact_type == svt_axi_transaction::WRITE)?($sformatf(" WLAST('b%0b)",xact.is_last_write_data_beat)):""), ((xact != null) && (xact.xact_type == svt_axi_transaction::READ)?($sformatf(" RLAST('b%0b)",xact.is_last_read_data_beat)):""), ((xact != null && xact.get_transmitted_channel() == svt_axi_transaction::WRITE)?($sformatf(" DATA_BEFORE_ADDR('b%0b)",xact.data_before_addr)):""), ((xact != null)?((xact.xact_type == svt_axi_transaction::COHERENT)?{$sformatf(" COHERENT_XACT_TYPE(%0s)",xact.coherent_xact_type.name)}:""):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" ID('h%0x)",xact.id)):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" SECURE('h%0h)",!xact.prot_type[1])):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" ADDR('h%0x)",xact.addr)):""), ((xact != null && xact.xact_type.name!="DATA_STREAM")?($sformatf(" CACHE_TYPE('h%0h)",xact.cache_type)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TID('h%0x)",xact.tid)):""), ((xact != null && xact.xact_type.name == "DATA_STREAM")?($sformatf(" TDEST('h%0x)",xact.tdest)):""), ((xact != null)?(xact.atomic_type==svt_axi_transaction::EXCLUSIVE)?" EXCL":"":""), ((xact != null)?((xact.get_begin_time()==-1)?"":($sformatf(" START_TIME(%0t)",xact.get_begin_realtime()))):""), ((xact != null)?((xact.get_end_time()==-1)?"":($sformatf(" END_TIME(%0t)",xact.get_end_realtime()))):"")) |
|
|
0
|
|
|
1
|
|
|
2
|
|
|
0
|
|
|
0
|
|
|
1
|
|
|
3
|
|
|
5
|
|
|
1
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
( (xact.get_xact_type() == svt_axi_master_transaction::COHERENT) && ( ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READONCE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::WRITEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHARED) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANSHAREDPERSIST) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCECLEANINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READONCEMAKEINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::MAKEINVALID) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READCLEAN) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READCLEAN) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READNOTSHAREDDIRTY) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READNOTSHAREDDIRTY) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READSHARED) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READSHARED) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::READUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::READUNIQUE) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::CLEANUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::CLEANINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::MAKEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) || ( (xact.coherent_xact_type == svt_axi_master_transaction::WRITELINEUNIQUE) && (snoop.snoop_xact_type == svt_axi_snoop_transaction::MAKEINVALID) ) ) ) |
|
|
2
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
2
|
|
|
`define var``_``val |
|
|
0
|
|
|
3
|
|
|
1
|
|
|
svt_axi_slave_if
|
|
|
1
|
|
|
0
|
|
|
6
|
|
|
0
|
|
|
5
|
|
|
3
|
|
|
2
|
|
|
4
|
|
|
1
|
|
|
0
|
|
|
svt_axi_slave_transaction_scenario_gen_callbacks
|
|
|
svt_axi_slave_transaction_scenario_gen
|
|
|
svt_axi_slave_transaction_scenario
|
|
|
svt_axi_slave_transaction
|
|
|
4
|
|
|
'b10
|
|
|
16
|
|
|
1
|
|
|
2
|
|
|
4
|
|
|
8
|
|
|
0
|
|
|
1
|
|
|
5
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
1
|
|
|
0
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
9
|
|
|
8
|
|
|
14
|
|
|
15
|
|
|
13
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
7
|
|
|
|
|
128
|
|
|
16
|
|
|
512
|
|
|
$sformatf("{%0sOBJECT_NUM('d%0d) PORT_ID('d%0d) PORT_NAME(%0s) TYPE(%0s) BURST_LENGTH('d%0d) TID('h%0x) TDEST('h%0x)%0s%0s} ", (((xact != null) && (xact.object_info != ""))?$sformatf("OBJ_INFO(%0s) ", xact.object_info):""), ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), (((xact != null) && (xact.port_cfg!=null))?xact.port_cfg.get_port_name():""), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.stream_burst_length:0), ((xact != null)?xact.tid:0), ((xact != null)?xact.tdest:0), ((xact != null)?((xact.get_begin_time()==-1)?"":($sformatf(" START_TIME(%0t)",xact.get_begin_realtime()))):""), ((xact != null)?((xact.get_end_time()==-1)?"":($sformatf(" END_TIME(%0t)",xact.get_end_realtime()))):"")) |
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
3
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
7
|
|
|
4
|
|
|
1
|
|
|
8
|
|
|
5
|
|
|
2
|
|
|
9
|
|
|
6
|
|
|
3
|
|
|
0
|
|
|
2
|
|
|
4
|
|
|
7
|
|
|
6
|
|
|
1
|
|
|
0
|
|
|
2
|
|
|
0
|
|
|
0
|
|
|
4
|
|
|
3
|
|
|
2
|
|
|
1
|
|
|
5
|
|
|
3
|
|
|
2
|
|
|
0
|
|
|
6
|
|
|
1
|
|
|
'b101
|
|
|
3
|
|
|
4
|
|
|
2
|
|
|
0
|
|
|
5
|
|
|
1
|
|
|
'b111
|
|
|
1
|
|
|
1
|
|
|
7
|
|
|
1
|
|
|
|
|
`define SVT_AXI_VALID_MASTER_IDX_0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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`define SVT_AXI_VALID_SLAVE_IDX_0 |
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10
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12
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14
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15
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2,4,8,16
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0
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1
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2
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0
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0
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1
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16
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0
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3
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2
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5
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17
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4
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7
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6
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9
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18
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11
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10
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13
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19
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12
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15
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14
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8
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2
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0
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1
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1
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( ( ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) || (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE) ) && (this_xact.is_coherent_xact_dropped == 1) ) || ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) && ( (this_xact.ack_status == svt_axi_transaction::ACCEPT) || (this_xact.ack_status == svt_axi_transaction::ABORTED) ) ) || ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (SVT_AXI_IS_TRANSMITTED_CHANNEL_WRITE(this_xact)) && ( ( (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) || (this_xact.write_resp_status == svt_axi_transaction::ABORTED) ) ) ) || `ifdef SVT_ACE5_ENABLE ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (`SVT_AXI_IS_TRANSMITTED_CHANNEL_READ_WRITE(this_xact)) && ( ( (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) || (this_xact.write_resp_status == svt_axi_transaction::ABORTED) || (this_xact.atomic_read_data_status == svt_axi_transaction::ACCEPT) || (this_xact.atomic_read_data_status == svt_axi_transaction::ABORTED) ) ) ) || `endif ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (SVT_AXI_IS_TRANSMITTED_CHANNEL_READ(this_xact)) && ( ( (this_xact.data_status == svt_axi_transaction::ACCEPT) || (this_xact.data_status == svt_axi_transaction::ABORTED) ) ) ) ) |
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1
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2
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1
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3
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((1<<SVT_AXI_MAX_BURST_LENGTH_WIDTH)-1)
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17
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17
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`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::ENDED) `else xact.get_end_realtime() `endif |
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`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::STARTED) `else xact.get_begin_realtime() `endif |
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1
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16
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16
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1
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$sformatf("{%0s KIND(%0s) %0s CHAN(%0s) %0s %0s %0s %0s %0s %0s %0s %0s %0s %0s MSG(%0s) STS(%0s)}", ((xact != null)? ($sformatf("OBJECT_NUM('d%0d)",xact.object_id)):"OBJECT_NUM(-1)"), ((xact != null)?xact.port_cfg.dti_port_kind.name():""), ((xact != null)? ($sformatf("PORT_ID('d%0d)",xact.port_cfg.port_id)):""), ((xact != null)?xact.channel_type.name():""), ((xact != null)? ($sformatf("ID('h%0h)",xact.id)):""), ((xact != null && xact.message_type==0)?($sformatf("PROTOCOL_VERSION('h%0h)",xact.protocol_version)):""), ((xact != null)? ($sformatf("DTI_VERSION(%0s)",xact.port_cfg.dti_version)):""), ((xact != null && (xact.message_type==3 ||xact.message_type==16))? ($sformatf("BYPASS('h%0h)",xact.bypass)):""), ((xact != null && (xact.message_type==1 ||xact.message_type==14))? ($sformatf("OAS('h%0h)",xact.output_address_size)):""), ((xact != null && (xact.message_type==2))? ($sformatf("SEC_SID('h%0h)",xact.secure_stream_id)):""), ((xact != null && (xact.message_type==2 && xact.port_cfg.dti_version==2))? ($sformatf("MMUV('h%0h)",xact.mmuv)):""), ((xact != null && (xact.message_type==2 && xact.port_cfg.dti_version==1))? ($sformatf("FLOW('%0s)",xact.flow)):""), ((xact != null && (xact.message_type.name()=="DTI_TBU_REG_RDATA"))? ($sformatf("DATA(%0s)",xact.get_data_string())):""), ((xact != null && (xact.message_type.name()=="DTI_TBU_REG_READ"))? ($sformatf("DATA(%0s)",xact.get_data_string())):""), ((xact != null)?xact.message_type.name():""), ((xact != null)?xact.xact_status.name():"")) |
|
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`define var``_``val |
|
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( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h00|| xact.operation == 9'h10|| xact.operation ==9'h18|| xact.operation == 9'h20|| xact.operation == 9'h30|| xact.operation ==9'h38 )) || ((xact.port_cfg.dti_version != svt_dti_port_configuration::DTI3_0 && xact.port_cfg.dti_version != svt_dti_port_configuration::DTI4_0) && ( xact.operation == 8'h00|| xact.operation == 8'h10|| xact.operation ==8'h18|| xact.operation == 8'h20|| xact.operation == 8'h30|| xact.operation ==8'h38 )) ) ) |
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( xact.operation == 9'h100|| xact.operation == 9'h110|| xact.operation ==9'h118 ) |
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( xact.operation == 9'h104|| xact.operation == 9'h105 ) |
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( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'h40|| xact.operation == 8'h41 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'h40|| xact.operation == 8'h41|| xact.operation == 8'h82|| xact.operation == 8'h85|| xact.operation == 8'h90|| xact.operation == 8'h95|| xact.operation == 8'hC0|| xact.operation == 8'hC9|| xact.operation == 8'hC1|| xact.operation == 8'hC8 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h80|| xact.operation == 9'h81|| xact.operation == 9'h88|| xact.operation == 9'h89|| xact.operation == 9'hA0|| xact.operation == 9'hB2|| xact.operation == 9'hB0|| xact.operation == 9'hB1|| xact.operation == 9'hB8|| xact.operation == 9'hB9|| xact.operation == 9'hB5|| xact.operation == 9'hE0|| xact.operation == 9'hE1|| xact.operation == 9'hE8|| xact.operation == 9'hE9|| xact.operation == 9'h40|| xact.operation == 9'h41|| xact.operation == 9'h82|| xact.operation == 9'h85|| xact.operation == 9'h90|| xact.operation == 9'h95|| xact.operation == 9'hC0|| xact.operation == 9'hC9|| xact.operation == 9'hC1|| xact.operation == 9'hC8 ) ) ) ) |
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( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h47|| xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) ) |
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$sformatf("{OBJECT_NUM('d%0d) PORT_ID('d%0d) TYPE(%0s) TID('h%0x) TDATA('h%0x) TDEST('h%0x) } ", ((xact != null)?xact.object_id:-1), ((xact != null)?xact.port_id:-1), ((xact != null)?xact.xact_type.name:"null"), ((xact != null)?xact.tid:0), ((xact != null)?xact.tdata[0]:0), ((xact != null)?xact.tdest:0)) |
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( xact.operation == 8'h31 || xact.operation==8'h33 ||xact.operation==8'h39 ) |
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( xact.operation == 8'h31 || xact.operation==8'h33 || xact.operation==8'h39 ) |
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( xact.operation==8'h39 ) |
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( xact.operation == 8'h31 || xact.operation==8'h33 || xact.operation==8'h39 ) |
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`define SVT_DTI_VALID_MASTER_IDX_0 |
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`define SVT_DTI_VALID_SLAVE_IDX_0 |
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( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation==8'h88||xact.operation==8'h89|| xact.operation==8'hB8||xact.operation==8'hB9|| xact.operation==8'hE8||xact.operation==8'hE9 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0) && ( xact.operation==8'h88||xact.operation==8'h89|| xact.operation==8'hB8||xact.operation==8'hB9|| xact.operation==8'hE8||xact.operation==8'hE9|| xact.operation==8'h88||xact.operation==8'h89|| xact.operation==8'hC8||xact.operation==8'hC9 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation==9'h88||xact.operation==9'h89|| xact.operation==9'hB8||xact.operation==9'hB9|| xact.operation==9'hE8||xact.operation==9'hE9|| xact.operation==9'h88||xact.operation==9'h89|| xact.operation==9'hC8||xact.operation==9'hC9|| xact.operation==9'h198||xact.operation==9'h199|| xact.operation==9'h1C8||xact.operation==9'h1C9 ) ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h100 ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h104 ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h105 ) ) ) |
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( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'h41 ) ) || (( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0)&& ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40|| xact.operation == 8'h82|| xact.operation == 8'h85|| xact.operation == 8'h90|| xact.operation == 8'h95|| xact.operation == 8'hC0|| xact.operation == 8'hC1|| xact.operation == 8'h88|| xact.operation == 8'h89|| xact.operation == 8'hB8|| xact.operation == 8'hB9|| xact.operation == 8'hE8|| xact.operation == 8'hE9|| xact.operation == 8'hB9|| xact.operation == 8'hE8|| xact.operation == 8'h41|| xact.operation == 8'hC8|| xact.operation == 8'hC9 ) ) || (( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0)&& ( xact.operation == 9'h80|| xact.operation == 9'h81|| xact.operation == 9'hA0|| xact.operation == 9'hB2|| xact.operation == 9'hB0|| xact.operation == 9'hB1|| xact.operation == 9'hB5|| xact.operation == 9'hE0|| xact.operation == 9'hE1|| xact.operation == 9'h40|| xact.operation == 9'h82|| xact.operation == 9'h85|| xact.operation == 9'h90|| xact.operation == 9'h95|| xact.operation == 9'hC0|| xact.operation == 9'hC1|| xact.operation == 9'h88|| xact.operation == 9'h89|| xact.operation == 9'hB8|| xact.operation == 9'hB9|| xact.operation == 9'hE8|| xact.operation == 9'hE9|| xact.operation == 9'hB9|| xact.operation == 9'hE8|| xact.operation == 9'h41|| xact.operation == 9'hC8|| xact.operation == 9'hC9|| xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) ) |
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( ( (xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h80 || xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40 ) ) || ( (xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation == 8'h80|| xact.operation == 8'h81|| xact.operation == 8'hA0|| xact.operation == 8'hB2|| xact.operation == 8'hB0|| xact.operation == 8'hB1|| xact.operation == 8'hB5|| xact.operation == 8'hE0|| xact.operation == 8'hE1|| xact.operation == 8'h40|| xact.operation == 8'h82|| xact.operation == 8'h85|| xact.operation == 8'h90|| xact.operation == 8'h95|| xact.operation == 8'hC0|| xact.operation == 8'hC1 ) ) || ( ( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 ||xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h80|| xact.operation == 9'h81|| xact.operation == 9'hA0|| xact.operation == 9'hB2|| xact.operation == 9'hB0|| xact.operation == 9'hB1|| xact.operation == 9'hB5|| xact.operation == 9'hE0|| xact.operation == 9'hE1|| xact.operation == 9'h40|| xact.operation == 9'h82|| xact.operation == 9'h85|| xact.operation == 9'h90|| xact.operation == 9'h95|| xact.operation == 9'hC0|| xact.operation == 9'hC1|| xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && (xact.operation ==8'hB2 ||xact.operation==8'hB0 ||xact.operation==8'hB1||xact.operation==8'hB8 ||xact.operation==8'hB9||xact.operation==8'hB5 ||xact.operation==8'h10||xact.operation==8'h30 )) || ( ( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0) && (xact.operation == 8'hB2||xact.operation==8'hB0 ||xact.operation==8'hB1||xact.operation==8'hB8 ||xact.operation==8'hB9||xact.operation==8'hB5 ||xact.operation==8'h10||xact.operation==8'h30 ||xact.operation==8'h81||xact.operation==8'h82 ||xact.operation==8'h85||xact.operation==8'h88 ||xact.operation==8'h89||xact.operation==8'h90 ||xact.operation==8'h95 )) || ( ( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && (xact.operation == 9'hB2||xact.operation==9'hB0 ||xact.operation==9'hB1||xact.operation==9'hB8 ||xact.operation==9'hB9||xact.operation==9'hB5 ||xact.operation==9'h10||xact.operation==9'h30 ||xact.operation==9'h81||xact.operation==9'h82 ||xact.operation==9'h85||xact.operation==9'h88 ||xact.operation==9'h89||xact.operation==9'h90 ||xact.operation==9'h95 ||xact.operation==9'h190||xact.operation==9'h191 ||xact.operation==9'h192||xact.operation==9'h195 ||xact.operation==9'h198||xact.operation==9'h199 ||xact.operation==9'h110 )) ) |
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( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation ==8'h81 || xact.operation==8'h85 || xact.operation ==8'h89 || xact.operation==8'h95 || xact.operation ==8'hB1 || xact.operation==8'hB9 || xact.operation ==8'hB5 || xact.operation==8'hC9 || xact.operation ==8'hC1 || xact.operation==8'hE1 || xact.operation ==8'hE9 || xact.operation==8'h41 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0 ) && ( xact.operation ==9'h81 || xact.operation==9'h85 || xact.operation ==9'h89 || xact.operation==9'h95 || xact.operation ==9'hB1 || xact.operation==9'hB9 || xact.operation ==9'hB5 || xact.operation==9'hC9 || xact.operation ==9'hC1 || xact.operation==9'hE1 || xact.operation ==9'hE9 || xact.operation==9'h41 || xact.operation ==9'h191 || xact.operation==9'h195 || xact.operation ==9'h199 || xact.operation==9'h1C1 || xact.operation==9'h1C9 ) ) ) ) |
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( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h38 || xact.operation==9'h30 || xact.operation == 9'h18 || xact.operation==9'h10 )) || ((xact.port_cfg.dti_version != svt_dti_port_configuration::DTI3_0 && xact.port_cfg.dti_version != svt_dti_port_configuration::DTI4_0) && ( xact.operation == 8'h38 || xact.operation==8'h30 || xact.operation == 8'h18 || xact.operation==8'h10 )) ) ) |
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( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h18|| xact.operation==9'h38 )) || ((xact.port_cfg.dti_version != svt_dti_port_configuration::DTI3_0 && xact.port_cfg.dti_version != svt_dti_port_configuration::DTI4_0) && ( xact.operation ==8'h18|| xact.operation==8'h38 )) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h198 || xact.operation==9'h199 || xact.operation ==9'h1C8 || xact.operation==9'h1C9 ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h118 || xact.operation ==9'h110 ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation==9'h118 ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h47 || xact.operation ==9'h191 || xact.operation ==9'h195 || xact.operation ==9'h199 || xact.operation ==9'h1C1 || xact.operation ==9'h1C9 || xact.operation ==9'h100 || xact.operation ==9'h105 ) ) ) |
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'h190 || xact.operation==9'h191 || xact.operation ==9'h192 || xact.operation==9'h195 || xact.operation ==9'h198 || xact.operation==9'h199 ) ) ) |
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( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation == 8'h81|| xact.operation == 8'h89|| xact.operation == 8'hB1|| xact.operation == 8'hB9|| xact.operation == 8'hE1|| xact.operation == 8'hE9|| xact.operation == 8'h41|| xact.operation == 8'hB5 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation == 8'h81|| xact.operation == 8'h89|| xact.operation == 8'hB1|| xact.operation == 8'hB9|| xact.operation == 8'hE1|| xact.operation == 8'hE9|| xact.operation == 8'h41|| xact.operation == 8'hB5|| xact.operation == 8'h85|| xact.operation == 8'h95|| xact.operation == 8'hC9|| xact.operation == 8'hC1 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0 ) && ( xact.operation == 9'h81|| xact.operation == 9'h89|| xact.operation == 9'hB1|| xact.operation == 9'hB9|| xact.operation == 9'hE1|| xact.operation == 9'hE9|| xact.operation == 9'h41|| xact.operation == 9'hB5|| xact.operation == 9'h85|| xact.operation == 9'h95|| xact.operation == 9'hC9|| xact.operation == 9'hC1|| xact.operation == 9'h47|| xact.operation == 9'h191||xact.operation == 9'h199|| xact.operation == 9'h1C1|| xact.operation == 9'h1C9|| xact.operation == 9'h195 ) ) ) ) |
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|
( ( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI1_0) && ( xact.operation ==8'hB2 || xact.operation==8'hB0 || xact.operation ==8'hB1 || xact.operation==8'hB8 || xact.operation ==8'hB9 || xact.operation==8'hB5 ) ) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI2_0 ) && ( xact.operation ==8'hB2 || xact.operation==8'hB0 || xact.operation ==8'hB1 || xact.operation==8'hB8 || xact.operation ==8'hB9 || xact.operation==8'hB5 || xact.operation ==8'h81 || xact.operation==8'h82 || xact.operation ==8'h85 || xact.operation==8'h88 || xact.operation ==8'h89 || xact.operation==8'h90 || xact.operation ==8'h95 ) ) || (( xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation ==9'hB2 || xact.operation==9'hB0 || xact.operation ==9'hB1 || xact.operation==9'hB8 || xact.operation ==9'hB9 || xact.operation==9'hB5 || xact.operation ==9'h81 || xact.operation==9'h82 || xact.operation ==9'h85 || xact.operation==9'h88 || xact.operation ==9'h89 || xact.operation==9'h90 || xact.operation ==9'h95|| xact.operation ==9'h190 || xact.operation==9'h191 || xact.operation ==9'h192 || xact.operation==9'h195 || xact.operation ==9'h198 || xact.operation==9'h199 ) ) ) ) |
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2,4,8,16
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1
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0
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0
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|
`ifdef SVT_UVM_TECHNOLOGY uvm_object_utils(obj) `elsif SVT_OVM_TECHNOLOGY `ovm_object_utils(obj) `endif |
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128
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2
|
|
|
id[11:8]
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token_translation[11:8]
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`define var``_``val |
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|
`ifdef SVT_AMBA_DATA_UTIL_ENABLE_INTERNAL_MESSAGING svt_debug(id, msg) `else do begin end while(0) `endif |
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svt_err_check_stats
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2
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6
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slave_0,slave_1,slave_2,slave_3,slave_4,slave_5
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`ifdef SVT_AMBA_DATA_UTIL_ENABLE_INTERNAL_MESSAGING svt_verbose(id, msg) `else do begin end while(0) `endif |
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2
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`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COMPARE) begin if (!svt_axi_cache_compare_hook(this.__vmm_rhs, this.__vmm_image)) begin this.__vmm_status = 0; end end `endif | |
Add some customized logic to compare the actual memory elements
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`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COPY) begin svt_axi_cache_copy_hook(this.__vmm_rhs); end `endif | |
Add some customized logic to copy the actual memory elements
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(xact_type == COHERENT) && ( (coherent_xact_type == CLEANUNIQUE) || (coherent_xact_type == MAKEUNIQUE) || (coherent_xact_type == CLEANSHARED) || (coherent_xact_type == CLEANINVALID) || (coherent_xact_type == CLEANSHAREDPERSIST) || (coherent_xact_type == MAKEINVALID) ) |
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28
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29
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0
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|
SVT_AXI_MASTER_DRIVE_SIGNAL(tdata,{SVT_AXI_MAX_TDATA_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_TDATA_WIDTH{1'b``disable_sig_val}},tdata_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tstrb,{SVT_AXI_TSTRB_WIDTH{1'b``enable_sig_val}} ,{SVT_AXI_TSTRB_WIDTH{1'b``disable_sig_val}} ,tstrb_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tkeep,{SVT_AXI_TKEEP_WIDTH{1'b``enable_sig_val}} ,{SVT_AXI_TKEEP_WIDTH{1'b``disable_sig_val}} ,tkeep_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tid ,{SVT_AXI_MAX_TID_WIDTH{1'b``enable_sig_val}} ,{SVT_AXI_MAX_TID_WIDTH{1'b``disable_sig_val}} ,tid_enable ) SVT_AXI_MASTER_DRIVE_SIGNAL(tdest,{SVT_AXI_MAX_TDEST_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_TDEST_WIDTH{1'b``disable_sig_val}},tdest_enable) `ifdef SVT_AXI5_STREAM_CHECK_TYPE_INTERNAL_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(tdatachk,{CEIL(SVT_AXI_MAX_TDATA_WIDTH,8){1'b``enable_sig_val}},{CEIL(SVT_AXI_MAX_TDATA_WIDTH,8){1'b``disable_sig_val}},tdata_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tstrbchk,{CEIL(SVT_AXI_TSTRB_WIDTH,8){1'b``enable_sig_val}} ,{CEIL(SVT_AXI_TSTRB_WIDTH,8){1'b``disable_sig_val}} ,tstrb_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tkeepchk,{CEIL(SVT_AXI_TKEEP_WIDTH,8){1'b``enable_sig_val}} ,{CEIL(SVT_AXI_TKEEP_WIDTH,8){1'b``disable_sig_val}} ,tkeep_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tidchk ,{CEIL(SVT_AXI_MAX_TID_WIDTH,8){1'b``enable_sig_val}} ,{CEIL(SVT_AXI_MAX_TID_WIDTH,8){1'b``disable_sig_val}} ,tid_enable ) SVT_AXI_MASTER_DRIVE_SIGNAL(tdestchk,{CEIL(SVT_AXI_MAX_TDEST_WIDTH,8){1'b``enable_sig_val}},{CEIL(SVT_AXI_MAX_TDEST_WIDTH,8){1'b``disable_sig_val}},tdest_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(tuserchk,{CEIL(SVT_AXI_MAX_TUSER_WIDTH,8){1'b``enable_sig_val}},{CEIL(SVT_AXI_MAX_TUSER_WIDTH,8){1'b``disable_sig_val}},tuser_enable) `endif SVT_AXI_MASTER_DRIVE_SIGNAL(tuser,{SVT_AXI_MAX_TUSER_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_TUSER_WIDTH{1'b``disable_sig_val}},tuser_enable) |
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`SVT_DATA_UTIL_IS_VALID_SUFFIX_INT_W_CONST(master_cfg[i].``param, ic_cfg.slave_cfg[i].``param, $psprintf(" based on master_cfg['d%0d].``param('d%0d) and ic_cfg.slave_cfg['d%0d].``param('d%0d) which should match", i,master_cfg[i].``param,i,ic_cfg.slave_cfg[i].``param)) |
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`SVT_DATA_UTIL_IS_VALID_SUFFIX_INT_W_CONST(slave_cfg[i].``param, ic_cfg.master_cfg[i].``param, $psprintf(" based on slave_cfg['d%0d].``param('d%0d) and ic_cfg.master_cfg['d%0d].``param('d%0d) which should match", i,master_cfg[i].``param,i,ic_cfg.slave_cfg[i].``param)) |
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0
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|
`ifdef SVT_VMM_TECHNOLOGY if (do_what == DO_COMPARE) begin if (!svt_axi_fifo_mem_compare_hook(this.__vmm_rhs, this.__vmm_image)) begin this.__vmm_status = 0; end end `endif | |
Add some customized logic to compare the actual memory elements
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`ifdef SVT_VMM_TECHNOLOGY if (do_what == DO_COPY) begin svt_axi_fifo_mem_copy_hook(this.__vmm_rhs); end `endif | |
Add some customized logic to copy the actual memory elements
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`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::ENDED) `else xact.get_end_realtime() `endif |
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`ifdef SVT_VMM_TECHNOLOGY xact.notify.timestamp(vmm_data::STARTED) `else xact.get_begin_realtime() `endif |
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|
((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
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((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
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`ifdef SVT_UVM_TECHNOLOGY svt_axi_ic_snoop_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_ic_snoop_input_port_type `else svt_axi_ic_snoop_input_port_type `endif |
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port_cfg.axi_interface_type
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(xact.xact_type == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || `endif (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER) ) |
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|
(xact.xact_type == svt_axi_transaction::COHERENT) && ( (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP) || `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNPFULL) || `endif (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) || `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || (xact.coherent_xact_type == svt_axi_transaction::CMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEZERO) || `endif `endif (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) || (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN) || (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK) || (xact.coherent_xact_type == svt_axi_transaction::EVICT) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT) ) |
|
|
if (SVT_AXI_MASTER_IS_SIGNAL_ENABLED(axi_signal_enable)) prop_name = observed_val; else prop_name = default_val; |
|
|
((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
|
|
if (suspended_snoop_xacts.size())begin driver_mp.axi_master_cb.acready <= 1'b0; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.acreadychk <= 1'b1; end else begin driver_mp.axi_master_cb.acready <= val; end |
|
|
if (SVT_AXI_MASTER_IS_SIGNAL_ENABLED(sig_enable)) driver_mp.axi_master_cb.sig_name <= enable_sig_val; else driver_mp.axi_master_cb.sig_name <= disable_sig_val; |
|
|
if (SVT_AXI_MASTER_IS_SIGNAL_ENABLED(axi_signal_enable)) begin if(!($cast(prop_name,observed_val))) svt_fatal("Failed when attempting to cast"); end else prop_name = default_val; |
|
|
`ifdef SVT_UVM_TECHNOLOGY svt_axi_master_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_master_input_port_type `else svt_axi_master_input_port_type `endif |
|
|
`ifdef SVT_UVM_TECHNOLOGY svt_axi_master_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_master_input_port_type `else svt_axi_master_input_port_type `endif |
|
|
(cfg.axi_interface_type != svt_axi_port_configuration::AXI4_LITE) && ( (cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || (cfg.axi_signal == 1) ) |
|
|
((xact.xact_type == svt_axi_transaction::READ) || (( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER)))) |
|
|
xact_event_pool = xact.get_event_pool(); xact_ev = xact_event_pool.get(event_name); xact_ev.wait_trigger(); |
|
|
uvm_event_pool xact_event_pool; uvm_event xact_ev; |
|
|
if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && (cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable)) begin observed_``sg_name = 1'b0; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
|
|
((xact.xact_type == svt_axi_transaction::WRITE) || ((( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE)|| (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE)|| `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || (xact.coherent_xact_type == svt_axi_transaction::CMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEZERO) || `endif `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNPFULL) || `endif `endif (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK)|| (xact.coherent_xact_type == svt_axi_transaction::EVICT)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEEVICT)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER))))) |
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8
| |
@groupname
|
|
|
|
|
8
| |
@groupname
|
|
|
|
|
|
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1
|
|
|
32
|
|
|
4
|
|
|
16
|
|
|
|
|
`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COMPARE) begin if (!svt_axi_passive_cache_compare_hook(this.__vmm_rhs, this.__vmm_image)) begin this.__vmm_status = 0; end end `endif | |
Add some customized logic to compare the actual memory elements
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`ifdef SVT_UVM_TECHNOLOGY `elsif SVT_OVM_TECHNOLOGY `else if (do_what == DO_COPY) begin svt_axi_passive_cache_copy_hook(this.__vmm_rhs); end `endif | |
Add some customized logic to copy the actual memory elements
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0
|
|
|
0
|
|
|
if (SVT_AXI_PORT_MONITOR_IS_SIGNAL_ENABLED(axi_signal_enable)) prop_name = observed_val; else prop_name = default_val; |
|
|
if (SVT_AXI_PORT_MONITOR_IS_SIGNAL_ENABLED(axi_signal_enable)) begin if(!($cast(prop_name,observed_val))) svt_error("SVT_AXI_PORT_MONITOR_ENUM_ASSIGN_SIGNAL_VAL",{"Failed to cast in macro for signal observed_val to prop_name"}); end else prop_name = default_val; |
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(cfg.axi_interface_type != svt_axi_port_configuration::AXI4_LITE) && ( (cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || (cfg.axi_signal_enable == 1) ) |
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(xact.transmitted_channel == svt_axi_transaction::READ) |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && (cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable)) begin observed_``sg_name = 1'b0; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
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(xact.transmitted_channel == svt_axi_transaction::WRITE) |
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driver_mp.axi_master_cb.araddr <= {SVT_AXI_MAX_ADDR_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.arvmidext <= {SVT_AXI_MAX_VMIDEXT_WIDTH{1'b``enable_sig_val}}; SVT_AXI_MASTER_DRIVE_SIGNAL(arid,{SVT_AXI_MAX_ID_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_ID_WIDTH{1'b``disable_sig_val}},arid_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arlen,{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``disable_sig_val}},arlen_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arsize,{SVT_AXI_SIZE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_SIZE_WIDTH{1'b``disable_sig_val}},arsize_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arburst,{SVT_AXI_BURST_WIDTH{1'b``enable_sig_val}},{SVT_AXI_BURST_WIDTH{1'b``disable_sig_val}},arburst_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arlock,{SVT_AXI_LOCK_WIDTH{1'b``enable_sig_val}},{SVT_AXI_LOCK_WIDTH{1'b``disable_sig_val}},arlock_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arcache,{SVT_AXI_CACHE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_CACHE_WIDTH{1'b``disable_sig_val}},arcache_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arprot,{SVT_AXI_PROT_WIDTH{1'b``enable_sig_val}},{SVT_AXI_PROT_WIDTH{1'b``disable_sig_val}},arprot_enable) `ifdef SVT_AXI_QVN_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(arvnet,{`SVT_AXI_QVN_ARVNET_WIDTH{1'b``enable_sig_val}},{`SVT_AXI_QVN_ARVNET_WIDTH{1'b``disable_sig_val}},qvn_enable) `endif `ifdef SVT_ACE5_ENABLE driver_mp.axi_master_cb.armpam <= {SVT_AXI_MAX_MPAM_WIDTH{1'b``enable_sig_val}}; SVT_AXI_MASTER_DRIVE_SIGNAL(aridunq,1'b``enable_sig_val,1'b``disable_sig_val,unique_id_enable) driver_mp.axi_master_cb.arloop <= {SVT_AXI_MAX_LOOP_R_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.arnsaid <= {SVT_AXI_MAX_NSAID_WIDTH{1'b``enable_sig_val}}; if(cfg.rdata_chunking_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(archunken,1'b``enable_sig_val,1'b``disable_sig_val,rdata_chunking_enable) `endif if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) || (cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) || (cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE)) begin if(cfg.arqos_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arqos,{SVT_AXI_QOS_WIDTH{1'b``enable_sig_val}},{SVT_AXI_QOS_WIDTH{1'b``disable_sig_val}},arqos_enable) if(cfg.arregion_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(arregion,{SVT_AXI_REGION_WIDTH{1'b``enable_sig_val}},{SVT_AXI_REGION_WIDTH{1'b``disable_sig_val}},arregion_enable) end else begin driver_mp.axi_master_cb.arqos <= SVT_AXI_QOS_WIDTH'bz; driver_mp.axi_master_cb.arregion <= SVT_AXI_REGION_WIDTH'bz; end if (cfg.aruser_enable) begin driver_mp.axi_master_cb.aruser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.aruserchk <= ~{CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.aruser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.aruserchk <= {CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'bz}}; end |
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driver_mp.axi_slave_cb.rid <= {SVT_AXI_MAX_ID_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rresp <= {SVT_AXI_RESP_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rdata <= {SVT_AXI_MAX_DATA_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rlast <= 1'b``val; `ifdef SVT_ACE5_ENABLE if(cfg.unique_id_enable) driver_mp.axi_slave_cb.ridunq <= {1'b``val}; if(cfg.rdata_chunking_enable)begin driver_mp.axi_slave_cb.rchunkstrb <= {SVT_AXI_MAX_CHUNK_STROBE_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.rchunknum <= {SVT_AXI_MAX_CHUNK_NUM_WIDTH{1'b``val}}; end if(cfg.enable_loopback_signaling)begin driver_mp.axi_slave_cb.rloop <= {SVT_AXI_MAX_LOOP_R_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.bloop <= {SVT_AXI_MAX_LOOP_W_WIDTH{1'b``val}}; end `endif if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL || cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_DATA) driver_mp.axi_slave_cb.rdatachk <= {CEIL(SVT_AXI_MAX_DATA_WIDTH,8){1'b``val}}; if(cfg.ruser_enable) begin driver_mp.axi_slave_cb.ruser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'b``val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.ruserchk <= ~{CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'b``val}}; end else begin driver_mp.axi_slave_cb.ruser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.ruserchk <= {CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'bz}}; end |
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EXCLUDE_UNSTARTED_XACT
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((cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || ((cfg.axi_interface_category != svt_axi_port_configuration::``interface_category) && (cfg.axi_interface_type == svt_axi_port_configuration::AXI4))) |
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(((active_xact_queue.size() >= cfg.num_outstanding_xact) && (cfg.num_outstanding_xact != -1)) || ((active_read_xact_count >= cfg.num_read_outstanding_xact) && (cfg.num_outstanding_xact == -1))) |
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(((active_xact_queue.size() >= cfg.num_outstanding_xact) && (cfg.num_outstanding_xact != -1)) || ((active_write_xact_count >= cfg.num_write_outstanding_xact) && (cfg.num_outstanding_xact == -1))) |
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(((active_xact_queue.size() > cfg.num_outstanding_xact) && (cfg.num_outstanding_xact != -1)) || ((active_write_xact_count > cfg.num_write_outstanding_xact) && (cfg.num_outstanding_xact == -1))) |
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(cfg.axi_interface_type != svt_axi_port_configuration::AXI4_LITE) && ( (cfg.axi_interface_type != svt_axi_port_configuration::AXI4) || (cfg.axi_signal == 1) ) |
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((xact.xact_type == svt_axi_transaction::READ) || (( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::READNOSNOOP) || (xact.coherent_xact_type == svt_axi_transaction::READONCE) || (xact.coherent_xact_type == svt_axi_transaction::READONCECLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READONCEMAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::MAKEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (xact.coherent_xact_type == svt_axi_transaction::CLEANSHAREDPERSIST) || (xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) || (xact.coherent_xact_type == svt_axi_transaction::DVMCOMPLETE) || (xact.coherent_xact_type == svt_axi_transaction::DVMMESSAGE) || (xact.coherent_xact_type == svt_axi_transaction::READBARRIER)))) |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && ((cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable) || (!(cfg_enable)))) begin driver_mp.axi_slave_cb.``sg_name <= width'bZ; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4_LITE) && lite_disable) begin driver_mp.axi_slave_cb.``sg_name <= width'bZ; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI3) && axi3_disable) begin driver_mp.axi_slave_cb.``sg_name <= width'bZ; end else begin driver_mp.axi_slave_cb.``sg_name <= val; end |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && ((cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable) || (!(cfg_enable)))) begin observed_``sg_name = val; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4_LITE) && lite_disable) begin observed_``sg_name = val; end else if((cfg.axi_interface_type == svt_axi_port_configuration::AXI3) && axi3_disable) begin observed_``sg_name = val; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
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if ((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) && (cfg.axi_interface_category == svt_axi_port_configuration::``interface_category_disable)) begin observed_``sg_name = 1'b0; end else begin observed_``sg_name = monitor_mp.axi_monitor_cb.``sg_name; end |
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((xact.xact_type == svt_axi_transaction::WRITE) || ((( xact.xact_type == svt_axi_transaction::COHERENT) && ((xact.coherent_xact_type == svt_axi_transaction::WRITENOSNOOP)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE)|| `ifdef SVT_ACE5_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEPTLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUEFULLSTASH) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCEUNIQUE) || (xact.coherent_xact_type == svt_axi_transaction::STASHONCESHARED) || (xact.coherent_xact_type == svt_axi_transaction::STASHTRANSLATION) || (xact.coherent_xact_type == svt_axi_transaction::CMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEPTLCMO) || (xact.coherent_xact_type == svt_axi_transaction::WRITEFULLCMO) || `ifdef SVT_AXI_WRITE_DEFERRABLE_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEDEFERRABLE) || `endif `ifdef SVT_AXI_PREFETCH_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::PREFETCH) || `endif `ifdef SVT_AXI_WRITE_ZERO_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITEZERO) || `endif `ifdef SVT_AXI_WRITENOSNPFULL_XACT_INTERNAL_ENABLE (xact.coherent_xact_type == svt_axi_transaction::WRITENOSNPFULL) || `endif `endif (xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE)|| (xact.coherent_xact_type == svt_axi_transaction::WRITECLEAN)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBACK)|| (xact.coherent_xact_type == svt_axi_transaction::EVICT)|| (xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER))))) |
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`ifdef SVT_UVM_TECHNOLOGY svt_axi_snoop_input_port_type `elsif SVT_OVM_TECHNOLOGY svt_axi_snoop_input_port_type `else svt_axi_snoop_input_port_type `endif |
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(master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (master_xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (master_xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (master_xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (master_xact.coherent_xact_type == svt_axi_transaction::READONCE) || (master_xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) ) |
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(master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (master_xact.coherent_xact_type == svt_axi_transaction::READSHARED) || (master_xact.coherent_xact_type == svt_axi_transaction::READCLEAN) || (master_xact.coherent_xact_type == svt_axi_transaction::READNOTSHAREDDIRTY) || (master_xact.coherent_xact_type == svt_axi_transaction::READONCE) || (master_xact.coherent_xact_type == svt_axi_transaction::READUNIQUE) || (master_xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (master_xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (master_xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (master_xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || (master_xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) ) |
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( /** Either this item has not been associated yet to any slave transaction, or if */ /** it is associated, then the slave_port_id should match that of the slave transaction */ /** since a single master transaction will not get routed to two different slaves */ /**((item.slave_port_id.size() == 0) || (slave_xact.port_cfg.port_id inside {item.slave_port_id})) && */ /** The exp_slave_port_id is set in the sys_xact based on the memory map. Unless slaves with */ /** overlapping addr is set (in which case the xact could be routed to another slave port), */ /** item.exp_slave_port_id and slave_xact.port_cfg.port_id should match */ (axi_sys_common_cfg.allow_slaves_with_overlapping_addr || is_amba_system_monitor || (slave_xact.port_cfg.port_id inside {item.exp_slave_port_id})) && ( ( ( (slave_xact.transmitted_channel == svt_axi_transaction::WRITE) && !( (slave_xact.converted_xact_type == svt_axi_transaction::COHERENT) && (slave_xact.coherent_xact_type == svt_axi_transaction::WRITEBARRIER) ) && ( (item.master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (item.master_xact.coherent_xact_type == svt_axi_transaction::WRITEUNIQUE) || (item.master_xact.coherent_xact_type == svt_axi_transaction::WRITELINEUNIQUE) ) ) && !item.is_xact_fully_mapped && (axi_sys_common_cfg.id_based_xact_correlation_enable && (!((item.master_xact.port_cfg.id_based_xact_correlation_enable && slave_xact.port_cfg.id_based_xact_correlation_enable) || !is_find_first_check_done) || (source_master_id == axi_sys_common_cfg.source_master_id_wu_wlu_xmit_to_slaves && axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type != svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) || ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (axi_sys_common_cfg.is_master_id_and_slave_id_correlated(item.master_xact,slave_xact)) ) ) ) ) || ( ( ( !( ( (item.master_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (item.master_xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (item.master_xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (item.master_xact.coherent_xact_type == svt_axi_transaction::CLEANUNIQUE) || (item.master_xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) ) ) || ( (slave_xact.converted_xact_type == svt_axi_transaction::COHERENT) && ( (slave_xact.coherent_xact_type == svt_axi_transaction::CLEANSHARED) || (slave_xact.coherent_xact_type == svt_axi_transaction::CLEANINVALID) || (slave_xact.coherent_xact_type == svt_axi_transaction::MAKEINVALID) ) ) ) && (item.master_xact.transmitted_channel == slave_xact.transmitted_channel) ) || ( (item.master_xact.converted_xact_type == slave_xact.converted_xact_type) && /** coherent_xact_type will match only when xact_type is COHERENT */ ( (item.master_xact.converted_xact_type != svt_axi_transaction::COHERENT) || (item.master_xact.coherent_xact_type == slave_xact.coherent_xact_type ) ) ) ) && !item.is_xact_fully_mapped && ( !axi_sys_common_cfg.id_based_xact_correlation_enable || !((item.master_xact.port_cfg.id_based_xact_correlation_enable && slave_xact.port_cfg.id_based_xact_correlation_enable) || !is_find_first_check_done) || ( ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (axi_sys_common_cfg.is_master_id_and_slave_id_correlated(item.master_xact,slave_xact)) ) || ( ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::STATIC_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (source_master_id == axi_sys_common_cfg.get_source_master_id_at_slave_from_master_id(item.master_xact.id,item.master_xact.port_cfg.port_id)) ) || ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::DYNAMIC_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (source_master_id == item.master_xact.dynamic_source_master_id_xmit_to_slaves) ) && (source_master_xact_id == axi_sys_common_cfg.get_master_xact_id_at_slave_from_master_id(item.master_xact.id,item.master_xact.port_cfg.port_id)) ) || ((item.master_xact.port_cfg.is_source_master_id_and_dest_slave_id_same == 1) && (slave_xact.id == item.master_xact.id)) ) ) ) ) || /** Dirty data may be written after all the other data is written in which case is_xact_fully_mapped will be set */ /** so don't check for is_xact_fully_mapped for dirty data write */ ( SVT_AXI_SYSTEM_MONITOR_IS_DIRTY_DATA_XACT(item.master_xact) && (slave_xact.transmitted_channel == svt_axi_transaction::WRITE) && (axi_sys_common_cfg.id_based_xact_correlation_enable && (!((item.master_xact.port_cfg.id_based_xact_correlation_enable && slave_xact.port_cfg.id_based_xact_correlation_enable) || !is_find_first_check_done) || (source_master_id == axi_sys_common_cfg.source_interconnect_id_xmit_to_slaves && axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type != svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES ) || ( (axi_sys_common_cfg.master_cfg[item.master_xact.port_cfg.port_id].source_master_id_xmit_to_slaves_type == svt_axi_port_configuration::CUSTOM_SOURCE_MASTER_ID_XMIT_TO_SLAVES) && (axi_sys_common_cfg.is_master_id_and_slave_id_correlated(item.master_xact,slave_xact)) ) ) ) ) ) && (SVT_AXI_GET_XACT_START_TIME(item.master_xact) <= SVT_AXI_GET_XACT_START_TIME(slave_xact)) && (item.master_xact.addr_status != svt_axi_transaction::ABORTED) && (item.master_xact.data_status != svt_axi_transaction::ABORTED) && (item.master_xact.write_resp_status != svt_axi_transaction::ABORTED) && ( ( (is_exact_match && (item.master_xact.cache_type[1] == 1'b0)) && (get_amba_min_byte_address(.xact(item.master_xact), .convert_to_global_addr(1), /** If tagged master and untagged slave is supported, get tagged address from master only if slave also uses it */ .use_tagged_addr(~axi_sys_common_cfg.support_tagged_master_and_untagged_slave), .convert_to_slave_addr(1), .requester_name(get_master_xact_requester_name(item.master_xact))) == slave_xact_min_addr) && (get_amba_max_byte_address(.xact(item.master_xact),.convert_to_global_addr(1), /** If tagged master and untagged slave is supported, get tagged address from master only if slave also uses it */ .use_tagged_addr(~axi_sys_common_cfg.support_tagged_master_and_untagged_slave), .convert_to_slave_addr(1), .requester_name(get_master_xact_requester_name(item.master_xact))) == slave_xact_max_addr) ) || ( (!is_exact_match || ((item.master_xact.cache_type[1] == 1'b1) || (axi_sys_common_cfg.master_to_slave_association_mode == 2))) && (is_amba_address_overlap(.xact(item.master_xact),.min_addr(slave_xact_min_addr), .max_addr(slave_xact_max_addr), .convert_to_global_addr(1), .use_tagged_addr(~axi_sys_common_cfg.support_tagged_master_and_untagged_slave), .convert_to_slave_addr(1), .requester_name(get_master_xact_requester_name(item.master_xact)))) ) ) ) |
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if ((port_cfg != null) && (port_cfg.``enablefieldwdth > 0)) begin `SVT_DATA_UTIL_COMPARE_BITVEC_SLICE(fieldname,fieldmaxwidth,port_cfg.``enablefieldwdth``-1,0) end else begin `SVT_DATA_UTIL_COMPARE_BITVEC(fieldname) end | |
Transaction Class Macros definition and utility methods definition
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if ((port_cfg != null) && (port_cfg.``enablefieldwdth > 0)) begin `SVT_DATA_UTIL_COMPARE_BITVEC_SLICE_SIZE_ARRAY(fieldname,fieldmaxwidth,port_cfg.``enablefieldwdth``-1,0) end else begin `SVT_DATA_UTIL_COMPARE_INT_SIZE_ARRAY(fieldname) end |
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( ( (xact.transmitted_channel == svt_axi_transaction::WRITE) && (xact.write_resp_status == svt_axi_transaction::ACCEPT ) && (xact.bresp == (xact.port_cfg.exclusive_access_enable == 1 && xact.atomic_type == svt_axi_transaction::EXCLUSIVE) ? svt_axi_transaction::EXOKAY : svt_axi_transaction::OKAY) ) || ( (xact.transmitted_channel == svt_axi_transaction::READ) && (xact.data_status == svt_axi_transaction::ACCEPT ) && (rresp == (xact.port_cfg.exclusive_access_enable == 1 && xact.atomic_type == svt_axi_transaction::EXCLUSIVE) ? svt_axi_transaction::EXOKAY : svt_axi_transaction::OKAY) ) ) |
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if (obj.data.size()) begin foreach (obj.data[i]) begin bit[SVT_AXI_MAX_DATA_WIDTH-1:0] _data_mask; _data_mask = ((1 << ((1 << obj.burst_size) << 3)) - 1); obj.data[i] = obj.data[i] & _data_mask; end end |
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if (obj.poison.size()) begin foreach (obj.poison[i]) begin bit[SVT_AXI_MAX_DATA_WIDTH/64-1:0] _poison_mask; if(obj.burst_size>3) _poison_mask = ((1 << ((1 << obj.burst_size) / 8)) - 1); else _poison_mask =1; obj.poison[i] = obj.poison[i] & _poison_mask; end end |
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if (obj.tag.size()) begin foreach (obj.tag[i]) begin bit[SVT_AXI_MAX_TAG_WIDTH-1:0] _tag_mask; _tag_mask =((1<<(((CEIL(((1 << obj.burst_size) << 3),128)))*4))-1); obj.tag[i] = obj.tag[i] & _tag_mask; end end |
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if (obj.data.size() != obj.wstrb.size()) begin svt_error("svt_axi_transaction", $sformatf("Cannot compare data because size of data array ('d%0d) is not equal to size of wstrb array ('d%0d). xact_type(%0s). coherent_xact_type(%0s). transmitted_channel(%0s) xact = %0s", obj.data.size(), obj.wstrb.size(), obj.xact_type.name(), obj.coherent_xact_type.name(), obj.transmitted_channel.name(),SVT_AXI_PRINT_PREFIX1(obj))); end foreach (obj.data[i]) begin bit[SVT_AXI_MAX_DATA_WIDTH-1:0] _data_mask; bit[(SVT_AXI_MAX_DATA_WIDTH/8)-1:0] _wstrb = obj.wstrb[i]; _data_mask = 'h0; foreach (_wstrb[i]) begin if (_wstrb[i] === 1'b1) _data_mask[i*8+:8] = 'hff; else _data_mask[i*8+:8] = 'h0; end obj.data[i] = obj.data[i] & _data_mask; end |
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if (obj.tag.size() != obj.tag_update.size()) begin svt_error("svt_axi_transaction", $sformatf("Cannot compare tag because size of tag array ('d%0d) is not equal to size of tag_update array ('d%0d). xact_type(%0s). coherent_xact_type(%0s). transmitted_channel(%0s) xact = %0s", obj.tag.size(), obj.tag_update.size(), obj.xact_type.name(), obj.coherent_xact_type.name(), obj.transmitted_channel.name(),SVT_AXI_PRINT_PREFIX1(obj))); end foreach (obj.tag[i]) begin bit[SVT_AXI_MAX_TAG_WIDTH-1:0] _tag_mask; bit[(SVT_AXI_MAX_TAGUPDATE_WIDTH)-1:0] _tag_update = obj.tag_update[i]; _tag_mask = 'h0; foreach (_tag_update[i]) begin if (_tag_update[i] === 1'b1) _tag_mask[i*4+:4] = 'hf; else _tag_mask[i*4+:4] = 'h0; end obj.tag[i] = obj.tag[i] & _tag_mask; end |
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`ifdef SVT_UVM_TECHNOLOGY begin uvm_event_pool xact_event_pool; uvm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `elsif SVT_OVM_TECHNOLOGY begin ovm_event_pool xact_event_pool; ovm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `else this_xact.notify.wait_for(vmm_data::ENDED); `endif |
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`ifdef SVT_UVM_TECHNOLOGY begin uvm_event_pool xact_event_pool; uvm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `elsif SVT_OVM_TECHNOLOGY begin ovm_event_pool xact_event_pool; ovm_event ended_event; xact_event_pool = this_xact.get_event_pool(); ended_event = xact_event_pool.get("end"); ended_event.wait_trigger(); end `else this_xact.notify.wait_for(vmm_data::ENDED); `endif |
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driver_mp.axi_master_cb.awaddr <= {SVT_AXI_MAX_ADDR_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awatop <= {SVT_ACE5_ATOMIC_TYPE_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awmpam <= {SVT_AXI_MAX_MPAM_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awloop <= {SVT_AXI_MAX_LOOP_W_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awnsaid <= {SVT_AXI_MAX_NSAID_WIDTH{1'b``enable_sig_val}}; driver_mp.axi_master_cb.awcmo <= {SVT_AXI_ACE_WCMO_WIDTH{1'b``enable_sig_val}}; SVT_AXI_MASTER_DRIVE_SIGNAL(awid,{SVT_AXI_MAX_ID_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_ID_WIDTH{1'b``disable_sig_val}},awid_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awlen,{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_BURST_LENGTH_WIDTH{1'b``disable_sig_val}},awlen_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awsize,{SVT_AXI_SIZE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_SIZE_WIDTH{1'b``disable_sig_val}},awsize_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awburst,{SVT_AXI_BURST_WIDTH{1'b``enable_sig_val}},{SVT_AXI_BURST_WIDTH{1'b``disable_sig_val}},awburst_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awlock,{SVT_AXI_LOCK_WIDTH{1'b``enable_sig_val}},{SVT_AXI_LOCK_WIDTH{1'b``disable_sig_val}},awlock_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awcache,{SVT_AXI_CACHE_WIDTH{1'b``enable_sig_val}},{SVT_AXI_CACHE_WIDTH{1'b``disable_sig_val}},awcache_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awprot,{SVT_AXI_PROT_WIDTH{1'b``enable_sig_val}},{SVT_AXI_PROT_WIDTH{1'b``disable_sig_val}},awprot_enable) `ifdef SVT_AXI_QVN_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(awvnet,{`SVT_AXI_QVN_AWVNET_WIDTH{1'b``enable_sig_val}},{`SVT_AXI_QVN_AWVNET_WIDTH{1'b``disable_sig_val}},qvn_enable) `endif `ifdef SVT_ACE5_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(awidunq,1'b``enable_sig_val,1'b``disable_sig_val,unique_id_enable) `endif if((cfg.axi_interface_type == svt_axi_port_configuration::AXI4) || (cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) || (cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE)) begin if(cfg.awqos_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awqos,{SVT_AXI_QOS_WIDTH{1'b``enable_sig_val}},{SVT_AXI_QOS_WIDTH{1'b``disable_sig_val}},awqos_enable) if(cfg.awregion_enable) SVT_AXI_MASTER_DRIVE_SIGNAL(awregion,{SVT_AXI_REGION_WIDTH{1'b``enable_sig_val}},{SVT_AXI_REGION_WIDTH{1'b``disable_sig_val}},awregion_enable) end else begin driver_mp.axi_master_cb.awqos <= SVT_AXI_QOS_WIDTH'bz; driver_mp.axi_master_cb.awregion <= SVT_AXI_REGION_WIDTH'bz; end if (cfg.awuser_enable) begin driver_mp.axi_master_cb.awuser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.awuserchk <= ~{CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.awuser <= {SVT_AXI_MAX_ADDR_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.awuserchk <= {CEIL(SVT_AXI_MAX_ADDR_USER_WIDTH,8){1'bz}}; end |
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driver_mp.axi_master_cb.wdata <= {SVT_AXI_MAX_DATA_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL || cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_DATA ) driver_mp.axi_master_cb.wdatachk <= ~{CEIL(SVT_AXI_MAX_DATA_WIDTH,8){1'b``enable_sig_val}}; driver_mp.axi_master_cb.wstrb <= {SVT_AXI_MAX_DATA_WIDTH/8{1'b``enable_sig_val}}; `ifdef SVT_AXI_QVN_ENABLE SVT_AXI_MASTER_DRIVE_SIGNAL(wvnet,{`SVT_AXI_QVN_WVNET_WIDTH{1'b``enable_sig_val}},{`SVT_AXI_QVN_WVNET_WIDTH{1'b``disable_sig_val}},qvn_enable) `endif if ((cfg.axi_interface_type == svt_axi_port_configuration :: AXI3 ) || (cfg.wid_for_non_axi3_enable == 1 )) begin driver_mp.axi_master_cb.wid <= {SVT_AXI_MAX_ID_WIDTH{1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.wid <= {SVT_AXI_MAX_ID_WIDTH{1'bz}}; end if (cfg.wuser_enable) begin driver_mp.axi_master_cb.wuser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'b``enable_sig_val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.wuserchk <= ~{CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'b``enable_sig_val}}; end else begin driver_mp.axi_master_cb.wuser <= {SVT_AXI_MAX_DATA_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_master_cb.wuserchk <= {CEIL(SVT_AXI_MAX_DATA_USER_WIDTH,8){1'bz}}; end SVT_AXI_MASTER_DRIVE_SIGNAL(wlast,{SVT_AXI_MAX_DATA_WIDTH{1'b``enable_sig_val}},{SVT_AXI_MAX_DATA_WIDTH{1'b``disable_sig_val}},wlast_enable) |
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driver_mp.axi_slave_cb.bid <= {SVT_AXI_MAX_ID_WIDTH{1'b``val}}; driver_mp.axi_slave_cb.bresp <= {SVT_AXI_RESP_WIDTH{1'b``val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.brespchk <= ~{CEIL(SVT_AXI_MAX_BRESP_USER_WIDTH,8){1'b``val}}; `ifdef SVT_ACE5_ENABLE if(cfg.unique_id_enable) driver_mp.axi_slave_cb.bidunq <= 1'b``val; `endif if(cfg.buser_enable) begin driver_mp.axi_slave_cb.buser <= {SVT_AXI_MAX_BRESP_USER_WIDTH{1'b``val}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.buserchk <= ~{CEIL(SVT_AXI_MAX_BRESP_USER_WIDTH,8){1'b``val}}; end else begin driver_mp.axi_slave_cb.buser <= {SVT_AXI_MAX_BRESP_USER_WIDTH{1'bz}}; if(cfg.check_type == svt_axi_port_configuration::ODD_PARITY_BYTE_ALL) driver_mp.axi_slave_cb.buserchk <= {CEIL(SVT_AXI_MAX_BRESP_USER_WIDTH,8){1'bz}}; end |
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( ( (this_xact.port_cfg.axi_interface_type == svt_axi_port_configuration::AXI_ACE) && (this_xact.ack_status == svt_axi_transaction::ACCEPT) ) || ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (this_xact.transmitted_channel == svt_axi_transaction::WRITE) && (this_xact.write_resp_status == svt_axi_transaction::ACCEPT) ) || ( (this_xact.port_cfg.axi_interface_type != svt_axi_port_configuration::AXI_ACE) && (this_xact.transmitted_channel == svt_axi_transaction::READ) && (this_xact.data_status == svt_axi_transaction::ACCEPT) ) ) |
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32
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6
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2
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covergroup trans_dti_allow_non_sec_inst_reads @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_NSX option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_non_sec_inst_reads.
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covergroup trans_dti_allow_priv_read_data_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_PR option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_priv_read_data_access.
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covergroup trans_dti_allow_priv_write_data_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_PW option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_priv_write_data_access.
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covergroup trans_dti_allow_priv_inst_reads @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_PX option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_priv_inst_reads.
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covergroup trans_dti_allow_data_read_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_R option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_data_read_access.
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covergroup trans_dti_allow_unpriv_data_read_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_UR option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_unpriv_data_read_access.
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covergroup trans_dti_allow_unpriv_data_write_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_UW option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_unpriv_data_write_access.
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covergroup trans_dti_allow_unpriv_instruction_reads @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_UX option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_unpriv_instruction_reads.
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covergroup trans_dti_allow_data_write_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_W option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_data_write_access.
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covergroup trans_dti_allow_instruction_read_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_X option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_allow_instruction_read_access.
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covergroup trans_dti_ats_condis_req_no_trans @(cov_sample_condis_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_CONDIS_REQ_NO_TRANS option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_condis_req_no_trans for NO_TRANS field for DTI_ATS_CONDIS_REQ message type.
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covergroup trans_dti_ats_error @(cov_sample_sync_ack_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ERROR option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_error for ERROR field for DTI_ATS_SYNC_ACK message type.
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covergroup trans_dti_ats_error_v3 @(cov_sample_sync_ack_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ERROR_V3 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_error_v3 for ERROR field for DTI_ATS_SYNC_ACK message type.
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covergroup trans_dti_ats_fault_type @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_FAULT_TYPE option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ats_fault_type.
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covergroup ats_inv_req_dti_operation @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_INV_REQ_OPERATION option.per_instance =1; endgroup | |
Macro to create covergroup:ats_inv_req_dti_operation .
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covergroup ats_inv_req_dti_sid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_INV_REQ_SID option.per_instance =1; endgroup | |
Macro to create covergroup:ats_inv_req_dti_sid .
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covergroup ats_inv_req_dti_ssid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_INV_REQ_SSID option.per_instance =1; endgroup | |
Macro to create covergroup:ats_inv_req_dti_ssid .
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covergroup ats_inv_req_dti_va_ipa @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_INV_REQ_VA_IPA option.per_instance =1; endgroup | |
Macro to create covergroup:ats_inv_req_dti_va_ipa .
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covergroup trans_dti_ats_page_execute_access @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_EXECUTE_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_execute_access for INST field for DTI_ATS_PAGE_REQ message type.
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covergroup trans_dti_ats_page_last @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_LAST option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_last for LAST field for DTI_ATS_PAGE_REQ message type.
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covergroup trans_dti_ats_page_priv_access @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_PRIV_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_priv_access for PRIV field for DTI_ATS_PAGE_REQ message type.
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covergroup trans_dti_ats_page_read_access @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_READ_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_read_access for READ field for DTI_ATS_PAGE_REQ message type.
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covergroup trans_dti_ats_page_request_group @(cov_sample_ats_page_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_REQUEST_GROUP option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_request_group for PRG_INDEX field for DTI_ATS_PAGE_REQ and DTI_ATS_PAGE_RESP message type.
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covergroup trans_dti_ats_page_resp @(cov_sample_ats_page_rsp_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_RESP option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_resp for RESP field for DTI_ATS_PAGE_RESP message type.
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covergroup trans_dti_ats_page_stream_id @(cov_sample_ats_page_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_STREAM_ID option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_stream_id for SID field for DTI_ATS_PAGE_REQ and DTI_ATS_PAGE_RESP message type.
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covergroup trans_dti_ats_page_sub_stream_id @(cov_sample_ats_page_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_SUB_STREAM_ID option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_sub_stream_id for SSID field for DTI_ATS_PAGE_REQ and DTI_ATS_PAGE_RESP message type.
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covergroup trans_dti_ats_page_valid_substream @(cov_sample_ats_page_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_VALID_SUBSTREAM option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_valid_substream for SSV field for DTI_ATS_PAGE_REQ and DTI_ATS_PAGE_RESP message type.
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covergroup trans_dti_ats_page_write_access @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_WRITE_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_page_write_access for WRITE field for DTI_ATS_PAGE_REQ message type.
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covergroup trans_dti_ats_range @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_RANGE option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_range for RANGE field for DTI_ATS_INV_REQ message type.
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covergroup trans_dti_ats_trans_resp_ats_memory_type_attributes_v1 @(cov_sample_trans_resp_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANS_ATS_MEMORY_TYPE_ATTRIBUTES_V1 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_trans_resp_ats_memory_type_attributes_v1 for AMA field for DTI_ATS_TRANS_RESP message type.
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covergroup trans_dti_ats_trans_resp_ats_memory_type_attributes_v2 @(cov_sample_trans_resp_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANS_ATS_MEMORY_TYPE_ATTRIBUTES_V2 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_trans_resp_ats_memory_type_attributes_v2 for AMA field for DTI_ATS_TRANS_RESP message type.
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covergroup trans_dti_ats_trans_resp_cxl_io_v1 @(cov_sample_trans_resp_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANS_RESP_CXL_IO_V1 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_trans_resp_cxl_io_v1 for CXL_IO field for DTI_ATS_TRANS_RESP message type.
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covergroup trans_dti_ats_trans_resp_cxl_io_v2 @(cov_sample_trans_resp_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANS_RESP_CXL_IO_V2 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_ats_trans_resp_cxl_io_v2 for CXL_IO field for DTI_ATS_TRANS_RESP message type.
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covergroup trans_dti_ats_translation_range_with_bypass_0 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANSLATION_RANGE_BYPASS_0 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ats_translation_range_with_bypass_0.
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covergroup trans_dti_ats_translation_range_with_bypass_1_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANSLATION_RANGE_BYPASS_1_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ats_translation_range_with_bypass_1_v1.
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covergroup trans_dti_ats_translation_range_with_bypass_1_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANSLATION_RANGE_BYPASS_1_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ats_translation_range_with_bypass_1_v2.
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covergroup trans_dti_ats_translation_resp_output_address @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANSLATION_RESP_OUTPUT_ADDR option.per_instance =1; option.auto_bin_max = SVT_DTI_DTI_TRANS_RESP_ADDR_AUTO_BINS; endgroup | |
Macro to create covergroup :trans_dti_ats_translation_resp_output_address.
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covergroup trans_dti_ats_untranslated @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_UNTRANSLATED option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ats_untranslated.
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covergroup trans_dti_ats_write_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_WRITE_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ats_write_access.
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covergroup trans_dti_override_attributes_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V1 option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_override_attributes_v1.
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covergroup trans_dti_override_attributes_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V2 option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_override_attributes_v2.
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covergroup trans_dti_bypassed_translation @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_BYPASS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_bypassed_translation.
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covergroup trans_dti_combined_allocate_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_COMBINED_ALLOCATE_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_combined_allocate_v1.
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covergroup trans_dti_combined_allocate_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_COMBINED_ALLOCATE_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_combined_allocate_v2.
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covergroup trans_dti_combined_memory_type_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_COMBINED_MEMORY_TYPE_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_combined_memory_type_v1.
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covergroup trans_dti_combined_memory_type_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_COMBINED_MEMORY_TYPE_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_combined_memory_type_v2.
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covergroup trans_dti_combined_shareability_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_COMBINED_SHAREABILITY_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_combined_shareability_v1.
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covergroup trans_dti_combined_shareability_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_COMBINED_SHAREABILITY_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_combined_shareability_v2.
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covergroup trans_dti_condis_ack_state_accepted @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_CONNECTION_ACCEPTED option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_condis_ack_state_accepted.
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covergroup trans_dti_condis_req_state_requested @(cov_sample_condis_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_CONNECTION_REQUESTED option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_condis_req_state_requested.
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covergroup trans_dti_contiguous_stream_id @(cov_sample_trans_resp_or_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_CONTIGUOUS_STREAM_ID option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_contiguous_stream_id.
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covergroup trans_dti_ctxtattr @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_CTXTATTR option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ctxtattr.
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covergroup trans_dti_destructive_reads_permitted @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DESTRUCTIVE_READS_PERMITTED option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_destructive_reads_permitted.
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covergroup trans_dti_directed_cache_prefetch @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DIRECTED_CACHE_PREFETCH option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_directed_cache_prefetch.
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covergroup trans_dti_donot_cache @(cov_sample_trans_resp_or_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DONOT_CACHE option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_donot_cache.
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covergroup trans_dti_tbu_fault_type @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_tbu_fault_type.
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covergroup trans_dti_tbu_fault_type_v1 @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_tbu_fault_type_v1.
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covergroup trans_dti_tbu_fault_type_v2 @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_tbu_fault_type_v2.
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covergroup trans_dti_flow_v1 @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_FLOW_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_flow_v1.
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covergroup trans_dti_flow_v2 @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_FLOW_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_flow_v2.
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covergroup trans_dti_global_valid @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_GLOBAL option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_global_valid.
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covergroup trans_dti_hardware_attributes @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_HARDWARE_ATTRIBUTES option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_hardware_attributes.
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covergroup trans_dti_inst_data_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_inst_data_access.
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covergroup inv_req_dti_asid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_asid .
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covergroup inv_req_dti_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_inc_aset1 .
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covergroup inv_req_dti_num @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_NUM option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_num .
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covergroup inv_req_dti_operation @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_operation .
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covergroup inv_req_dti_range @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_range .
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covergroup inv_req_dti_scale @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SCALE option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_scale .
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covergroup inv_req_dti_sid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SID option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_sid .
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covergroup inv_req_dti_ssid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SSID option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_ssid .
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covergroup inv_req_dti_translation_granule_size @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_GRANULE_SIZE option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_translation_granule_size .
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covergroup inv_req_dti_translation_table_level @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_TABLE_LEVEL option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_translation_table_level .
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covergroup inv_req_dti_va_ipa @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VA_IPA option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_va_ipa .
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covergroup inv_req_dti_vmid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID option.per_instance =1; endgroup | |
Macro to create covergroup:inv_req_dti_vmid .
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covergroup inv_rsp_dti_msg @(cov_sample_message_type); inv_ack_op : coverpoint cov_message_type iff(cov_xact.is_inv_rsp()) { bins inv_ack = {svt_dti_transaction::DTI_TBU_INV_ACK}; illegal_bins invalid_message = default; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup:inv_rsp_dti_msg .
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covergroup trans_dti_invalidation_range @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INVALIDATION_RANGE option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_invalidation_range.
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covergroup trans_dti_invalidation_token_granted @(cov_sample_condis_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INVALIDATION_TOKEN_GRANTED option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_invalidation_token_granted.
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covergroup trans_dti_message_type @(cov_sample_message_type); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_MESSAGE_TYPE option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_message_type .
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covergroup trans_dti_mpamns_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_MPAMNS_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_mpamns_v1.
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covergroup trans_dti_mpamns_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_MPAMNS_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_mpamns_v2.
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covergroup trans_dti_output_address_size @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_OUTPUT_ADDRESS_SIZE option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_output_address_size.
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covergroup trans_dti_override_allocation @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOCCFG option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_override_allocation.
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covergroup trans_dti_override_instruction_data_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTCFG option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_override_instruction_data_access.
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covergroup trans_dti_override_non_secure_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_NSOVR option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_override_non_secure_access.
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covergroup trans_dti_override_privileged_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIVCFG option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_override_privileged_access.
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covergroup trans_dti_part_id_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PARTID_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_part_id_v1.
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covergroup trans_dti_part_id_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PARTID_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_part_id_v2.
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covergroup trans_dti_permissions_required @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PERMISSIONS_REQUIRED option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_permissions_required.
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covergroup trans_dti_pmg_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PMG_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_pmg_v1.
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covergroup trans_dti_pmg_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PMG_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_pmg_v2.
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covergroup trans_dti_priv_unpriv_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_priv_unpriv_access.
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covergroup trans_dti_protocol @(cov_sample_message_type); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PROTOCOL option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_protocol for PROTOCOL for TBU and ATS message type.
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covergroup trans_dti_quality_of_service @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_QUALITY_OF_SERVICE option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_quality_of_service.
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covergroup trans_dti_secure_read_write_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_READ_WRITE_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_read_write_access.
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covergroup trans_dti_register_access_supported @(cov_sample_condis_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_REGISTER_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_register_access_supported.
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covergroup trans_dti_secure_non_secure_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_secure_non_secure_access.
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covergroup trans_dti_secure_stream_id @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_secure_stream_id.
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covergroup trans_dti_shareability_set @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ASET option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_shareability_set.
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covergroup trans_dti_smmu_stream_world @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STRW option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_smmu_stream_world.
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covergroup trans_dti_speculative_translation_request @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SPECULATIVE_TRANSLATION_REQ option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_speculative_translation_request.
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covergroup trans_dti_stage1_hardware_attributes @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STAGE_1_HARDWARE_ATTRIBUTES option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_stage1_hardware_attributes.
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covergroup trans_dti_stage2_hardware_attributes @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STAGE_2_HARDWARE_ATTRIBUTES option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_stage2_hardware_attributes.
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covergroup trans_dti_stream_id @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STREAM_ID option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_stream_id.
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covergroup trans_dti_sub_stream_id @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SUB_STREAM_ID option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_sub_stream_id.
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covergroup trans_dti_sup_pri @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SUP_PRI option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_sup_pri for SUP_PRI for DTI_ATS_CONDIS_ACK message type.
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covergroup sync_req_dti_msg @(cov_sample_message_type); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_MESSAGE_TYPE sync_req_op : coverpoint cov_message_type iff(cov_xact.is_sync_req()) { bins sync_req = {svt_dti_transaction::DTI_TBU_SYNC_REQ}; illegal_bins invalid_message = default; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup:sync_req_dti_msg .
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covergroup sync_rsp_dti_msg @(cov_sample_message_type); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_MESSAGE_TYPE sync_rsp_op : coverpoint cov_message_type iff(cov_xact.is_sync_rsp()) { bins sync_ack = {svt_dti_transaction::DTI_TBU_SYNC_ACK} ; illegal_bins invalid_message = default; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup:sync_rsp_dti_msg .
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covergroup trans_dti_translation_resp_tbi @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBI option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_resp_tbi.
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covergroup trans_dti_translation_resp_asid @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANS_RESP_ASID option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_trans_resp_asid.
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covergroup trans_dti_translation_resp_non_secure_access @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANS_RESP_NS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_resp_non_secure_access.
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covergroup trans_dti_translation_attributes @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_ATTRIBUTES option.per_instance =1; option.auto_bin_max = 256; endgroup | |
Macro to create covergroup :trans_dti_translation_attributes.
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covergroup trans_dti_translation_ids @(cov_sample_trans_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_IDS option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_ids.
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covergroup trans_dti_translation_ids_v1 @(cov_sample_trans_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_IDS_V1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_ids_v1.
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covergroup trans_dti_translation_ids_v2 @(cov_sample_trans_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_IDS_V2 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_ids_v2.
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covergroup trans_dti_translation_range_with_bypass_0 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RANGE_BYPASS_0 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_range_with_bypass_0.
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covergroup trans_dti_translation_range_with_bypass_1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RANGE_BYPASS_1 option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_range_with_bypass_1.
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covergroup trans_dti_ats_translated @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_REQ_ATS_TRANSLATED option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_ats_translated.
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covergroup trans_dti_req_input_address @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_REQ_INPUT_ADDR option.per_instance =1; option.auto_bin_max = SVT_DTI_DTI_TRANS_REQ_ADDR_AUTO_BINS; endgroup | |
Macro to create covergroup :trans_dti_req_input_address.
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covergroup trans_dti_translation_resp_output_address @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RESP_OUTPUT_ADDR option.per_instance =1; option.auto_bin_max = SVT_DTI_DTI_TRANS_RESP_ADDR_AUTO_BINS; endgroup | |
Macro to create covergroup :trans_dti_translation_resp_output_address.
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covergroup trans_dti_translation_scope @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_BP_TYPE option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_scope.
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covergroup trans_dti_translation_shareability @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RESP_SHAREABILITY option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_translation_shareability.
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covergroup trans_dti_translation_token_granted @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_GRANTED option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_translation_token_granted.
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covergroup trans_dti_translation_token_granted_v1 @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_GRANTED_V1 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_translation_token_granted_v1.
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covergroup trans_dti_translation_token_granted_v2 @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_GRANTED_V2 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_translation_token_granted_v2.
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covergroup trans_dti_translation_token_requested @(cov_sample_condis_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_REQUESTED option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_translation_token_requested.
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covergroup trans_dti_translation_token_requested_v1 @(cov_sample_condis_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_REQUESTED_V1 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_translation_token_requested_v1.
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covergroup trans_dti_translation_token_requested_v2 @(cov_sample_condis_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_REQUESTED_V2 option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_translation_token_requested_v2.
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covergroup trans_dti_valid_substream @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_VALID_SUBSTREAM option.per_instance =1; endgroup | |
Macro to create covergroup :trans_dti_valid_substream.
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covergroup trans_dti_version_ack @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_VERSION_ACK option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_version_ack for VERSION for DTI_TBU_CONDIS_ACK and DTI_ATS_CONDIS_ACK message type.
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covergroup trans_dti_version_req @(cov_sample_condis_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_VERSION_REQ option.per_instance =1; endgroup | |
Macro to create covergroup:trans_dti_version_req for VERSION for DTI_TBU_CONDIS_REQ and DTI_ATS_CONDIS_REQ message type.
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covergroup trans_dti_translation_response_vmid @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_VMID option.per_instance =1; endgroup | |
Macro to create covergroup : trans_dti_translation_request_vmid.
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alloccfg: coverpoint cov_xact.override_allocation { option.weight =1; illegal_bins reserved_alloccfg = {['h1:'h7]}; } |
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allow_nsx: coverpoint cov_xact.allow_permissions[5] iff(cov_xact.bypass){ option.weight =1; } |
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allow_pr: coverpoint cov_xact.allow_permissions[3] iff(!cov_xact.bypass){ option.weight =1; } |
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allow_pw: coverpoint cov_xact.allow_permissions[4] iff(! cov_xact.bypass){ option.weight =1; } |
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allow_px: coverpoint cov_xact.allow_permissions[5] iff( ! cov_xact.bypass){ option.weight =1; } |
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allow_r: coverpoint cov_xact.allow_permissions_ats[0] iff(!cov_xact.bypass){ option.weight =1; } |
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allow_ur: coverpoint cov_xact.allow_permissions[0] iff(!cov_xact.bypass){ option.weight =1; } |
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allow_uw: coverpoint cov_xact.allow_permissions[1] iff(!cov_xact.bypass){ option.weight =1; } |
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allow_ux: coverpoint cov_xact.allow_permissions[2] iff(!cov_xact.bypass){ option.weight =1; } |
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allow_w: coverpoint cov_xact.allow_permissions_ats[1] iff(!cov_xact.bypass){ option.weight =1; } |
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allow_x: coverpoint cov_xact.allow_permissions_ats[2] iff(!cov_xact.bypass){ option.weight =1; } |
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aset: coverpoint cov_xact.shareability_set iff(cov_xact.bypass ==0) { option.weight =1; } |
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ats_no_trans: coverpoint cov_xact.no_trans iff(cov_xact.is_con_req()){ bins no_trans_e = {0,1}; option.weight =1; } |
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ats_fault_type : coverpoint cov_xact.ats_fault_type iff(cov_xact.is_trl()){ option.weight =1; } |
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ats_operation: coverpoint cov_xact.operation { bins ATCI_NOPASID = {'h31}; bins ATCI_PASID_GLOBAL = {'h33}; bins ATCI_PASID = {'h39}; bins ATS_RESERVED_VAL = default; option.weight =1; } |
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ats_stream_id: coverpoint cov_xact.stream_id iff(cov_xact.operation inside {8'h31,8'h33,8'h39}) { option.weight =1; option.auto_bin_max =4; } |
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ats_substream_id: coverpoint cov_xact.substream_id iff(cov_xact.operation inside {8'h31,8'h33,8'h39}) { option.weight =1; option.auto_bin_max =4; } |
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ats_va_ipa: coverpoint cov_xact.addr iff(cov_xact.operation inside {8'h31,8'h33,8'h39}) { option.weight =1; option.auto_bin_max =4; } |
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ats_page_execute_access: coverpoint cov_xact.page_execute_access { option.weight =1; } |
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ats_last: coverpoint cov_xact.last { option.weight =1; } |
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ats_page_priv_access: coverpoint cov_xact.page_priv_access { option.weight =1; } |
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ats_page_read_access: coverpoint cov_xact.page_read_access { option.weight =1; } |
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ats_page_request_group: coverpoint cov_xact.prg_index { option.weight =1; } |
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ats_page_resp: coverpoint cov_xact.page_resp { option.weight =1; } |
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ats_page_req_strm_id: coverpoint cov_stream_id { option.weight =1; } |
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ats_page_req_sub_strm_id: coverpoint cov_xact.substream_id { option.weight =1; } |
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ats_page_req_val_sub_strm: coverpoint cov_valid_substream { option.weight =1; } |
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ats_page_write_access: coverpoint cov_xact.page_write_access { option.weight =1; } |
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ats_rage: coverpoint cov_xact.ats_inv_range_va_ia { option.weight =1; } |
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ats_no_trans_v1: coverpoint cov_xact.ats_memory_type iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0 ){ illegal_bins ama_rsvd = {3'b001,3'b010,3'b011,3'b100,3'b101,3'b110,3'b111}; option.weight =1; } |
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ats_no_trans_v2: coverpoint cov_xact.ats_memory_type iff(port_cfg.dti_version== svt_dti_port_configuration::DTI2_0 ){ bins ama_v2 ={3'b000,3'b001,3'b010,3'b011,3'b100,3'b101,3'b110,3'b111}; option.weight =1; } |
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ats_cxl_io_v1: coverpoint cov_xact.cxl_io iff(cov_xact.is_trl_rsp() && port_cfg.dti_version== svt_dti_port_configuration::DTI1_0 ){ illegal_bins cxl_io_rsvd ={1}; option.weight =1; } |
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ats_cxl_io_v2: coverpoint cov_xact.cxl_io iff(cov_xact.is_trl_rsp() && port_cfg.dti_version== svt_dti_port_configuration::DTI2_0 ){ bins cxl_io_v2 = {0,1}; option.weight =1; } |
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trans_ats_rng_bypass_0: coverpoint cov_xact.translation_address_range iff(!cov_xact.bypass){ `ifdef SVT_DTI_COV_VERSION_DTI3_0 illegal_bins ats_trans_rng_bypass_0_reserved_val_f = {['hC:'hF]}; `else illegal_bins ats_trans_rng_bypass_0_reserved_val = {['hA:'hF]}; `endif option.weight =1; } |
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trans_ats_rng_bypass_1_v1: coverpoint cov_xact.translation_address_range iff(cov_xact.bypass){ option.weight =1; illegal_bins ats_trans_rng_bypass_1_reserved_val_v1 = {['h7:'hF]}; } |
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trans_ats_rng_bypass_1_v2: coverpoint cov_xact.translation_address_range iff(cov_xact.bypass){ option.weight =1; illegal_bins ats_trans_rng_bypass_1_reserved_val_v2 = {['h1:'hF]}; } |
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ats_trans_resp_addr: coverpoint cov_xact.addr[63:12] iff(!cov_xact.bypass) { option.weight =1; } |
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ats_untranslated: coverpoint cov_xact.untranslated { option.weight =1; } |
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nW: coverpoint cov_xact.write_access { option.weight =1; } |
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ovr_attributes_v1: coverpoint cov_xact.override_attributes iff((cov_xact.bypass) ||( !cov_xact.bypass && cov_xact.smmu_stream_world == svt_dti_transaction::EXCEPTION_LEVEL_1_S2)) { illegal_bins reserved_attr_ovr_v1 = {['h00_80:'hFF_FF]}; option.weight =1; } |
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ovr_attributes_v2: coverpoint cov_xact.override_attributes iff((cov_xact.bypass) ||( !cov_xact.bypass && cov_xact.smmu_stream_world == svt_dti_transaction::EXCEPTION_LEVEL_1_S2) && (port_cfg.dti_version== svt_dti_port_configuration::DTI2_0)) { option.weight =1; illegal_bins reserved_attr_ovr_v2 = {['h02_00:'hFF_FF]}; } |
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bp_type: coverpoint cov_xact.bp_type iff(cov_xact.bypass ==1) { option.weight =1; illegal_bins invalid_bp_type = {2'b11, 2'b00}; } |
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bypass: coverpoint cov_xact.bypass { option.weight =1; } |
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comb_alloc_v1: coverpoint cov_xact.combined_allocate iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0) { illegal_bins comb_alloc_e_reserv_v1 = {1}; option.weight =1; } |
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comb_alloc_v2: coverpoint cov_xact.combined_allocate iff((cov_xact.bypass == 0) && (port_cfg.dti_version== svt_dti_port_configuration::DTI2_0)) { bins comb_alloc_e_b_v2 = {0,1}; option.weight =1; } |
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comb_mt_v1: coverpoint cov_xact.combined_memory_type iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0) { illegal_bins comb_mt_e_reserv_v1 = {1}; option.weight =1; } |
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comb_mt: coverpoint cov_xact.combined_memory_type iff((cov_xact.bypass == 0) && (port_cfg.dti_version== svt_dti_port_configuration::DTI2_0)) { bins comb_mt_e_b_v2 = {0,1}; option.weight =1; } |
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comb_sh_v1: coverpoint cov_xact.combined_shareability iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0) { illegal_bins comb_sh_e_reserv_v1 = {1}; option.weight =1; } |
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comb_sh_v2: coverpoint cov_xact.combined_shareability iff((cov_xact.bypass == 0) && (port_cfg.dti_version== svt_dti_port_configuration::DTI2_0)) { bins comb_sh_e_v2 = {0,1}; option.weight =1; } |
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con_accept: coverpoint cov_xact.connected_state iff(cov_xact.is_con_rsp()) { option.weight =1; } |
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con_req: coverpoint con_req_connected_state { option.weight =1; } |
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contiguous_stream: coverpoint cov_xact.contiguous_streamid { option.weight =1; } |
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ctxtattr: coverpoint cov_xact.ctxtattr { option.weight =1; } |
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dre: coverpoint cov_xact.destructive_read_permitted iff(!cov_xact.bypass){ option.weight =1; } |
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dcp: coverpoint cov_xact.directed_cache_prefetch iff(!cov_xact.bypass){ option.weight =1; } |
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dont_cache: coverpoint cov_xact.do_not_cache { option.weight =1; } |
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ats_error: coverpoint cov_xact.ats_sync_error iff(cov_xact.is_sync_rsp()) { option.weight =1; } |
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ats_error: coverpoint cov_xact.ats_sync_error iff(cov_xact.is_sync_rsp()) { illegal_bins ats_sync_error_v3 ={1}; option.weight =1; } |
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flow_v1: coverpoint cov_xact.flow iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0) { illegal_bins flow_v1_illegal = {svt_dti_transaction::NOSTALL,svt_dti_transaction::PRI}; option.weight =1; } |
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flow_v2: coverpoint cov_xact.flow iff(port_cfg.dti_version== svt_dti_port_configuration::DTI2_0) { option.weight =1; } |
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global_val: coverpoint cov_xact.global_valid iff(!cov_xact.bypass){ option.weight =1; } |
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hwattr: coverpoint cov_xact.hw_attr iff(port_cfg.dti_version== svt_dti_port_configuration::DTI2_0 ){ option.weight =1; } |
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ovr_rd_ind: coverpoint cov_xact.override_InD { option.weight =1; illegal_bins reserved_instcfg = {2'b01}; } |
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inst_data_access: coverpoint cov_instruction_access { bins data_access = {0}; bins inst_access = {1}; option.weight =1; } |
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asid: coverpoint cov_xact.asid iff(cov_xact.operation inside {8'h88,8'h89,8'hB8,8'hB9,8'hE8,8'hE9,8'h06}) { option.weight =1; option.auto_bin_max =4; } |
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inc_aset1: coverpoint cov_xact.inc_aset1 iff(cov_xact.operation inside {8'h80,8'h81,8'h88,8'h89,8'hA0,8'hB2,8'hB0,8'hB1,8'hB8,8'hB9,8'hB5,8'hE0,8'hE1,8'hE8,8'hE9,8'h40,8'h41,8'h06}) { option.weight =1; } |
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num: coverpoint cov_xact.num iff(SVT_DTI_VALID_TBU_INVOP_SCALE_NUM_TG_TTL(cov_xact)) { option.weight =1; } |
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operation: coverpoint cov_xact.operation { bins TLBI_S_EL1_ALL = {'h80}; bins TLBI_S_EL1_VAA = {'h81}; bins TLBI_S_EL1_ASID = {'h88}; bins TLBI_S_EL1_VA = {'h89}; bins TLBI_NS_EL1_ALL = {'hA0}; bins TLBI_NS_EL1_S1_VMID = {'hB2}; bins TLBI_NS_EL1_S12_VMID = {'hB0}; bins TLBI_NS_EL1_VAA = {'hB1}; bins TLBI_NS_EL1_ASID = {'hB8}; bins TLBI_NS_EL1_VA = {'hB9}; bins TLBI_NS_EL1_S2_IPA = {'hB5}; bins TLBI_NS_EL2_ALL = {'hE0}; bins TLBI_NS_EL2_VAA = {'hE1}; bins TLBI_NS_EL2_ASID = {'hE8}; bins TLBI_NS_EL2_VA = {'hE9}; bins TLBI_S_EL3_ALL = {'h40}; bins TLBI_S_EL3_VA = {'h41}; bins CFGI_S_ALL = {'h00}; bins CFGI_S_SID = {'h10}; bins CFGI_S_SID_SSID = {'h18}; bins CFGI_NS_ALL = {'h20}; bins CFGI_NS_SID = {'h30}; bins CFGI_NS_SID_SSID = {'h38}; bins INV_ALL = {'h06}; bins RESERVED_VAL = default; option.weight =1; } |
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sid_vmid_range: coverpoint cov_xact.sid_vmid_range iff(cov_xact.operation inside {8'hB2,8'hB0,8'hB1,8'hB8,8'hB9,8'hB5,8'h10,8'h30,8'h06}) { option.weight =1; } |
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scale: coverpoint cov_xact.scale iff(SVT_DTI_VALID_TBU_INVOP_SCALE_NUM_TG_TTL(cov_xact)) { option.weight =1; } |
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stream_id: coverpoint cov_xact.stream_id iff(cov_xact.operation inside {8'h88,8'h89,8'hB8,8'hB9,8'hE8,8'hE9,8'h10,8'h18,8'h30,8'h38,8'h06}) { option.weight =1; option.auto_bin_max =4; } |
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substream_id: coverpoint cov_xact.substream_id iff(cov_xact.operation inside {8'h18,8'h38,8'h06}) { option.weight =1; option.auto_bin_max =4; } |
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tg: coverpoint cov_xact.translation_granule_size iff(SVT_DTI_VALID_TBU_INVOP_SCALE_NUM_TG_TTL(cov_xact)) { option.weight =1; } |
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ttl: coverpoint cov_xact.translation_table_level iff(SVT_DTI_VALID_TBU_INVOP_SCALE_NUM_TG_TTL(cov_xact)) { option.weight =1; } |
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addr: coverpoint cov_xact.addr iff(cov_xact.operation inside {8'h81,8'h89,8'hB1,8'hB5,8'hB9,8'hE1,8'hE9,8'h41,8'h06}) { option.weight =1; option.auto_bin_max =4; } |
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vmid: coverpoint cov_xact.vmid iff(cov_xact.operation inside {8'hB2,8'hB0,8'hB1,8'hB8,8'hB9,8'hB5,8'h06}) { option.weight =1; option.auto_bin_max =4; } |
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inval_rng: coverpoint cov_xact.invalidation_address_range iff(!cov_xact.bypass){ option.weight =1; } |
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inv_token_req: coverpoint cov_xact.token_invalidation iff(cov_xact.connected_state && cov_xact.is_con_req()) { bins token_0 = {'h0}; bins token_1_to_3 = {['h1:'h3]}; bins token_4_to_6 = {['h4:'h6]}; bins token_7_to_9 = {['h7:'h9]}; bins token_A_to_C = {['hA:'hC]}; bins token_D_to_E = {['hD:'hE]}; bins token_F = {'hF}; option.weight =1; } |
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message_type : coverpoint cov_message_type { bins condis_req = {svt_dti_transaction::DTI_TBU_CONDIS_REQ}; bins condis_ack = {svt_dti_transaction::DTI_TBU_CONDIS_ACK}; bins trans_req = {svt_dti_transaction::DTI_TBU_TRANS_REQ}; bins trans_resp = {svt_dti_transaction::DTI_TBU_TRANS_RESP}; bins trans_fault = {svt_dti_transaction::DTI_TBU_TRANS_FAULT}; bins inv_req = {svt_dti_transaction::DTI_TBU_INV_REQ}; bins inv_ack = {svt_dti_transaction::DTI_TBU_INV_ACK}; bins sync_req = {svt_dti_transaction::DTI_TBU_SYNC_REQ}; bins sync_ack = {svt_dti_transaction::DTI_TBU_SYNC_ACK} ; bins reg_write = {svt_dti_transaction::DTI_TBU_REG_WRITE}; bins reg_write_ack = {svt_dti_transaction::DTI_TBU_REG_WACK}; bins reg_read = {svt_dti_transaction::DTI_TBU_REG_READ}; bins reg_rdata = {svt_dti_transaction::DTI_TBU_REG_RDATA}; bins imp_def_type1_req = {svt_dti_transaction::DTI_TBU_MASTER_IMP_DEF_TYPE1_REQ,svt_dti_transaction::DTI_TBU_SLAVE_IMP_DEF_TYPE1_REQ}; bins imp_def_type2_req = {svt_dti_transaction::DTI_TBU_MASTER_IMP_DEF_TYPE2_REQ,svt_dti_transaction::DTI_TBU_SLAVE_IMP_DEF_TYPE2_REQ}; bins imp_def_type1_resp = {svt_dti_transaction::DTI_TBU_SLAVE_IMP_DEF_TYPE1_RESP,svt_dti_transaction::DTI_TBU_MASTER_IMP_DEF_TYPE1_RESP}; bins imp_def_type2_resp = {svt_dti_transaction::DTI_TBU_SLAVE_IMP_DEF_TYPE2_RESP,svt_dti_transaction::DTI_TBU_MASTER_IMP_DEF_TYPE2_RESP}; bins ats_condis_req = {svt_dti_transaction::DTI_ATS_CONDIS_REQ}; bins ats_condis_ack = {svt_dti_transaction::DTI_ATS_CONDIS_ACK}; bins ats_trans_req = {svt_dti_transaction::DTI_ATS_TRANS_REQ}; bins ats_trans_resp = {svt_dti_transaction::DTI_ATS_TRANS_RESP}; bins ats_trans_fault = {svt_dti_transaction::DTI_ATS_TRANS_FAULT}; bins ats_inv_req = {svt_dti_transaction::DTI_ATS_INV_REQ}; bins ats_inv_ack = {svt_dti_transaction::DTI_ATS_INV_ACK}; bins ats_sync_req = {svt_dti_transaction::DTI_ATS_SYNC_REQ}; bins ats_sync_ack = {svt_dti_transaction::DTI_ATS_SYNC_ACK} ; bins ats_page_req = {svt_dti_transaction::DTI_ATS_PAGE_REQ} ; bins ats_page_ack = {svt_dti_transaction::DTI_ATS_PAGE_ACK} ; bins ats_page_resp = {svt_dti_transaction::DTI_ATS_PAGE_RESP} ; bins ats_page_respack = {svt_dti_transaction::DTI_ATS_PAGE_RESPACK} ; bins ats_inv_comp = {svt_dti_transaction::DTI_ATS_INV_COMP} ; illegal_bins invalid_message = default; option.weight =1; } |
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mpamns_v1: coverpoint cov_xact.mpamns iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0) { illegal_bins mpamns_e_reserv_v1 = {1}; option.weight =1; } |
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mpamns_v2: coverpoint cov_xact.mpamns iff(port_cfg.dti_version== svt_dti_port_configuration::DTI2_0) { bins mpamns_e_v2 = {0,1}; option.weight =1; } |
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nsovr: coverpoint cov_xact.override_non_secure_access iff(cov_xact.bypass ==1) { option.weight =1; } |
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output_address_size : coverpoint cov_output_address_size iff(cov_xact.is_con_rsp() && (!((port_cfg.dti_port_kind==svt_dti_port_configuration::DTI_MASTER_ATS||port_cfg.dti_port_kind==svt_dti_port_configuration::DTI_SLAVE_ATS ) && port_cfg.dti_version == svt_dti_port_configuration::DTI2_0))) { bins size_32_bits = {svt_dti_transaction::ADDR_SIZE_32BITS}; bins size_36_bits = {svt_dti_transaction::ADDR_SIZE_36BITS}; bins size_40_bits = {svt_dti_transaction::ADDR_SIZE_40BITS}; bins size_42_bits = {svt_dti_transaction::ADDR_SIZE_42BITS}; bins size_44_bits = {svt_dti_transaction::ADDR_SIZE_44BITS}; bins size_48_bits = {svt_dti_transaction::ADDR_SIZE_48BITS}; bins size_52_bits = {svt_dti_transaction::ADDR_SIZE_52BITS}; illegal_bins invalid_oas = default; option.weight =1; } |
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part_id_v1: coverpoint cov_xact.part_id iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0) { illegal_bins part_id_reserv_v1 = {[16:$]}; option.weight =1; } |
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part_id_v2: coverpoint cov_xact.part_id iff(port_cfg.dti_version== svt_dti_port_configuration::DTI2_0) { option.weight =1; } |
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permission_req: coverpoint cov_perm_req { option.weight =1; } |
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pmg_v1: coverpoint cov_xact.pmg iff(port_cfg.dti_version== svt_dti_port_configuration::DTI1_0) { illegal_bins pmg_e_reserv = {1}; option.weight =1; } |
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pmg_v2: coverpoint cov_xact.pmg iff(port_cfg.dti_version== svt_dti_port_configuration::DTI2_0) { bins pmg_e_b = {0,1}; option.weight =1; } |
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priv_unpriv_access: coverpoint cov_privileged_access { bins priv_access = {1}; bins unpriv_access = {0}; option.weight =1; } |
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ovr_rd_pnu: coverpoint cov_xact.override_PnU { option.weight =1; illegal_bins reserved_privcfg = {2'b01}; } |
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protocol: coverpoint cov_xact.protocol { bins protocol_tbu = {'h0}; bins protocol_ats = {'h1}; option.weight =1; } |
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quality_of_service: coverpoint cov_xact.qos iff(cov_xact.is_trl_req()) { bins qos[] = {[0:15]}; option.weight =1; } |
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read_write_access: coverpoint cov_read_write_access { option.weight =1; } |
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reg_access_supported: coverpoint cov_xact.support_register_access iff(cov_xact.connected_state && cov_xact.is_con_req()) { option.weight =1; } |
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sec_nsec_access: coverpoint cov_non_secure_access { option.weight =1; } |
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sec_sid: coverpoint cov_secure_stream_id { option.weight =1; } |
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speculative: coverpoint cov_speculative_translation { option.weight =1; } |
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s1hwattr: coverpoint cov_xact.stage1_hw_attr{ option.weight =1; } |
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s2hwattr: coverpoint cov_xact.stage2_hw_attr{ option.weight =1; } |
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strm_id: coverpoint cov_stream_id { option.weight =1; } |
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strw: coverpoint cov_xact.smmu_stream_world iff(cov_xact.bypass ==0) { option.weight =1; } |
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sub_strm_id: coverpoint cov_xact.substream_id { option.weight =1; } |
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sup_pri: coverpoint cov_xact.support_ats_pri_msgs iff(cov_xact.is_con_rsp()) { option.weight =1; } |
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tbi: coverpoint cov_xact.tbi iff(!cov_xact.bypass){ option.weight =1; } |
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fault_type : coverpoint cov_xact.fault_type iff(cov_xact.is_trl()){ option.weight =1; } |
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fault_type_v1 : coverpoint cov_xact.fault_type iff((cov_xact.is_trl()) && ((port_cfg.dti_version== svt_dti_port_configuration::DTI1_0))){ bins fault_type_e_NON_ABORT_v1 = {svt_dti_transaction::NON_ABORT}; bins fault_type_e_ABORT_v1 = {svt_dti_transaction::ABORT}; bins fault_type_e_STREAM_DISABLED_v1 = {svt_dti_transaction::STREAM_DISABLED}; bins fault_type_e_GLOBAL_DISABLED_v1 = {svt_dti_transaction::GLOBAL_DISABLED}; illegal_bins fault_type_e_reserv_v1 = default; option.weight =1; } |
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fault_type_v2 : coverpoint cov_xact.fault_type iff((cov_xact.is_trl()) && ((port_cfg.dti_version== svt_dti_port_configuration::DTI2_0))){ bins fault_type_e_NON_ABORT_v2 = {svt_dti_transaction::NON_ABORT}; bins fault_type_e_ABORT_v2 = {svt_dti_transaction::ABORT}; bins fault_type_e_STREAM_DISABLED_v2 = {svt_dti_transaction::STREAM_DISABLED}; bins fault_type_e_GLOBAL_DISABLED_v2 = {svt_dti_transaction::GLOBAL_DISABLED}; bins fault_type_e_TRANSLATION_PRI_v2 = {svt_dti_transaction::TRANSLATION_PRI}; bins fault_type_e_TRANSLATION_STALL_v2 = {svt_dti_transaction::TRANSLATION_STALL}; illegal_bins fault_type_e_reserv_v2 = default; option.weight =1; } |
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if(signal_enable) begin group_name = new(); group_name.set_inst_name($sformatf("%0s_%0s", port_cfg.inst, SVT_DATA_UTIL_ARG_TO_STRING(group_name))); end | |
Macro to create cross covergroup instances
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trans_resp_asid: coverpoint cov_xact.asid iff(!cov_xact.bypass && cov_xact.smmu_stream_world != svt_dti_transaction::EXCEPTION_LEVEL_1_S2) { option.weight =1; } |
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trans_resp_ns: coverpoint cov_xact.non_secure_access{ option.weight =1; } |
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trans_attr: coverpoint cov_xact.translation_attributes iff(!cov_xact.bypass){ option.weight =1; } |
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trans_id: coverpoint cov_xact.id iff(cov_xact.is_trl()) { bins ids[16] = {['h0:'hFF]}; option.weight =1; } |
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trans_id_v1: coverpoint cov_xact.id iff((cov_xact.is_trl()) && (port_cfg.dti_version== svt_dti_port_configuration::DTI1_0)) { bins ids_v1[16] = {['h0:'hFF]}; illegal_bins ids_100_to_FFF_reserv_v1 = {['h100:'hFFF]}; option.weight =1; } |
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trans_id_v2: coverpoint cov_xact.id iff((cov_xact.is_trl()) && (port_cfg.dti_version== svt_dti_port_configuration::DTI2_0)) { bins ids_v2[16] = {['h0:'hFFF]}; option.weight =1; } |
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trans_rng_bypass_0: coverpoint cov_xact.translation_address_range iff(!cov_xact.bypass){ `ifdef SVT_DTI_COV_VERSION_DTI3_0 illegal_bins trans_rng_bypass_0_reserved_val_f = {'h9,['hC:'hF]}; `elsif SVT_DTI_COV_VERSION_DTI2_0 illegal_bins trans_rng_bypass_0_reserved_val_e_b = {['h9:'hF]}; `else illegal_bins trans_rng_bypass_0_reserved_val = {['hA:'hF]}; `endif option.weight =1; } |
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trans_rng_bypass_1: coverpoint cov_xact.translation_address_range iff(cov_xact.bypass){ option.weight =1; `ifdef SVT_DTI_COV_VERSION_DTI3_0 illegal_bins trans_rng_bypass_1_reserved_val = {'h9, ['hC:'hE]}; `else illegal_bins trans_rng_bypass_1_reserved_val = {['h7:'hF]}; `endif } |
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atst: coverpoint cov_xact.ats_translated { option.weight =1; } |
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trans_req_addr: coverpoint cov_xact.addr { option.weight =1; } |
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trans_resp_addr: coverpoint cov_xact.addr[51:12] iff(!cov_xact.bypass) { option.weight =1; } |
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sh: coverpoint cov_xact.shareability iff(!cov_xact.bypass) { option.weight =1; illegal_bins reserved_sh = {2'b01}; } |
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token_granted: coverpoint cov_xact.token_translation iff(cov_xact.connected_state && cov_xact.is_con_rsp()) { bins token_gnt_00 = {'h0} iff(num_tokens_requested >= 'h0); bins token_gnt_01_to_03 = {['h01:'h03]} iff(num_tokens_requested >= 'h01); bins token_gnt_04_to_07 = {['h04:'h07]} iff(num_tokens_requested >= 'h04); bins token_gnt_08_to_0B = {['h08:'h0B]} iff(num_tokens_requested >= 'h08); bins token_gnt_0C_to_0F = {['h0C:'h0F]} iff(num_tokens_requested >= 'h0C); bins token_gnt_10_to_13 = {['h10:'h13]} iff(num_tokens_requested >= 'h10); bins token_gnt_14_to_17 = {['h14:'h17]} iff(num_tokens_requested >= 'h14); bins token_gnt_18_to_1B = {['h18:'h1B]} iff(num_tokens_requested >= 'h18); bins token_gnt_1C_to_1F = {['h1c:'h1F]} iff(num_tokens_requested >= 'h1C); bins token_gnt_20_to_23 = {['h20:'h23]} iff(num_tokens_requested >= 'h20); bins token_gnt_24_to_27 = {['h24:'h27]} iff(num_tokens_requested >= 'h24); bins token_gnt_28_to_2B = {['h28:'h2B]} iff(num_tokens_requested >= 'h28); bins token_gnt_2C_to_2F = {['h2C:'h2F]} iff(num_tokens_requested >= 'h2C); bins token_gnt_30_to_33 = {['h30:'h33]} iff(num_tokens_requested >= 'h30); bins token_gnt_34_to_37 = {['h34:'h37]} iff(num_tokens_requested >= 'h34); bins token_gnt_38_to_3B = {['h38:'h3B]} iff(num_tokens_requested >= 'h38); bins token_gnt_3C_to_3F = {['h3C:'h3F]} iff(num_tokens_requested >= 'h3C); bins token_gnt_40_to_43 = {['h40:'h43]} iff(num_tokens_requested >= 'h40); bins token_gnt_44_to_47 = {['h44:'h47]} iff(num_tokens_requested >= 'h44); bins token_gnt_48_to_4B = {['h48:'h4B]} iff(num_tokens_requested >= 'h48); bins token_gnt_4C_to_4F = {['h4C:'h4F]} iff(num_tokens_requested >= 'h4C); bins token_gnt_50_to_53 = {['h50:'h53]} iff(num_tokens_requested >= 'h50); bins token_gnt_54_to_57 = {['h54:'h57]} iff(num_tokens_requested >= 'h54); bins token_gnt_58_to_5B = {['h58:'h5B]} iff(num_tokens_requested >= 'h58); bins token_gnt_5C_to_5F = {['h5C:'h5F]} iff(num_tokens_requested >= 'h5C); bins token_gnt_60_to_63 = {['h60:'h63]} iff(num_tokens_requested >= 'h60); bins token_gnt_64_to_67 = {['h64:'h67]} iff(num_tokens_requested >= 'h64); bins token_gnt_68_to_6B = {['h68:'h6B]} iff(num_tokens_requested >= 'h68); bins token_gnt_6C_to_6F = {['h6C:'h6F]} iff(num_tokens_requested >= 'h6C); bins token_gnt_70_to_73 = {['h70:'h73]} iff(num_tokens_requested >= 'h70); bins token_gnt_74_to_77 = {['h74:'h77]} iff(num_tokens_requested >= 'h74); bins token_gnt_78_to_7B = {['h78:'h7B]} iff(num_tokens_requested >= 'h78); bins token_gnt_7C_to_7F = {['h7C:'h7F]} iff(num_tokens_requested >= 'h7C); bins token_gnt_80_to_83 = {['h80:'h83]} iff(num_tokens_requested >= 'h80); bins token_gnt_84_to_87 = {['h84:'h87]} iff(num_tokens_requested >= 'h84); bins token_gnt_88_to_8B = {['h88:'h8B]} iff(num_tokens_requested >= 'h88); bins token_gnt_8C_to_8F = {['h8C:'h8F]} iff(num_tokens_requested >= 'h8C); bins token_gnt_90_to_93 = {['h90:'h93]} iff(num_tokens_requested >= 'h90); bins token_gnt_94_to_97 = {['h94:'h97]} iff(num_tokens_requested >= 'h94); bins token_gnt_98_to_9B = {['h98:'h9B]} iff(num_tokens_requested >= 'h98); bins token_gnt_9C_to_9F = {['h9C:'h9F]} iff(num_tokens_requested >= 'h9C); bins token_gnt_A0_to_A3 = {['hA0:'hA3]} iff(num_tokens_requested >= 'hA0); bins token_gnt_A4_to_A7 = {['hA4:'hA7]} iff(num_tokens_requested >= 'hA4); bins token_gnt_A8_to_AB = {['hA8:'hAB]} iff(num_tokens_requested >= 'hA8); bins token_gnt_AC_to_AF = {['hAC:'hAF]} iff(num_tokens_requested >= 'hAC); bins token_gnt_B0_to_B3 = {['hB0:'hB3]} iff(num_tokens_requested >= 'hB0); bins token_gnt_B4_to_B7 = {['hB4:'hB7]} iff(num_tokens_requested >= 'hB4); bins token_gnt_B8_to_BB = {['hB8:'hBB]} iff(num_tokens_requested >= 'hB8); bins token_gnt_BC_to_BF = {['hBC:'hBF]} iff(num_tokens_requested >= 'hBC); bins token_gnt_C0_to_C3 = {['hC0:'hC3]} iff(num_tokens_requested >= 'hC0); bins token_gnt_C4_to_C7 = {['hC4:'hC7]} iff(num_tokens_requested >= 'hC4); bins token_gnt_C8_to_CB = {['hC8:'hCB]} iff(num_tokens_requested >= 'hC8); bins token_gnt_CC_to_CF = {['hCC:'hCF]} iff(num_tokens_requested >= 'hCC); bins token_gnt_D0_to_D3 = {['hD0:'hD3]} iff(num_tokens_requested >= 'hD0); bins token_gnt_D4_to_D7 = {['hD4:'hD7]} iff(num_tokens_requested >= 'hD4); bins token_gnt_D8_to_DB = {['hD8:'hDB]} iff(num_tokens_requested >= 'hD8); bins token_gnt_DC_to_DF = {['hDC:'hDF]} iff(num_tokens_requested >= 'hDC); bins token_gnt_E0_to_E3 = {['hE0:'hE3]} iff(num_tokens_requested >= 'hE0); bins token_gnt_E4_to_E7 = {['hE4:'hE7]} iff(num_tokens_requested >= 'hE4); bins token_gnt_E8_to_EB = {['hE8:'hEB]} iff(num_tokens_requested >= 'hE8); bins token_gnt_EC_to_EF = {['hEC:'hEF]} iff(num_tokens_requested >= 'hEC); bins token_gnt_F0_to_F3 = {['hF0:'hF3]} iff(num_tokens_requested >= 'hF0); bins token_gnt_F4_to_F7 = {['hF4:'hF7]} iff(num_tokens_requested >= 'hF4); bins token_gnt_F8_to_FB = {['hF8:'hFB]} iff(num_tokens_requested >= 'hF8); bins token_gnt_FC_to_FE = {['hFC:'hFE]} iff(num_tokens_requested >= 'hFC); bins token_gnt_FF = {'hFF} iff(num_tokens_requested == 'hFF); option.weight =1; } |
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token_granted_v1: coverpoint cov_xact.token_translation iff((cov_xact.connected_state && cov_xact.is_con_rsp()) && (port_cfg.dti_version== svt_dti_port_configuration::DTI1_0)) { bins token_gnt_000_v1 = {'h0} iff(num_tokens_requested >= 'h0); bins token_gnt_001_to_003_v1 = {['h001:'h003]} iff(num_tokens_requested >= 'h01); bins token_gnt_004_to_007_v1 = {['h004:'h007]} iff(num_tokens_requested >= 'h04); bins token_gnt_008_to_00B_v1 = {['h008:'h00B]} iff(num_tokens_requested >= 'h08); bins token_gnt_00C_to_00F_v1 = {['h00C:'h00F]} iff(num_tokens_requested >= 'h0C); bins token_gnt_010_to_013_v1 = {['h010:'h013]} iff(num_tokens_requested >= 'h10); bins token_gnt_014_to_017_v1 = {['h014:'h017]} iff(num_tokens_requested >= 'h14); bins token_gnt_018_to_01B_v1 = {['h018:'h01B]} iff(num_tokens_requested >= 'h18); bins token_gnt_01C_to_01F_v1 = {['h01c:'h01F]} iff(num_tokens_requested >= 'h1C); bins token_gnt_020_to_023_v1 = {['h020:'h023]} iff(num_tokens_requested >= 'h20); bins token_gnt_024_to_027_v1 = {['h024:'h027]} iff(num_tokens_requested >= 'h24); bins token_gnt_028_to_02B_v1 = {['h028:'h02B]} iff(num_tokens_requested >= 'h28); bins token_gnt_02C_to_02F_v1 = {['h02C:'h02F]} iff(num_tokens_requested >= 'h2C); bins token_gnt_030_to_033_v1 = {['h030:'h033]} iff(num_tokens_requested >= 'h30); bins token_gnt_034_to_037_v1 = {['h034:'h037]} iff(num_tokens_requested >= 'h34); bins token_gnt_038_to_03B_v1 = {['h038:'h03B]} iff(num_tokens_requested >= 'h38); bins token_gnt_03C_to_03F_v1 = {['h03C:'h03F]} iff(num_tokens_requested >= 'h3C); bins token_gnt_040_to_043_v1 = {['h040:'h043]} iff(num_tokens_requested >= 'h40); bins token_gnt_044_to_047_v1 = {['h044:'h047]} iff(num_tokens_requested >= 'h44); bins token_gnt_048_to_04B_v1 = {['h048:'h04B]} iff(num_tokens_requested >= 'h48); bins token_gnt_04C_to_04F_v1 = {['h04C:'h04F]} iff(num_tokens_requested >= 'h4C); bins token_gnt_050_to_053_v1 = {['h050:'h053]} iff(num_tokens_requested >= 'h50); bins token_gnt_054_to_057_v1 = {['h054:'h057]} iff(num_tokens_requested >= 'h54); bins token_gnt_058_to_05B_v1 = {['h058:'h05B]} iff(num_tokens_requested >= 'h58); bins token_gnt_05C_to_05F_v1 = {['h05C:'h05F]} iff(num_tokens_requested >= 'h5C); bins token_gnt_060_to_063_v1 = {['h060:'h063]} iff(num_tokens_requested >= 'h60); bins token_gnt_064_to_067_v1 = {['h064:'h067]} iff(num_tokens_requested >= 'h64); bins token_gnt_068_to_06B_v1 = {['h068:'h06B]} iff(num_tokens_requested >= 'h68); bins token_gnt_06C_to_06F_v1 = {['h06C:'h06F]} iff(num_tokens_requested >= 'h6C); bins token_gnt_070_to_073_v1 = {['h070:'h073]} iff(num_tokens_requested >= 'h70); bins token_gnt_074_to_077_v1 = {['h074:'h077]} iff(num_tokens_requested >= 'h74); bins token_gnt_078_to_07B_v1 = {['h078:'h07B]} iff(num_tokens_requested >= 'h78); bins token_gnt_07C_to_07F_v1 = {['h07C:'h07F]} iff(num_tokens_requested >= 'h7C); bins token_gnt_080_to_083_v1 = {['h080:'h083]} iff(num_tokens_requested >= 'h80); bins token_gnt_084_to_087_v1 = {['h084:'h087]} iff(num_tokens_requested >= 'h84); bins token_gnt_088_to_08B_v1 = {['h088:'h08B]} iff(num_tokens_requested >= 'h88); bins token_gnt_08C_to_08F_v1 = {['h08C:'h08F]} iff(num_tokens_requested >= 'h8C); bins token_gnt_090_to_093_v1 = {['h090:'h093]} iff(num_tokens_requested >= 'h90); bins token_gnt_094_to_097_v1 = {['h094:'h097]} iff(num_tokens_requested >= 'h94); bins token_gnt_098_to_09B_v1 = {['h098:'h09B]} iff(num_tokens_requested >= 'h98); bins token_gnt_09C_to_09F_v1 = {['h09C:'h09F]} iff(num_tokens_requested >= 'h9C); bins token_gnt_0A0_to_0A3_v1 = {['h0A0:'h0A3]} iff(num_tokens_requested >= 'hA0); bins token_gnt_0A4_to_0A7_v1 = {['h0A4:'h0A7]} iff(num_tokens_requested >= 'hA4); bins token_gnt_0A8_to_0AB_v1 = {['h0A8:'h0AB]} iff(num_tokens_requested >= 'hA8); bins token_gnt_0AC_to_0AF_v1 = {['h0AC:'h0AF]} iff(num_tokens_requested >= 'hAC); bins token_gnt_0B0_to_0B3_v1 = {['h0B0:'h0B3]} iff(num_tokens_requested >= 'hB0); bins token_gnt_0B4_to_0B7_v1 = {['h0B4:'h0B7]} iff(num_tokens_requested >= 'hB4); bins token_gnt_0B8_to_0BB_v1 = {['h0B8:'h0BB]} iff(num_tokens_requested >= 'hB8); bins token_gnt_0BC_to_0BF_v1 = {['h0BC:'h0BF]} iff(num_tokens_requested >= 'hBC); bins token_gnt_0C0_to_0C3_v1 = {['h0C0:'h0C3]} iff(num_tokens_requested >= 'hC0); bins token_gnt_0C4_to_0C7_v1 = {['h0C4:'h0C7]} iff(num_tokens_requested >= 'hC4); bins token_gnt_0C8_to_0CB_v1 = {['h0C8:'h0CB]} iff(num_tokens_requested >= 'hC8); bins token_gnt_0CC_to_0CF_v1 = {['h0CC:'h0CF]} iff(num_tokens_requested >= 'hCC); bins token_gnt_0D0_to_0D3_v1 = {['h0D0:'h0D3]} iff(num_tokens_requested >= 'hD0); bins token_gnt_0D4_to_0D7_v1 = {['h0D4:'h0D7]} iff(num_tokens_requested >= 'hD4); bins token_gnt_0D8_to_0DB_v1 = {['h0D8:'h0DB]} iff(num_tokens_requested >= 'hD8); bins token_gnt_0DC_to_0DF_v1 = {['h0DC:'h0DF]} iff(num_tokens_requested >= 'hDC); bins token_gnt_0E0_to_0E3_v1 = {['h0E0:'h0E3]} iff(num_tokens_requested >= 'hE0); bins token_gnt_0E4_to_0E7_v1 = {['h0E4:'h0E7]} iff(num_tokens_requested >= 'hE4); bins token_gnt_0E8_to_0EB_v1 = {['h0E8:'h0EB]} iff(num_tokens_requested >= 'hE8); bins token_gnt_0EC_to_0EF_v1 = {['h0EC:'h0EF]} iff(num_tokens_requested >= 'hEC); bins token_gnt_0F0_to_0F3_v1 = {['h0F0:'h0F3]} iff(num_tokens_requested >= 'hF0); bins token_gnt_0F4_to_0F7_v1 = {['h0F4:'h0F7]} iff(num_tokens_requested >= 'hF4); bins token_gnt_0F8_to_0FB_v1 = {['h0F8:'h0FB]} iff(num_tokens_requested >= 'hF8); bins token_gnt_0FC_to_0FE_v1 = {['h0FC:'h0FE]} iff(num_tokens_requested >= 'hFC); bins token_gnt_0FF_v1 = {'h0FF} iff(num_tokens_requested == 'hFF); illegal_bins token_gnt_100_to_FFF_v1 = {['h100:'hFFF]}; option.weight =1; } |
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token_granted_v2: coverpoint cov_xact.token_translation iff((cov_xact.connected_state && cov_xact.is_con_rsp()) && (port_cfg.dti_version== svt_dti_port_configuration::DTI2_0)) { bins token_gnt_000_v2 = {'h0} iff(num_tokens_requested >= 'h0); bins token_gnt_001_to_003_v2 = {['h001:'h003]} iff(num_tokens_requested >= 'h01); bins token_gnt_004_to_007_v2 = {['h004:'h007]} iff(num_tokens_requested >= 'h04); bins token_gnt_008_to_00B_v2 = {['h008:'h00B]} iff(num_tokens_requested >= 'h08); bins token_gnt_00C_to_00F_v2 = {['h00C:'h00F]} iff(num_tokens_requested >= 'h0C); bins token_gnt_010_to_013_v2 = {['h010:'h013]} iff(num_tokens_requested >= 'h10); bins token_gnt_014_to_017_v2 = {['h014:'h017]} iff(num_tokens_requested >= 'h14); bins token_gnt_018_to_01B_v2 = {['h018:'h01B]} iff(num_tokens_requested >= 'h18); bins token_gnt_01C_to_01F_v2 = {['h01c:'h01F]} iff(num_tokens_requested >= 'h1C); bins token_gnt_020_to_023_v2 = {['h020:'h023]} iff(num_tokens_requested >= 'h20); bins token_gnt_024_to_027_v2 = {['h024:'h027]} iff(num_tokens_requested >= 'h24); bins token_gnt_028_to_02B_v2 = {['h028:'h02B]} iff(num_tokens_requested >= 'h28); bins token_gnt_02C_to_02F_v2 = {['h02C:'h02F]} iff(num_tokens_requested >= 'h2C); bins token_gnt_030_to_033_v2 = {['h030:'h033]} iff(num_tokens_requested >= 'h30); bins token_gnt_034_to_037_v2 = {['h034:'h037]} iff(num_tokens_requested >= 'h34); bins token_gnt_038_to_03B_v2 = {['h038:'h03B]} iff(num_tokens_requested >= 'h38); bins token_gnt_03C_to_03F_v2 = {['h03C:'h03F]} iff(num_tokens_requested >= 'h3C); bins token_gnt_040_to_043_v2 = {['h040:'h043]} iff(num_tokens_requested >= 'h40); bins token_gnt_044_to_047_v2 = {['h044:'h047]} iff(num_tokens_requested >= 'h44); bins token_gnt_048_to_04B_v2 = {['h048:'h04B]} iff(num_tokens_requested >= 'h48); bins token_gnt_04C_to_04F_v2 = {['h04C:'h04F]} iff(num_tokens_requested >= 'h4C); bins token_gnt_050_to_053_v2 = {['h050:'h053]} iff(num_tokens_requested >= 'h50); bins token_gnt_054_to_057_v2 = {['h054:'h057]} iff(num_tokens_requested >= 'h54); bins token_gnt_058_to_05B_v2 = {['h058:'h05B]} iff(num_tokens_requested >= 'h58); bins token_gnt_05C_to_05F_v2 = {['h05C:'h05F]} iff(num_tokens_requested >= 'h5C); bins token_gnt_060_to_063_v2 = {['h060:'h063]} iff(num_tokens_requested >= 'h60); bins token_gnt_064_to_067_v2 = {['h064:'h067]} iff(num_tokens_requested >= 'h64); bins token_gnt_068_to_06B_v2 = {['h068:'h06B]} iff(num_tokens_requested >= 'h68); bins token_gnt_06C_to_06F_v2 = {['h06C:'h06F]} iff(num_tokens_requested >= 'h6C); bins token_gnt_070_to_073_v2 = {['h070:'h073]} iff(num_tokens_requested >= 'h70); bins token_gnt_074_to_077_v2 = {['h074:'h077]} iff(num_tokens_requested >= 'h74); bins token_gnt_078_to_07B_v2 = {['h078:'h07B]} iff(num_tokens_requested >= 'h78); bins token_gnt_07C_to_07F_v2 = {['h07C:'h07F]} iff(num_tokens_requested >= 'h7C); bins token_gnt_080_to_083_v2 = {['h080:'h083]} iff(num_tokens_requested >= 'h80); bins token_gnt_084_to_087_v2 = {['h084:'h087]} iff(num_tokens_requested >= 'h84); bins token_gnt_088_to_08B_v2 = {['h088:'h08B]} iff(num_tokens_requested >= 'h88); bins token_gnt_08C_to_08F_v2 = {['h08C:'h08F]} iff(num_tokens_requested >= 'h8C); bins token_gnt_090_to_093_v2 = {['h090:'h093]} iff(num_tokens_requested >= 'h90); bins token_gnt_094_to_097_v2 = {['h094:'h097]} iff(num_tokens_requested >= 'h94); bins token_gnt_098_to_09B_v2 = {['h098:'h09B]} iff(num_tokens_requested >= 'h98); bins token_gnt_09C_to_09F_v2 = {['h09C:'h09F]} iff(num_tokens_requested >= 'h9C); bins token_gnt_0A0_to_0A3_v2 = {['h0A0:'h0A3]} iff(num_tokens_requested >= 'hA0); bins token_gnt_0A4_to_0A7_v2 = {['h0A4:'h0A7]} iff(num_tokens_requested >= 'hA4); bins token_gnt_0A8_to_0AB_v2 = {['h0A8:'h0AB]} iff(num_tokens_requested >= 'hA8); bins token_gnt_0AC_to_0AF_v2 = {['h0AC:'h0AF]} iff(num_tokens_requested >= 'hAC); bins token_gnt_0B0_to_0B3_v2 = {['h0B0:'h0B3]} iff(num_tokens_requested >= 'hB0); bins token_gnt_0B4_to_0B7_v2 = {['h0B4:'h0B7]} iff(num_tokens_requested >= 'hB4); bins token_gnt_0B8_to_0BB_v2 = {['h0B8:'h0BB]} iff(num_tokens_requested >= 'hB8); bins token_gnt_0BC_to_0BF_v2 = {['h0BC:'h0BF]} iff(num_tokens_requested >= 'hBC); bins token_gnt_0C0_to_0C3_v2 = {['h0C0:'h0C3]} iff(num_tokens_requested >= 'hC0); bins token_gnt_0C4_to_0C7_v2 = {['h0C4:'h0C7]} iff(num_tokens_requested >= 'hC4); bins token_gnt_0C8_to_0CB_v2 = {['h0C8:'h0CB]} iff(num_tokens_requested >= 'hC8); bins token_gnt_0CC_to_0CF_v2 = {['h0CC:'h0CF]} iff(num_tokens_requested >= 'hCC); bins token_gnt_0D0_to_0D3_v2 = {['h0D0:'h0D3]} iff(num_tokens_requested >= 'hD0); bins token_gnt_0D4_to_0D7_v2 = {['h0D4:'h0D7]} iff(num_tokens_requested >= 'hD4); bins token_gnt_0D8_to_0DB_v2 = {['h0D8:'h0DB]} iff(num_tokens_requested >= 'hD8); bins token_gnt_0DC_to_0DF_v2 = {['h0DC:'h0DF]} iff(num_tokens_requested >= 'hDC); bins token_gnt_0E0_to_0E3_v2 = {['h0E0:'h0E3]} iff(num_tokens_requested >= 'hE0); bins token_gnt_0E4_to_0E7_v2 = {['h0E4:'h0E7]} iff(num_tokens_requested >= 'hE4); bins token_gnt_0E8_to_0EB_v2 = {['h0E8:'h0EB]} iff(num_tokens_requested >= 'hE8); bins token_gnt_0EC_to_0EF_v2 = {['h0EC:'h0EF]} iff(num_tokens_requested >= 'hEC); bins token_gnt_0F0_to_0F3_v2 = {['h0F0:'h0F3]} iff(num_tokens_requested >= 'hF0); bins token_gnt_0F4_to_0F7_v2 = {['h0F4:'h0F7]} iff(num_tokens_requested >= 'hF4); bins token_gnt_0F8_to_0FB_v2 = {['h0F8:'h0FB]} iff(num_tokens_requested >= 'hF8); bins token_gnt_0FC_to_0FE_v2 = {['h0FC:'h0FE]} iff(num_tokens_requested >= 'hFC); bins token_gnt_0FF_v2 = {'h0FF} iff(num_tokens_requested == 'hFF); bins token_100_to_1FF_v2 = {['h100:'h1FF]} iff(num_tokens_requested >= 'h100); bins token_200_to_2FF_v2 = {['h200:'h2FF]} iff(num_tokens_requested >= 'h200); bins token_300_to_3FF_v2 = {['h300:'h3FF]} iff(num_tokens_requested >= 'h300); bins token_400_to_4FF_v2 = {['h400:'h4FF]} iff(num_tokens_requested >= 'h400); bins token_500_to_5FF_v2 = {['h500:'h5FF]} iff(num_tokens_requested >= 'h500); bins token_600_to_6FF_v2 = {['h600:'h6FF]} iff(num_tokens_requested >= 'h600); bins token_700_to_7FF_v2 = {['h700:'h7FF]} iff(num_tokens_requested >= 'h700); bins token_800_to_8FF_v2 = {['h800:'h8FF]} iff(num_tokens_requested >= 'h800); bins token_900_to_9FF_v2 = {['h900:'h9FF]} iff(num_tokens_requested >= 'h900); bins token_A00_to_AFF_v2 = {['hA00:'hAFF]} iff(num_tokens_requested >= 'hA00); bins token_B00_to_BFF_v2 = {['hB00:'hBFF]} iff(num_tokens_requested >= 'hB00); bins token_C00_to_CFF_v2 = {['hC00:'hCFF]} iff(num_tokens_requested >= 'hC00); bins token_D00_to_DFF_v2 = {['hD00:'hDFF]} iff(num_tokens_requested >= 'hD00); bins token_E00_to_EFF_v2 = {['hE00:'hEFF]} iff(num_tokens_requested >= 'hE00); bins token_F00_to_FFE_v2 = {['hF00:'hFFE]} iff(num_tokens_requested >= 'hF00); bins token_FFF_v2 = {'hFFF} iff(num_tokens_requested == 'hFFF); option.weight =1; } |
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token_requested: coverpoint translation_token_requested iff(cov_xact.connected_state ) { bins token_00 = {'h0}; bins token_01_to_0F = {['h01:'h0F]}; bins token_10_to_1F = {['h10:'h1F]}; bins token_20_to_2F = {['h20:'h2F]}; bins token_30_to_3F = {['h30:'h3F]}; bins token_40_to_4F = {['h40:'h4F]}; bins token_50_to_5F = {['h50:'h5F]}; bins token_60_to_6F = {['h60:'h6F]}; bins token_70_to_7F = {['h70:'h7F]}; bins token_80_to_8F = {['h80:'h8F]}; bins token_90_to_9F = {['h90:'h9F]}; bins token_A0_to_AF = {['hA0:'hAF]}; bins token_B0_to_BF = {['hB0:'hBF]}; bins token_C0_to_CF = {['hC0:'hCF]}; bins token_D0_to_DF = {['hD0:'hDF]}; bins token_E0_to_EF = {['hE0:'hEF]}; bins token_F0_to_FE = {['hF0:'hFE]}; bins token_FF = {'hFF}; ignore_bins token_ignore = {['h100:$]}; option.weight =1; } |
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token_requested_v1: coverpoint translation_token_requested iff((cov_xact.connected_state) && (port_cfg.dti_version== svt_dti_port_configuration::DTI1_0)) { bins token_000_v1 = {'h0}; bins token_001_to_00F_v1 = {['h001:'h00F]}; bins token_010_to_01F_v1 = {['h010:'h01F]}; bins token_020_to_02F_v1 = {['h020:'h02F]}; bins token_030_to_03F_v1 = {['h030:'h03F]}; bins token_040_to_04F_v1 = {['h040:'h04F]}; bins token_050_to_05F_v1 = {['h050:'h05F]}; bins token_060_to_06F_v1 = {['h060:'h06F]}; bins token_070_to_07F_v1 = {['h070:'h07F]}; bins token_080_to_08F_v1 = {['h080:'h08F]}; bins token_090_to_09F_v1 = {['h090:'h09F]}; bins token_0A0_to_0AF_v1 = {['h0A0:'h0AF]}; bins token_0B0_to_0BF_v1 = {['h0B0:'h0BF]}; bins token_0C0_to_0CF_v1 = {['h0C0:'h0CF]}; bins token_0D0_to_0DF_v1 = {['h0D0:'h0DF]}; bins token_0E0_to_0EF_v1 = {['h0E0:'h0EF]}; bins token_0F0_to_0FE_v1 = {['h0F0:'h0FE]}; bins token_0FF_v1 = {'h0FF}; illegal_bins token_100_to_FFF_v1 = {['h100:'hFFF]}; option.weight =1; } |
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token_requested_v2: coverpoint translation_token_requested iff((cov_xact.connected_state) && (port_cfg.dti_version== svt_dti_port_configuration::DTI2_0)) { bins token_000_v2 = {'h0}; bins token_001_to_00F_v2 = {['h001:'h00F]}; bins token_010_to_01F_v2 = {['h010:'h01F]}; bins token_020_to_02F_v2 = {['h020:'h02F]}; bins token_030_to_03F_v2 = {['h030:'h03F]}; bins token_040_to_04F_v2 = {['h040:'h04F]}; bins token_050_to_05F_v2 = {['h050:'h05F]}; bins token_060_to_06F_v2 = {['h060:'h06F]}; bins token_070_to_07F_v2 = {['h070:'h07F]}; bins token_080_to_08F_v2 = {['h080:'h08F]}; bins token_090_to_09F_v2 = {['h090:'h09F]}; bins token_0A0_to_0AF_v2 = {['h0A0:'h0AF]}; bins token_0B0_to_0BF_v2 = {['h0B0:'h0BF]}; bins token_0C0_to_0CF_v2 = {['h0C0:'h0CF]}; bins token_0D0_to_0DF_v2 = {['h0D0:'h0DF]}; bins token_0E0_to_0EF_v2 = {['h0E0:'h0EF]}; bins token_0F0_to_0FE_v2 = {['h0F0:'h0FE]}; bins token_0FF_v2 = {'h0FF}; bins token_100_to_1FF_v2 = {['h100:'h1FF]}; bins token_200_to_2FF_v2 = {['h200:'h2FF]}; bins token_300_to_3FF_v2 = {['h300:'h3FF]}; bins token_400_to_4FF_v2 = {['h400:'h4FF]}; bins token_500_to_5FF_v2 = {['h500:'h5FF]}; bins token_600_to_6FF_v2 = {['h600:'h6FF]}; bins token_700_to_7FF_v2 = {['h700:'h7FF]}; bins token_800_to_8FF_v2 = {['h800:'h8FF]}; bins token_900_to_9FF_v2 = {['h900:'h9FF]}; bins token_A00_to_AFF_v2 = {['hA00:'hAFF]}; bins token_B00_to_BFF_v2 = {['hB00:'hBFF]}; bins token_C00_to_CFF_v2 = {['hC00:'hCFF]}; bins token_D00_to_DFF_v2 = {['hD00:'hDFF]}; bins token_E00_to_EFF_v2 = {['hE00:'hEFF]}; bins token_F00_to_FFE_v2 = {['hF00:'hFFE]}; bins token_FFF_v2 = {'hFFF} ; option.weight =1; } |
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val_sub_strm: coverpoint cov_valid_substream { option.weight =1; } |
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version_ack: coverpoint cov_xact.protocol_version { `ifdef SVT_DTI_COV_VERSION_DTI3_0 bins version_ack_e_b_v1 = {'h0}; bins version_ack_e_b_v2 = {'h1}; bins version_ack_f_b_v3 = {'h2}; ignore_bins version_req_f_b_reserv = {['h3:'hF]}; `elsif SVT_DTI_COV_VERSION_DTI2_0 bins version_ack_e_b_v1 = {'h0}; bins version_ack_e_b_v2 = {'h1}; ignore_bins version_req_e_b_reserv = {['h2:'hF]}; `else bins version_ack = {'h0}; ignore_bins version_ack_reserv = {['h1:'hF]}; `endif option.weight =1; } |
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version_req: coverpoint cov_xact.protocol_version { `ifdef SVT_DTI_COV_VERSION_DTI3_0 bins version_req_e_b_v1 = {'h0}; bins version_req_e_b_v2 = {'h1}; bins version_req_f_b_v3 = {'h2}; ignore_bins version_req_f_b_reserv = {['h3:'hF]}; `elsif SVT_DTI_COV_VERSION_DTI2_0 bins version_req_e_b_v1 = {'h0}; bins version_req_e_b_v2 = {'h1}; ignore_bins version_req_e_b_reserv = {['h2:'hF]}; `else bins version_req = {'h0}; ignore_bins version_req_reserv = {['h1:'hF]}; `endif option.weight =1; } |
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trans_resp_vmid: coverpoint cov_xact.vmid { option.weight =1; } |
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covergroup trans_cross_asid_with_aset @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANS_RESP_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ASET aset_trans_resp_asid : cross aset, trans_resp_asid { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_asid_with_aset.
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covergroup trans_cross_attr_ovr_with_alloccfg_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOCCFG attr_ovr_alloccfg : cross ovr_attributes_v1, alloccfg{ option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_attr_ovr_with_alloccfg_v1.
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covergroup trans_cross_attr_ovr_with_alloccfg_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOCCFG attr_ovr_alloccfg : cross ovr_attributes_v2, alloccfg{ option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_attr_ovr_with_alloccfg_v2.
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covergroup trans_cross_attr_ovr_with_attr_with_sh_v1 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_ATTRIBUTES SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RESP_SHAREABILITY attr_ovr_attr_sh : cross ovr_attributes_v1, trans_attr, sh { illegal_bins inval_attr_ovr_attr_sh = binsof(sh) intersect{2'b01}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_attr_ovr_with_attr_with_sh_v1.
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covergroup trans_cross_attr_ovr_with_attr_with_sh_v2 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_ATTRIBUTES SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RESP_SHAREABILITY attr_ovr_attr_sh : cross ovr_attributes_v2, trans_attr, sh { illegal_bins inval_attr_ovr_attr_sh = binsof(sh) intersect{2'b01}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_attr_ovr_with_attr_with_sh_v2.
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covergroup trans_cross_bp_type_with_bypass @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_BP_TYPE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_BYPASS bypass_bp_type : cross bypass, bp_type { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_bp_type_with_bypass.
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covergroup trans_cross_condis_req_state_condis_ack_state @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_CONNECTION_REQUESTED SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_CONNECTION_ACCEPTED state_ack_or_deny : cross con_req, con_accept { illegal_bins invalid_state_field = binsof(con_req) intersect {0} && binsof(con_accept) intersect{1}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_condis_req_state_condis_ack_state.
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covergroup trans_cross_fault_type_with_donot_cache @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DONOT_CACHE fault_type_donot_cache : cross fault_type, dont_cache { illegal_bins invalid_fault_type_donot_cache = binsof(fault_type) intersect {svt_dti_transaction::NON_ABORT, svt_dti_transaction::ABORT} && binsof(dont_cache) intersect {0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_fault_type_with_donot_cache.
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covergroup trans_cross_fault_type_with_donot_cache_v1 @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE_V1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DONOT_CACHE fault_type_donot_cache_v1 : cross fault_type_v1, dont_cache { illegal_bins invalid_fault_type_donot_cache_v1 = binsof(fault_type_v1) intersect {svt_dti_transaction::NON_ABORT, svt_dti_transaction::ABORT} && binsof(dont_cache) intersect {0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_fault_type_with_donot_cache_v1.
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covergroup trans_cross_fault_type_with_donot_cache_v2 @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DONOT_CACHE fault_type_donot_cache_v2 : cross fault_type_v2, dont_cache { illegal_bins invalid_fault_type_donot_cache_v2 = binsof(fault_type_v2) intersect {svt_dti_transaction::NON_ABORT, svt_dti_transaction::ABORT} && binsof(dont_cache) intersect {0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_fault_type_with_donot_cache_v2.
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covergroup trans_cross_global_with_asid @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_GLOBAL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANS_RESP_ASID global_asid : cross global_val, trans_resp_asid{ option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_global_with_asid.
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covergroup trans_cross_global_with_shareability @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_GLOBAL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RESP_SHAREABILITY global_sh : cross global_val, sh{ illegal_bins inval_global_sh = binsof(sh) intersect{2'b01}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_global_with_shareability.
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covergroup trans_cross_global_with_smmu_stream_world @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_GLOBAL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STRW global_strw : cross global_val, strw{ illegal_bins inval_global_strw = binsof(strw) intersect{svt_dti_transaction::EXCEPTION_LEVEL_3} && binsof(global_val) intersect{0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_global_with_smmu_stream_world.
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covergroup trans_cross_ind_with_instcfg @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTCFG ind_instcfg : cross inst_data_access, ovr_rd_ind { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_ind_with_instcfg.
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covergroup trans_cross_inst_pnu_with_allow_pr_allow_ur_instcfg_privcfg @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTCFG SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIVCFG SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_PR SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_UR inst_pnu_instcfg_priv_allow_ur_pr : cross inst_data_access, ovr_rd_ind, priv_unpriv_access, ovr_rd_pnu,allow_pr,allow_ur { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_inst_pnu_with_allow_pr_allow_ur_instcfg_privcfg.
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covergroup trans_cross_inst_pnu_with_allow_pw_allow_uw_instcfg_privcfg @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTCFG SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIVCFG SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_PW SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_UW inst_pnu_instcfg_priv_allow_uw_pw : cross inst_data_access, ovr_rd_ind, priv_unpriv_access, ovr_rd_pnu,allow_pw,allow_uw { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_inst_pnu_with_allow_pw_allow_uw_instcfg_privcfg.
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covergroup trans_cross_inst_pnu_with_allow_px_allow_ux_instcfg_privcfg @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTCFG SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIVCFG SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_PX SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_UX inst_pnu_instcfg_priv_allow_ux_px : cross inst_data_access, ovr_rd_ind, priv_unpriv_access, ovr_rd_pnu,allow_px,allow_ux { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_inst_pnu_with_allow_px_allow_ux_instcfg_privcfg.
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covergroup inv_req_cross_op_asid_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_asid_inc_aset1 : cross operation, asid, inc_aset1 { ignore_bins invalid_op_asid_aset1 = !binsof(operation) intersect {8'h88, 8'hE8} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_asid_inc_aset1. cross bins 2x4x2 = 16
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covergroup inv_req_cross_op_asid_vmid_va_ipa_range_inc_aset1_sid_ssid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VA_IPA SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SSID op_asid_vmid_va_ipa_range_inc_aset1_sid_ssid : cross operation, asid, vmid, addr, sid_vmid_range, inc_aset1, stream_id, substream_id { bins CROSS_TLBI_S_EL1_ALL = binsof(operation.TLBI_S_EL1_ALL) && binsof(inc_aset1); option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_asid_vmid_va_ipa_range_inc_aset1_sid_ssid.
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covergroup inv_req_cross_op_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_inc_aset1 : cross operation, inc_aset1 { ignore_bins invalid_op_aset1 = !binsof(operation) intersect {8'h40, 8'h80, 8'hA0, 8'hE0} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_inc_aset1. cross bins 2x2 = 4
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covergroup inv_req_cross_op_sid_range @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE op_sid_range : cross operation, stream_id, sid_vmid_range { ignore_bins invalid_op_sid_range = !binsof(operation) intersect {8'h10, 8'h30} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_sid_range. cross bins 2x4x32 = 256
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covergroup inv_req_cross_op_sid_ssid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SSID op_sid_ssid : cross operation, stream_id, substream_id { ignore_bins invalid_op_sid_ssid = !binsof(operation) intersect {8'h18, 8'h38} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_sid_ssid. cross bins 2x4x4 = 32
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covergroup inv_req_cross_op_va_asid_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VA_IPA SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_va_asid_inc_aset1 : cross operation, addr, asid, inc_aset1 { ignore_bins invalid_op_va_asid_aset1 = !binsof(operation) intersect {8'h89, 8'hE9} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_va_asid_inc_aset1. cross bins 2x8x4x2 = 128
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covergroup inv_req_cross_op_va_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VA_IPA SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_inc_aset1 : cross operation, addr, inc_aset1 { ignore_bins invalid_op_aset1 = !binsof(operation) intersect {8'h41, 8'h81, 8'hE1} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_va_inc_aset1. cross bins 2x8x2 = 32
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covergroup inv_req_cross_op_vmid_asid_range_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_vmid_asid_range_inc_aset1 : cross operation, vmid, asid, sid_vmid_range, inc_aset1 { ignore_bins invalid_op_vmid_asid_range_aset1 = !binsof(operation) intersect {8'hB5} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_vmid_asid_range_inc_aset1. cross bins 1x4x4x32x2=1K
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covergroup inv_req_cross_op_vmid_asid_va_range_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VA_IPA SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_vmid_asid_va_range_inc_aset1 : cross operation, vmid, asid, addr, sid_vmid_range, inc_aset1 { ignore_bins invalid_op_vmid_asid_va_range_aset1 = !binsof(operation) intersect {8'hB5} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_vmid_asid_va_range_inc_aset1. cross bins 1x4x4x8x32x2=8K
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covergroup inv_req_cross_op_vmid_ipa_range_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VA_IPA SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_vmid_ipa_range_inc_aset1 : cross operation, vmid, addr, sid_vmid_range, inc_aset1 { ignore_bins invalid_op_vmid_ipa_range_aset1 = !binsof(operation) intersect {8'hB1} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_vmid_ipa_range_inc_aset1. cross bins 1x4x8x32x2=2K
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covergroup inv_req_cross_op_vmid_range_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_vmid_range_inc_aset1 : cross operation, vmid, sid_vmid_range, inc_aset1 { ignore_bins invalid_op_vmid_range_aset1 = !binsof(operation) intersect {8'hB2, 8'hB0} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_vmid_range_inc_aset1. cross bins 2x4x32x2=512
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covergroup inv_req_cross_op_vmid_va_range_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_OPERATION SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VA_IPA SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 op_vmid_va_range_inc_aset1 : cross operation, vmid, addr, sid_vmid_range, inc_aset1 { ignore_bins invalid_op_vmid_va_range_aset1 = !binsof(operation) intersect {8'hB1} ; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_op_vmid_va_range_inc_aset1. cross bins 1x4x8x32x2=2K
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covergroup inv_req_cross_scale_num_tg_ttl_range @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SCALE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_NUM SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_GRANULE_SIZE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_TABLE_LEVEL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INVALIDATION_RANGE scale_num_tg_ttl_range: cross scale, num, tg, ttl, inval_rng { option.weight = 1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_scale_num_tg_ttl_range.
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covergroup inv_req_cross_scale_num_tg_ttl_range_asid_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SCALE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_NUM SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_GRANULE_SIZE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_TABLE_LEVEL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INVALIDATION_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 scale_num_tg_ttl_range_asid_inc_aset1: cross scale, num, tg, ttl, inval_rng, asid, inc_aset1 { option.weight = 1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_scale_num_tg_ttl_range_asid_inc_aset1.
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covergroup inv_req_cross_scale_num_tg_ttl_range_asid_vmid_inc_aset1 @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SCALE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_NUM SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_GRANULE_SIZE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_TABLE_LEVEL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INVALIDATION_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_ASID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_VMID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_INC_ASET1 scale_num_tg_ttl_range_asid_vmid_inc_aset1: cross scale, num, tg, ttl, inval_rng, asid, vmid, inc_aset1 { option.weight = 1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_scale_num_tg_ttl_range_asid_vmid_inc_aset1.
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covergroup inv_req_cross_scale_num_tg_ttl_sec_sid @(cov_sample_inv_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_SCALE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_NUM SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_GRANULE_SIZE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INV_REQ_TRANSLATION_TABLE_LEVEL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID scale_num_tg_ttl_sec_sid: cross scale, num, tg, ttl, sec_sid { option.weight = 1; } option.per_instance =1; endgroup | |
Macro to create covergroup : inv_req_cross_scale_num_tg_ttl_sec_sid.
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covergroup trans_cross_invalidation_range_with_translation_range_with_bypass_0 @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INVALIDATION_RANGE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RANGE_BYPASS_0 inval_rng_trans_rng : cross inval_rng, trans_rng_bypass_0{ `ifdef SVT_DTI_COV_VERSION_DTI3_0 illegal_bins inval_rng_trans_rng = binsof(trans_rng_bypass_0) intersect{4'b1001, 4'b1100, 4'b1101, 4'b1110, 4'b1111}; `elsif SVT_DTI_COV_VERSION_DTI2_0 illegal_bins inval_rng_trans_rng = binsof(trans_rng_bypass_0) intersect{4'b1001, 4'b1010, 4'b1011, 4'b1100, 4'b1101, 4'b1110, 4'b1111}; `else illegal_bins inval_rng_trans_rng = binsof(trans_rng_bypass_0) intersect{4'b1010, 4'b1011, 4'b1100, 4'b1101, 4'b1110, 4'b1111}; `endif option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_invalidation_range_with_translation_range_with_bypass_0.
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covergroup trans_cross_non_secure_with_override_non_secure @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_NSOVR SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANS_RESP_NS ns_nsovr : cross nsovr, trans_resp_ns { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_non_secure_with_override_non_secure.
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covergroup trans_cross_ns_inst_priv_with_fault_type_donot_cache @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DONOT_CACHE ns_inst_priv_fault_type_donot_cache : cross sec_nsec_access, inst_data_access,priv_unpriv_access,fault_type, dont_cache { illegal_bins invalid_ns_inst_priv_fault_type_donot_cache = binsof(fault_type) intersect {svt_dti_transaction::NON_ABORT, svt_dti_transaction::ABORT} && binsof(dont_cache) intersect {0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_ns_inst_priv_with_fault_type_with_donot_cache.
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covergroup trans_cross_ns_inst_priv_with_fault_type_donot_cache_v1 @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE_V1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DONOT_CACHE ns_inst_priv_fault_type_donot_cache_v1 : cross sec_nsec_access, inst_data_access,priv_unpriv_access,fault_type_v1, dont_cache { illegal_bins invalid_ns_inst_priv_fault_type_donot_cache_v1 = binsof(fault_type_v1) intersect {svt_dti_transaction::NON_ABORT, svt_dti_transaction::ABORT} && binsof(dont_cache) intersect {0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_ns_inst_priv_with_fault_type_with_donot_cache_v1.
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covergroup trans_cross_ns_inst_priv_with_fault_type_donot_cache_v2 @(cov_sample_trans_fault_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TBU_FAULT_TYPE_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DONOT_CACHE ns_inst_priv_fault_type_donot_cache_v2 : cross sec_nsec_access, inst_data_access,priv_unpriv_access,fault_type_v2, dont_cache { illegal_bins invalid_ns_inst_priv_fault_type_donot_cache_v2 = binsof(fault_type_v2) intersect {svt_dti_transaction::NON_ABORT, svt_dti_transaction::ABORT} && binsof(dont_cache) intersect {0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_ns_inst_priv_with_fault_type_with_donot_cache_v2.
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covergroup trans_cross_non_secure_access_with_ind_with_pnu @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS ns_ind_pnu : cross sec_nsec_access, inst_data_access,priv_unpriv_access{ option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_non_secure_access_with_ind_with_pnu.
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covergroup trans_cross_non_secure_access_with_perm_req_with_instruction_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PERMISSIONS_REQUIRED SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_INSTRUCTION_DATA_ACCESS ns_perm_ind : cross sec_nsec_access, permission_req,inst_data_access { illegal_bins invalid_ns_perm_ind = binsof(permission_req) intersect{svt_dti_transaction::WRITE_PERM_REQ, svt_dti_transaction::READ_WRITE_PERM_REQ, svt_dti_transaction::NO_PERM_REQ} && binsof(inst_data_access) intersect{1}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_non_secure_access_with_perm_req_with_instruction_access.
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covergroup trans_cross_non_secure_access_with_perm_req_with_privileged_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PERMISSIONS_REQUIRED SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS ns_perm_pnu : cross sec_nsec_access, permission_req,priv_unpriv_access{ illegal_bins invalid_ns_perm_pnu = binsof(permission_req) intersect{svt_dti_transaction::NO_PERM_REQ} && binsof(priv_unpriv_access) intersect{1}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_non_secure_access_with_perm_req_with_privileged_access.
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covergroup trans_cross_ns_with_strw_with_dre @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANS_RESP_NS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_DESTRUCTIVE_READS_PERMITTED SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STRW ns_dre_stwr : cross trans_resp_ns, dre, strw { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_ns_with_strw_with_dre.
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covergroup page_cross_prg_idx_addr @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_REQUEST_GROUP SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANSLATION_RESP_OUTPUT_ADDR page_cross_prg_idx_addr: cross ats_page_request_group,ats_trans_resp_addr { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : page_cross_prg_idx_addr for DTI_ATS_PAGE_REQ
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covergroup page_cross_prg_idx_addr_last_sid_ssid_ssv @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_REQUEST_GROUP SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_TRANSLATION_RESP_OUTPUT_ADDR SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_LAST SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_SUB_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_VALID_SUBSTREAM page_cross_prg_idx_addr_last_sid_ssid_ssv: cross ats_page_request_group,ats_trans_resp_addr,ats_last,ats_page_req_strm_id,ats_page_req_sub_strm_id,ats_page_req_val_sub_strm { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : page_cross_prg_idx_addr_last_sid_ssid_ssv for DTI_ATS_PAGE_REQ
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covergroup page_cross_prg_idx_resp @(cov_sample_ats_page_rsp_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_REQUEST_GROUP SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_RESP page_cross_prg_idx_resp: cross ats_page_request_group,ats_page_resp { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : page_cross_prg_idx_resp for DTI_ATS_PAGE_RESP
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covergroup page_cross_prg_idx_sid_ssid_ssv @(cov_sample_ats_page_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_REQUEST_GROUP SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_SUB_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_VALID_SUBSTREAM page_cross_prg_idx_sid_ssid_ssv: cross ats_page_request_group,ats_page_req_strm_id,ats_page_req_sub_strm_id,ats_page_req_val_sub_strm { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : page_cross_prg_idx_sid_ssid_ssv for DTI_ATS_PAGE_REQ and DTI_ATS_PAGE_RESP
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covergroup page_cross_write_read_inst_priv @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_WRITE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_READ_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_EXECUTE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_PRIV_ACCESS page_cross_write_read_inst_priv: cross ats_page_write_access,ats_page_read_access,ats_page_execute_access,ats_page_priv_access { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : page_cross_write_read_inst_priv for DTI_ATS_PAGE_REQ
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covergroup page_cross_write_read_last_sid_ssid_ssv @(cov_sample_ats_page_req_msg); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_WRITE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_READ_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_LAST SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_SUB_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATS_PAGE_VALID_SUBSTREAM page_cross_write_read_last_sid_ssid_ssv: cross ats_page_write_access,ats_page_read_access,ats_last,ats_page_req_strm_id,ats_page_req_sub_strm_id,ats_page_req_val_sub_strm { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : page_cross_write_read_last_sid_ssid_ssv for DTI_ATS_PAGE_REQ
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covergroup trans_cross_pnu_with_privcfg @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIV_UNPRIV_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PRIVCFG priv_privcfg : cross priv_unpriv_access, ovr_rd_pnu { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_pnu_with_privcfg.
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covergroup trans_cross_secure_streamid_with_non_secure_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID secsid_ns : cross sec_nsec_access, sec_sid { illegal_bins invalid_secsid_ns = binsof(sec_nsec_access) intersect{0} && binsof(sec_sid) intersect{0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_secure_streamid_with_non_secure_access.
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covergroup trans_cross_secure_streamid_with_streamid @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STREAM_ID secsid_sid : cross strm_id, sec_sid { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_secure_streamid_with_streamid.
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covergroup trans_cross_shareability_with_translation_attribute @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_RESP_SHAREABILITY SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_ATTRIBUTES sh_trans_attr : cross sh, trans_attr{ option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_shareability_with_translation_attribute.
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covergroup trans_cross_speculative_with_read_write_access @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SPECULATIVE_TRANSLATION_REQ SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_READ_WRITE_ACCESS speculative_rnw : cross speculative, read_write_access { illegal_bins invalid_speculative_rnw = binsof(speculative) intersect{1} && binsof(read_write_access) intersect{svt_dti_transaction::WRITE_ACCESS}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_speculative_with_read_write_access.
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covergroup trans_cross_sub_streamid_with_valid_substream @(cov_sample_trans_req_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SUB_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_VALID_SUBSTREAM ssid_ssv : cross val_sub_strm, sub_strm_id { illegal_bins invalid_ssid_ssv = binsof(val_sub_strm) intersect {0} && !binsof(sub_strm_id) intersect{0}; option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_sub_streamid_with_valid_substream.
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covergroup trans_cross_tok_trans_req_tok_trans_gnt @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_GRANTED SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_REQUESTED tok_req_tok_gnt: cross token_requested, token_granted { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_tok_trans_req_tok_trans_gnt.
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covergroup trans_cross_tok_trans_req_tok_trans_gnt_v1 @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_GRANTED_V1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_REQUESTED_V1 tok_req_tok_gnt: cross token_requested_v1, token_granted_v1 { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_tok_trans_req_tok_trans_gnt_v1.
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covergroup trans_cross_tok_trans_req_tok_trans_gnt_v2 @(cov_sample_condis_ack_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_GRANTED_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANSLATION_TOKEN_REQUESTED_V2 tok_req_tok_gnt: cross token_requested_v2, token_granted_v2 { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_tok_trans_req_tok_trans_gnt_v2.
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covergroup trans_cross_allow_x_allow_w_allow_r @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_X SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_W SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ALLOW_R trans_cross_allow_x_allow_w_allow_r: cross allow_x,allow_w,allow_r { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_allow_x_allow_w_allow_r for DTI_ATS_TRANS_RESP
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covergroup trans_cross_attr_ovr_v2_sec_sid_sid @(cov_sample_trans_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STREAM_ID attr_ovr_v2_sec_sid_sid: cross ovr_attributes_v2, sec_sid, strm_id { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_attr_ovr_v2_sec_sid_sid.
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covergroup trans_cross_attr_ovr_v2_sec_sid_sid_ns @(cov_sample_trans_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_ATTR_OVR_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS attr_ovr_v2_sec_sid_sid_ns: cross ovr_attributes_v2, sec_sid, strm_id,sec_nsec_access { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_attr_ovr_v2_sec_sid_sid_ns.
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covergroup trans_cross_global_ssid_ssv @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_GLOBAL SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SUB_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_VALID_SUBSTREAM trans_cross_global_ssid_ssv: cross global_val,sub_strm_id,val_sub_strm { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_global_ssid_ssv for DTI_ATS_TRANS_RESP
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covergroup trans_cross_mpamns_sec_sid_part_id_pmg_v1 @(cov_sample_trans_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_MPAMNS_V1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PARTID_V1 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PMG_V1 mpamns_sec_sid_part_id_pmg_v1: cross mpamns_v1, sec_sid, part_id_v1, pmg_v1 { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_mpamns_sec_sid_part_id_pmg_v1
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covergroup trans_cross_mpamns_sec_sid_part_id_pmg_v2 @(cov_sample_trans_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_MPAMNS_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_STREAM_ID SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PARTID_V2 SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_PMG_V2 mpamns_sec_sid_part_id_pmg_v2: cross mpamns_v2, sec_sid, part_id_v2, pmg_v2 { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_mpamns_sec_sid_part_id_pmg_v2
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covergroup trans_cross_req_ns_with_resp_ns @(cov_sample_trans_resp_msg_fields); SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_SECURE_NON_SECURE_ACCESS SVT_DTI_COMMON_MONITOR_DEF_COV_UTIL_TRANS_RESP_NS trans_req_ns_trans_resp_ns : cross sec_nsec_access, trans_resp_ns { option.weight =1; } option.per_instance =1; endgroup | |
Macro to create covergroup : trans_cross_req_ns_with_resp_ns.
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256
| |
Number of automatic_bins to create for ADDR field of DTI_TBU_TRANS_REQ message
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256
| |
Number of automatic_bins to create for ADDR field of DTI_TBU_TRANS_RESP message
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`ifdef SVT_DTI_VALID_MASTER_IDX_``idx idx : get_master_if = svt_dti_if.dti_master_if[idx]; `endif |
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`ifdef SVT_DTI_VALID_SLAVE_IDX_``idx idx : get_slave_if = svt_dti_if.dti_slave_if[idx]; `endif |
|
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9
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2
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|
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0
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|
xact_event_pool = xact.get_event_pool(); xact_ev = xact_event_pool.get(event_name); xact_ev.wait_trigger(); |
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uvm_event_pool xact_event_pool; uvm_event xact_ev; |
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svt_dti_master_transaction
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64
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|
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256
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|
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|
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12
|
|
|
32
|
|
|
256
| |
Maximum number of outstanding transactions
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64
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32
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20
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4096
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12
| |
Macros to support higher spec versions DTI Spec G,F,E,E_b
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8
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1
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0
| |
PAGE RESPONSE field types of DTI_ATS_PAGE_RESP message
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3
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2
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12
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|
100
| |
Number of invalidation and sync request messages to be sent
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3
| |
Number of translations done before sending invalidation -sync request messages
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`ifdef SVT_DTI_VALID_MASTER_IDX_``idx idx : svt_dti_if.dti_master_if[idx].clock_enable = enable; `endif |
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`ifdef SVT_DTI_VALID_MASTER_IDX_``idx idx : svt_dti_if.dti_master_if[idx].common_clk_mode = mode; `endif |
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`ifdef SVT_DTI_VALID_MASTER_IDX_``idx idx : svt_dti_if.dti_master_if[idx].common_reset_mode = mode; `endif |
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`ifdef SVT_DTI_VALID_SLAVE_IDX_``idx idx : svt_dti_if.dti_slave_if[idx].clock_enable = enable; `endif |
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`ifdef SVT_DTI_VALID_SLAVE_IDX_``idx idx : svt_dti_if.dti_slave_if[idx].common_clk_mode = mode; `endif |
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`ifdef SVT_DTI_VALID_SLAVE_IDX_``idx idx : svt_dti_if.dti_slave_if[idx].common_reset_mode = mode; `endif |
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3
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1
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|
|
svt_dti_transaction
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SVT_DTI_TBU_IMPTYPE1_MASTER_REQRESP_MSG
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SVT_DTI_TBU_IMPTYPE2_MASTER_REQRESP_MSG
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|
|
160
|
|
|
25
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|
|
26
|
|
|
160
|
|
|
27
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28
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|
if (cfg.env_cfg.dti_tx_cfg[0].tid_enable && cfg.env_cfg.dti_tx_cfg[0].tdest_enable) { tid==val;tdest==tid; }else if(cfg.env_cfg.dti_tx_cfg[0].tid_enable ) { tid==val; } | |
@groupnameambausernonmodifiable
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SVT_DTI_TBU_IMPTYPE1_SLAVE_REQRESP_MSG
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SVT_DTI_TBU_IMPTYPE2_SLAVE_REQRESP_MSG
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|
|
160
|
|
|
29
|
|
|
30
|
|
|
160
|
|
|
31
|
|
|
32
|
|
|
if (cfg.env_cfg.dti_tx_cfg[0].tid_enable && cfg.env_cfg.dti_tx_cfg[0].tdest_enable) { tid==val;tdest==tid; }else if(cfg.env_cfg.dti_tx_cfg[0].tdest_enable ) { tdest==val; } |
|
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4
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if ((port_cfg != null) && (port_cfg.``enablefieldwdth > 0)) begin `SVT_DATA_UTIL_COMPARE_BITVEC_SLICE(fieldname,fieldmaxwidth,port_cfg.``enablefieldwdth``-1,0) end else begin `SVT_DATA_UTIL_COMPARE_BITVEC(fieldname) end | |
Transaction Class Macros definition and utility methods definition
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if ((port_cfg != null) && (port_cfg.``enablefieldwdth > 0)) begin `SVT_DATA_UTIL_COMPARE_BITVEC_SLICE_SIZE_ARRAY(fieldname,fieldmaxwidth,port_cfg.``enablefieldwdth``-1,0) end else begin `SVT_DATA_UTIL_COMPARE_INT_SIZE_ARRAY(fieldname) end |
|
|
1
|
|
|
1
|
|
|
3
|
|
|
0
|
|
|
0
|
|
|
3
|
|
|
2
|
|
|
4
|
|
|
5
|
|
|
2
|
|
|
3
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
6
|
|
|
3
|
|
|
4
|
|
|
0
|
|
|
8
|
|
|
5
|
|
|
2
|
|
|
7
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
5
|
|
|
6
|
|
|
3
|
|
|
1
|
|
|
2
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
|
|
3
|
|
|
0
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
0
|
|
|
2
|
|
|
|
|
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( (((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 ) && (xact.operation ==9'h47)) || ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0 ) && (xact.operation ==9'h47 || xact.operation==9'h105)) ) ) | |
@groupnameambausernonmodifiable
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( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) |
|
|
( ((xact.port_cfg.dti_version == svt_dti_port_configuration::DTI3_0 || xact.port_cfg.dti_version == svt_dti_port_configuration::DTI4_0) && ( xact.operation == 9'h180|| xact.operation == 9'h190|| xact.operation == 9'h191|| xact.operation == 9'h192|| xact.operation == 9'h195|| xact.operation == 9'h198|| xact.operation == 9'h199|| xact.operation == 9'h1C0|| xact.operation == 9'h1C1|| xact.operation == 9'h1C8|| xact.operation == 9'h1C9 ) ) ) |
|
|
0
|
|
|
1
|
|
|
1
|
|
|
2
|
|
|
3
|
|
|
2
|
|
|
3
|
|
|
4
|
|
|
5
|
|
|
|
|
|
4
|
|
|
|
64
|
|
|
if(!axi_sys_common_cfg.debug_system_monitor) svt_amba_debug(id, msg); else if(axi_sys_common_cfg.debug_system_monitor < 4) svt_amba_debug(id, msg) |
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`ifdef SVT_UVM_TECHNOLOGY ,reporter `elsif SVT_OVM_TECHNOLOGY ,reporter `else `endif |