VIP Smartsearch

X
  • VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.

  • How to download VIP smartsearch?

    1. Get VIP Smartsearch (Available as a seperate run file).
    2. Set environment variable 
      DESIGNWARE_HOME
      to required designware home location where VIP Smartsearch should be downloaded.
    3. Run 
      vip_smartsearch_<version>.run
      file.
      VIP Smartsearch will be downloaded to the location 
      $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

  • How to install VIP Smartsearch?

    Please refer to the file 
    VIP_Smartsearch_installation_and_usage_guide.pdf
    in 
    $DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
    for installation steps.

  • Customer Support

    For more details about VIP smartsearch tool, contact support_center@synopsys.com.
    Mention your queries along with below details and send email to above email id.
    Product: Verification IP
    Sub Product: <vip_title>
    Tool: VIP Smartsearch
13 August 2024, Copyright © 2024 Synopsys, Inc.

AMBA SVT UVM Documentation - Other Class List

Here are the Other classes with brief descriptions:
svt_apb_memory This is an SVT memory class customized for APB.
svt_apb_slave_toggle_bit_cov Coverage class declaration consists of covergroup for single bit coverpoint variable. For variable width signal instantiated as per the individual bit index.
svt_apb_reg_adapter The svt_apb_reg_adapter encapsulates the master reg transaction class, This class contains the uvm_sequence_item reg2bus and uvm_sequence_item bus2reg implementation for APB which converts between UVM RAL transactions and APB transactions
svt_apb_master_transition_high_cov Description-Unavailable
svt_apb_master_transition_cov Description-Unavailable
svt_apb_master_transition_low_cov Description-Unavailable
svt_apb_master_toggle_bit_cov Coverage class declaration consists of covergroup for single bit coverpoint variable. For variable width signal instantiated as per the individual bit index.
svt_apb_common Description-Unavailable
svt_ahb_slave_toggle_bit_cov Coverage class declaration consists of covergroup for single bit coverpoint variable. For variable width signal instantiated as per the individual bit index.
svt_ahb_reg_adapter The svt_ahb_reg_adapter encapsulates the master reg transaction class, This class contains the uvm_sequence_item reg2bus and uvm_sequence_item bus2reg implementation for AHB which converts between UVM RAL transactions and AHB transactions
svt_ahb_master_toggle_bit_cov Coverage class declaration consists of covergroup for single bit coverpoint variable. For variable width signal instantiated as per the individual bit index.
uvm_blocking_put_imp_sn_rsp_flit Description-Unavailable
uvm_blocking_put_imp_sn_dat_flit Description-Unavailable
uvm_blocking_put_imp_rn_dat_flit Description-Unavailable
uvm_blocking_put_imp_rn_rsp_flit Description-Unavailable
uvm_blocking_put_imp_rn_req_flit Description-Unavailable
svt_chi_rn_f_port_chi_rn_i_port_pair_concurrent_overlapping_chi_e_xacts_cov_container The covergroup container class used to define the covergroups across multiple RN ports when concurrent overlapping transactions are observed arross RN_F and RN-I nodes. class itself contain cover groups. The constructor of this class gets instance name handle , RN-F and RN-I node indices as arguments which is used set the instance name of the respective covergroup constructed.
svt_chi_rn_f_port_chi_rn_f_port_pair_concurrent_non_overlapping_coherent_exclusive_xacts_cov_container Description-Unavailable
svt_chi_rn_f_port_chi_rn_i_port_pair_concurrent_non_overlapping_coherent_exclusive_xacts_cov_container Description-Unavailable
svt_chi_rn_f_port_chi_rn_f_port_pair_concurrent_overlapping_coherent_exclusive_xacts_cov_container Description-Unavailable
svt_chi_rn_f_port_chi_rn_i_port_pair_concurrent_overlapping_coherent_exclusive_xacts_cov_container Description-Unavailable
svt_chi_rn_f_port_chi_rn_f_port_pair_concurrent_overlapping_atomic_xacts_cov_container The covergroup container class used to define the covergroups across multiple RN ports when concurrent overlapping transactions are observed across pair of RN_F nodes. class itself contain cover groups. The constructor of this class gets instance name handle , RN-F node indices as arguments which is used to set the instance name of the respective covergroup constructed.
svt_chi_rn_f_port_chi_rn_i_port_pair_concurrent_overlapping_chi_rn_f_xacts_with_chi_rn_i_atomic_xacts_cov_container The covergroup container class used to define the covergroups across multiple RN ports when concurrent overlapping transactions are observed arross RN_F and RN-I nodes. class itself contain cover groups. The constructor of this class gets instance name handle , RN-F and RN-I node indices as arguments which is used set the instance name of the respective covergroup constructed.
svt_chi_rn_f_port_chi_rn_f_port_pair_concurrent_overlapping_non_atomic_xacts_cov_container The covergroup container class used to define the covergroups across multiple RN ports when concurrent overlapping transactions are observed across pair of RN_F nodes. class itself contain cover groups. The constructor of this class gets instance name handle , RN-F node indices as arguments which is used to set the instance name of the respective covergroup constructed.
svt_chi_rn_f_port_chi_rn_i_port_pair_concurrent_overlapping_xacts_cov_container The covergroup container class used to define the covergroups across multiple RN ports when concurrent overlapping transactions are observed across RN_F and RN-I nodes. class itself contain cover groups. The constructor of this class gets instance name handle , RN-F and RN-I node indices as arguments which is used set the instance name of the respective covergroup constructed.
uvm_analysis_imp_sn_xact Description-Unavailable
uvm_analysis_imp_rn_snp_xact Description-Unavailable
uvm_analysis_imp_rn_coh_xact Description-Unavailable
svt_chi_system_monitor_common_utils Description-Unavailable
svt_axi_system_monitor_common_utils Description-Unavailable
uvm_analysis_imp_sn_tx_dat_flit Description-Unavailable
uvm_analysis_imp_sn_tx_rsp_flit Description-Unavailable
uvm_analysis_imp_sn_rx_dat_flit Description-Unavailable
uvm_analysis_imp_sn_rx_req_flit Description-Unavailable
uvm_blocking_put_imp_sn_rx_dat_flit Description-Unavailable
uvm_blocking_put_imp_sn_rx_req_flit Description-Unavailable
svt_chi_reg_adapter The svt_chi_reg_adapter encapsulates the chi uvm reg adapter class, This class contains the uvm_sequence_item reg2bus and uvm_sequence_item bus2reg implementation for CHI RN-F VIP
svt_chi_ic_rn_link_cb_exec_common CHI Protocol Driver callback execution class defines the cb_exec methods supported by the CHI Link component.
svt_chi_link_sysco_coherency_disconnect_state Class implementing the COHERENCY_DISCONNECT state.
svt_chi_link_sysco_coherency_enabled_state Class implementing the COHERENCY_ENABLED state.
svt_chi_link_sysco_coherency_connect_state Class implementing the COHERENCY_CONNECT state.
svt_chi_link_sysco_coherency_disabled_state Class implementing the COHERENCY_DISABLED state.
svt_chi_link_rxla_deactivate_state Class implementing the RXLA state machine RXLA_DEACTIVATE state.
svt_chi_link_rxla_run_state Class implementing the RXLA state machine RXLA_RUN state.
svt_chi_link_rxla_activate_state Class implementing the RXLA state machine RXLA_ACTIVATE state.
svt_chi_link_rxla_stop_state Class implementing the RXLA state machine RXLA_STOP state.
svt_chi_link_txla_deactivate_state Class implementing the TXLA state machine TXLA_DEACTIVATE state.
svt_chi_link_txla_run_state Class implementing the TXLA state machine TXLA_RUN state.
svt_chi_link_txla_activate_state Class implementing the TXLA state machine TXLA_ACTIVATE state.
svt_chi_link_txla_stop_state Class implementing the TXLA state machine TXLA_STOP state.
svt_chi_link_sysco_interface_fsm Class implementing the SYSCO Interface state machine.
svt_chi_link_rxla_fsm Class implementing the RXLA state machine.
svt_chi_link_txla_fsm Class implementing the TXLA state machine.
uvm_analysis_imp_rx_snp_flit Description-Unavailable
uvm_analysis_imp_rx_rsp_flit Description-Unavailable
uvm_analysis_imp_rx_dat_flit Description-Unavailable
uvm_analysis_imp_tx_dat_flit Description-Unavailable
uvm_analysis_imp_tx_rsp_flit Description-Unavailable
uvm_analysis_imp_tx_req_flit Description-Unavailable
svt_chi_coverage_per_src_id_container Description-Unavailable
uvm_blocking_get_imp_snp_xact Description-Unavailable
uvm_blocking_put_imp_rx_snp_flit Description-Unavailable
uvm_blocking_put_imp_rx_rsp_flit Description-Unavailable
uvm_blocking_put_imp_rx_dat_flit Description-Unavailable
svt_chi_node_pmu Base class for all common files for the AMBA CHI VIP.
svt_axi_reg_adapter The svt_axi_reg_adapter encapsulates the master reg transaction class, This class contains the uvm_sequence_item reg2bus and uvm_sequence_item bus2reg implementation for AXI
svt_axi_cov_data Description-Unavailable
svt_axi_locked_followed_by_excl_xact_sequence This Class represents the following pattern sequence, which needs to be scanned within the AXI Locked READ transaction followed by Exclusive transaction with response.
LOCKED READ transaction followed by EXCLUSIVE transaction
svt_axi_barrier_pair_wr_after_rd_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the AXI Barrier transactions.
WRITEBARRIER followed by READBARRIER
svt_axi_barrier_pair_rd_after_wr_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the AXI Barrier transactions.
READBARRIER followed by WRITEBARRIER
svt_axi_toggle_bit_cov Coverage class declaration consists of covergroup for single bit coverpoint variable. For variable width signal instantiated as per the individual bit index.
svt_axi_cov Class containing the coverage groups
svt_axi_exclusive_monitor Description-Unavailable
svt_axi_sysco_coherency_disconnect_state Class implementing the COHERENCY_DISCONNECT state.
svt_axi_sysco_coherency_enabled_state Class implementing the COHERENCY_ENABLED state.
svt_axi_sysco_coherency_connect_state Class implementing the COHERENCY_CONNECT state.
svt_axi_sysco_coherency_disabled_state Class implementing the COHERENCY_DISABLED state.
svt_axi_sysco_interface_fsm Class implementing the SYSCO Interface state machine.
svt_axi_passive_cache This class is used to model a single cache.
svt_amba_chi_sys_to_axi_sys_mapper Represents all System ID and Node or Port ID mapping between CHI and AXI Systems.
svt_chi_scenario_coverage Class containing the coverage groups
svt_chi_scenario_coverage_database Description-Unavailable
svt_chi_load_followed_by_store_followed_by_store_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Load followed by Store followed by Store
svt_chi_load_followed_by_store_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Load followed by Store
svt_chi_dvmop_tlbi_followed_by_cmo_followed_by_dvmop_tlbi_followed_by_dvmop_sync_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
DVMOp TLBI followed by CMO followed by DVMOp TLBI followed by DVMOp SYNC Transaction
svt_chi_dvmop_tlbi_followed_by_cmo_followed_by_dvmop_sync_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
DVMOp TLBI followed by CMO followed by DVMOp SYNC Transaction
svt_chi_dvmop_tlbi_followed_by_cancel_dvmop_tlbi_followed_by_non_dvmop_of_same_txnid_followed_by_dvmop_sync_followed_by_cancel_dvmop_sync_followed_by_dvmop_sync_of_same_txnid_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
svt_chi_dvmop_tlbi_followed_by_dvmop_sync_followed_by_dvmop_sync_followed_by_dvmop_tlbi_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
DVMOp TLBI followed by DVMOp SYNC Transaction followed by DVMOp SYNC Transaction followed by DVMOp TLBI Transaction
svt_chi_dvmop_tlbi_followed_by_cancel_dvmop_tlbi_followed_by_dvmop_tlbi_of_same_txnid_followed_by_dvmop_sync_followed_by_cancel_dvmop_sync_followed_by_dvmop_sync_of_same_txnid_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
svt_chi_dvmop_tlbi_transaction_followed_by_retry_dvmop_tlbi_transaction_followed_by_dvmop_sync_transaction_followed_by_retry_dvmop_sync_transaction_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
svt_chi_dvmop_tlbi_followed_by_dvmop_tlbi_followed_by_dvmop_sync_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
DVMOp TLBI followed by DVMOp TLBI followed by DVMOp SYNC Transaction
svt_chi_dvmop_tlbi_outstanding_followed_by_dvmop_tlbi_followed_by_retry_dvmop_tlbi_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
DVMOp TLBI outstanding followed by DVMOp TLBI followed by Retry DVMOp SYNC Transaction
svt_chi_dvmop_tlbi_outstanding_followed_by_dvmop_sync_followed_by_retry_dvmop_sync_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
DVMOp TLBI outstanding followed by DVMOp Sync followed by Retry DVMOp SYNC Transaction
svt_chi_dvmop_tlbi_followed_by_dvmop_sync_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
DVMOp TLBI followed by DVMOp SYNC Transaction
svt_chi_cancel_transaction_after_two_normal_transaction_of_same_txnid_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
svt_chi_retry_transaction_after_two_normal_transaction_of_same_txnid_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
svt_chi_cancel_transaction_between_two_normal_transaction_of_same_txnid_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
svt_chi_retry_transaction_between_two_normal_transaction_of_same_txnid_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
svt_chi_three_read_request_ordering_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
CHI-B Spec Figure 2-23::Three Read Request Order Example Ordered READ#1 ---> Ordered READ#2 ---> Retry Ordered READ#2 ---> Ordered READ#3
svt_chi_back2back_transaction_same_src_id_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
'N' times Back2Back CHI Transactions of Same Source-ID
svt_chi_no_ordering_rd_after_two_non_no_ordering_transaction_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Non No-Ordering Order Write/Read followed by Non No-Ordering Order Write/Read followed by No-Ordering Read with Same Address/Different-Different Address.
svt_chi_back2back_order_type_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
'N' times Back2Back Order Type Transaction
svt_chi_read_followed_by_write_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Read followed by Write
svt_chi_read_followed_by_read_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Read followed by Read
svt_chi_write_followed_by_write_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Write followed by Write
svt_chi_write_followed_by_read_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Write followed by Read
svt_chi_req_ordered_wr_followed_by_req_ordered_rd_pattern_sequence This Class represents the following pattern sequence, which needs to be scanned within the CHI Transactions.
Request Order Write followed by Request Order Read
svt_chi_memory Description-Unavailable
svt_chi_system_monitor_chi_coherent_snoop_association_callback_data The data object of this class will be used as an argument to 'post_process_associated_snoop_transactions_to_chi_coherent_xact' callback in CHI system monitor to provide the required information to tweak the chi coherent and snoop transaction association performed by the CHI system monitor. All the required arguments are the members of this class.
svt_chi_system_monitor_l2_icn_to_l1_icn_snoop_transaction_activity_callback_data The data object of this class will be used as argument for callbacks of CHI system monitor related to:
  • L1-ICN downstream Snoop transaction started.
  • L1-ICN downstream Snoop transaction ended.
  • L1-ICN upstream Snoop transaction started.
  • L1-ICN upstream Snoop transaction ended.
All the required arguments are the members of this class. Any additional arguments if required can be added to this class.
svt_chi_system_monitor_l1_icn_to_l2_icn_rn_transaction_activity_callback_data The data object of this class will be used as argument for callbacks of CHI system monitor related to:
  • L1-ICN downstream RN transaction started.
  • L1-ICN downstream RN transaction ended.
  • L1-ICN upstream RN transaction started.
  • L1-ICN upstream RN transaction ended.
All the required arguments are the members of this class. Any additional arguments if required can be added to this class.
svt_chi_system_monitor_end_of_simulation_callback_data The data object of this class will be used as argument to end_of_simulation callbacks of CHI system monitor. All the required arguments of end_of_simulation callbacks are the members of this class. The additional arguments, if required to be added to end_of_simulation callback, can be added to this class.
svt_chi_system_monitor_callback_data Base class for system monitor callback data object. The data object of this class will be used as argument to newly aaded callbacks in CHI system monitor.
svt_chi_callback_data Base class for callback data object. The data object of this class will be used as argument to newly aaded callbacks in CHI VIP.
svt_chi_exclusive_monitor Description-Unavailable
svt_chi_system_monitor_exclusive_sequence_transaction_activity_callback_data The data object of this class will be used as argument for callback in CHI system monitor to set the expectation for the excluisve load/store transaction All the required arguments are the members of this class. Any additional arguments if required can be added to this class.
svt_chi_system_domain_item Description-Unavailable
svt_chi_hn_addr_range Defines a range of address identified by a starting address(start_addr) and end address(end_addr).
svt_axi_callback_data Description-Unavailable
svt_axi_gp_utils Utility class with a collection of routines to assist with Generic Protocol transaction conversions.
svt_axi_fifo_mem This class is used to model a single FIFO.
svt_axi_cache This class is used to model a single cache.
svt_axi_cache_line This class is used to represent a single cache line. It is intended to be used to create a sparse array of stored cache line data, with each element of the array representing a full cache line in the cache. The object is initilized with, and stores the information about the index, the address associated with this cache line, the corresponding data and the status of the cache line.
svt_axi_system_monitor_exclusive_sequence_transaction_activity_callback_data The data object of this class will be used as argument for callback in AXI system monitor to set the expectation for the excluisve store transaction All the required arguments are the members of this class. Any additional arguments if required can be added to this class.
svt_axi_slave_region_range Defines a range of address region identified by a starting address(start_addr) and end address(end_addr).
svt_axi_slave_addr_range Defines a range of address region identified by a starting address(start_addr) and end address(end_addr).
svt_axi_system_domain_item Defines a system domain map. Refer Section C 1.6.1 on Domains. Applicable when svt_axi_port_configuration :: AXI_ACE is used in any of the ports. Each inner domain/outer domain/non-shareable domain/system shareable domain is represented by an instance of this class. There can be multiple address ranges for a single domain, but no address range should overlap. For example if M0 and M1 are in the inner domain and share the addresses (0x00-0xFF and 0x200-0x2FF), the following apply: domain_type = svt_axi_system_domain_item :: INNERSHAREABLE start_addr[0] = 0x00 end_addr[0] = 0xFF start_addr[1] = 0x200 end_addr[1] = 0x2FF domain_idx = master_ports[] = {0,1}; The following utility methods are provided in svt_axi_system_configuration to define and set the above variables svt_axi_system_configuration :: create_new_domain; svt_axi_system_configuration :: set_addr_for_domain;
svt_ahb_bus_status Defines attributes that are shared between the arbiter, decoder
svt_ahb_slave_addr_range Defines a range of address region identified by a starting address(start_addr) and end address(end_addr).
svt_ahb_slave_multi_hsel_addr_range Defines a range of address for each HSEL specific to single slave identified by a starting address(start_addr_hsel) and end address(end_addr_hsel).
svt_apb_slave_addr_range Defines a range of address region identified by a starting address(start_addr) and end address(end_addr).
svt_amba_fifo_rate_control Utility class which may be used by agents to model a FIFO based resource class to control the rate at which transactions are sent from a component
svt_amba_addr_mapper Description-Unavailable
svt_amba_pv_extension TLM 2.0 Generic Payload extension class used to model AXI transactions using a LT coding style. It corresponds to the ARM amba_pv_extension class. See the ARM AMBA-PV Extensions to OSCI TLM 2.0 Reference Manual for detailed documentation.
svt_amba_pv Container class for enum declarations
13 August 2024, Copyright © 2024 Synopsys, Inc.