This configuration parameter controls the values driven on the address bus by the AHB master model when the address bus is inactive. This helps in detecting any issue in the RTL which is sampling the address bus at an incorrect clock edge.
Note that during reset, addr will be driven to a value of zero irrespective of this parameter setting Also this parameter will not be effective when xact_type is set to idle_xact.

Address width of this port in bits.

Configuration type: Static

A unique ID assigned to master/slave port corresponding to this port configuration. This ID must be unique across all AMBA components instantiated in the testbench. This is currently applicable only when the AMBA system monitor is used and is configured using a configuration plain text file (as opposed to a SystemVerilog code that sets the configuration).

The AHB_V6 extension supports unaligned transfers. In case of an unaligned address access (which crosses the bus-width boundary) must be split into 2 accesses resulting an addtional transfer.
For example, an INCR4 burst starting from an unaligned address can have 5 transfers.

HTRANS	HADDR	HUNALIGN	HSIZE	HBSTRB
NSEQ	0x1006	1	0x2	11000000
SEQ	0x1008	1	0x2	00001111
SEQ	0x100C	1	0x2	11110000
SEQ	0x1010	1	0x2	00001111
SEQ	0x1014	1	0x2	00110000

This attribute provides configuration support to combine or separate the addtional beat level values in transaction object. This is currently applicable for data and all_beat_response arrays additional beat in their transfers.

• When set to 0, specifies that the VIP must separate the beat level values for each beat in the unaligned transfer, hence there would be more values in the array compared to the burst_type.
  

  Transfer index	data[index]	all_beat_response[index]
  1	0xC1B8	OKAY
  2	0x4B3CD24D	OKAY
  3	0x9B0BB437	OKAY
  4	0x1AC32A3A	ERROR
  5	0x2A3A	OKAY

• When set to 1, specifies that the VIP must combine the beat level values for each beat such that values are in aligned size.
  

  Transfer index	data[index]	all_beat_response[index]
  1	0xD24DC1B8	OKAY
  2	0xB4374B3C	OKAY
  3	0x2A3A9B0B	ERROR
  4	0x2A3A1AC3	ERROR

• The default value is 1.

Configuration type : Static
Applicable : Active Manager

Enables control_huser sideband signal in the VIP. control_huser signal can be used when ahb_interface_type is set to AHB or AHB_LITE.

• Setting control_huser_enable parameter to 1 will enable control_huser sideband signal for specific manager/subordinate. By default, the sideband signals are disabled for all AHB managers and subordinates.
• In the AHB5 specification, it is defined as HAUSER. However in the AHB5 VIP, the signal and associated transaction class members are named as control_huser, in order to bring the consistency with other existing user signals already supported by the VIP.

Configuration type: Static

Note: Though control_huser, hwdata_huser, hrdata_huser were added in AHB VIP prior to AHB5 specification, since there was no protocol requirements from the specification point of view prior to AHB5, no protocol checks were added on these signals. Now that AHB5 specification specifies the requirements on these user signals, the AHB5 compliant AHB VIP supports corresponding protocol checks.

Defines the width of AHB control sideband signal control_huser for specific master or slave.

• Minimum value is 1
• Maximum value is `SVT_AHB_MAX_USER_WIDTH

Configuration type: Static

This configuration parameter controls the values driven on the following AHB control signals by AHB master, slave drivers in active mode:

• hburst
• hwrite
• hprot
• hnonsec: when svt_ahb_configuration :: secure_enable is set to 1
• hsize
• control_huser: when svt_ahb_configuration :: control_huser_enable is set to 1

Note that when reset is active, the above signals will be driven to a value of zero irrespective of this parameter setting

Following are the different Idle conditions

• Normal Idle cycles
• Idles during two cycle responses
• Idles during EBT

Used by the AHB master and slave models. This configuration parameter controls the values driven on the:

• read data bus by slave when HTRANS is BUSY.
• write data bus by master when HTRANS is BUSY.
• currently supported values are: INACTIVE_LOW_VALUE : Signal is driven to 0 INACTIVE_HIGH_VALUE : Signal is driven to 1 INACTIVE_X_VALUE : Signal is driven to x INACTIVE_Z_VALUE : Signal is driven to z IACTIVE_RAND_VALUE : Signal is driven to random value INACTIVE_PREV_VALUE : Signal is driven to hrdata/hwdata previous value
• Default value is : INACTIVE_PREV_VALUE

Enables hwdata_huser and hrdata_huser sideband signals in the VIP. data_huser signal can be used when ahb_interface_type is set to AHB or AHB_LITE.

• Setting data_huser_enable parameter to 1 will enable hwdata_huser and hrdata_huser sideband signals for specific manager/subordinate. By default, the sideband signals are disabled for all AHB managers and subordinates.
• In the AHB5 specification, they are defined as HWUSER and HRUSER. However in the AHB5 VIP, the signal and associated transaction class members are named as data_huser, in order to bring the consistency with other existing user signals already supported by the VIP.

Configuration type: Static

Note: Though control_huser, hwdata_huser, hrdata_huser were added in AHB VIP prior to AHB5 specification, since there was no protocol requirements from the specification point of view prior to AHB5, no protocol checks were added on these signals. Now that AHB5 specification specifies the requirements on these user signals, the AHB5 compliant AHB VIP supports corresponding protocol checks.

Defines the width of AHB data sideband signals hwdata_huser and hrdata_huser for specific master or slave.

• Minimum value is 1
• Maximum value is `SVT_AHB_MAX_USER_DATA_WIDTH

Configuration type: Static

Used by the AHB master, slave models. This configuration parameter controls the values driven on the:

• inactive byte lanes of write data bus by the AHB master model, and also when write data bus is inactive.
• inactive byte lanes of read data bus by the AHB slave model, and also when read data bus is inactive.

This helps in detecting any issue in the RTL which is sampling the data bus at an incorrect clock edge.

Data width of this port in bits.

Configuration type: Static

Address map that maps global address to a local address at destination Typically applicable to slave components Applicable only if svt_ahb_system_configuration :: enable_complex_memory_map is set

This configuration parameter makes sure that if master looses grant during INCR burst type transfer, the transaction is not treated as EBT. Value 1 means that the transaction will be treated as EBT. VAlue 0 means that the transaction will not be treated as EBT. Applicable for : passive master, active/passive slave. .

Determines if transaction reporting is enabled.

• 1'b1 : Enable transaction reporting.
• 1'b0 : Disable transaction reporting.

type: Static

Determines if the transaction trace file generation is enabled.

• 1'b1 : Enable trace file generation.
• 1'b0 : Disable trace file generation.

type: Static

Determines if Verdi Protocol Analyzer FSDB generation is enabled. type: Static

Enables termination of INCR burst with BUSY transfer. When default to 0, driving of BUSY after last beat for INCR burst is not allowed. When set to 1, driving of BUSY cycles after last beat in INCR burst is allowed. Thus terminating of INCR burst with BUSY transfer changing HTRANS to NONSEQ/IDLE is achieved. When end_incr_with_busy is 1 either in AHB3 mode, svt_ahb_system_configuration :: ahb3=1 or in AHB5 mode, svt_ahb_system_configuration :: ahb5=1 change of HTRANS from BUSY to either NSEQ/IDLE is allowed. Currently applicable in AHB-Lite mode configuration, svt_ahb_system_configuration :: ahb_lite = 1. In AHB-Full mode, this is supported only when svt_ahb_configuration :: enable_ebt_for_incr = 0. A transaction with this feature enabled and having burst length greater than or equal to 1 should not target the last address location of the slave as there is a possibility of crossing the slave boundary. There are constraints and is_valid check in the master transaction class will take care of 1KB boundary crossing with this feature enabled. With the feature enabled the busy cycle for the last beat of the INCR burst has to be programed with nonzero value. Configuration type : Static Applicable : Active Master and Passive Master

This configuration parameter defines the AHB5 extended memory types property being defined / enabled or not when 'ahb5' of system configuration is asserted.

Note:

• According to ARM IHI 0033C : Section 3.9.7 Legacy Considerations, the subordinate needs to know whether the current communicating manager has extended memory types support. If the manager is not supporting (ie: manager interface has only HPROT[3:0] signals), the supported subordinate should populate HPROT[6:4] mapping by refering to the ARM IHI 0033C Table 3-8.
• If the system configuration which the subordinate is refering does not contain the communicating manager's port configuration, the subordinate VIP assumes that the manager has extended memory support if the subordinate is supporting extended memory types.
• Else if the subordinate has access to the communicating manager's port configuration, the subordinate will populate HPROT[6:4] signals based on the manager's extended memeory support configuration.

Specifies whether output signals from master/slave IFs should be initialized to 0 asynchronously at 0 simulation time.

• 1: Intializes output signals from master/slave IFs to 0 asynchronously at 0 simulation time.
• 0: Initializes output signals from master/slave IFs synchronously at 0 simulation time.

Configuration type: Static
Default value: 0

This configuration parameter defines the invariant modes in AHB5. Applicable for both Read and Write transactions Applicable for both AHB Master/Slave Active/Passive modes Applicable only when svt_ahb_system_configuration :: ahb5=1 and when svt_ahb_system_configuration :: little_endian=0(Big-endian format)

The default value is set to SVT_AHB_CONFIGURATION_NO_INVARIANT indicating little-endian mode without any invariance in ahb5 mode. This is required to maintain backward-compatible When set to SVT_AHB_CONFIGURATION_BYTE_INVARIANT indicates byte-invariant(BE8) mode. When set to SVT_AHB_CONFIGURATION_WORD_INVARIANT indicates word-invariant(BE32) mode.

This will enable the user to configure different endian schemes.

Specifies if the agent is an active or passive component. Allowed values are:

• 1: Configures component in active mode. Enables sequencer, driver and monitor in the the agent.
• 0: Configures component in passive mode. Enables only the monitor in the agent.
• Configuration type: Static

This configuration attribute is used to achieve following scenario
last_beat_tr1 first_beat_tr2 Htrans >> NSEQ1/SEQ1 IDLE/NSEQ2 NSEQ2
Haddr >> ADDR1 0000 ADDR2
Hready >> HIGH LOW HIGH
Hresp >> OKAY 1st_ERR 2nd_ERR
In order to drive IDLE during first cycle of ERROR response, following sequence has to be driven

• Drive svt_ahb_transaction.xact_type = svt_ahb_transaction :: IDLE_XACT between two transactions without wait states and make sure svt_ahb_master_transaction :: num_idle_cycles=1
  This configuration attribute is applicable only under following setting
  
• svt_ahb_system_configuration :: error_response_policy is set to CONTINUE_ON_ERROR
  When set to 1, the active master drives new transaction during second cycle of ERROR response. The address phase of the next transaction (NSEQ) commences during this second cycle of ERROR response when HREADY is high
  By default the value is set to 0
  Extra info: This attribute covers the functionality of the removed configuration nseq_in_second_cycle_error_response_for_single_burst Known issue: As the new transaction is driven in the second cycle of ERROR response, the transaction is put on analysis port by active master in the second cycle itself. Hence scoreboard issues needs to be taken care

When set to '1', enables positive protocol checks coverage. When set to '0', enables negative protocol checks coverage. type: Static

This queue will hold the names of all the slaves, including non-AHB slaves, to which an AHB master can communicate.

Determines in which format the file should write the transaction data. Only following setting is supported: FSDB indicates FSDB format.

A unique ID assigned to the master/slave port corresponding to this port configuration. This ID must be unique across all masters/slaves of the AHB system configuration to which this port belongs. A master and a slave may share the same port_id, but two masters or two slaves cannot share the same port_id. If not assigned by the user, it is auto assigned by the VIP.

Enables protocol checks coverage. type: Dynamic

Enables protocol checking. In a disabled state, no protocol violation messages (error or warning) are issued. type: Dynamic

Used by the AHB master, slave models. This configuration parameter controls the values driven on the:

• HWDATA bus by the AHB master model when there is an active READ transaction. When set to '1', AHB master will retain the HWDATA bus value. When set to '0', AHB master will drive HWDATA to default value as per svt_ahb_configuration :: data_idle_value.
• HRDATA bus by the AHB slave model when there is an active WRITE transaction. When set to '1', AHB slave will retain the HRDATA bus value. When set to '0', AHB slave will drive HRDATA to default value as per svt_ahb_configuration :: data_idle_value.
• HRDATA bus by the AHB slave model on wait cycles (when HREADY is low). When set to '1', AHB slave will retain the HRDATA bus value. When set to '0', AHB slave will drive HRDATA to default value as per svt_ahb_configuration :: data_idle_value.

The default value of this variable is '1'.

Slave for which separate secure & non-secure address space is enabled i.e. bit is set to '1', it will accept both secure and non-secure transactions targeted for the same address. However, while updating memory it will use tagged address i.e. address attribute, in this case security bit, will be appended to the original address as the MSB bits.

Specifies if the component is enabled to perform signal valid level checks during reset.

• 1: Enables the signal valid level checks during reset
• 0: Disables the signal valid level checks during reset

Configuration type: Static
Default value: 1
The below listed checks are executed when this attribute is set to 1 under the following conditions: svt_ahb_configuration :: protocol_checks_enable is set to 1 AND the respective checks are enabled.
Following are the checks:

• svt_ahb_checker :: hready_out_from_bus_high_during_reset
• svt_ahb_checker :: hready_out_from_slave_not_X_or_Z_during_reset
• svt_ahb_checker :: htrans_idle_during_reset
• svt_ahb_checker :: signal_valid_haddr_check
• svt_ahb_checker :: signal_valid_hwrite_check
• svt_ahb_checker :: signal_valid_hsize_check
• svt_ahb_checker :: signal_valid_hburst_check
• svt_ahb_checker :: signal_valid_htrans_check
• svt_ahb_checker :: signal_valid_hlock_check
• svt_ahb_checker :: signal_valid_hprot_check
• svt_ahb_checker :: signal_valid_hbusreq_check
• svt_ahb_checker :: signal_valid_hready_in_check
• svt_ahb_checker :: signal_valid_hgrant_check
• svt_ahb_checker :: signal_valid_hsel_check
• svt_ahb_checker :: signal_valid_hmaster_check
• svt_ahb_checker :: signal_valid_hmastlock_check
• svt_ahb_checker :: signal_valid_hready_check

Note that when svt_ahb_system_configuration :: common_reset_mode is set to 0, a given VIP component cannot reliably perform the validity checks on it's input signals during the reset. Below are the details:
All the signals that are inputs for a given component can be checked for validity during the reset, provided common reset mode is enabled (svt_ahb_system_configuration :: common_reset_mode is set to 1). If the common reset mode is not enabled (svt_ahb_system_configuration :: common_reset_mode is set to 0), different components will have independent input hresetn signals. In such case, during reset for a give component, it's not reliable to perform checks on the input signals as the driving component of such signals need not be in reset. So, under such condition, the checks on input signals will not be performed.

• For a master agent, following checks are not performed:
  • svt_ahb_checker :: hready_out_from_bus_high_during_reset
  • svt_ahb_checker :: signal_valid_hgrant_check
  • svt_ahb_checker :: signal_valid_hready_check
• For a slave agent, following checks are not performed:
  • svt_ahb_checker :: hready_out_from_bus_high_during_reset
  • svt_ahb_checker :: htrans_idle_during_reset
  • svt_ahb_checker :: signal_valid_haddr_check
  • svt_ahb_checker :: signal_valid_hwrite_check
  • svt_ahb_checker :: signal_valid_hsize_check
  • svt_ahb_checker :: signal_valid_hburst_check
  • svt_ahb_checker :: signal_valid_htrans_check
  • svt_ahb_checker :: signal_valid_hprot_check
  • svt_ahb_checker :: signal_valid_hnonsec_check
  • svt_ahb_checker :: signal_valid_hready_in_check
  • svt_ahb_checker :: signal_valid_hsel_check
  • svt_ahb_checker :: signal_valid_hmaster_check
  • svt_ahb_checker :: signal_valid_hmastlock_check

When silent_mode is set to 1, the "Transaction started" and "Transaction ended" messages are printed in UVM_HIGH verbosity. When silent_mode is set to 0, the "Transaction started" and "Transaction ended" messages are printed in UVM_LOW verbosity.

Applicable only to slave VIP Address map for this slave Must be used only if the svt_ahb_system_env and svt_ahb_system_configuration is not used. Typically used in an environment where only one slave VIP is instantiated.

Address map that maps a local address to a global address at a source Typically applicable to master components. However, it can be applicable to a slave component if that is connected downstream through another interconnect/bridge to components which are further downstream. Applicable only if svt_ahb_system_configuration :: enable_complex_memory_map is set

Name of the master as used in path coverage This field can also be used to specify master specific slave address mapping. Refer to the documentation of svt_amba_addr_mapper for more details

Enables state coverage of signals. State Coverage covers all possible states of a signal. type: Dynamic

Enables toggle coverage. Toggle Coverage gives us information on whether a bit toggled from 0 to 1 and back from 1 to 0. This does not indicate that every value of a multi-bit vector was seen, but measures if individual bits of a multi-bit vector toggled. This coverage gives information on whether a system is connected properly or not. type: Dynamic

- Applicable only when enable_tracing is set to 1’b1.

• When set to a non-null string, this string type attribute indicates the name of the transaction trace file generated by the monitor.
  • Eg: ahb_sys_cfg.master_cfg[0].trace_file_name = “chip0.master0.log”;
  • Eg: ahb_sys_cfg.slave_cfg[0].trace_file_name = "chip0.slave0.log";
• When this is set to a null string (default value), the trace file name follows standard SVT VIP naming conventions.
• Note:
  • The string settings should follow the standard SystemVerilog string literal requirements. For example, should not include following charaters: [, ], \, :, /, "
  • In case there are multiple agents, user needs to ensure that the trace file name settings across the agents are unique for a given simulation.
• Default value: ""
• Type: Static

Enables transaction level coverage. type: Static

Enables AHB transaction level coverage group trans_ahb_beat_hresp_transistion_abort_on_error_ahb_full type: Static

Enables AHB transaction level coverage group trans_ahb_beat_hresp_transistion_abort_on_error_ahb_lite type: Static

Enables AHB transaction level coverage group trans_ahb_beat_hresp_transistion_continue_on_error_ahb_full type: Static

Enables AHB transaction level coverage group trans_ahb_beat_hresp_transistion_continue_on_error_ahb_lite type: Static

Enables AHB transaction level coverage group trans_ahb_full_hresp_first_beat_ahb_lite type: Static

Enables AHB transaction level coverage group trans_ahb_full_hresp_first_beat type: Static

Enables AHB transaction level coverage group trans_ahb_hburst_transition type: Static

Enables AHB transaction level coverage group trans_ahb_hmaster type: Static

Enables AHB transaction level coverage group trans_ahb_hready_in_when_hsel_high type: Static

Enables AHB transaction level coverage group trans_ahb_hresp_all_beat_ahb_full type: Static

Enables AHB transaction level coverage group trans_ahb_hresp_all_beat_ahb_lite type: Static

Enables AHB transaction level coverage group trans_ahb_htrans_cov_diff_xact_ahb_full type: Static

Enables AHB transaction level coverage group trans_ahb_htrans_transition_read_xact type: Static

Enables AHB transaction level coverage group trans_ahb_htrans_transition_read_xact_hready type: Static

Enables AHB transaction level coverage group trans_ahb_htrans_transition_write_xact type: Static

Enables AHB transaction level coverage group trans_ahb_htrans_transition_write_xact_hready type: Static

Enables AHB transaction level coverage group trans_ahb_idle_to_nseq_hready_low type: Static

Enables AHB transaction level coverage group trans_cross_ahb_burst_incr_number_of_beats type: Static

Enables AHB transaction level coverage group trans_cross_ahb_burst_with_busy type: Static

Enables AHB transaction level coverage group trans_cross_ahb_burst_wrapped_addr_boundary type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_haddr type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_haddr_hsize type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hlock type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hlock_hsize type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hnonsec type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hprot0 type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hprot1 type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hprot2 type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hprot3 type: Static

Enables AHB transaction level coverage group, trans_cross_ahb_hburst_hprot3_ex type: Static

Enables AHB transaction level coverage group, trans_cross_ahb_hburst_hprot4_ex type: Static

Enables AHB transaction level coverage group, trans_cross_ahb_hburst_hprot5_ex type: Static

Enables AHB transaction level coverage group, trans_cross_ahb_hburst_hprot6_ex type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hresp type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_hsize type: Static

Enables AHB transaction level coverage group trans_cross_ahb_hburst_num_wait_cycles type: Static

Enables AHB transaction level coverage group trans_cross_ahb_htrans_xact type: Static

Enables AHB transaction level coverage group trans_cross_ahb_num_busy_cycles type: Static

Enables AHB transaction level coverage group trans_cross_ahb_num_wait_cycles type: Static

Enables AHB transaction level coverage group trans_cross_ahb_page_boundary_size type: Static

Enables AHB transaction level coverage group trans_cross_ahb_size_addr_align type: Static

Used by the AHB active and passive components. This timer looks at HREADY, when a change occurs, and if sampled LOW the timer task starts counting cycles. HREADY is sampled every clock cycle, and if the number of clock cycles exceeds wait_state_timeout, an error is reported. The integer value wait_state_timeout represents the number of clock cycles. If set to 0, the timer is not started.

Used by the AHB active and passive components. This timer starts when a transaction starts. If the number of clock cycles exceeds xact_timeout and the transaction does not complete by the set time, an error is repoted. The timer is incremented by 1 every clock and is reset when the transaction ends. The integer value xact_timeout represents the number of clock cycles. If set to 0, the timer is not started.