A unique ID assigned to master/slave port corresponding to this configuration. This ID must be unique across all AMBA components instantiated in the testbench. This is currently applicable only when the AMBA system monitor is used and is configured using a configuration plain text file (as opposed to a SystemVerilog code that sets the configuration).

Enables checking of pwdata only on valid byte lanes based on pstrb for the checks signal_valid_pwdata_check and pwdata_changed_during_transfer. In a disabled state, whole pwdata will be taken into consideration to perform the checks. Applicable only when svt_apb_system_configuration :: apb4_enable set to 1. .

Enables control_puser sideband signal in APB interface

Defines the width of control_puser sideband signal in APB interface. Default value of SVT_APB_MAX_CONTROL_PUSER_WIDTH is 5. width is user can configure the width using SVT_APB_MAX_CONTROL_PUSER_WIDTH macro

Used by the APB master, slave models. This configuration parameter controls the values during the IDLE period,data signals will take this value.

Address map that maps global address to a local address at destination Typically applicable to slave components Applicable only if svt_apb_system_configuration :: enable_complex_memory_map is set

Determines if Verdi Protocol Analyzer FSDB generation is enabled. type: Static

Enables to implement a new object for each transaction, instead of reuse the same one

Specifies whether output signals from master/slave IFs should be initialized to 0 asynchronously at 0 simulation time.

• 1: Intializes output signals from master/slave IFs to 0 asynchronously at 0 simulation time.
• 0: Initializes output signals from master/slave IFs to 0 synchronously at 0 simulation time.

Configuration type: Static
Default value: 0

Specifies if the agent is an active or passive component. Allowed values are:

• 1: Configures component in active mode. Enables driver, monitor and sequencer in the the agent.
• 0: Configures component in passive mode. Enables only the monitor in the agent.

type: Static

Determines in which format the file should write the transaction data. Only following setting is supported: FSDB indicates FSDB format.

Enables coverage for protocol checking. In a disabled state, no protocol checks coverage is generated.

• In case of svt_apb_system_configuration object, this field controls enabling of protocol checks coverage for master.
• In case of svt_apb_slave_configuration object, this field controls enabling of protocol checks coverage for slave.
• This can be enabled only when protocol_checks_enable is enabled.
• type: Dynamic

- Enables protocol checking. In a disabled state, no protocol violation messages (error or warning) are issued.

• In case of svt_apb_system_configuration object, this field controls enabling of protocol checks for master.
• In case of svt_apb_slave_configuration object, this field controls enabling of protocol checks for slave.
• type: Dynamic

Determines whether transaction report information is generated in log file.

• 1’b1: Enable trace report generation.
• 1’b0: Disable trace report generation

• Default value: 1'b0
• Type: Dynamic

Address map that maps a local address to a global address at a source Typically applicable to master components. However, it can applicable to a slave component if that is connected downstream through another interconnect/bridge to components which are further downstream. Applicable only if svt_apb_system_configuration :: enable_complex_memory_map is set in the configuration

Enables state coverage of signals. State Coverage covers all possible states of a signal.
type: Dynamic

Enables coverage. Toggle Coverage gives us information on whether a bit toggled from 0 to 1 and back from 1 to 0. This does not indicate that every value of a multi-bit vector was seen, but measures if individual bits of a multi-bit vector toggled. This coverage gives information on whether a system is connected properly or not.
type: Dynamic

Determines whether transaction trace file generation is enabled.

• 1’b1: Enable trace file generation.
• 1’b0: Disable trace file generation

• Default value: 1'b0
• Type: Dynamic

- Applicable only when trace_enable is set to 1’b1.

• When set to a non-null string, this string type attribute indicates the name of the transaction trace file generated by the monitor.
  • Eg: apb_sys_cfg.trace_file_name = “periph_i2c.log”;
  • Eg: apb_sys_cfg.slave_cfg[0].trace_file_name = “periph_slave_i2c.log”;
• When this is set to a null string (default value), the trace file name follows standard SVT VIP naming conventions.
• Note:
  • The string settings should follow the standard SystemVerilog string literal requirements. For example, should not include following charaters: [, ], \, :, /, "
  • In case there are multiple agents, user needs to ensure that the trace file name settings across the agents are unique for a given simulation.
• Default value: ""
• Type: Static

Enables transaction level coverage. This parameter also enables delay coverage. Delay coverage is coverage on wait states.
type: Dynamic

Enables coverage group apb state after reset deasserted. type: Static

Enables coverage for covergroup trans_apb_states_covered.
type: Static

Enables APB transaction coverage group for APB master_to_slave_path_access
type: Static

Enables coverage group for cross coverage between WRITE transaction type and PSTRB.
type: Static

Only applicable when svt_apb_system_configuration :: apb4_enable is set.

Enables coverage group for cross coverage between transaction type and address.
type: Static

Enables coverage group for cross coverage between transaction type and PPROT.
type: Static

Only applicable when svt_apb_system_configuration :: apb4_enable is set.

Enables coverage group for cross coverage between transaction type and PSLVERR.
type: Static

Enables coverage group for cross coverage between transaction type and number of wait states.
type: Static

Enables coverage group for coverage of a ERR response for a sequence of four transactions
type: Static

Enables coverage group for coverage of a sequence of four transactions
type: Static

Enables coverage group for default low value of PSLVERR signal and valid transitions of PSLVERR signal i.e only goes high when PREADY and PENABLE are 1
type: Static

Enables coverage group for coverage of if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when pdata_width is 16bit
type: Static

Only applicable when svt_apb_system_configuration :: apb4_enable is set.

Enables coverage group for coverage of if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when pdata_width is 32bit
type: Static

Only applicable when svt_apb_system_configuration :: apb4_enable is set.

Enables coverage group for coverage of if the RD/WR transfer is Aligned/Unaligned based on address and pstrb when pdata_width is 64bit
type: Static

Only applicable when svt_apb_system_configuration :: apb4_enable is set.

Enables coverage group x on prdata when pslverr=1.
type: Static

This attribute controls the unaligned address support. Enabling this configuration provides the VIP support for Unaligned transfers.

• This will generate unaligned addresses and perform any checks for the unaligned addresses which the manager generate.
• Subordinate will not flag any errors or warnings for unaligned addresses and manage the unaligned address by aligning it to appropriate aligned address and write/read for the correct byte lane using PSTRB or address alignment.

In active mode, creates an AMBA-PV-compatible socket that can be used to connect APB Master VIP component to an AMBA-PV master model.

Enabling this functionality causes the instantiation of socket b_fwd of type uvm_tlm_b_target_socket in class svt_apb_master_agent.

Generic payload transactions received through the forward b_fwd interface are executed on the tlm_generic_payload_sequencer in the agent.

When this option is set, it implies that use_tlm_generic_payload is also set, whether it actually is or not.

In active mode, creates a tlm_generic_payload_sequencer sequencer capable of generating UVM TLM Generic Payload transactions and connects the sequencer to it. The master sequencer starts a layering sequence that gets transactions from the tlm_generic_payload_sequencer, converts them to (one or more) APB transaction(s) and sends them to the driver.

APB transactions observed by the agent are also made available as TLM GP transactions through the tlm_generic_payload_observed_port in the monitor. Note that the TLM GP transactions issued through the analysis port may not match one to one with GP sequence items created by the tlm_generic_payload_sequencer because the GP sequence items may have to be mapped to multiple APB transactions according to protocol requirements. The TLM GP that is available through the tlm_generic_payload_observed_port of the monitor is a direct mapping of the observed APB transactions converted to a TLM GP. No attempt is made to re-assemble a set of APB transaction into a larger TLM GP.

The layering sequence that converts the TLM GP to APB transactions is the svt_apb_tlm_gp_to_apb_sequence and is available at $DESIGNWAREHOME/vip/svt/amba_svt//apb_master_agent_svt/sverilog/src/vcs/svt_apb_tlm_gp_sequence_collection.svp Transactions created by the layering sequence are of type cust_svt_tlm_gp_to_apb_master_transaction. Any user constraints specific to APB must be provided in a class extended from this class.

In passive mode, observed APB transactions are made available as TLM GP transactions through the tlm_generic_payload_observed_port in the monitor.

Randomizable variables