VIP Smartsearch

VIP Smartsearch is a framework that supports search within VIP reference documents using query in natural language. It facilitates reordering of search results and keeps record of user’s decision for the ordering of result display and applies that in search of same query on subsequent usage.
How to download VIP smartsearch?
1. Get VIP Smartsearch (Available as a seperate run file).
2. Set environment variable
```
DESIGNWARE_HOME
```
  to required designware home location where VIP Smartsearch should be downloaded.
3. Run
```
vip_smartsearch_<version>.run
```
  file.
  VIP Smartsearch will be downloaded to the location
```
$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>
```

How to install VIP Smartsearch?

Please refer to the file

VIP_Smartsearch_installation_and_usage_guide.pdf

$DESIGNWARE_HOME/vip/svt/vip_smartsearch/<version>

for installation steps.

Customer Support
For more details about VIP smartsearch tool, contact support_center@synopsys.com.
Mention your queries along with below details and send email to above email id.
Product: Verification IP
Sub Product: <vip_title>
Tool: VIP Smartsearch

Product Base	Group	Protocol Check Class
amba_svt	APB2	svt_apb_checker
APB3	svt_apb_checker
APB4 Protection Unit Support	svt_apb_checker
APB4 Write Strobes	svt_apb_checker
AHB System	svt_ahb_system_checker
AHB_COMMON	svt_ahb_checker
AHB_FULL	svt_ahb_checker
AHB_Lite	svt_ahb_checker
ARM11/AHB_V6 Exclusive Accesses	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	svt_ahb_checker
AHB5 Extended Memory Types	svt_ahb_checker
AHB5 Secure Transfers	svt_ahb_checker
AHB_Lite_Multilayer	svt_ahb_checker
CHI Link Layer	svt_chi_link_err_check
CHI Protocol Layer	svt_chi_protocol_err_check
SYSTEM: ACE	svt_axi_system_checker
SYSTEM: AXI3 Onwards	svt_axi_system_checker
PORT: AXI_LP	svt_axi_lp_checker
AXI5,ACE5_Lite	svt_axi_checker
ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE5,ACE5_LiteDVM	svt_axi_checker
AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE	svt_axi_checker
AXI3	svt_axi_checker
ACE,ACE_Lite	svt_axi_checker
ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE,ACE5	svt_axi_checker
ACE,ACE5,ACE5_LiteDVM	svt_axi_checker
ACE5_LiteDVM	svt_axi_checker
AXI4,AXI5	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
ACE5	svt_axi_checker
AXI5,ACE5,ACE5_Lite	svt_axi_checker
ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI3 Onwards	svt_axi_checker
AXI3,AXI4,AXI5,ACE5_Lite	svt_axi_checker
AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM	svt_axi_checker
AXI5_STREAM	svt_axi_checker
AXI4_STREAM,AXI5_STREAM	svt_axi_checker
None	svt_amba_system_checker
AMBA Multi Chip System	svt_amba_multi_chip_system_err_check
CHI System	svt_chi_system_err_check

Product Base

Group

Protocol Check Class

APB4 Protection Unit Support

svt_ahb_system_checker

ARM11/AHB_V6 Exclusive Accesses

svt_ahb_checker

ARM11/AHB_V6 Unaligned Transfers

svt_ahb_checker

AHB5 Extended Memory Types

svt_ahb_checker

AHB5 Secure Transfers

svt_chi_link_err_check

CHI Protocol Layer

svt_chi_protocol_err_check

SYSTEM: ACE

svt_axi_system_checker

SYSTEM: AXI3 Onwards

svt_axi_system_checker

ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

ACE5,ACE5_LiteDVM

svt_axi_checker

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

ACE,ACE5

svt_axi_checker

ACE,ACE5,ACE5_LiteDVM

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

ACE5,ACE5_Lite,ACE5_LiteDVM

ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI3 Onwards

svt_axi_checker

AXI3,AXI4,AXI5,ACE5_Lite

svt_axi_checker

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

svt_axi_checker

AXI5_STREAM

svt_axi_checker

AXI4_STREAM,AXI5_STREAM

svt_axi_checker

None

svt_amba_system_checker

AMBA Multi Chip System

svt_amba_multi_chip_system_err_check

CHI System

svt_chi_system_err_check

Group	Sub Group	Protocol Check Instance name	Reference	Description	Check Intent	Error Category	Protocol Check Class
APB2	State Transition	initial_bus_state_after_reset	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	After reset the bus initially should be in either IDLE or SETUP State	Checks that after reset de-assertion, APB Bus is in either IDLE or SETUP state.	ERROR	svt_apb_checker
APB2	Slave Selection	multiple_select_signals_active_during_transfer	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.4.2 APB bridge description	Only one select signal can be active during a transfer	Checks if multiple select signals asserted during transfer	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_prdata_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PRDATA must be valid when PSEL, PENABLE and PREADY are asserted for read transfer	Checks that PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer	ERROR	svt_apb_checker
APB2	Unaligned Transfers	address_not_aligned_when_unaligned_address_support_not_enabled	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus	Unaligned address should not be driven on PADDR when unaligned_address_support is not enabled	Checks if unaligned address is driven on PADDR when unaligned_address_support is not enabled.	WARNING	svt_apb_checker
APB2	Signal Stability	pwdata_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers	PWDATA must be stable until the write transfer completes	Checks if PWDATA changed value during write transfer	ERROR	svt_apb_checker
APB2	Signal Stability	pwrite_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PWRITE must be stable until the transfer completes	Checks if PWRITE changed value during transfer	ERROR	svt_apb_checker
APB2	Signal Stability	paddr_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PADDR must be stable until the transfer completes	Checks if PADDR changed value during transfer	ERROR	svt_apb_checker
APB2	Signal Stability	psel_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PSEL must be stable until the transfer completes	Checks if PSEL changed value during transfer	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_pwdata_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PWDATA must be valid when PSEL is asserted for write transfer	Checks that PWDATA is not X or Z when PSEL is asserted for write transfer	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_penable_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PENABLE must be valid when PSEL is asserted	Checks that PENABLE is not X or Z when PSEL is asserted	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_pwrite_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PWRITE must be valid when PSEL is asserted	Checks that PWRITE is not X or Z when PSEL is asserted	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_paddr_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PADDR must be valid when PSEL is asserted	Checks that PADDR is not X or Z when PSEL is asserted	ERROR	svt_apb_checker
APB2	Signal Validity	signal_valid_psel_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSEL must be always valid	Checks that PSEL is not X or Z	ERROR	svt_apb_checker
APB2	State Transition	penable_after_psel	AMBA APB Protocol Specification ARM IHI 0011A: 5.2.1 State diagram	PENABLE should be asserted after one clock cycle of PSEL being asserted	Checks that PENABLE is asserted after one clock cycle of PSEL being asserted.	ERROR	svt_apb_checker
APB2	Address Mapping	psel_match_with_address_map	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.5.2 APB slave description	Asserted PSEL should match with the address map	Checks that asserted PSEL matches with the address map. Refer to ARM IHI 0011A section 2.4, signal description of PSELx for the protocol info.	ERROR	svt_apb_checker
APB2	State Transition	setup_to_setup	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	SETUP to SETUP is an illegal state transition	Checks that if illegal state transition occured from setup to setup	ERROR	svt_apb_checker
APB2	APB2 State Transition	access_to_access	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	ACCESS to ACCESS is an illegal state transition in APB2	Checks that if illegal state transition occured from access to access in APB2. In APB3 state transition from access to access is valid transition.	ERROR	svt_apb_checker
APB2	State Transition	setup_to_idle	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	SETUP to IDLE is an illegal state transition	Checks that if illegal state transition occured from setup to idle	ERROR	svt_apb_checker
APB2	APB2 State Transition	bus_in_enable_state_for_one_clock	AMBA APB Protocol Specification ARM IHI 0011A: Section 5.2.1 State diagram	ENABLE state lasts only for a single clock cycle in APB2	Checks that bus remains in ENABLE state for one clock cycle in APB2	ERROR	svt_apb_checker
APB3	Signal Validity	signal_valid_pslverr_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSLVERR must be valid when PSEL, PENABLE and PREADY are asserted	Checks that PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted	ERROR	svt_apb_checker
APB3	Signal Validity	signal_valid_pready_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PREADY must be valid when PSEL and PENABLE are asserted	Checks that PREADY is not X or Z when PSEL and PENABLE are asserted	ERROR	svt_apb_checker
APB3	Transaction Timeout	pready_timeout_check	Synopsys Defined	PREADY should be asserted by the slave within the timeout period	Checks that PREADY signal is asserted by slave within timeout period slave_pready_timeout	ERROR	svt_apb_checker
APB3	Signal Stability	penable_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PENABLE must be stable until the transfer completes	Checks if PENABLE changed value during access phase of transfer	ERROR	svt_apb_checker
APB3	State Transition	idle_to_access	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states	IDLE to ACCESS is an illegal state transition	Checks that if illegal state transition occured from idle to access	ERROR	svt_apb_checker
APB4 Protection Unit Support	Signal Stability	pprot_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers	PPROT must be stable until the transfer completes	Checks if PPROT changed value during transfer	ERROR	svt_apb_checker
APB4 Protection Unit Support	Signal Validity	signal_valid_pprot_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PPROT must be valid when PSEL is asserted	Checks that PPROT is not X or Z when PSEL is asserted	ERROR	svt_apb_checker
APB4 Write Strobes	Signal Stability	pstrb_changed_during_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers	PSTRB must be stable until the transfer completes	Checks if PSTRB changed value during write transfer	ERROR	svt_apb_checker
APB4 Write Strobes	PSTRB Validity	pstrb_low_for_read	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.2 Write strobes	All bits of PSTRB must be LOW for read transfer	Checks that PSTRB is low for read transfer	ERROR	svt_apb_checker
APB4 Write Strobes	Signal Validity	signal_valid_pstrb_check	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules	PSTRB must be valid when PSEL is asserted	Checks that PSTRB is not X or Z when PSEL is asserted	ERROR	svt_apb_checker
APB4 Write Strobes	Unaligned Transfers	pstrb_asserted_for_invalid_byte_in_unaligned_transfer	AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus & 3.2 Write strobes	PSTRB should be correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled	Checks if PSTRB is correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled.	ERROR	svt_apb_checker
AHB System	Manager Subordinate Transaction Association	master_slave_xact_resp_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Response signals should match between manager transaction and the corresponding subordinate transaction.	Checks that response signals match between manager transaction and the corresponding subordinate transaction.	ERROR	svt_ahb_system_checker
AHB System	Manager Subordinate Transaction Association	master_slave_xact_data_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Data values should match between manager transaction and the corresponding subordinate transaction.	Checks that data values match between manager transaction and the corresponding subordinate transaction.	ERROR	svt_ahb_system_checker
AHB System	Manager Subordinate Transaction Association	master_slave_xact_addr_ctrl_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Address and control signals should match between manager transaction and the corresponding subordinate transaction.	Checks that address and control signals match between manager transaction and the corresponding subordinate transaction. Following control signal attributes are compared. addr xact_type burst_type burst_size prot_type	ERROR	svt_ahb_system_checker
AHB System	Dummy Manager	xact_not_idle_when_dummy_master_active	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus manager	Transfer type of the transaction is not IDLE when dummy manager is active.	Checks that IDLE transactions are driven when the dummy manager is active	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	hmastlock_changed_during_incr	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked transfers	HMASTLOCK signal changed during INCR burst transfer.	Checks that the HMASTLOCK signal remains constant during an INCR burst	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	arbiter_asserted_hmastlock_without_hlock	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers	Arbiter asserted HMASTLOCK signal when the manager has not requested.	Checks that the arbiter does not assert HMASTLOCK when the manager has not requested	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	arbiter_lock_last_grant	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers	Arbiter did not keep manager granted for an additional transfer after a locked sequence.	Checks that the arbiter keeps the manager granted for an additional transfer after a locked sequence	ERROR	svt_ahb_system_checker
AHB System	Locked Transfers in Arbiter	arbiter_changed_hmaster_during_lock	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers	HMASTER signal changed during locked transfer.	Checks that the arbiter does not change HMASTER during a locked transfer	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Split Transfer in Arbiter	mask_hgrant_until_hsplit_assert	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12.1 Split transfer sequence	Manager should not be regranted until the subordinate is ready to complete the transfer and asserts HSPLIT.	Checks that if the manager has got split, grant must be not given to that manager until subordinate asserts hsplitx	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Split Transfer in Arbiter	grant_to_default_master_during_allmaster_split	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus master	If all managers has received a SPLIT response then the default manager is granted the bus.	Checks that If all managers has received a SPLIT response then the default manager is granted the bus.	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Arbiter	arbiter_changed_hmaster_during_wait	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.11.3 Granting bus access	HMASTER signal changed during waited state.	Checks that the arbiter does not change HMASTER during a waited transfer	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Arbiter	arbiter_asserted_hmaster_ne_granted_master	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access	HMASTER signal does not reflect the granted manager.	Checks that the arbiter assert HMASTER to reflect the Granted manager	ERROR	svt_ahb_system_checker
AHB System	Granted Manager in Arbiter	arbiter_asserted_multi_hgrant	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access	Arbiter asserted more than one HGRANT signal.	Checks that the arbiter does not assert more than one HGRANT signal	ERROR	svt_ahb_system_checker
AHB System	Subordinate Selection in Decoder	decoder_not_asserted_any_hsel	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals	Decoder not asserted any HSEL signal.	Checks that the decoder does assert atleast one HSEL signal	ERROR	svt_ahb_system_checker
AHB System	Subordinate Selection in Decoder	decoder_asserted_multi_hsel	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals	Decoder asserted more than one HSEL signal.	Checks that the decoder does not assert more than one HSEL signal	ERROR	svt_ahb_system_checker
AHB System	Data Integrity	data_integrity_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921	Transaction data inconsistent with subordinate memory.	Checks that data in transaction is consistent with data in memory when the transaction completes. This checks that a WRITE transaction issued by a manager is written to memory correctly. Similarly, it checks that a READ transaction fetches the correct data from memory. The check assumes that a transaction issued by a manager completes only after response is received from the subordinate to which that transaction was routed. It also assumes that there is no other transaction that accesses an overlapping address during the period that the response is issued by the subordinate and the transaction completes in the manager that issued the transaction. Note that this check is not performed on the transactions that are routed to the default subordinate.	ERROR	svt_ahb_system_checker
AHB System	Routing	slave_transaction_routing_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.1 Interconnect	Transaction not routed to the correct subordinate based on system address map.	Checks that a transaction is routed correctly to a slave port based on address. This check is not performed on default_slave if the default slave is set to -1 through svt_ahb_system_configuration :: default_slave. If svt_ahb_system_configuration :: default_slave is set to a value in the range 0 to 15, then this check is performed on the default slave also. This check is preformed on all the slaves other than the default slave irrespective of the value of svt_ahb_system_configuration :: default_slave.	ERROR	svt_ahb_system_checker
AHB_COMMON	Address Phase Timing	ahb_address_phase_extended	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 1.3 Operation	A Subordinate cannot request that the address phase is extended.	Checks that address phase is not extended by the Subordinate	ERROR	svt_ahb_checker
AHB_COMMON	During Reset	hready_out_from_bus_high_during_reset	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset	During reset, HREADY output from bus must be HIGH	Checks that HREADY output signal from bus is HIGH when reset is active	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_write_throughput	SYNOPSYS DEFINED	Checks that the throughput of write transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of write transactions in a given interval is not less that the configured min value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_write_throughput	SYNOPSYS DEFINED	Checks that the throughput of write transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of write transactions in a given interval is not more that the configured max value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_read_throughput	SYNOPSYS DEFINED	Checks that the throughput of read transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of read transactions in a given interval is not less that the configured min value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_read_throughput	SYNOPSYS DEFINED	Checks that the throughput of read transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of read transactions in a given interval is not more that the configured max value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_min_read_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of read transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of read transactions in a given interval is not less than the configured min value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_max_read_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of read transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of read transactions in a given interval is not more than the configured max value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_read_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a read transaction is more than or equal to the configured min value	Checks that the latency of a read transaction is not lesser than the configured min value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_read_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a read transaction is less than or equal to the configured max value	Checks that the latency of a read transaction is not greater than the configured max value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_min_write_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of write transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of write transactions in a given interval is not less than the configured min value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_avg_max_write_xact_latency	SYNOPSYS DEFINED	Checks that the average latency of write transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of write transactions in a given interval is not more than the configured max value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_min_write_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a write transaction is more than or equal to the configured min value	Checks that the latency of a write transaction is not lesser than the configured min value	ERROR	svt_ahb_checker
AHB_COMMON	Performance Metrics	perf_max_write_xact_latency	SYNOPSYS DEFINED	Checks that the latency of a write transaction is less than or equal to the configured max value	Checks that the latency of a write transaction is not greater than the configured max value	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hrdata_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HRDATA must not be X/Z	Checks that HRDATA is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hwdata_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HWDATA must not be X/Z	Checks that HWDATA is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Response Type	zero_wait_cycle_okay	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	IDLE and BUSY transfers must receive zero wait cycle OKAY response.	Checks that IDLE and BUSY transfers receive zero wait cycle OKAY response	ERROR	svt_ahb_checker
AHB_COMMON	Two Cycle Response	two_cycle_error_resp	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response	ERROR response was not completed in two cycles.	Checks that ERROR response completes in two cycles	ERROR	svt_ahb_checker
AHB_COMMON	Response Type	non_okay_response_in_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.2 Transfer pending	Response other than OKAY response was received during wait state.	Checks that only OKAY responses are received during wait state	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hresp_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HRESP must not be X/Z	Checks that HRESP is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hready_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HREADY must not be X/Z	Checks that HREADY is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Burst Length	burst_length_exceeded	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Burst length exceeded for fixed length burst.	Checks number of beats in a fixed length burst	ERROR	svt_ahb_checker
AHB_COMMON	Locked Transfers	hlock_asserted_during_non_locked_xact	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.1 Signal description	Manager should not assert lock signal in the middle of a non-locked transaction.	Checks that manager shouldn't assert hlock in the middle of a non-locked transaction	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hlock_check	AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list	HLOCK must not be X/Z	Checks that HLOCK is not X or Z on manager interface	ERROR	svt_ahb_checker
AHB_COMMON	Locked Transfers	different_subordinate_addr_region_during_locked_sequence	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked Transfers	It is required that all transfers in a locked sequence are to the same Subordinate address region.	It is required that all transfers in a locked sequence are to the same subordinate address region.	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	htrans_not_changed_to_idle_during_error	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response	HTRANS did not change to IDLE during ERROR response.	Checks that HTRANS changes to IDLE during second cycle of ERROR response	ERROR	svt_ahb_checker
AHB_COMMON	During Reset	htrans_idle_during_reset	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset	During reset, HTRANS must be IDLE2'b00	Checks that HTRANS output signal from manager/bus is IDLE when reset is active	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	seq_or_busy_before_nseq_during_xfer	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Manager started burst with SEQ or BUSY instead of NSEQ.	Checks that a manager started burst with SEQ or BUSY instead of NSEQ	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	illegal_idle2seq	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Manager attempted SEQ transfer following IDLE.	Checks for IDLE changed to SEQ	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	illegal_idle2busy	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Manager attempted BUSY transfer following IDLE.	Checks for IDLE changed to BUSY	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	idle_changed_to_busy_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Manager cancelled IDLE transfer during wait state and changed it to BUSY transfer.	Checks for IDLE changed to BUSY during wait state	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	idle_changed_to_seq_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Manager cancelled IDLE transfer during wait state and changed it to SEQ transfer.	Checks for IDLE changed to SEQ during wait state	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	ctrl_or_addr_changed_during_busy	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Control signalsother than HTRANS or address changed during BUSY.	Checks whether control signals(other than HTRANS) or address changed during BUSY	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	illegal_control_transition	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals	Control signals other than HTRANS changed during burst.	Checks whether control signals(other than HTRANS) changed during burst	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	ahb_valid_beat_address_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	valid beat address check.	Checks for valid beat address of each beat in a transaction	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	illegal_address_transition	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Illegal address transition during burst.	Checks for illegal address transition during burst	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	boundry_crossing_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Burst transfer crossed boundary	Checks that burst transfer does not cross configured boundary limit	ERROR	svt_ahb_checker
AHB_COMMON	Burst Address	one_k_boundry_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation	Burst transfer crossed 1 KB boundary.	Checks that burst transfer does not cross 1 KB boundary	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Size	hsize_too_big_for_data_width	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.3.3 Implementing a Manager on a wide bus	Manager attempted transfer size greater than data bus width.	Checks that manager attempted transfer size greater than data bus width	ERROR	svt_ahb_checker
AHB_COMMON	Early Burst Termination	burst_terminated_early_after_okay	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination	Manager terminated burst early after OKAY response.	Checks that burst transaction was not terminated early: AHB manager should never terminate a burst transfer when OKAY response is received. In case of Full-AHB mode, the manager should rebuild the burst transfer in case of EBT/SPLIT/RETRY before initiating new burst.	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	hwdata_changed_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.1.1 HWDATA	HWDATA changed during wait state.	Checks that write data does not change during waited state	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	ctrl_or_addr_changed_end_of_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Control or address changed at the end of wait state.	Checks that control and address does not change at the end of wait state	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	ctrl_or_addr_changed_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	Control or address changed during wait state.	Checks that contol and address does not change during wait state except when htrans changes from IDLE to NSEQ	ERROR	svt_ahb_checker
AHB_COMMON	Signal Stability	htrans_changed_during_wait_state	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers	HTRANS changed during wait state.	Checks that htrans does not change during wait state except when htrans changes from IDLE to NSEQ during wait state for all burst types BUSY to SEQ during wait state for all burst types BUSY to NSEQ during wait state for unspecified length burst BUSY to IDLE during wait state for unspecified length burst	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	seq_or_busy_during_active_xact	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	In active transaction, SEQ or BUSY transfer should only occur after NSEQ.	Checks that a SEQ or BUSY trans only occur during active transaction after nseq	ERROR	svt_ahb_checker
AHB_COMMON	Transfer Type	trans_during_single_is_nseq	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types	Transfer type of a SINGLE burst is not NSEQ	Checks that transfer type of a SINGLE burst is NSEQ	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hprot_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HPROT must not be X/Z	Checks that HPROT is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hburst_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HBURST must not be X/Z	Checks that HBURST is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hsize_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HSIZE must not be X/Z	Checks that HSIZE is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_htrans_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HTRANS must not be X/Z	Checks that HTRANS is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hwrite_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HWRITE must not be X/Z	Checks that HWRITE is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_haddr_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HADDR must not be X/Z	Checks that HADDR is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	hready_out_from_slave_not_X_or_Z_when_data_phase_not_pending	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.3 Subordinate signals	HREADY output from subordinate must be either HIGH or LOW when there is no pending data phase.	Checks that HREADY output from subordinate must be either HIGH or LOW when there is no data phase pending. That is, checks that the subordinate cannot request that the address phase is extended.	ERROR	svt_ahb_checker
AHB_COMMON	During Reset	hready_out_from_slave_not_X_or_Z_during_reset	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset	During reset, HREADY output from subordinate must be either HIGH or LOW	Checks that HREADY output signal from subordinate is either HIGH or LOW when reset is active	ERROR	svt_ahb_checker
AHB_COMMON	Response Type	illegal_default_slave_resp_to_nseq_seq	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.1 Default Subordinate	Default subordinate should provide ERROR response for NON_SEQ or SEQ transfer.	Checks that for non existent memory location default subordinate should provide ERROR response for NSEQ/SEQ transfers	ERROR	svt_ahb_checker
AHB_COMMON	Subordinate Selection	invalid_hsel_assert_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.2 Multiple Subordinate select	Invalid HSEL signal asserted for selected subordinate	Checks that if invalid HSEL is asserted for selected subordinate. This is applicable only in mutli_hsel_enable mode	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hready_in_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HREADY_IN must not be X/Z	Checks that HREADY_IN is not X or Z	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hmastlock_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HMASTLOCK must not be X/Z	Checks that HMASTLOCK is not X or Z on subordinate interface	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hmaster_range_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals	HMASTER should not be beyond SVT_AHB_MAX_NUM_MASTERS	Checks that HMASTER value is in valid range based on SVT_AHB_MAX_NUM_MASTERS	ERROR	svt_ahb_checker
AHB_COMMON	Signal Validity	signal_valid_hsel_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HSEL must not be X/Z	Checks that HSEL is not X or Z	ERROR	svt_ahb_checker
AHB_FULL	Two Cycle Response	two_cycle_retry_resp	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	RETRY response was not completed in two cycles.	Checks that RETRY response completes in two cycles	ERROR	svt_ahb_checker
AHB_FULL	Two Cycle Response	two_cycle_split_resp	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	SPLIT response was not completed in two cycles.	Checks that SPLIT response completes in two cycles	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_idle_or_nseq_during_no_grant	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access	Manager should drive HTRANS to IDLE or NSEQ when it does not have access to the bus.	Checks that manager drives HTRANS to IDLE or NSEQ when it does not have access to the bus	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_retry	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during RETRY response.	Checks that HTRANS changes to IDLE during second cycle of RETRY response	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_split	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during SPLIT response.	Checks that HTRANS changes to IDLE during second cycle of SPLIT response	ERROR	svt_ahb_checker
AHB_FULL	Signal Validity	signal_valid_hbusreq_check	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access	HBUSREQ must not be X/Z	Checks that HBUSREQ is not X or Z	ERROR	svt_ahb_checker
AHB_FULL	Rebuild Transaction	rebuild_xact_with_valid_combination_of_bursts	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry	Manager should restart an interrupted burst with a valid combination of bursts.	Checks that the manager restarted an interrupted burst with a valid combination of bursts	ERROR	svt_ahb_checker
AHB_FULL	Rebuild Transaction	rebuild_xact_with_expected_addr	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry	Manager should restart an interrupted burst from the address of the aborted beat.	Checks that the manager restarted an interrupted burst from the address of the aborted beat	ERROR	svt_ahb_checker
AHB_FULL	Response Type	hsplit_asserted_for_non_split_master	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers	Subordinate should not assert HSPLIT corresponding to a manager it has not split earlier.	Checks that HSPLIT is not asserted for a manager that has not SPLIT earlier.	ERROR	svt_ahb_checker
AHB_FULL	Response Type	hsplit_asserted_for_one_cycle	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers	Subordinate should assert a bit of HSPLIT only for one clock cycle	Checks that HSPLIT is asserted for only one clock cycle	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_retry	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during RETRY response.	Checks that HTRANS changes to IDLE during second cycle of RETRY response	ERROR	svt_ahb_checker
AHB_FULL	Transfer Type	htrans_not_changed_to_idle_during_split	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response	HTRANS did not change to IDLE during SPLIT response.	Checks that HTRANS changes to IDLE during second cycle of SPLIT response	ERROR	svt_ahb_checker
AHB_FULL	Bus Grant	illegal_hgrant_on_split_resp	AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers	Manager should lose the bus once it gets the split response from the subordinate.	Checks that manager loses the bus once it gets the split response from the subordinate.	ERROR	svt_ahb_checker
AHB_FULL	Signal Validity	signal_valid_hgrant_check	AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list	HGRANT must not be X/Z	Checks that HGRANT is not X or Z	ERROR	svt_ahb_checker
AHB_FULL	Signal Validity	signal_valid_hmaster_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HMASTER must not be X/Z	Checks that HMASTER is not X or Z	ERROR	svt_ahb_checker
AHB_Lite	Response Type	ahb_lite_split_response	AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses	SPLIT response was received when configured as AHB Lite system.	Checks that SPLIT responses are not received when configured for AHB Lite	ERROR	svt_ahb_checker
AHB_Lite	Response Type	ahb_lite_retry_response	AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses	RETRY response was received when configured as AHB Lite system.	Checks that RETRY responses are not received when configured for AHB Lite	ERROR	svt_ahb_checker
ARM11/AHB_V6 Exclusive Accesses	Two Cycle Response	two_cycle_xfail_resp	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.3.1 Exclusive Access Protocol	XFAIL response was not completed in two cycles.	Checks that XFAIL response completes in two cycles	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Valid Unaligned Transfer	valid_unaligned_transfer	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1.2 Burst, Unaligned accesses and Byte Lane Strobes	HUNALIGN should be asserted for an unaligned transfer	Checks that HUNALIGN signal is correctly set for unaligned transfers. Based on ARMv6 AMBA Extension Spec (Document No: PR022-GENC-001011) section 3.1.2, example 3.1.2.2 in the document and ARM discussions following items are mandatory. It would be mandatory for any initiator using the ARM11 extensions generating an unaligned AHB transfer to drive HUNALIGN=1 If HUNALIGN=0 it tells the target that HADDR will be fully AHB v2.0 compliant and HADDR will be aligned to HSIZE	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Signal Stability	hunalign_changed_during_transfer	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HUNALIGN should not change in middle of a transfer	Checks that HUNALIGN output signal from manager dosenot changes its value in middle of a transfer	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Valid Byte Lane Strobes	valid_byte_lane_for_hbstrb	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HRDATA/HWDATA byte lanes corresponding to HBSTRB should be selected	Checks that HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB signal which have value 1	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Signal Validity	signal_valid_hunalign_check	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HUNALIGN must not be X/Z	Checks that HUNALIGN is not X or Z	ERROR	svt_ahb_checker
ARM11/AHB_V6 Unaligned Transfers	Signal Validity	signal_valid_hbstrb_check	ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes	HBSTRB must not be X/Z	Checks that HBSTRB is not X or Z	ERROR	svt_ahb_checker
AHB5 Extended Memory Types	Signal Validity	signal_valid_hprot_ex_range_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.9 Memory types	HPROT signal is not having the valid value	Checks that Extended_Memory_Type supporting HPROT[6:2] is having valid values	ERROR	svt_ahb_checker
AHB5 Secure Transfers	Signal Validity	signal_valid_hnonsec_check	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules	HNONSEC must not be X/Z	Checks that HNONSEC is not X or Z	ERROR	svt_ahb_checker
AHB_Lite_Multilayer	Rebuild Transaction	rebuild_xact_with_valid_combination_of_bursts	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination	Manager should restart an interrupted burst with a valid combination of bursts.	Checks that the manager restarted an interrupted burst with a valid combination of bursts	ERROR	svt_ahb_checker
AHB_Lite_Multilayer	Rebuild Transaction	rebuild_xact_with_expected_addr	AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination	Manager should restart an interrupted burst from the address of the aborted beat.	Checks that the manager restarted an interrupted burst from the address of the aborted beat	ERROR	svt_ahb_checker
CHI Link Layer	signal validity	valid_rxdatflit_signal_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit. Description : RXDATFLIT must not be X/Z when RXDATFLITV is asserted	RXDATFLIT must not be X/Z when RXDATFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_txdatflit_signal_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit. Description : TXDATFLIT must not be X/Z when TXDATFLITV is asserted	TXDATFLIT must not be X/Z when TXDATFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_reqflit_signal_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit. Description : REQFLIT must not be X/Z when REQFLITV is asserted	REQFLIT must not be X/Z when REQFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txdatlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATLCRDV must be 0 during reset	TXDATLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxdatflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATFLITV must be 0 during reset	RXDATFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txrsplcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPLCRDV must be 0 during reset	TXRSPLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxreqlcrdv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request L-Credit Valid Description : RXREQLCRDV must not be X/Z	RXREQLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxreqlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQLCRDV must be 0 during reset	RXREQLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_compstashdone_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : CompStashDone Description : Check fields for response VC flit of a CompStashDone	Response VC message fields must be set to valid values for a CompStashDone transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_stashdone_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : StashDone Description : Check fields for response VC flit of a StashDone	Response VC message fields must be set to valid values for a StashDone transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_dbidrespord_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : DBIDRespOrd Description : Check fields for response VC flit of a DBIDRespOrd	Response VC message fields must be set to valid values for a DBIDRespOrd transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsnpflitv_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop Flit Valid Description : RXSNPFLITV must not be X/Z	RXSNPFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsnpflitpend_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop Flit Pending Description : RXSNPFLITPEND must not be X/Z	RXSNPFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxrspflitv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Valid Description : RXRSPFLITV must not be X/Z	RXRSPFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxrspflitpend_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Pending Description : RXRSPFLITPEND must not be X/Z	RXRSPFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txreqlcrdv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request L-Credit Valid Description : TXREQLCRDV must not be X/Z	TXREQLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_rxrspflit_signal_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit. Description : RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted	RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxrspflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPFLITV must be 0 during reset	RXRSPFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txreqlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQLCRDV must be 0 during reset	TXREQLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxreqflitv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Valid Description : RXREQFLITV must not be X/Z	RXREQFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxreqflitpend_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Pending Description : RXREQFLITPEND must not be X/Z	RXREQFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxreqflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQFLITV must be 0 during reset	RXREQFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxrsplcrdv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response L-Credit Valid Description : RXRSPLCRDV must not be X/Z	RXRSPLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txreqflitv_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Valid Description : TXREQFLITV must not be X/Z	TXREQFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsnplcrdv_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop L-Credit Valid Description : RXSNPLCRDV must not be X/Z	RXSNPLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txreqflitpend_check	ARM-IHI0050E.b:13.8.1 Request,REQ ,channel	Spec Text : Request Flit Pending Description : TXREQFLITPEND must not be X/Z	TXREQFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxrsplcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPLCRDV must be 0 during reset	RXRSPLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txreqflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQFLITV must be 0 during reset	TXREQFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxlinkactivereq_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEREQ must be 0 during reset	RXLINKACTIVEREQ must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txlinkactiveack_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEACK must be 0 during reset	TXLINKACTIVEACK must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxlinkactivereq_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEREQ must not be X/Z	RXLINKACTIVEREQ must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxdatflitv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Valid Description : RXDATFLITV must not be X/Z	RXDATFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxdatflitpend_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Pending Description : RXDATFLITPEND must not be X/Z	RXDATFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txrsplcrdv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response L-Credit Valid Description : TXRSPLCRDV must not be X/Z	TXRSPLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txdatlcrdv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data L-Credit Valid Description : TXDATLCRDV must not be X/Z	TXDATLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxsactive_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : RXSACTIVE signal Description : RXSACTIVE must not be X/Z	RXSACTIVE must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txlinkactiveack_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEACK must not be X/Z	TXLINKACTIVEACK must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_txrspflit_signal_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit. Description : TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted	TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxdatlcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATLCRDV must be 0 during reset	RXDATLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txdatflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATFLITV must be 0 during reset	TXDATFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txrspflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPFLITV must be 0 during reset	TXRSPFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxlinkactiveack_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEACK must be 0 during reset	RXLINKACTIVEACK must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_txlinkactivereq_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEREQ must be 0 during reset	TXLINKACTIVEREQ must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxdatlcrdv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data L-Credit Valid Description : RXDATLCRDV must not be X/Z	RXDATLCRDV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txrspflitv_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Valid Description : TXRSPFLITV must not be X/Z	TXRSPFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txrspflitpend_check	ARM-IHI0050E.b:13.8.2 Response,RSP ,channel	Spec Text : Response Flit Pending Description : TXRSPFLITPEND must not be X/Z	TXRSPFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txdatflitv_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Valid Description : TXDATFLITV must not be X/Z	TXDATFLITV must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txdatflitpend_check	ARM-IHI0050E.b:13.8.4 Data,DAT ,channel	Spec Text : Data Flit Pending Description : TXDATFLITPEND must not be X/Z	TXDATFLITPEND must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_rxlinkactiveack_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEACK must not be X/Z	RXLINKACTIVEACK must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txsactive_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : TXSACTIVE signal Description : TXSACTIVE must not be X/Z	TXSACTIVE must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	signal_valid_txlinkactivereq_check	ARM-IHI0050E.b:14: Link Handshake	Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEREQ must not be X/Z	TXLINKACTIVEREQ must not be X/Z. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_lcredit_range_check	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : The minimum number of L-Credits that a Receiver can provide is one.The maximum number of L-Credits that a Receiver can provide is 15 Description : The l-credit must be within the valid range	The minimum number of L-Credits that a receiver can provide is one. The maximum number of L-Credits that a receiver can provide is defined as follows based on vc_id RXREQ: svt_chi_node_configuration :: rx_req_vc_flit_buffer_size RXDAT: svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size RXRSP: svt_chi_node_configuration :: rx_rsp_vc_flit_buffer_size RXSNP: svt_chi_node_configuration :: rx_snp_vc_flit_buffer_size	ERROR	svt_chi_link_err_check
CHI Link Layer	link deactivation	tx_link_deactive_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner Description : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner	Link deactivation must complete in a timely manner in response to a received request.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	tx_link_active_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner Description : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner	Link activation must complete in a timely manner in response to a received request.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	tx_link_not_active_during_flit_transfer	ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake	Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be sent on its virtual channel only if the link is active.	Flits must not be transmitted while the link is not active	ERROR	svt_chi_link_err_check
CHI Link Layer	link deactivation	rx_link_deactive_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If a component moves the TXLINK to the DEACTIVATE state, which it controls, it can expect the RXLINK to also move to the DEACTIVATE state, in a timely manner Description : If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner	Link deactivation must complete in a timely manner in response to a received request. If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	rx_link_active_request_timeout_check	ARM-IHI0050E.b:14.6.1 Introduction	Spec Text : If a component moves the TXLINK to the ACTIVATE state, which it controls, it can expect the RXLINK to also move to the ACTIVATE state, in a timely manner Description : If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner	Link activation must complete in a timely manner in response to a received request. If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner.	ERROR	svt_chi_link_err_check
CHI Link Layer	link activation	rx_link_not_active_during_flit_reception	ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake	Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be observed on its RX virtual channel only if the corresponding link is active.	Flits must be observed only when the link is active	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	invalid_data_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : DAT channel opcodes encoding Description : Check for Reserved opcode bits for Data VC commands	Reserved (opcodes) Data VC commands cannot be used.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_lcrdreturn_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : DatLCrdReturn Description : Check fields for a DataLCrdReturn flit	Data VC message fields must be set to valid values for a DataLCrdReturn transaction	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_lcrdreturn_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : RspLCrdReturn Description : Check fields for a RspLCrdReturn flit	Response VC message fields must be set to valid values for a RspLCrdReturn transaction	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_lcrdreturn_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReqLCrdReturn Description : Check fields for a ReqLCrdReturn flit	Request VC message fields must be set to valid values for a ReqLCrdReturn transaction	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_tagmatch_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : TagMatch Description : Check fields for response VC flit of a TagMatch transaction	Response VC message fields must be set to valid values for a TagMatch transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	invalid_rsp_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : RSP channel opcodes encoding Description : Check for Reserved opcode bits for Response VC commands	Reserved (opcodes) Response VC commands cannot be used.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_datasepresp_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : DataSepResp Description : Check fields for data VC flit of a DataSepResp	Data VC message fields must be set to valid values for a DataSepResp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_compdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : CompData Description : Check fields for data VC flit of a CompData transaction	Data VC message fields must be set to valid values for a CompData transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_pcrdgrant_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : PCrdGrant Description : Check fields for response VC flit of a PCrdGrant transaction	Response VC message fields must be set to valid values for a PCrdGrant transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_dbidresp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : DBIDResp Description : Check fields for response VC flit of a DBIDResp transaction	Response VC message fields must be set to valid values for a DBIDResp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_compdbidresp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : CompDBIDResp Description : Check fields for response VC flit of a CompDBIDResp transaction	Response VC message fields must be set to valid values for a CompDBIDResp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_compcmo_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : CompCMO Description : Check fields for response VC flit of a CompCMO response	Response VC message fields must be set to valid values for a CompCMO response.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_persist_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : Persist Description : Check fields for response VC flit of a Persist response	Response VC message fields must be set to valid values for a Persist response to a CompPersistSep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_comppersist_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : CompPersist Description : Check fields for response VC flit of a CompPersist response	Response VC message fields must be set to valid values for a CompPersist response to CleanSharedPersistSep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_comp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : Comp Description : Check fields for response VC flit of a Comp transaction	Response VC message fields must be set to valid values for a Comp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_retryack_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : RetryAck Description : Check fields for response VC flit of a RetryAck transaction	Response VC message fields must be set to valid values for a RetryAck transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_ncbwrdatacompack_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : NCBWrDataCompAck Description : Check fields for data VC flit of a NcbWrDataCompack flit	Data VC message fields must be set to valid values for a NCBWrDataCompAck transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readnosnpsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadNoSnpSep Description : Check fields for request VC flit of a ReadNoSnpSep transaction	Request VC message fields must be set to valid values for a ReadNoSnpSep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_respsepdata_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : RespSepData Description : Check fields for response VC flit of a RespSepData	Response VC message fields must be set to valid values for a RespSepData transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	valid_xact_attributes_combination_check	ARM-IHI0050E.b:2.9.4 Transaction attribute combinations	Spec Text : Legal combinations of MemAttr, SnpAttr, and Order field values Description : check combinations of MemAttr, SnpAttr, LikelyShared and Order for a transaction	Transaction attributes in the Request VC message must take valid combinations.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	invalid_req_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : REQ channel opcodes Description : Check for Reserved opcode bits for Request VC commands	Reserved (opcodes) Request VC commands cannot be used.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_writedatacancel_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : WriteDataCancel Description : Check fields for data VC flit of a WriteDataCancel transaction	Data VC message fields must be set to valid values for a writedatacancel transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_noncopybackwrdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : NonCopyBackWrData Description : Check fields for data VC flit of a NonCopyBackWrData transaction	Data VC message fields must be set to valid values for a NonCopyBackWrData transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readnosnp_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadNoSnp Description : Check fields for request VC flit of a ReadNoSnp transaction	Request VC message fields must be set to valid values for a ReadNoSnp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpptl_cleansharedpersistsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpPtlCleanShPerSep Description : Check fields for request VC flit of a WriteNoSnpPtl_CleanSharedpersistsep transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpPtl_CleanSharedpersistsep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpfull_cleansharedpersistsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpFullCleanShPerSep Description : Check fields for request VC flit of a WriteNoSnpFull_CleanSharedpersistsep transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpFull_CleanSharedpersistsep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpptl_cleaninvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpPtlCleanInv Description : Check fields for request VC flit of a WriteNoSnpPtl_CleanInvalid transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpPtl_CleanInvalid transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpptl_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpPtlCleanSh Description : Check fields for request VC flit of a WriteNoSnpPtl_CleanShared transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpPtl_CleanShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpfull_cleaninvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpFullCleanInv Description : Check fields for request VC flit of a WriteNoSnpFull_CleanInvalid transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpFull_CleanInvalid transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpfull_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpFullCleanSh Description : Check fields for request VC flit of a WriteNoSnpFull_CleanShared transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpFull_CleanShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpzero_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpZero Description : Check fields for request VC flit of a WriteNoSnpZero transaction	Request VC message fields must be set to valid values for a WriteNoSnpZero transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleansharedpersistsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanSharedPersistSep Description : check fields for request VC flit of a CleanSharedPersistSep transaction	Request VC message fields must be set to valid values for a CleanSharedPersistSep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpFull Description : Check fields for request VC flit of a WriteNoSnpFull transaction	Request VC message fields must be set to valid values for a WriteNoSnpFull transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writenosnpptl_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteNoSnpPtl Description : Check fields for request VC flit of a WriteNoSnpPtl transaction	Request VC message fields must be set to valid values for a WriteNoSnpPtl transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_pcrdreturn_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : PCrdReturn Description : Check fields for request VC flit of a PCrdReturn transaction	Request VC message fields must be set to valid values for a PCrdReturn transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_stashoncesepshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : StashOnceSepShared Description : check fields for request VC flit of an StashOnceSepShared transaction	Request VC message fields must be set to valid values for an StashOnceSepShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_stashoncesepunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : StashOnceSepUnique Description : check fields for request VC flit of an StashOnceSepUnique transaction	Request VC message fields must be set to valid values for an StashOnceSepUnique transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_stashonceshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : StashOnceShared Description : check fields for request VC flit of an StashOnceShared transaction	Request VC message fields must be set to valid values for an StashOnceShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_stashonceunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : StashOnceUnique Description : check fields for request VC flit of an StashOnceUnique transaction	Request VC message fields must be set to valid values for an StashOnceUnique transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniquefullstash_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniqueFullStash Description : check fields for request VC flit of an WriteUniquefullstash transaction	Request VC message fields must be set to valid values for an WriteUniquefullstash transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniqueptlstash_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniquePtlStash Description : check fields for request VC flit of an WriteUniquePtlstash transaction	Request VC message fields must be set to valid values for an WriteUniquePtlstash transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_prefetchtgt_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : PrefetchTgt Description : Check fields for request VC flit of a Prefetch transaction	Request VC message fields must be set to valid values for a Prefetch transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readoncemakeinvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadOnceMakeInvalid Description : check fields for request VC flit of a ReadOnceMakeInvalid transaction	Request VC message fields must be set to valid values for a ReadOnceMakeInvalid transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readoncecleaninvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadOnceCleanInvalid Description : check fields for request VC flit of a ReadOnceCleanInvalid transaction	Request VC message fields must be set to valid values for a ReadOnceCleanInvalid transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_compack_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : CompAck Description : Check fields for response VC flit of a CompAck transaction	Response VC message fields must be set to valid values for a CompAck transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readonce_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadOnce Description : Check fields for request VC flit of a ReadOnce transaction	Request VC message fields must be set to valid values for a ReadOnce transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniquefull_cleansharedpersistsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniqueFullCleanShPerSep Description : Check fields for request VC flit of a WriteUniqueFull_CleanSharedpersistsep transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniqueFull_CleanSharedpersistsep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniqueptl_cleansharedpersistsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniquePtlCleanShPerSep Description : Check fields for request VC flit of a WriteUniquePtl_CleanSharedpersistsep transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniquePtl_CleanSharedpersistsep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniqueptl_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniquePtlCleanSh Description : Check fields for request VC flit of a WriteUniquePtl_CleanShared transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniquePtl_CleanShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniquefull_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniqueFullCleanSh Description : Check fields for request VC flit of a WriteUniqueFull_CleanShared transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniqueFull_CleanShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readpreferunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadPreferUnique Description : Check fields for request VC flit of a ReadPreferUnique transaction	Request VC message fields must be set to valid values for a ReadPreferUnique transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_makereadunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : MakeReadUnique Description : Check fields for request VC flit of a MakeReadUnique transaction	Request VC message fields must be set to valid values for a MakeReadUnique transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniquezero_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniqueZero Description : Check fields for request VC flit of a WriteUniqueZero transaction	Request VC message fields must be set to valid values for a WriteUniqueZero transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniquefull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniqueFull Description : Check fields for request VC flit of a WriteUniqueFull transaction	Request VC message fields must be set to valid values for a WriteUniqueFull transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeuniqueptl_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteUniquePtl Description : Check fields for request VC flit of a WriteUniquePtl transaction	Request VC message fields must be set to valid values for a WriteUniquePtl transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_makeinvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : MakeInvalid Description : Check fields for request VC flit of a MakeInvalid transaction	Request VC message fields must be set to valid values for a MakeInvalid value for transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleaninvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanInvalid Description : Check fields for request VC flit of a CleanInvalid transaction	Request VC message fields must be set to valid values for a CleanInvalid value for transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanShared Description : Check fields for request VC flit of a CleanShared transaction	Request VC message fields must be set to valid values for a CleanShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_atomiccompare_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : AtomicCompare Description : check fields for request VC flit of an AtomicCompare transaction	Request VC message fields must be set to valid values for an AtomicCompare transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_atomicswap_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : AtomicSwap Description : check fields for request VC flit of an AtomicSwap transaction	Request VC message fields must be set to valid values for an AtomicSwap transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_atomicload_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : AtomicLoad Description : check fields for request VC flit of an AtomicLoad transaction	Request VC message fields must be set to valid values for an AtomicLoad transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_atomicstore_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : AtomicStore Description : check fields for request VC flit of an AtomicStore transaction	Request VC message fields must be set to valid values for an AtomicStore transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleansharedpersist_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanSharedPersist Description : check fields for request VC flit of a CleanSharedPersist transaction	Request VC message fields must be set to valid values for a CleanSharedPersist transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	invalid_snp_flit_check	ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode	Spec Text : SNP channel opcodes encoding Description : Check for Reserved opcode bits for Snoop VC commands	Reserved (opcodes) Snoop VC commands cannot be used.	ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	snoop_flit_lcrdreturn_check	ARM-IHI0050E.b:A.4 Snoop Request message field mappings	Spec Text : SnpLCrdReturn Description : Check fields for a SnpLCrdReturn flit	Data VC message fields must be set to valid values for a SnoopLCrdReturn transaction	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_snpflit_signal_check	ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel	Spec Text : Snoop Flit. Description : SNPFLIT must not be X/Z when SNPFLITV is asserted	SNPFLIT must not be X/Z when SNPFLITV is asserted. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxsnpflitv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPFLITV must be 0 during reset	RXSNPFLITV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	snoop_flit_snpdvmop_check	ARM-IHI0050E.b:A.4 Snoop Request message field mappings	Spec Text : SnpDVMOp Description : Check fields for snoop VC flit of a SnpDVMOp transaction	Snoop VC message fields must be set to valid values for a SnpDVMOp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	During reset	signal_valid_rxsnplcrdv_during_reset	ARM-IHI0050E.b:14.1.3 Initialization	Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPLCRDV must be 0 during reset	RXSNPLCRDV must be 0 during reset i.e. when reset is active. Performed from second clock edge onwards once the reset is asserted	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_snprespfwded_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : SnpRespFwded Description : Check fields for response VC flit of a SnpRspFwded transaction	Response VC message fields must be set to valid values for a SnpRspFwded transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_snpresp_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : SnpResp Description : Check fields for response VC flit of a SnpRsp transaction	Response VC message fields must be set to valid values for a SnpRsp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_dvmop_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : DVMOp Description : Check fields for request VC flit of a DVMOp transaction	Request VC message fields must be set to valid values for a DVMOp transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	rsp flit valid	rsp_flit_readreceipt_check	ARM-IHI0050E.b:A.2 Response message field mappings	Spec Text : ReadReceipt Description : Check fields for response VC flit of a ReadReceipt transaction	Response VC message fields must be set to valid values for a ReadReceipt transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_ecbarrier_check	ARM-IHI0050A:A.1 Request message field mappings	Check fields for request VC flit of a ECBarrier transaction	Request VC message fields must be set to valid values for a ECBarrier transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_eobarrier_check	ARM-IHI0050A:A.1 Request message field mappings	Check fields for request VC flit of a EOBarrier transaction	Request VC message fields must be set to valid values for a EOBarrier transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	snp flit valid	snoop_flit_snpreq_check	ARM-IHI0050E.b:A.4 Snoop Request message field mappings	Spec Text : Snoop Request message Description : Check fields for snoop VC flit of a Snoop transaction	Snoop VC message fields must be set to valid values for a Snoop transaction (non-DVMOp).	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writebackfull_cleansharedpersistsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteBackFullCleanShPerSep Description : check fields for request VC flit of a WriteBackFull_CleanSharedpersistsep transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteBackFull_CleanSharedpersistsep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writecleanfull_cleansharedpersistsep_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteCleanFullCleanShPerSep Description : check fields for request VC flit of a WriteCleanFull_CleanSharedpersistsep transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteCleanFull_CleanSharedpersistsep transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writecleanfull_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteCleanFullCleanSh Description : check fields for request VC flit of a WriteCleanFull_CleanShared transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteCleanFull_CleanShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writebackfull_cleaninvalid_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteBackFullCleanInv Description : check fields for request VC flit of a WriteBackFull_CleanInvalid transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteBackFull_CleanInvalid transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writebackfull_cleanshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteBackFullCleanSh Description : check fields for request VC flit of a WriteBackFull_CleanShared transaction	Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteBackFull_CleanShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeevictorevict_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteEvictOrEvict Description : check fields for request VC flit of a WriteEvictorEvict transaction	Request VC message fields must be set to valid values for a WriteEvictorEvict transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_snprespdataptl_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : SnpRespDataPtl Description : Check fields for data VC flit of a SnpRespDataPtl transaction	Data VC message fields must be set to valid values for a SnpRespDataPtl transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_copybackwrdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : CopyBackWrData Description : Check fields for data VC flit of a CopyBackWrData transaction	Data VC message fields must be set to valid values for a CopyBackWrData transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_snprespdatafwded_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : SnpRespDataFwded Description : Check fields for data VC flit of a SnpRespDatafwded transaction	Data VC message fields must be set to valid values for a SnpRespDataFwded transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	data_flit_snprespdata_check	ARM-IHI0050E.b:A.3 Data message field mappings	Spec Text : SnpRespData Description : Check fields for data VC flit of a SnpRespData transaction	Data VC message fields must be set to valid values for a SnpRespData transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_evict_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : Evict Description : Check fields for request VC flit of a Evict transaction	Request VC message fields must be set to valid values for a Evict transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writecleanptl_check	ARM-IHI0050A:A.1 Request message field mappings	Check fields for request VC flit of a WriteCleanPtl transaction	Request VC message fields must be set to valid values for a WriteCleanPtl transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writebackptl_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteBackPtl Description : Check fields for request VC flit of a WriteBackPtl transaction	Request VC message fields must be set to valid values for a WriteBackPtl transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writeevictfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteEvictFull Description : Check fields for request VC flit of a WriteEvictFull transaction	Request VC message fields must be set to valid values for a WriteEvictFull transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writecleanfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteCleanFull Description : Check fields for request VC flit of a WriteCleanFull transaction	Request VC message fields must be set to valid values for a WriteCleanFull transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_writebackfull_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : WriteBackFull Description : Check fields for request VC flit of a WriteBackFull transaction	Request VC message fields must be set to valid values for a WriteBackFull transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_makeunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : MakeUnique Description : Check fields for request VC flit of a MakeUnique transaction	Request VC message fields must be set to valid values for a MakeUnique transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_cleanunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : CleanUnique Description : Check fields for request VC flit of a CleanUnique transaction	Request VC message fields must be set to valid values for a CleanUnique transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readunique_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadUnique Description : Check fields for request VC flit of a ReadUnique transaction	Request VC message fields must be set to valid values for a ReadUnique transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readclean_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadClean Description : Check fields for request VC flit of a ReadClean transaction	Request VC message fields must be set to valid values for a ReadClean transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readnotshareddirty_check	ARM-IHI0050E.b:A.1 Request message field mappings	check fields for request VC flit of a ReadNotSharedDirty transaction, ARM-IHI0050E.b:A.1 Request message field mappings	Request VC message fields must be set to valid values for a ReadNotSharedDirty transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	req flit valid	req_flit_readshared_check	ARM-IHI0050E.b:A.1 Request message field mappings	Spec Text : ReadShared Description : check fields for request VC flit of a ReadShared transaction	Request VC message fields must be set to valid values for a ReadShared transaction.	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_num_prot_flits_in_txlasm_deactivate_state_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : The Transmitter must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit Description : The Transmitter in Deactivate state is allowed to transmit protocol flits For each additional credit received it must send an L-Credit return flit to return the credit.	The maximum number of protocol flits that a transmitter (per channel) can send in Deactivate state is the number of l-credits available at the time of entry into Deactivate state. In other words, The Transmitter in Deactivate state must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit.	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_lcredit_count_in_rx_stop_state_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : Before entering a low power state, the sending of payload flits must be stopped and all credits must be returned to the Receiver Description : The reciever must ensure that it has received all the lcredits before moving to the stop state	The reciever must ensure that it has received all the lcredits before moving to the stop state i.e before deasserting the RXLINKACTIVEACK signal. Applicable channels: RN_I: RXRSP VC and RXDAT VC RN_F/RN_D: RXSNP VC, RXRSP VC and RXDAT VC SN: RXREQ VC and RXDAT VC	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	rx_no_lcredit_issued_for_flit_type	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : When the link is active, the Receiver must provide L-Credits in a timely manner without requiring any action on the part of the Transmitter Description : When the link is active, the receiver at each virtual channel must distribute L-credits for all its flit buffers in a timely manner without requiring any action on the part of the transmitter.	Checks if credits are sent, in a timely manner, by the corresponding active node. While the number of available L-Credits is less than the configured number of L-Credits (rx_\*_vc_flit_buffer_size in svt_chi_node_configuration), an L-Credit should be returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.	ERROR	svt_chi_link_err_check
CHI Link Layer	port interleaving	port_interleaving_check	SYNOPSYS DEFINED:SYNOPSYS DEFINED	Monitor checks that if interleaved port is expected port for the given flit	Checks if address does fall to correct interleaved port. Valid when node cfg svt_chi_node_configuration :: port_interleaving_enable = 1. Applicable for snoop transactions in case of active and passive RN. Applicable for RN transactions in case of passive RN.	ERROR	svt_chi_link_err_check
CHI Link Layer	dat flit valid	unexpected_poison_value_in_dat_flit_check	SYNOPSYS DEFINED:SYNOPSYS DEFINED	The Poison field in the data flits must be set to all zeroes	Check that the poison field in set to zero in the data flits observed at the node.	ERROR	svt_chi_link_err_check
CHI Link Layer	reserved fields	illegal_reserved_fields_check	ARM-IHI0050E.b:13.9 Flit packet definitions	Spec Text : The following key is used: SBZ Should Be Zero Description : The reserved fields in a flit must be set to zero as defined in CHI Specification.	Check that reserved fields in a flit must be set to zero as per the CHI specification (Section 13.9 Flit packet definitions).	ERROR	svt_chi_link_err_check
CHI Link Layer	SYSCO Interface FSM	sysco_interface_illegal_state_transition	ARM-IHI0050E.b:15.2 Handshake	Spec Text : SYSCOREQ can only change when SYSCOACK is at the same logic state Description : Transition of SYSCO Interface state must be valid	Illegal transition of the SYSCO Interface State. This check monitors the SYSCOREQ and SYSCOACK signals and records illegal state transitions.	ERROR	svt_chi_link_err_check
CHI Link Layer	signal validity	valid_flitpend_and_flitv_signal_check	ARM-IHI0050E.b:14.4 Flit level clock gating	Spec Text : It is required that the signal is asserted exactly one cycle before a flit is sent from the Transmitter Description : FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter	FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_entry_into_banned_output_race_state_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : The red states can only be reached by observing a race between two output signals. A race between two outputs is not permitted at the edge of a component and therefore the transition into these states is labeled with Banned Output Race Description : The component's Link Active State Machine entry into Banned Output Race state condition is not expected.	lasm is acronym for "Link Active State Machine". A given component's Link Active State Machine entry into Banned Output Race states can happen when there is a race condition at the output signals of the local component. A given component's Link Active State Machine entry into Banned Output Race states results in the connected link partner component being entering Async Input Race States. When a component’s Link Active State Machine entry into Banned Output Race state is observed this check will fail, if not the check will pass. This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected is set to 0.	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	illegal_tx_rx_state_transition_combinations_from_async_input_race_state	ARM-IHI0050E.b:14.6.3 Expected transitions	Combination of Tx and Rx link active state machine together from async input race combination must be valid	Check to monitor the illegal Tx and Rx link active state combinations from the async input race states for a given node Legal Tx and Rx link active state combinations from the async input race states are: TXRUN+/RXSTOP to TXRUN/RXACT TXACT/RXDEACT+ to TXRUN/RXDEACT TXSTOP+/RXRUN to TXSTOP/RXDEACT TXDEACT/RXACT+ to TXSTOP/RXDEACT	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_entry_into_async_input_race_state_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : The yellow states can only be reached by observing a race between two input signals. The transition into these states is labeled with Async Input Race Description : The component's Link Active State Machine entry into Async Input Race state condition is not expected.	lasm is acronym for "Link Active State Machine". A given component Link Active State Machine entry into Async Input Race States can only be reached by observing a race between the two input signals. In other words, entry into Async Input Race states for a given component can happen only when the connected link partner component observes a Banned Output Signal race condition. A given component Link Active State Machine entry into Async Input Race state implies that the connected link partner copmonent has entered Banned Output Race state. When a component’s Link Active State Machine entry into Async Input Race state is observed this check will fail, if not the check will pass. This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 0.	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_in_banned_output_race_state_timeout_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Banned Output Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by local component.	lasm is acronym for "Link Active State Machine". A given components Link Active State Machine entry into Banned Output Race states can happen when there is Async Input Signal race condition at the connected link partner component. The component observing Link Active States corresponding to Banned Output race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component. When a component’s state machine stays in Banned Output Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued. This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	lasm_in_async_input_race_state_timeout_check	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Async Input Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by link partner component.	lasm is acronym for "Link Active State Machine". A given components Link Active State Machine entry into Async Input Race states can happen when there is a Banned Output Signal race condition at the connected link partner component. The component observing Link Active States corresponding to Async Input race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component. When a component’s state machine stays in Async Input Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued. This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	illegal_tx_rx_state_transition_combinations_from_banned_output_race_state	ARM-IHI0050E.b:14.6.3 Expected transitions	Combination of Tx and Rx link active state machine together from banned output race combination must be valid	Check to monitor the illegal Tx and Rx link active state combinations from the banned output race states for a given node Legal Tx and Rx link active state combinations from the banned output race states are: TXSTOP/RXRUN to TXACT/RXRUN TXRUN/RXSTOP to TXDEACT/RXSTOP TXDEACT/RXACT to TXDEACT/RXRUN TXACT/RXDEACT to TXACT/RXSTOP	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	illegal_tx_rx_state_transition_combinations	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : Stop/Stop to Run/Run state paths Description : Combination of Tx and Rx link active state machine together must be valid	Check to monitor the following illegal Tx and Rx link active state combinations for a given node: TXSTOP/RXRUN TXRUN/RXSTOP TXDEACT/RXACT TXACT/RXDEACT	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	rx_illegal_state_transition	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Rx link active state machine must be valid	Illegal transition of the Receiver Interface State. This check monitors the RXLINKACTIVEREQ and RXLINKACTIVEACK signals and records illegal state transitions.	ERROR	svt_chi_link_err_check
CHI Link Layer	link active sm	tx_illegal_state_transition	ARM-IHI0050E.b:14.6.3 Expected transitions	Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Tx link active state machine must be valid	Illegal transition of the Transmitter Interface State. This check monitors the TXLINKACTIVEREQ and TXLINKACTIVEACK signals and records illegal state transitions.	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	valid_lcredit_count_in_tx_stop_state_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : The Transmitter has no credits and must not send any flits Description : All the applicable lcredit counter should be zero in tx stop state	When Tx is in stop state all the applicable lcredit counters should be 0. The Interconnect should not deassert the TXLINKACTIVEACK signal before it has recieved back all the lcredits. RN: TXREQ VC: txreq_lcrd_count should be 0. TXRSP VC: txrsp_lcrd_count should be 0. TXDAT VC: txdat_lcrd_count should be 0. SN: TXRSP VC: txrsp_lcrd_count should be 0. TXDAT VC: txdat_lcrd_count should be 0.	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	invalid_lcredit_check	ARM-IHI0050E.b:14.5 Interface activation and deactivation	Spec Text : The Receiver must not send any credits Description : The receiver must not send lcredit in stop and activate state.	The receiver must not send lcredit in stop and activate state.	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	tx_lcredit_used_same_cycle_which_recieved	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : An L-Credit cannot be used in the cycle it is received Description : An L-credit cannot be used in the cycle it is received.	Flits must not be transmitted on the same cycle that a credit is received	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	rx_no_lcredit_sent_for_flit_transfer	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : On exit from reset, credits are held by the Receiver and must be passed to the Transmitter before flit transfer can begin Description : A flit can be sent on its virtual channel only if a corresponding L-credit is available at the transmitter and the link is active.	Credits must be available for every transmitted Flit	ERROR	svt_chi_link_err_check
CHI Link Layer	l-credit	tx_no_lcredit_for_flit_transfer	ARM-IHI0050E.b:14.2 Link layer Credit	Spec Text : On exit from reset, credits are held by the Receiver and must be passed to the Transmitter before flit transfer can begin Description : A flit can be sent on its virtual channel only if a corresponding L-credit is available at the transmitter and the link is active.	Credits must be available for every transmitted Flit	ERROR	svt_chi_link_err_check
CHI Protocol Layer	Node performance metrics	perf_min_write_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of write transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of write transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_write_throughput	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_write_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of write transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of write transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_write_throughput	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_min_read_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of read transactions in a given interval is more than or equal to the configured min value	Checks that the throughput of read transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_read_throughput	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_read_throughput_check	SYNOPSYS DEFINED	Monitor Check that the throughput of read transactions in a given interval is less than or equal to the configured max value	Checks that the throughput of read transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_read_throughput	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_min_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of read transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of read transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_read_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_max_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of read transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of read transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_read_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_min_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a read transaction is more than or equal to the configured min value	Checks that the latency of a read transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_read_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_read_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a read transaction is less than or equal to the configured max value	Checks that the latency of a read transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_read_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_min_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of write transactions in a given interval is more than or equal to the configured min value	Checks that the average latency of write transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_write_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_avg_max_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the average latency of write transactions in a given interval is less than or equal to the configured max value	Checks that the average latency of write transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_write_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_min_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a write transaction is more than or equal to the configured min value	Checks that the latency of a write transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_write_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Node performance metrics	perf_max_write_xact_latency_check	SYNOPSYS DEFINED	Monitor Check that the latency of a write transaction is less than or equal to the configured max value	Checks that the latency of a write transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_write_xact_latency	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Snoop Transaction timeout check	snp_transaction_inactivity_timeout_check	SYNOPSYS DEFINED	Check that a Snoop transaction ends within the programmed number of clock cycles.	Checks that a given Snoop transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: snp_xact_inactivity_timeout. Vip will continue to process the snoop transaction even the snoop transaction has timedout. The timeout of the snoop transaction doesn't have any impact on the procesing or completion of the snoop transaction. The timer started for snoop transaction will continue to increment even there is a link deactivation when snoop transaction is outstanidng. This check is currently not designed to handle the cases when there is a dynamic reset.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Transaction timeout check	transaction_inactivity_timeout_check	SYNOPSYS DEFINED	Check that a transaction ends within the programmed number of clock cycles.	Checks that a given transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: xact_inactivity_timeout. Vip will continue to process the transaction even the transaction has timedout. The timeout of the transaction doesn't have any impact on the procesing or completion of the transaction. The timer started for a transaction will continue to increment even there is a link deactivation when transaction is outstanidng. This check is currently not designed to handle the cases when there is a dynamic reset.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	exclusive access legal data_size transfer check	non_coherent_excl_access_legal_data_size_transfer_check	ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations	Check that the number of bytes to be transferred in an exclusive access must be a legal data transfer size, that is, 1, 2,4, 8, 16, 32, or 64 bytes.	Check that the number of bytes to be transferred in an exclusive access must be a legal data transfer size, that is, 1, 2,4, 8, 16, 32, or 64 bytes.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	exclusive access address aligned to total bytes check	non_coherent_excl_access_aligned_total_bytes_transaction_check	ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations	Check that the address of an exclusive access must be aligned to the total number of bytes in the transaction.	Check that the address of an exclusive access must be aligned to the total number of bytes in the transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	non-coherent exclusive access same lpid check	non_coherent_excl_read_multiple_entry_for_same_lpid_check	ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations	Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time.	Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time. Multiple exclusive transactions to Non-snoopable memory locations, either read or write, to the same or different addresses, from the same LP must not be outstanding at the same time.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	SACTIVE signal validity	valid_rxsactive_signal_check	ARM-IHI0050E.b: 14.7 Protocol layer activity indication	RXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received at the link partner node.	RXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received at the link partner node. A transaction that is given a RetryAck response is considered to be in progress, so RXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned. The check is performed under following conditions: while the link is active and there is no active reset -- Whenever there is a flit activity observed(TXFLITV/RXFLITV asserted), RXSACTIVE must be sampled as HIGH. Otherwise the check fails. Following are the specific conditions under which this check is performed: In case of SN: if REQ flit is received, then rxsactive must be HIGH at the same clock In case of RN: The same clock where the CompAck RSP is observed, this must be high In case of RN: The same clock where SNPRSP is sampled by all receiving/observing components, this must be high In case of RN: The same clock where SNP flit is observed, this must be HIGH In the same cycle the RSP flit is received/observed, this must be high In the same cycle the Read Data flit is received/observed, this must be high In the same cycle the Snp Data flit is received/observed, this must be high In the same cycle the Write Data flit is received/observed, this must be high Whenever the signal RXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity at the link partner node. Otherwise the check fails. Following is the definition of 'pending protocol layer activity': Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits) Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions) Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	SACTIVE signal validity	valid_txsactive_signal_check	ARM-IHI0050E.b: 14.7 Protocol layer activity indication	TXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received.	TXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received. A transaction that is given a RetryAck response is considered to be in progress, so TXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned. Applicable when : the agent is in PASSIVE mode (svt_chi_node_configuration :: is_active = 0), and svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK The check is performed under following conditions: while the link is active and there is no active reset -- Whenever there is a flit activity observed(TXFLITV/RXFLITV asserted), TXSACTIVE must be sampled as HIGH. Otherwise the check fails. Following are the specific conditions under which this check is performed: REQ flit is received by PASSIVE agent, then txsactive must be HIGH at: at the same clock, in case of RN In case of RN: the same clock where CompAack RSP flit is observed, this must be high In case of RN: The same clock where SNPRSP is observed, this must be high In the same cycle the RSP flit is received/observed, this must be high In the same cycle the Read Data flit is received/observed, this must be high In the same cycle the Snp Data flit is received/observed, this must be high In the same cycle the Write Data flit is received/observed, this must be high Whenever the signal TXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity. Otherwise the check fails. Following is the definition of 'pending protocol layer activity': Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits) Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions) Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_readreceipt_to_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	If the request Order field indicates that ordering is required then a ReadReceipt response must be returned on the CRSP channel when order has been established	Check that the Ordering field of the transaction corresponding to the readreceipt is set.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	valid_rn_d_snoop_flit_check	ARM-IHI0050E.b: Table B-2 Snoop communicating nodes	Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.	Check that only DVMOp related snoop transactions are seen on the Snoop Channel in case of RN-D. Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readunique_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadUnique transaction. The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readnotshareddirty_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadNotSharedDirty transaction. The cache state in the associated CompData flits of a ReadNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readshared_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadShared transaction. The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readclean_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Compdata packet has valid cache state value for a ReadClean transaction. The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleanunique_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a CleanUnique transaction. The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makeunique_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a MakeUnique transaction. The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	evict_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp response has valid cache state value for a Evict transaction. The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readunique_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.	Check that the associated Compdata packet has valid resp_err value for ReadUnique transaction. The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	expected_response_for_makereadunique_xact_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The Home Node must send a data response for a MakeReadUnique transaction if the line is not cached at the requester at the time of response.	Check that the home node sends a data response for a MakeReadUnique transaction if the line is not cached at the requester at the time of response.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readpreferunique_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData or DataSepResp flits of a ReadPreferUnique transaction should take a valid value when the Resperr field does not indicate any error.	Check that the associated CompData or DataSepResp packet has valid cache state value for a ReadPreferUnique transaction. The cache state in the associated CompData or DataSepResp flits of a ReadPreferUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	makereadunique_associated_compdata_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated CompData or DataSepResp flits of a MakeReadUnique transaction should take a valid value when the Resperr field does not indicate any error.	Check that the associated CompData or DataSepResp packet has valid cache state value for a MakeReadUnique transaction. The cache state in the associated CompData or DataSepResp flits of a MakeReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makereadunique_associated_comp_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache state in the associated Comp or RespSepData flit of a MakeReadUnique transaction should take a valid value when the Resperr field does not indicate any error.	Check that the associated Comp or RespSepData packet has valid cache state value for a MakeReadUnique transaction. The cache state in the associated Comp or RespSepData flits of a MakeReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readpreferunique_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The associated CompData or DataSepResp packet's resp_err field should not take EXOK value for ReadPreferUnique transaction.	Check that the associated CompData or DataSepResp flits have valid resp_err value for ReadPreferUnique transaction. The associated CompData or DataSepResp flit's resp_err field should not take EXOK for ReadPreferUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	makereadunique_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The associated CompData or DataSepResp packet's resp_err field should not take EXOK value for MakeReadUnique transaction.	Check that the associated CompData or DataSepResp flits have valid resp_err value for MakeReadUnique transaction. The associated CompData or DataSepResp flit's resp_err field should not take EXOK for MakeReadUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makereadunique_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The associated Comp or RespSepData response packet's resp_err field should not take EXOK value for MakeReadUnique transaction.	Check that the associated Comp or RespSepData response flit has valid resp_err value for MakeReadUnique transaction. The associated Comp or RespSepData response flit's resp_err field should not take EXOK for MakeReadUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	expected_snoop_xact_type_check	SYNOPSYS DEFINED	Stash and Forward type snoops are expected to be received only by a CHI-B or later compliant RN-F, when Stashing and DCT features are enabled in the corresponding HN, respectively.	Check that only supported snoop transactions are seen on the Snoop Channel in case of RN-F. SYNOPSYS DEFINED : Stash and Forward type snoops are expected to be received only by a CHI-B or later compliant RN-F, when Stashing and DCT features are enabled in the corresponding HN, respectively. SnpNotSharedDirty, Stash and Forward type snoops are expected to be received only by a CHI-B or later compliant RN-F.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readnotshareddirty_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Compdata packet has valid resp_err value for ReadNotSharedDirty transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readshared_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Compdata packet has valid resp_err value for ReadShared transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	readclean_associated_compdata_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Compdata packet has valid resp_err value for ReadClean transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleanunique_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.	Check that the associated Comp response packet has valid resp_err value for CleanUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	makeunique_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.	Check that the associated Comp response packet has valid resp_err value for MakeUnique transaction. The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	evict_associated_comp_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.	Check that the associated Comp response packet has valid resp_err value for Evict transaction. The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpstashshared_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.2 Stash snoop transactions	The cache state in the associated response of a SnpStashUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated RespSepData, DataSepResp or CompData has valid cache state for SnpStashShared transaction. The cache state in the associated response of a SnpStashShared transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpstashshared_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp or RespSepData should not take EXOK or DERR resp_err value for SnpStashShared transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.	Check that the associated SnpResp packet has valid resp_err value for SnpStashShared transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpstashunique_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp or RespSepData should not take EXOK or DERR resp_err value for SnpStashUnique transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.	Check that the associated SnpResp packet has valid resp_err value for SnpStashUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpstashunique_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.2 Stash snoop transactions	The cache state in the associated response of a SnpStashUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated RespSepData, DataSepResp or CompData has valid cache state for SnpStashUnique transaction. The cache state in the associated response of a SnpStashUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpmakeinvalidstash_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.2 Stash snoop transactions	The cache state in the associated response of a SnpMakeInvalidStash transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp,RespSepData,DataSepResp or CompData has valid cache state for SnpMakeInvalidStash transaction. The cache state in the associated response of a SnpMakeInvalidStash transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpmakeinvalidstash_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp or RespSepData should not take EXOK or DERR resp_err value for SnpMakeInvalidStash transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.	Check that the associated SnpResp, RespSepData, DataSepResp or CompData packet has valid resp_err value for SnpMakeInvalidStash transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpuniquestash_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.2 Stash snoop transactions	The cache state in the associated response of a SnpUniqueStash transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp, SnpRespData, RespSepData, DataSepResp or CompData has a valid cache state for SnpUniqueStash transaction. The cache state in the associated response of a SnpUniqueStash transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpuniquestash_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp or RespSepData should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUniqueStash transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpUniqueStash transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeevict_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction.	Check that the associated response and data packets has valid resp_err value for WriteEvict transaction. The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction. The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteEvict transaction. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeclean_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction.	Check that the associated response and data packets has valid resp_err value for WriteClean transaction. The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction. The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteClean transaction. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeback_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction.	Check that the associated response and data packets has valid resp_err value for WriteBack transaction. The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction. The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteBack transaction. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	writecleanfull_cleanshared_associated_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated write data flits of WriteCleanFull_CleanShared should take legal values as per CHI ISSUE E Specifications.	Check that the associated write data flits has valid resp_err value for WriteCleanFull_CleanShared transaction. The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteCleanFull_CleanShared transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	writebackfull_cleaninvalid_associated_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated write data flits of WriteBackFull_CleanInvalid should take legal values as per CHI ISSUE E Specifications.	Check that the associated write data flits has valid resp_err value for WriteBackFull_CleanInvalid transaction. The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteBackFull_CleanInvalid transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	writecleanfull_cleansharedpersistsep_associated_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated write data flits of WriteCleanFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.	Check that the associated write data flits has valid resp_err value for WriteCleanFull_CleanSharedPersistSep transaction. The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteCleanFull_CleanSharedPersistSep transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	writebackfull_cleansharedpersistsep_associated_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated write data flits of WriteBackFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.	Check that the associated write data flits has valid resp_err value for WriteBackFull_CleanSharedPersistSep transaction. The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteBackFull_CleanSharedPersistSep transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	writebackfull_cleanshared_associated_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated write data flits of WriteBackFull_CleanShared should take legal values as per CHI ISSUE E Specifications.	Check that the associated write data flits has valid resp_err value for WriteBackFull_CleanShared transaction. The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteBackFull_CleanShared transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	ordering check	new_req_before_comp_or_compdbid_resp_for_copyback_writes_with_optional_data_to_same_cacheline_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	An RN-F must wait for the Comp/CompDBIDResp response to be received for an outstanding CopyBack Writes with Optional Data transactions WriteEvictorEvict before issuing another request to the same cache line.	Check that a request to a cache line is issued when there are no outstanding Copyback Writes with Optional Data transactions (WriteEvictorEvict) that are expecting Comp/CompDBIDResp. An RN-F must wait for the Comp/CompDBIDResp response to be received for an outstanding WriteEvictorEvict transaction before issuing another request to the same cache line.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	data_pull_set_for_stash_snoop_when_outstanding_xacts_with_dbidrespord	ARM-IHI0050E.b: 7.2 Write with Stash hint	The data pull in snoop response to stash snoop should be 0 .	The data_pull in the Snoop response to a stash snoop should be set to 0 when there exists outstanding transactions to the cache line which have received DBIDRespOrd response.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writecleanfull_cleanshared_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The resp field cache state, Pass Dirty value in associated response flits of WriteCleanFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteCleanFull_CleanShared transaction. The cache state and resp_pass_dirty fields in the associated CompCMO/Comp response flit of a WriteCleanFull_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writebackfull_cleaninvalid_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The resp field cache state, Pass Dirty value in associated response flits of WriteBackFull_CleanInvalid transaction should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteBackFull_CleanInvalid transaction. The cache state and resp_pass_dirty fields in the associated CompCMO/Comp response flit of a WriteBackFull_CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writecleanfull_cleansharedpersistsep_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The resp field cache state, Pass Dirty value in associated response flits of WriteCleanFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteCleanFull_CleanSharedPersistSep transaction. The cache state and resp_pass_dirty fields in the associated CompCMO/CompPersist/Comp response flit of a WriteCleanFull_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writecleanfull_cleansharedpersistsep_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated response flits of WriteCleanFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp_err value for WriteCleanFull_CleanSharedPersistSep transaction. The associated responses (CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value. The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writebackfull_cleansharedpersistsep_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The resp field cache state, Pass Dirty value in associated response flits of WriteBackFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteBackFull_CleanSharedPersistSep transaction. The cache state and resp_pass_dirty fields in the associated CompCMO/CompPersist/comp response flit of a WriteBackFull_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writebackfull_cleansharedpersistsep_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated response flits of WriteBackFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp_err value for WriteBackFull_CleanSharedPersistSep transaction. The associated responses (CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value. The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writebackfull_cleanshared_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The resp field cache state, Pass Dirty value in associated response flits of WriteBackFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteBackFull_CleanShared transaction. The cache state and resp_pass_dirty fields in the associated CompCMO/Comp response flit of a WriteBackFull_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writecleanfull_cleanshared_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated response flits of WriteCleanFull_CleanShared should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp_err value for WriteCleanFull_CleanShared transaction. The associated responses (CompDBIDResp, CompCMO) should not take EXOK resp_err value. The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writebackfull_cleaninvalid_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated response flits of WriteBackFull_CleanInvalid should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp_err value for WriteBackFull_CleanInvalid transaction. The associated responses (CompDBIDResp, CompCMO) should not take EXOK resp_err value. The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	writebackfull_cleanshared_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated response flits of WriteBackFull_CleanShared should take legal values as per CHI ISSUE E Specifications.	Check that the associated response flits has valid resp_err value for WriteBackFull_CleanShared transaction. The associated responses (CompDBIDResp, CompCMO) should not take EXOK resp_err value. The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeevictorevict_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The resp field cache state, Pass Dirty value in associated response and data packets of WriteEvictorEvict should take legal values as per CHI ISSUE E Specifications.	Check that the associated response and data packets has valid resp field {cahe state and resp_pass_dirty} value for a WriteEvictorEvict transaction. The cache state in the associated Write data flits or Comp reponse flits of a WriteEvictorEvict transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeevictorevict_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.3 Write transactions	The resp_err value in associated response and data packets of WriteEvictorEvict should take legal values as per CHI ISSUE E Specifications.	Check that the associated response and data packets has valid resp_err value for WriteEvictorEvict transaction. The associated CompDBIDResp should not take EXOK resp_err value for WriteEvictorEvict transaction. The associated Comp should not take EXOK or DATA_ERROR resp_err value for WriteEvictorEvict transaction. The associated write data packets should not take EXOK or NON_DATA_ERROR resp_err value for WriteEvictorEvict transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	cache_transitioned_to_dirty_from_uce_for_read	ARM-IHI0050E.b: 4.7.1 Read request transactions	The cache transitioned to dirty stateUD/UDP from UCE.	Check if the RN has transitioned from UCE to UD/UDP state while there is an ongoing READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions. This check will flag an error in case the cache is updated via frontdoor or backdoor accesses to move from UCE to dirty state while there is an outstanding Read. .	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	makereadunique_data_response_cache_data_match_check	ARM-IHI0050E.b: 4.7 Cache state transitions at a Requester	The data returned in the data response for a MakeReadUnique should be the same as the data cached in the Requester if the cachestate at the requester before receiving the response is SC and the final state in the associated data response is UD.	Check that the data returned in the data response for a MakeReadUnique is the same as the data cached in the Requester when the cachestate at the requester before receiving the response is SC and the final state in the associated data response is UD. This check is applicable only when there are no error responses seen in the data response for the MakeReadUnique and the data cached in the RN is not poisoned.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	valid_final_state_for_non_invalidating_snp_when_outstanding_makereadunique_to_same_cacheline_check	ARM-IHI0050E.b: 4.7 Cache state transitions at a Requester	A requester must not invalidate the line in response to receiving a non-invalidating snoop while MakeReadUnique is outstanding.	Check that the final state in the Snoop response for a non-invaldating type snoop is not I if there is already an outstanding MakeReadUnique transaction to the same cacheline given that the snoop response does not indicate a NON_DATA_ERROR. The MakeReadUnique transaction will be considered only if there were no prior invalidating type Snoops seen while the MakeReadUnique was outstanding. In other words, this check will not be performed if the RN had already received a an invalidating type Snoop overlapping with the MakeReadUnique.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	invalid_data_pull_in_snoop_response_check	ARM-IHI0050E.b: 7.2 Write with Stash hint	Stash target must not request Data Pull if: DoNotDataPull bit is set or Snoop has an address hazard with an outstanding request	Check that the DataPull value in the Snoop response for a Stash type Snoop is set to a valid value. DataPull must not be set to 1 when DoNotDataPull in the Snoop requests was set to 1 sysco interface state is in a state other than Coherency Enabled(when svt_chi_node_configuration :: sysco_interface_enable is set to 1) There are ongoing transactions to the same cacheline	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	dbid_in_snoop_response_with_data_pull_check	ARM-IHI0050E.b: 2.5 Details of transaction identifier fields	The DBID value used by a Snoop Completer in response to a Stash type snoop that includes a Data Pull must be unique with respect to: the DBID values in other Snoop responses to Stash type snoops that use Data Pull and the TxnID of any outstanding Request from that Snoop Completer	Check that the DBID value in the Snoop response for a Stash type Snoop is set to a unique value when DataPull is asserted. The DBID must not coincide with the TxnID of any of the outstanding transactions at the RN or the DBID of any of the outstanding Stash type Snoops involving DataPull.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	snprspdatafwded_compdata_data_integrity_check	ARM-IHI0050E.b: 4.5.3 Snoop response	The data in the SnpRespDataFwded response matches with the data in the CompData response sent for a Forward type Snoop transaction	Check that the data sent in the SnpRespDataFwded response matches with the data sent in the forwarded CompData for a given Forward type Snoop request.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	valid_fwd_state_in_fwded_snoop_response_check	ARM-IHI0050E.b: 13.10.45 Forward State, FwdState	The FwdState indicated in the SnpRespFwded or SnpRespDataFwded response must indicate the state in the CompData sent from the Snoopee to the Requester	Check that the FwdState indicated in the SnpRespFwded or SnpRespDataFwded response matches with the Resp field in the forwarded CompData.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	valid_fwded_response_type_for_ret_to_src_check	ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions	For a Forwarding type Snoop request, snooped RN must return a copy to Home using SnpRspDataFwded if the cache line is Dirty or Clean.	Check that SnpRespFwded is issued from the snooped RN to the Interconnect in case DCT is observed for a Forward type snoop with RetToSrc asserted.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_snprspfwded_flit_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The SrcID, TgtID, TxnID fields of the SnpRspFwded flit must match the TgtID, FwdNID, FwdTxnID and TxnID of the Forward type Snoop request	Check that the Transaction ID, SourceID and TargetID fields are set correctly in Snoop response flits. The TgtID must be set to the the Src of the Forward type Snoop request. The TxnID must be set to the same value as the TxnID of the Forward type Snoop request. The SrcID must be set to the same value as the TgtID of the Forward type Snoop request.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_compdata_flit_with_fwd_type_snp_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The SrcID, TgtID, TxnID and DBID fields of the forwarded CompData flit must match the TgtID, FwdNID, FwdTxnID and TxnID of the Forward type Snoop request	Check that the SourceID, TargetID, Transaction ID and DBID fields are set correctly in the CompData flits used for DCT. The TgtID must be set to the the FwdNID of the Snoop request. The SrcID must be set to the the TgtID of the Snoop request. The TxnID must be set to the FwdTxnID of the Snoop request. The DBID must be set to the TxnID of the Snoop request.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snppreferuniquefwd_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions	The cache state in the associated response of a SnpPreferUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpPreferUniqueFwd transaction. The cache state in the associated response of a SnpPreferUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error. A Snoopee that is not executing an exclusive sequence treats SnpPreferUniqueFwd as SnpUniqueFwd. Snoopee that is in the process of executing an exclusive sequence treats SnpPreferUniqueFwd as SnpNotSharedDirtyFwd, with the exception that it must not invalidate its cached copy.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snppreferuniquefwd_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR, The associated SnpRespFwd should not take EXOK, whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpPreferUniqueFwd transaction.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid resp_err value for SnpPreferUniqueFwd transaction. The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpPreferUniqueFwd transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpnotshareddirtyfwd_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions	The cache state in the associated response of a SnpNotSharedDirtyFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpNotSharedDirtyFwd transaction. The cache state in the associated response of a SnpNotSharedDirtyFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpnotshareddirtyfwd_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirtyFwd transaction.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid resp_err value for SnpNotSharedDirtyFwd transaction. The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirtyFwd transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpuniquefwd_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions	The cache state in the associated response of a SnpUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpUniqueFwd transaction. The cache state in the associated response of a SnpUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpuniquefwd_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpUniqueFwd transaction.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid resp_err value for SnpUniqueFwd transaction. The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpUniqueFwd transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpsharedfwd_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions	The cache state in the associated response of a SnpSharedFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpSharedFwd transaction. The cache state in the associated response of a SnpSharedFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpsharedfwd_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpSharedFwd transaction.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData valid resp_err value for SnpSharedFwd transaction. The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpSharedFwd transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleanfwd_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions	The cache state in the associated response of a SnpCleanFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpCleanFwd transaction. The cache state in the associated response of a SnpCleanFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleanfwd_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpCleanFwd transaction.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has valid resp_err value for SnpCleanFwd transaction. The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpCleanFwd transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snponcefwd_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions	The cache state in the associated response of a SnpOnceFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpOnceFwd transaction. The cache state in the associated response of a SnpOnceFwd transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snponcefwd_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpOnceFwd transaction.	Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData packet has valid resp_err value for SnpOnceFwd transaction. The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packets should not take EXOK or NDERR resp_err value for SnpOnceFwd transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	copyback_cancellation_write_data_check	ARM-IHI0050E.b: 4.11.1 At the RN-F node	The cache state in the WriteData response after CopyBack cancellation must be I and all byte enables must be deasserted.If all the byte enables are deasserted then the data must be zeroed	Check that when Byte Enables in the CopyBackWriteData are all de-asserted during CopyBack cancellation the Write Data bytes are all zeroed.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snppreferunique_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpPreferUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpPreferUnique transaction. The cache state in the associated response of a SnpPreferUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snppreferunique_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpPreferUnique transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpPreferUnique transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpPreferUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpnotshareddirty_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpNotSharedDirty transaction. The cache state in the associated response of a SnpNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpnotshareddirty_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirty transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpNotSharedDirty transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirty transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_snprespdata_when_be_is_zero_check	ARM-IHI0050E.b: 2.10.3 Byte Enables	In Snoop Data, a byte enable value of zero must set the associated data byte value to zero.	Check that in Snoop Data, a byte enable value of zero must set the associated data byte value to zero.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	expected_tagop_value_in_fwded_compdata_check	ARM-IHI0050E.b: 12.9.2 Forwarding snoops	The TagOp field in the Forwarded CompData must be set to either Invalid or Transfer	Check that the TagOp field in the Comp response is set to a value that is permitted by the specification for the corresponding transaction type.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	same_tagop_value_in_all_fwded_compdata_flits_check	ARM-IHI0050E.b: 12.9 Snoop requests	In case there are multiple Forwarded CompData response flits corresponding to a Forward type Snoop, the TagOp field must be set to the same value across all the Forwarded CompData flits	Check that, in case there are multipe Forwarded CompData flits corresponding to a Forward type Snoop, the TagOp field is set to the same value in all the Forwarded Compdata flits.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	expected_tagop_value_in_data_pull_compdata_check	ARM-IHI0050E.b: 12.8 Stash transactions	The TagOp field in the DataPull CompData must be set to either Invalid or Transfer	Check that the TagOp field in the DataPull Compdata response corresponding to a Stash type Snoop involving DataPull is set to a value that is permitted by the specification.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	same_tagop_value_in_all_data_pull_compdata_flits_check	ARM-IHI0050E.b: 12.8 Stash transactions	In case there are multiple DataPull CompData flits corresponding to a Stash type Snoop involving DataPull, the TagOp field must be set to the same value across all the DataPull CompData flits	Check that, in case there are multipe DataPull CompData flits corresponding to a Stash type Snoop involving DataPull, the TagOp field is set to the same value in all the DataPull Compdata flits.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	same_tagop_value_in_all_snoop_data_response_flits_check	ARM-IHI0050E.b: 12.9 Snoop requests	In case there are multiple Snoop data response flits corresponding to a Snoop, the TagOp field must be set to the same value across all the SnpRespData flits	Check that, in case there are multiple Snoop data response flits corresponding to a Snoop transaction, the TagOp field is set to the same value across all the Snoop data response flits.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpquery_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The resp_pass_dirty attribute in the associated response of a SnpQuery transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp has valid cache state for SnpQuery transaction. The resp_pass_dirty attribute in the associated response of a SnpQuery transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpquery_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR resp_err value for SnpQuery transaction.	Check that the associated SnpResp packet has valid resp_err value for SnpQuery transaction. The associated SnpResp should not take EXOK or DERR resp_err value for SnpQuery transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	ordering check	new_req_before_compdbid_resp_for_copyback_to_same_cacheline_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.	Check that a request to a cache line is issued when there are no outstanding Copyback transactions that are expecting CompDBIDResp. An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpmakeinvalid_associated_response_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp has valid cache state for SnpMakeInvalid transaction. The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleaninvalid_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanInvalid transaction. The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleanshared_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanShared transaction. The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpunique_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpUnique transaction. The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpshared_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpShared transaction. The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpclean_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpClean transaction. The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snponce_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions	The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated SnpResp or SnpRespData has a valid cache state for SnpOnce transaction. The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpmakeinvalid_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.	Check that the associated SnpResp packet has valid resp_err value for SnpMakeInvalid transaction. The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleaninvalid_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanInvalid transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpcleanshared_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanShared transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpunique_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpUnique transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpshared_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpShared transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snpclean_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.5 Other transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpClean transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	snponce_associated_response_data_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.7 Snoop transactions	The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.	Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpOnce transaction. The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	associate_snprspdata_flit_with_snp_xact_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.	Check that the Transaction ID, SourceID and TargetID fields are set correctly in SnpResp Data flits. The TgtID must be set to the the SrcID of the Snoop request. The TxnID must be set to the same value as the TxnID of the Snoop request.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_snprsp_flit_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.	Check that the Transaction ID, SourceID and TargetID fields are set correctly in Snoop response flits. The TgtID must be set to the the SrcID of the Snoop request. The TxnID is set to the same value as the TxnID of the Snoop request.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeevict_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteEvict transaction. The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeclean_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteClean transaction. The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeback_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteBack transaction. The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_dat_flit_type_for_snp_xact_check	ARM-IHI0050E.b: 4.5 Response types	Data flit type must be set to one of the permitted values for the Request	Check that the data type of the flit matches the expected value. Data flit type must be set to one of the permitted values for the Snoop Request	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_cbwrdata_flit_for_xact_check	ARM-IHI0050E.b: 4.5.2 WriteData response	Data flit type must be set to one of the permitted values for the Request	Check that the data type of the flit matches the expected value. COPYBACKWRDATA is valid only in case of WriteBack, WriteClean and WriteEvict type transactions	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	new_snp_req_before_compack_of_coherent_xact_which_received_comp_to_same_cacheline_check	ARM-IHI0050E.b: 4.11 Hazard conditions	The completer can send out the Snoop requests to an RN-F only when there are no outstanding coherent transactions from that particular RN-F targetting the same cache line that received completion response and has not yet received the CompAck/WrData	Check that for an RN-F node, Snoop request is observed when there are no outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck or Write Data. Once a completion is received for a transaction, the completer must not send a snoop request to the same cache line until it receives: A CompAck for any Read and Dataless requests except for ReadOnce* and ReadNoSnp. A WriteData response for CopyBack and Atomic requests. For WriteUnique, a WriteData response and, if applicable, CompAck.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	snp req validity	new_snp_req_before_completion_of_previous_snp_xact_to_same_cacheline_check	ARM-IHI0050E.b: 4.11 Hazard conditions	The completer can send out the Snoop requests to an RN-F only when there are no outstanding Snoop transactions targetting the same cache line to that particular RN-F	Check that for an RN-F node, Snoop request is observed when there are no outstanding Snoop transactions targetting the same cache line.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_tlbi_fields_in_snpdvmop_check	ARM-IHI0050E.b: 8.2 DVM Operation types	The Range, Num, Scale, TG and TTL fields in a SnpDVMOp transaction are set to legal values	Check that the Range, Num, Scale, TG and TTL fields are set to valid values in a TLB Invalidate Type SnpDVMOp transaction. Range bit can be set to 1 only in case of SnpDVMOp TLBI requests that are invalidate by VA or PA. Num and Scale fields can be set to non-zero values only in case of Range based SnpDVMOp TLBI requests. TG and TTL can be set to non-zero values only in case of TLBI requests that are invalidate by VA or PA.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_order_of_dvmop_rspflits_check	ARM-IHI0050E.b: 2.3.7 DVM transactions	Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete	Check that the order of the responses sent by the Completer is correct in case of DVMOp transactions. Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete. When the spec_revision is ISSUE_D or later and the DVMOp is a Non-sync DVMOp, then the interconnect is permitted but not required to wait for WriteData before sending the Comp. Currently VIP does not support early COMP support for DVM transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_snpdvmop_part_check	ARM-IHI0050E.b: 8.1.3 Flow control	SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID	Check that both parts of a SnpDVMOp request are received at the RN. SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	single_outstanding_snpdvmop_per_txn_id_check	ARM-IHI0050E.b: 2.4 Transaction identifier fields	The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID	Check that the TxnID of a SnpDVMOp must be unique for a given Requester. The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	single_outstanding_snpdvmop_sync_check	ARM-IHI0050E.b: 8.1.3 Flow control	Only one SnpDVMOpSync transaction can be outstanding from an MN to an RN.	Check that there is only one outstanding DVMOp sync transaction at a given point in time. Only one SnpDVMOp(Sync) transaction can be outstanding from an MN to an RN.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	valid_resp_err_status_for_dvmop_xact_check	ARM-IHI0050E.b: 9.4.5 Other transactions	For DVMOP transaction, resp_err_status field of the associated Comp RSP flit must have one of the following values: 1NORMAL_OKAY 2NON_DATA_ERROR 3in case of chi_spec_revision >= ISSUE_B,DATA_ERROR.	Check that the comp response has valid resp_err value for DVMop transaction. The associated Comp response should take one of the following resp_err values: 1)NORMAL_OKAY 2)NON_DATA_ERROR 3)in case of svt_chi_node_configuration :: chi_spec_revision >= ISSUE_B,DATA_ERROR for DVMop transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_rspflit_for_dvmop_check	ARM-IHI0050E.b: 4.5.1 Completion response	A Comp response, with the Resp field set to zero, is always used for DVM transaction completion	Check that only Comp Response is used for DVMOp transactions, and not CompDBIDResp When the spec_revision is ISSUE_D or later the Completer is permitted to opportunistically combine Comp and DBIDResp into CompDBIDResp response. This is applicable only in case of early comp support. Currently VIP does not support early COMP support for DVM transaction. A Comp response, with the Resp field set to zero, is always used for Barrier and DVM transaction completion.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpdvmop_associated_response_packets_legal_resperr_check	ARM-IHI0050E.b: 9.4.5 Other transactions	The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.	Check that the associated SnpResp packet has valid resp_err value for SnpDVMop transaction. The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpresp_for_snpdvmop_sync_only_after_completion_of_prior_snpdvmop_check	ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow	Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no prior SnpDVMOp transactions that are yet to receive a SnpResp from the RN. Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	snpresp_for_snpdvmop_sync_only_after_completion_of_all_non_dvm_sync_check	ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow	Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no outstanding DVMOp transactions at the RN. Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_tlbi_fields_in_dvmop_check	ARM-IHI0050E.b: 8.2 DVM Operation types	The Range, Num, Scale, TG and TTL fields in a DVMOp transaction are set to legal values	Check that the Range, Num, Scale, TG and TTL fields are set to valid values in a TLB Invalidate Type DVMOp transaction. Range bit can be set to 1 only in case of DVMOp TLBI requests that are invalidate by VA or PA. Num and Scale fields can be set to non-zero values only in case of Range based DVMOp TLBI requests. TG and TTL can be set to non-zero values only in case of TLBI requests that are invalidate by VA or PA.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_snprsp_for_snpdvmop_check	ARM-IHI0050E.b: 8.1.3 Flow control	An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction.	Check that the SnpDVMOpResp is observed only after both SnpDVMOp request packets. An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction. The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	valid_snpdvmop_req_part_num_check	ARM-IHI0050E.b: 8.2 DVM Operation types	Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.	Check that the part numbers of the SnpDVMOp request packets are set correctly. Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	single_outstanding_dvmop_sync_request_check	SYNOPSYS DEFINED	There can only be one outstanding DVMOpSync transaction from an RN at any point in time.	Check that there are no outstanding DVMOp(Sync) transactions when a DVMOp(Sync) request is received. SYNOPSYS DEFINED Not more than one DVMOp(Sync) transaction is expected to be outstanding from an RN at any given point in time, when svt_chi_node_configuration :: allow_multiple_dvm_sync_oustanding_xacts is set to 0.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	unused_bits_in_dvm_write_data_check	ARM-IHI0050E.b: 8.1.4 DVMOp field value restrictions	All the unused bits in the write data of a DVMOp transaction must be set to zero.	Check that the unused bits in the Write data of a DVMOp transaction are set to zero.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dvm xact	expected_dvmop_sync_request_check	ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow	All previous DVMOp requests whose completion needs to be guaranteed by the DVMOpSync must have received a Comp response before the RN can send a DVMOpSync.	Check that there are no outstanding DVMOp(Non-sync) transactions when a DVMOp(Sync) request is received. All previous DVMOp requests whose completion needs to be guaranteed by the DVMOp(Sync) must have received a Comp response before the RN can send a DVMOp(Sync).	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleansharedpersistsep_associated_response_legal_cache_state_check	ARM-IHI0050E.b: 4.7.2 Dataless request transactions	The cache state in the associated comp/comp_persist response packets of a CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate any error.	Check that the associated Comp/CompPersist response packet has valid cache state value for a CleanSharedPersistSep transaction. The cache state in the associated comp/comppersist response packets of a CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	cleansharedpersistsep_associated_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.2 Dataless transactions	The associated comp/persist/comppersist response packet's resp_err field should not take EXOK value for CleanSharedPersistSep transaction	Check that the associated Comp/Persist/CompPersist response packet has valid resp_err value for CleanSharedPersistSep transaction. The associated comp/persist/comppersist response packet's resp_err field should not take EXOK value for CleanSharedPersistSep transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_response_combinations_for_cleansharedpersistsep_check	ARM-IHI0050E.b: 4.5 Response types	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	The Response type must correspond to one of the permitted combinations for the CleanSharedPersistSep transaction	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_comppersist_flit_type_for_xact_check	ARM-IHI0050E.b: 4.5 Response types	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_persist_flit_type_for_xact_check	ARM-IHI0050E.b: 4.5 Response types	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	associate flit to xact	valid_parity_datacheck_for_snoop_data_check	ARM-IHI0050E.b: 9.6 Data Check	For Snoop transactions involving data transfer, datacheck is set appropriatly such that ODD Byte parity is generated.	Checks that the Datacheck is set correctly such that ODD Byte parity is generated for Snoop Data For all snoop transactions that involve data transfers, datacheck bit is set appropriatly such that ODD Byte parity is generated across the data that is being transmited.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	barrier xact	normal_non_cacheable_or_device_writes_between_barriers_check	ARM-IHI0050A: 7.5.1	It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.	Check that Normal Non-cacheable or Device type writes were received, prior to the current Barrier and after the previous Barrier transaction It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.	WARNING	svt_chi_protocol_err_check
CHI Protocol Layer	barrier xact	comp_received_for_normal_non_cacheable_or_device_writes_before_barrier_check	ARM-IHI0050A: 7.5 Barriers	An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request	Check that there are no outstanding Normal Non-cacheable or Device type writes, that are targeting an HN-I, which haven't received a Comp Repsonse, before a Barrier is issued by an RN. An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	expected_tgt_id_in_rn_xact_check	ARM-IHI0050E.b: 3.3.1 Target ID determination for Request messages	The Target ID in the request sent by the RN must be set as per the SAM, when target ID remapping is not expected at the Interconnect	Check that the Target ID field in the transaction request is set to the node ID of the HN as per the RN SAM. When Target ID is not expected to be remapped at the Interconnect, RN must program the tgt_id of the request flit to the correct value as per the SAM.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	atomic_compare_valid_tag_check	ARM-IHI0050E.b: 12.7 Atomic transactions	The memory tag value should be same in the Tag fields corresponding to the compare and swap data	Checks that the memory tag is same in the Tag fields corresponding to the compare and swap data. Applicable only for ATOMICCOMARE transaction when tag_op is set to TAG_FETCH_MATCH.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeuniquefullstash_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteUniqueptlstash transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteUniquefullstash transaction. The cache state in the associated Write data flits of a WriteUniquefullstash transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeuniqueptlstash_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteUniqueptlstash transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteUniqueptlstash transaction. The cache state in the associated Write data flits of a WriteUniqueptlstash transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Compack timing	owo_combined_writeunique_cmo_compack_timing_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	CompAck for an OWO Combined WriteUnique and CMO type transaction must be sent only after all the previous OWO Combined WriteUnique and CMO type transactions have received Comp response and the current OWO Combined WriteUnique and CMO type transaction transaction has received either Comp or DBIDResp or COMPDBIDRESP response.	Check that the CompAck response for an ordered Combined WriteUnique_(P)CMO type transaction is sent only afer following conditions are met: Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current Combined WriteUnique_(P)CMO type transaction are received. DBIDResp or CompDBIDResp or Comp response for the current Combined WriteUnique_(P)CMO type transaction is received.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Compack timing	owo_combined_writenosnp_cmo_compack_timing_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	CompAck for an OWO Combined WriteNoSnp and CMO type transaction must be sent only after all the previous OWO Combined WriteNoSnp and CMO type transactions have received Comp response and the current OWO Combined WriteNoSnp and CMO type transaction transaction has received either Comp or DBIDResp or COMPDBIDRESP response.	Check that the CompAck response for an ordered Combined WriteNoSnp_(P)CMO type transaction is sent only afer following conditions are met: Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current Combined WriteNoSnp_CMO type transaction are received. DBIDResp or CompDBIDResp or Comp response for the current Combined WriteNoSnp_(P)CMO type transaction is received.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Compack timing	owo_writenosnp_compack_timing_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	CompAck for an OWO WriteNoSnp must be sent only after the Comp response for all previous OWO WriteNoSnp transactions are received and Comp or DBIDResp or COMPDBIDRESP for current WriteNoSnp transaction is received.	Check that the CompAck response for an ordered WriteNoSnp transaction is sent only afer following conditions are met: Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteNoSnp transaction are received. DBIDResp or CompDBIDResp or Comp response for the current OWO WriteNoSnp transaction is received.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	Compack timing	owo_writeunique_compack_timing_check	ARM-IHI0050E.b: 2.8.5 Transaction ordering	CompAck for an OWO WriteUnique must be sent once the Comp for all previous OWO WriteUnique transactions are received and comp When chi_spec_revision is less than or equal to ISSUE_C/Comp or DBIDResp or CompDBIDReespWhen chi_spec_revision is ISSUE_D or later for current WriteUnique transaction is received.	Check that the CompAck response for an ordered WriteUnique transaction is sent only afer following conditions are met: Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transaction are received. When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Comp response for the current OWO WriteUnique is received.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	new_req_before_completion_of_previous_cmo_xacts_to_same_cacheline_check	ARM-IHI0050E.b: 4.2.2 Dataless transactions	Transaction intended for a particular address that can allocate data in Requester caches must not be sent to the interconnect before a previous CMO sent to the same address has completed.	Check that an allocating read request is issued when there are no outstanding CMO transactions to the same cache line.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	request validity	cmo_xact_before_completion_of_previous_xacts_to_same_cacheline_check	ARM-IHI0050E.b: 4.2.2 Dataless transactions	A CMO intended for a particular address must not be sent before all previous requests, targeting the same cacheline, that can allocate data in the requester cache ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique are complete.	Check that a CMO request is issued when there are no outstanding transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches: ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	writeunique_associated_response_data_packets_legal_cache_state_check	ARM-IHI0050E.b: 4.7.3 Write request transactions	The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	Check that the associated data packets has valid cache state value for a WriteUnique transaction. The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	expected_compack_check	ARM-IHI0050E.b: 2.3 Transaction structure	CompAck must be observed only after Comp or all CompData responses are received.	Check that the CompAck response is sent only afer Comp* or CompData response. CompAck, if part of the transaction, must be observed only after Comp* or CompData responses are received.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_compack_rsp_flit_check	ARM-IHI0050E.b: 2.6.1 Read transactions	The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively. The TxnID is set to the same value as the DBID value provided in the read data response.	Check that the TransactionID, TargetID and SourceID fields are set correctly in the CompAck response. The TgtID and SrcID must be set to the the SrcID and TgtID of the read data/comp/dbidresp/compdbidresp respectively. The TxnID is set to the same value as the DBID value provided in the read data/comp/dbidresp/compdbidresp response.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	single req order stream	single_req_order_stream_check	ARM-IHI0050E.b: 2.8 Ordering	The ordering requirements must be met for preceding active transactions with ReqOrder asserted before initiating next ordered transaction	Check that single ordered stream of requests from RN are ordered as per Request Ordering rules. Request Ordering Rules update from CHI Issue D onwards: In CHI Issue C or earlier, the Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range and includes the guarantee of Request Order. In CHI Issue D or later, there will be no ordering guarantees between two ordered transactions from the same source that have different ordering requirements. In other words, Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range, but doesn’t include the guarantee of Request Order.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	DWT	dwt_used_by_hn_with_dwt_enabled_check	SYNOPSYS DEFINED	DWT can be used by a HN only when: DWT is enabled for that HN through svt_chi_system_configuration::set_hn_dwt_enable	DWT can be used by an HN only when DWT is enabled for that HN through svt_chi_system_configuration :: set_hn_dwt_enable	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	CMO Propagation	cmos_forwarded_to_slave_by_hn_with_forward_cmos_to_slave_enable_check	SYNOPSYS DEFINED	CMO Propagation transactios can only be received by an SN from HN when the required configuration is set to 1 through svt_chi_system_configuration::set_hn_forward_cmos_to_slaves_enable method	SN can receive CleanShared, CLeanInvalid, MakeInvalid, CleanInvalidPOPA transaction from HN only when the required configuration is set through svt_chi_system_configuration :: set_hn_forward_cmos_to_slaves_enable method.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	CMO Propagation	persist_cmos_forwarded_to_slave_by_hn_with_forward_persist_cmos_to_slave_enable_check	SYNOPSYS DEFINED	Persist CMO Propagation transations can only be received by an SN from HN when the required configuration is set to 1 through svt_chi_system_configuration::set_hn_forward_persist_cmos_to_slaves_enable method	SN can receive CleanSharedPersist/CleanSharedPersistSep transaction from HN only when the required configuration is set through svt_chi_system_configuration :: set_hn_forward_persist_cmos_to_slaves_enable method.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	DMT	dmt_used_by_hn_with_dmt_enabled_check	SYNOPSYS DEFINED	DMT can be used by a HN only when: DMT is enabled for that HN through svt_chi_system_configuration::set_hn_dmt_enable	DMT can be used by an HN only when DMT is enabled for that HN through svt_chi_system_configuration :: set_hn_dmt_enable	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_snp_response_check	ARM-IHI0050E.b: 4.11.1 At the RN-F node	If a pending request to the same cache line is present at the RN-F and the pending request has received at least one Data response packet or RespSepData, the RN-F must wait to receive all Data response packets before responding to the Snoop request.	An RN-F must wait for any outstanding Read or DataPull transaction that has received at least one Read data or RespSepData flit to complete before issuing a Snoop response for a Snoop targeting the same cacheline.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	ncbwrdatacompack_flit_timing_check	ARM-IHI0050E.b: 2.3.2 Write Transactions	NCBWrDataCompAck which implies the combined flit of NCBWrData and compack responses must satisfy the compack response timing rule that all the previous OWO Write*order_type set to REQ_ORDERING_REQUIRED and exp_comp_ack set to 1 transactions should have received the comp response.	Check that the NCBWRDATACOMPACK response for an Ordered Write Observation Write* transaction is seen after all earlier OWO Write* transactions which are required to be ordered with respect to the current OWO Write* transaction received Comp responses.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	ncbwrdatacompack_after_comp_and_dbid_check	ARM-IHI0050E.b: 2.3.2 Write Transactions	An RN can send combined NCBWrDataCompAck response once it receives both DBIDResp and Comp or CompDBIDResp response from Home. Once RN receives DBIDResp it must send WrData and must not wait for Comp to combine WrData with CompAck	Check that NCBWRDATACOMPACK flits are seen for WriteUnique transactions only after the reception of both Comp and DBIDResp, or, CompDBIDResp response. Additionally checks that, in case separate Comp and DBID responses were observed, NCBWRDATACOMPACK flits are seen only if the Comp response was received first followed by the DBIDResp Response.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_ncbwrdatacompack_flit_for_xact_check	ARM-IHI0050E.b: 4.5.2 WriteData response	NCBWrDataCompAck can be sent only for a Writeunique transaction with ExpCompAck asserted. When svt_chi_node_configuration::chi_spec_revision is ISSUE_D or later, NCBWrDataCompAck can also be sent for a Writenosnp transaction with ExpCompAck asserted	When svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_C, check that NCBWRDATACOMPACK flits are seen only for WriteUnique* transactions with ExpCompAck asserted. When svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_D or later, check that NCBWRDATACOMPACK flits are seen only for WriteUnique* or WriteNoSnp* transactions with ExpCompAck asserted.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	matching_resp_err_nderr_in_respsepdata_datasepresp_check	ARM-IHI0050E.b: 9.4.1 Read transactions	For a given RN transaction, when resp_err_status field of RespSepData RSP flit is set to NON_DATA_ERROR, resp_err_status field of DataSepResp DAT flits must be set to NON_DATA_ERROR as well as RespSepData and associated DataSepResp flits must be generated from the same HN	For a given RN Read transaction, if resp_err_status is set to NON_DATA_ERROR in RespSepData then the subsequent DataSepResp should also have the resp_err_status set to NON_DATA_ERROR. Moreover, in such cases, the DataSepResp should be issued by the Home node that issued RespSepData	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	dat flit valid	valid_data_source_in_datasepresp_check	ARM-IHI0050E.b: 11.1 Data Source indication	The DataSource field in the DataSepResp flits corresponding to a transaction must take legal values.	Check that the DataSource field in the associated Compdata packets have a valid value.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp and dat flit valid	matching_dbid_home_nid_in_respsepdata_datasepresp_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	The DBID and HomeNID values in the DataSepResp flits must match the DBID and SrcID values in the RespSepData flit	Check that the DBID and HomeNID values in the DataSepResp flits match the DBID and SrcID values in the corresponding RespSepData.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	associated_respsepdata_response_legal_resperr_check	ARM-IHI0050E.b: 9.4.1 Read transactions	The associated RespSepData response packet's resp_err field should not take EXOK or DERR value	Check that the associated RespSepData response packet has valid resp_err value.. The associated RespSepData response packet's resp_err field should not take EXOK or DERR value.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit validity	valid_respsepdata_flit_type_for_xact_check	ARM-IHI0050E.b: 4.5 Response types	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	The Response flit type must correspond to one of the permitted values depending on the type of the transaction	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	associate_respsepdata_to_xact_check	ARM-IHI0050E.b: 2.8.4 Ordering semantics of RespSepData and DataSepResp	RespSepData response is not permitted for Read transactions with Exclusives or ordered Read transactions without CompAck or ordered Read transactions which have received a READRECEIPT.	Check that RespSepData response is seen only for Read transactions with: exclusive bit de-asserted. order field de-asserted or order field asserted along with ExpCompAck. Also, if order field is asserted in the request, there should be no READRECEIPT response in case RespSepData flow is seen.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	DMT	valid_return_txn_id_check	ARM-IHI0050E.b: 2.6 Transaction identifier field flows	If DMT is used the RetrunNID should be the NodeID of the Requester, whereas if DMT is not used the RetrunNID should be the NodeID of the Home	A transaction request from Home to Slave also includes a ReturnTxnID field to convey the value of TxnID in the data response from the Slave. Its value, when applicable, must be either: The TxnID generated by Home, when the ReturnNID is the Node ID of the Home when DMT is not used The TxnID of the original Requester, when the ReturnNID is the Node ID of the original Requester when DMT is used	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	DMT	valid_order_type_for_non_dmt_check	ARM-IHI0050E.b: 5.1.8 ReadNoSnp transaction with DMT and separate Non-data and Data-only response	Order field can be set to REQ_ACCEPTED for readnosnp from HN to SN only when DMT is used	Order field can be set to REQ_ACCEPTED for readnosnp from HN to SN only when DMT is used	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	associate_compstashdone_to_xact_check	ARM-IHI0050E.b: 2.5 Details of transaction identifier fields	TargetID and DBID[7:0] in a CompStashDone response must match the SrcID and StashGroupID fields of the corresponding StashOnceSep* transaction	Check that the TargetID and DBID[7:0] fields are set correctly in CompStashDone responses. A CompStashDone response can be received only for StashOnceSep* transaction.	ERROR	svt_chi_protocol_err_check
CHI Protocol Layer	resp flit valid	associate_stashdone_to_xact_check	ARM-IHI0050E.b: 2.5 Details of transaction identifier fields	TargetID and DBID[7:0] in a StashDone response must match the SrcID and StashGroupID fields of the corresponding StashOnceSep* transaction	Check that the TargetID and DBID[7:0] fields are set correctly in StashDone responses. A StashDone response can be received only for StashOnceSep* transaction.	ERROR	svt_chi_protocol_err_check

Group

Sub Group

Protocol Check Instance name

Reference

Description

Check Intent

Error Category

Protocol Check Class

APB2

State Transition

initial_bus_state_after_reset

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

After reset the bus initially should be in either IDLE or SETUP State

Checks that after reset de-assertion, APB Bus is in either IDLE or SETUP state.

ERROR

APB2

Slave Selection

multiple_select_signals_active_during_transfer

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.4.2 APB bridge description

Only one select signal can be active during a transfer

Checks if multiple select signals asserted during transfer

ERROR

APB2

Signal Validity

signal_valid_prdata_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PRDATA must be valid when PSEL, PENABLE and PREADY are asserted for read transfer

Checks that PRDATA is not X or Z when PSEL, PENABLE and PREADY are asserted for read transfer

ERROR

APB2

Unaligned Transfers

address_not_aligned_when_unaligned_address_support_not_enabled

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus

Unaligned address should not be driven on PADDR when unaligned_address_support is not enabled

Checks if unaligned address is driven on PADDR when unaligned_address_support is not enabled.

WARNING

APB2

Signal Stability

pwdata_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers

PWDATA must be stable until the write transfer completes

Checks if PWDATA changed value during write transfer

ERROR

APB2

Signal Stability

pwrite_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PWRITE must be stable until the transfer completes

Checks if PWRITE changed value during transfer

ERROR

APB2

Signal Stability

paddr_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PADDR must be stable until the transfer completes

Checks if PADDR changed value during transfer

ERROR

APB2

Signal Stability

psel_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PSEL must be stable until the transfer completes

Checks if PSEL changed value during transfer

ERROR

APB2

Signal Validity

signal_valid_pwdata_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PWDATA must be valid when PSEL is asserted for write transfer

Checks that PWDATA is not X or Z when PSEL is asserted for write transfer

ERROR

APB2

Signal Validity

signal_valid_penable_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PENABLE must be valid when PSEL is asserted

Checks that PENABLE is not X or Z when PSEL is asserted

ERROR

APB2

Signal Validity

signal_valid_pwrite_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PWRITE must be valid when PSEL is asserted

Checks that PWRITE is not X or Z when PSEL is asserted

ERROR

APB2

Signal Validity

signal_valid_paddr_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PADDR must be valid when PSEL is asserted

Checks that PADDR is not X or Z when PSEL is asserted

ERROR

APB2

Signal Validity

signal_valid_psel_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSEL must be always valid

Checks that PSEL is not X or Z

ERROR

APB2

State Transition

penable_after_psel

AMBA APB Protocol Specification ARM IHI 0011A: 5.2.1 State diagram

PENABLE should be asserted after one clock cycle of PSEL being asserted

Checks that PENABLE is asserted after one clock cycle of PSEL being asserted.

ERROR

APB2

Address Mapping

psel_match_with_address_map

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.5.2 APB slave description

Asserted PSEL should match with the address map

Checks that asserted PSEL matches with the address map. Refer to ARM IHI 0011A section 2.4, signal description of PSELx for the protocol info.

ERROR

APB2

State Transition

setup_to_setup

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

SETUP to SETUP is an illegal state transition

Checks that if illegal state transition occured from setup to setup

ERROR

APB2

APB2 State Transition

access_to_access

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

ACCESS to ACCESS is an illegal state transition in APB2

Checks that if illegal state transition occured from access to access in APB2. In APB3 state transition from access to access is valid transition.

ERROR

APB2

State Transition

setup_to_idle

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

SETUP to IDLE is an illegal state transition

Checks that if illegal state transition occured from setup to idle

ERROR

APB2

APB2 State Transition

bus_in_enable_state_for_one_clock

AMBA APB Protocol Specification ARM IHI 0011A: Section 5.2.1 State diagram

ENABLE state lasts only for a single clock cycle in APB2

Checks that bus remains in ENABLE state for one clock cycle in APB2

ERROR

APB3

Signal Validity

signal_valid_pslverr_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSLVERR must be valid when PSEL, PENABLE and PREADY are asserted

Checks that PSLVERR is not X or Z when PSEL, PENABLE and PREADY are asserted

ERROR

APB3

Signal Validity

signal_valid_pready_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PREADY must be valid when PSEL and PENABLE are asserted

Checks that PREADY is not X or Z when PSEL and PENABLE are asserted

ERROR

APB3

Transaction Timeout

pready_timeout_check

Synopsys Defined

PREADY should be asserted by the slave within the timeout period

Checks that PREADY signal is asserted by slave within timeout period slave_pready_timeout

ERROR

APB3

Signal Stability

penable_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PENABLE must be stable until the transfer completes

Checks if PENABLE changed value during access phase of transfer

ERROR

APB3

State Transition

idle_to_access

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 4.1 Operating states

IDLE to ACCESS is an illegal state transition

Checks that if illegal state transition occured from idle to access

ERROR

APB4 Protection Unit Support

Signal Stability

pprot_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers & 3.3 Read transfers

PPROT must be stable until the transfer completes

Checks if PPROT changed value during transfer

ERROR

APB4 Protection Unit Support

Signal Validity

signal_valid_pprot_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PPROT must be valid when PSEL is asserted

Checks that PPROT is not X or Z when PSEL is asserted

ERROR

APB4 Write Strobes

Signal Stability

pstrb_changed_during_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.1 Write transfers

PSTRB must be stable until the transfer completes

Checks if PSTRB changed value during write transfer

ERROR

APB4 Write Strobes

PSTRB Validity

pstrb_low_for_read

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 3.2 Write strobes

All bits of PSTRB must be LOW for read transfer

Checks that PSTRB is low for read transfer

ERROR

APB4 Write Strobes

Signal Validity

signal_valid_pstrb_check

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Appendix A.1 Validity rules

PSTRB must be valid when PSEL is asserted

Checks that PSTRB is not X or Z when PSEL is asserted

ERROR

APB4 Write Strobes

Unaligned Transfers

pstrb_asserted_for_invalid_byte_in_unaligned_transfer

AMBA APB Protocol Specification ARM IHI 0024E ID022823: Section 2.1.1 Address bus & 3.2 Write strobes

PSTRB should be correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled

Checks if PSTRB is correctly asserted when unaligned address is driven on PADDR with unaligned_address_support enabled.

ERROR

AHB System

Manager Subordinate Transaction Association

master_slave_xact_resp_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Response signals should match between manager transaction and the corresponding subordinate transaction.

Checks that response signals match between manager transaction and the corresponding subordinate transaction.

ERROR

AHB System

Manager Subordinate Transaction Association

master_slave_xact_data_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Data values should match between manager transaction and the corresponding subordinate transaction.

Checks that data values match between manager transaction and the corresponding subordinate transaction.

ERROR

AHB System

Manager Subordinate Transaction Association

master_slave_xact_addr_ctrl_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Address and control signals should match between manager transaction and the corresponding subordinate transaction.

Checks that address and control signals match between manager transaction and the corresponding subordinate transaction.
Following control signal attributes are compared.

addr
xact_type
burst_type
burst_size
prot_type

ERROR

AHB System

Dummy Manager

xact_not_idle_when_dummy_master_active

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus manager

Transfer type of the transaction is not IDLE when dummy manager is active.

Checks that IDLE transactions are driven when the dummy manager is active

ERROR

AHB System

Locked Transfers in Arbiter

hmastlock_changed_during_incr

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked transfers

HMASTLOCK signal changed during INCR burst transfer.

Checks that the HMASTLOCK signal remains constant during an INCR burst

ERROR

AHB System

Locked Transfers in Arbiter

arbiter_asserted_hmastlock_without_hlock

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers

Arbiter asserted HMASTLOCK signal when the manager has not requested.

Checks that the arbiter does not assert HMASTLOCK when the manager has not requested

ERROR

AHB System

Locked Transfers in Arbiter

arbiter_lock_last_grant

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers

Arbiter did not keep manager granted for an additional transfer after a locked sequence.

Checks that the arbiter keeps the manager granted for an additional transfer after a locked sequence

ERROR

AHB System

Locked Transfers in Arbiter

arbiter_changed_hmaster_during_lock

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.5 Locked transfers

HMASTER signal changed during locked transfer.

Checks that the arbiter does not change HMASTER during a locked transfer

ERROR

AHB System

Granted Manager in Split Transfer in Arbiter

mask_hgrant_until_hsplit_assert

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12.1 Split transfer sequence

Manager should not be regranted until the subordinate is ready to complete the transfer and asserts HSPLIT.

Checks that if the manager has got split, grant must be not given to that manager until subordinate asserts hsplitx

ERROR

AHB System

Granted Manager in Split Transfer in Arbiter

grant_to_default_master_during_allmaster_split

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.6 Default bus master

If all managers has received a SPLIT response then the default manager is granted the bus.

Checks that If all managers has received a SPLIT response then the default manager is granted the bus.

ERROR

AHB System

Granted Manager in Arbiter

arbiter_changed_hmaster_during_wait

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.11.3 Granting bus access

HMASTER signal changed during waited state.

Checks that the arbiter does not change HMASTER during a waited transfer

ERROR

AHB System

Granted Manager in Arbiter

arbiter_asserted_hmaster_ne_granted_master

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access

HMASTER signal does not reflect the granted manager.

Checks that the arbiter assert HMASTER to reflect the Granted manager

ERROR

AHB System

Granted Manager in Arbiter

arbiter_asserted_multi_hgrant

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.3 Granting bus access

Arbiter asserted more than one HGRANT signal.

Checks that the arbiter does not assert more than one HGRANT signal

ERROR

AHB System

Subordinate Selection in Decoder

decoder_not_asserted_any_hsel

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals

Decoder not asserted any HSEL signal.

Checks that the decoder does assert atleast one HSEL signal

ERROR

AHB System

Subordinate Selection in Decoder

decoder_asserted_multi_hsel

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.4 Decoder signals

Decoder asserted more than one HSEL signal.

Checks that the decoder does not assert more than one HSEL signal

ERROR

AHB System

Data Integrity

data_integrity_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921

Transaction data inconsistent with subordinate memory.

Checks that data in transaction is consistent with data in memory when the transaction completes. This checks that a WRITE transaction issued by a manager is written to memory correctly. Similarly, it checks that a READ transaction fetches the correct data from memory. The check assumes that a transaction issued by a manager completes only after response is received from the subordinate to which that transaction was routed. It also assumes that there is no other transaction that accesses an overlapping address during the period that the response is issued by the subordinate and the transaction completes in the manager that issued the transaction.
Note that this check is not performed on the transactions that are routed to the default subordinate.

ERROR

AHB System

Routing

slave_transaction_routing_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.1 Interconnect

Transaction not routed to the correct subordinate based on system address map.

Checks that a transaction is routed correctly to a slave port based on address.

This check is not performed on default_slave if the default slave is set to -1 through svt_ahb_system_configuration :: default_slave.
If svt_ahb_system_configuration :: default_slave is set to a value in the range 0 to 15, then this check is performed on the default slave also.
This check is preformed on all the slaves other than the default slave irrespective of the value of svt_ahb_system_configuration :: default_slave.

ERROR

AHB_COMMON

Address Phase Timing

ahb_address_phase_extended

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 1.3 Operation

A Subordinate cannot request that the address phase is extended.

Checks that address phase is not extended by the Subordinate

ERROR

AHB_COMMON

During Reset

hready_out_from_bus_high_during_reset

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset

During reset, HREADY output from bus must be HIGH

Checks that HREADY output signal from bus is HIGH when reset is active

ERROR

AHB_COMMON

Performance Metrics

perf_min_write_throughput

SYNOPSYS DEFINED

Checks that the throughput of write transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of write transactions in a given interval is not less that the configured min value

ERROR

AHB_COMMON

Performance Metrics

perf_max_write_throughput

SYNOPSYS DEFINED

Checks that the throughput of write transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of write transactions in a given interval is not more that the configured max value

ERROR

AHB_COMMON

Performance Metrics

perf_min_read_throughput

SYNOPSYS DEFINED

Checks that the throughput of read transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of read transactions in a given interval is not less that the configured min value

ERROR

AHB_COMMON

Performance Metrics

perf_max_read_throughput

SYNOPSYS DEFINED

Checks that the throughput of read transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of read transactions in a given interval is not more that the configured max value

ERROR

AHB_COMMON

Performance Metrics

perf_avg_min_read_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of read transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of read transactions in a given interval is not less than the configured min value

ERROR

AHB_COMMON

Performance Metrics

perf_avg_max_read_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of read transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of read transactions in a given interval is not more than the configured max value

ERROR

AHB_COMMON

Performance Metrics

perf_min_read_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a read transaction is more than or equal to the configured min value

Checks that the latency of a read transaction is not lesser than the configured min value

ERROR

AHB_COMMON

Performance Metrics

perf_max_read_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a read transaction is less than or equal to the configured max value

Checks that the latency of a read transaction is not greater than the configured max value

ERROR

AHB_COMMON

Performance Metrics

perf_avg_min_write_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of write transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of write transactions in a given interval is not less than the configured min value

ERROR

AHB_COMMON

Performance Metrics

perf_avg_max_write_xact_latency

SYNOPSYS DEFINED

Checks that the average latency of write transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of write transactions in a given interval is not more than the configured max value

ERROR

AHB_COMMON

Performance Metrics

perf_min_write_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a write transaction is more than or equal to the configured min value

Checks that the latency of a write transaction is not lesser than the configured min value

ERROR

AHB_COMMON

Performance Metrics

perf_max_write_xact_latency

SYNOPSYS DEFINED

Checks that the latency of a write transaction is less than or equal to the configured max value

Checks that the latency of a write transaction is not greater than the configured max value

ERROR

AHB_COMMON

Signal Validity

signal_valid_hrdata_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HRDATA must not be X/Z

Checks that HRDATA is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_hwdata_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HWDATA must not be X/Z

Checks that HWDATA is not X or Z

ERROR

AHB_COMMON

Response Type

zero_wait_cycle_okay

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

IDLE and BUSY transfers must receive zero wait cycle OKAY response.

Checks that IDLE and BUSY transfers receive zero wait cycle OKAY response

ERROR

AHB_COMMON

Two Cycle Response

two_cycle_error_resp

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response

ERROR response was not completed in two cycles.

Checks that ERROR response completes in two cycles

ERROR

AHB_COMMON

Response Type

non_okay_response_in_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.2 Transfer pending

Response other than OKAY response was received during wait state.

Checks that only OKAY responses are received during wait state

ERROR

AHB_COMMON

Signal Validity

signal_valid_hresp_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HRESP must not be X/Z

Checks that HRESP is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_hready_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HREADY must not be X/Z

Checks that HREADY is not X or Z

ERROR

AHB_COMMON

Burst Length

burst_length_exceeded

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Burst length exceeded for fixed length burst.

Checks number of beats in a fixed length burst

ERROR

AHB_COMMON

Locked Transfers

hlock_asserted_during_non_locked_xact

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.1 Signal description

Manager should not assert lock signal in the middle of a non-locked transaction.

Checks that manager shouldn't assert hlock in the middle of a non-locked transaction

ERROR

AHB_COMMON

Signal Validity

signal_valid_hlock_check

AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list

HLOCK must not be X/Z

Checks that HLOCK is not X or Z on manager interface

ERROR

AHB_COMMON

Locked Transfers

different_subordinate_addr_region_during_locked_sequence

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.3 Locked Transfers

It is required that all transfers in a locked sequence are to the same Subordinate address region.

It is required that all transfers in a locked sequence are to the same subordinate address region.

ERROR

AHB_COMMON

Transfer Type

htrans_not_changed_to_idle_during_error

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 5.1.3 ERROR response

HTRANS did not change to IDLE during ERROR response.

Checks that HTRANS changes to IDLE during second cycle of ERROR response

ERROR

AHB_COMMON

During Reset

htrans_idle_during_reset

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset

During reset, HTRANS must be IDLE2'b00

Checks that HTRANS output signal from manager/bus is IDLE when reset is active

ERROR

AHB_COMMON

Transfer Type

seq_or_busy_before_nseq_during_xfer

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Manager started burst with SEQ or BUSY instead of NSEQ.

Checks that a manager started burst with SEQ or BUSY instead of NSEQ

ERROR

AHB_COMMON

Transfer Type

illegal_idle2seq

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Manager attempted SEQ transfer following IDLE.

Checks for IDLE changed to SEQ

ERROR

AHB_COMMON

Transfer Type

illegal_idle2busy

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Manager attempted BUSY transfer following IDLE.

Checks for IDLE changed to BUSY

ERROR

AHB_COMMON

Transfer Type

idle_changed_to_busy_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Manager cancelled IDLE transfer during wait state and changed it to BUSY transfer.

Checks for IDLE changed to BUSY during wait state

ERROR

AHB_COMMON

Transfer Type

idle_changed_to_seq_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Manager cancelled IDLE transfer during wait state and changed it to SEQ transfer.

Checks for IDLE changed to SEQ during wait state

ERROR

AHB_COMMON

Signal Stability

ctrl_or_addr_changed_during_busy

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Control signalsother than HTRANS or address changed during BUSY.

Checks whether control signals(other than HTRANS) or address changed during BUSY

ERROR

AHB_COMMON

Signal Stability

illegal_control_transition

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals

Control signals other than HTRANS changed during burst.

Checks whether control signals(other than HTRANS) changed during burst

ERROR

AHB_COMMON

Burst Address

ahb_valid_beat_address_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

valid beat address check.

Checks for valid beat address of each beat in a transaction

ERROR

AHB_COMMON

Burst Address

illegal_address_transition

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Illegal address transition during burst.

Checks for illegal address transition during burst

ERROR

AHB_COMMON

Burst Address

boundry_crossing_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Burst transfer crossed boundary

Checks that burst transfer does not cross configured boundary limit

ERROR

AHB_COMMON

Burst Address

one_k_boundry_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6 Burst operation

Burst transfer crossed 1 KB boundary.

Checks that burst transfer does not cross 1 KB boundary

ERROR

AHB_COMMON

Transfer Size

hsize_too_big_for_data_width

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.3.3 Implementing a Manager on a wide bus

Manager attempted transfer size greater than data bus width.

Checks that manager attempted transfer size greater than data bus width

ERROR

AHB_COMMON

Early Burst Termination

burst_terminated_early_after_okay

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination

Manager terminated burst early after OKAY response.

Checks that burst transaction was not terminated early:

AHB manager should never terminate a burst transfer when OKAY response is received.
In case of Full-AHB mode, the manager should rebuild the burst transfer in case of EBT/SPLIT/RETRY before initiating new burst.

ERROR

AHB_COMMON

Signal Stability

hwdata_changed_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 6.1.1 HWDATA

HWDATA changed during wait state.

Checks that write data does not change during waited state

ERROR

AHB_COMMON

Signal Stability

ctrl_or_addr_changed_end_of_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Control or address changed at the end of wait state.

Checks that control and address does not change at the end of wait state

ERROR

AHB_COMMON

Signal Stability

ctrl_or_addr_changed_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

Control or address changed during wait state.

Checks that contol and address does not change during wait state except when htrans changes from IDLE to NSEQ

ERROR

AHB_COMMON

Signal Stability

htrans_changed_during_wait_state

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.7 Waited transfers

HTRANS changed during wait state.

Checks that htrans does not change during wait state except when htrans changes from

IDLE to NSEQ during wait state for all burst types
BUSY to SEQ during wait state for all burst types
BUSY to NSEQ during wait state for unspecified length burst
BUSY to IDLE during wait state for unspecified length burst

ERROR

AHB_COMMON

Transfer Type

seq_or_busy_during_active_xact

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

In active transaction, SEQ or BUSY transfer should only occur after NSEQ.

Checks that a SEQ or BUSY trans only occur during active transaction after nseq

ERROR

AHB_COMMON

Transfer Type

trans_during_single_is_nseq

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.2 Transfer types

Transfer type of a SINGLE burst is not NSEQ

Checks that transfer type of a SINGLE burst is NSEQ

ERROR

AHB_COMMON

Signal Validity

signal_valid_hprot_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HPROT must not be X/Z

Checks that HPROT is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_hburst_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HBURST must not be X/Z

Checks that HBURST is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_hsize_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HSIZE must not be X/Z

Checks that HSIZE is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_htrans_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HTRANS must not be X/Z

Checks that HTRANS is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_hwrite_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HWRITE must not be X/Z

Checks that HWRITE is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_haddr_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HADDR must not be X/Z

Checks that HADDR is not X or Z

ERROR

AHB_COMMON

Signal Validity

hready_out_from_slave_not_X_or_Z_when_data_phase_not_pending

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.3 Subordinate signals

HREADY output from subordinate must be either HIGH or LOW when there is no pending data phase.

Checks that HREADY output from subordinate must be either HIGH or LOW when there is no data phase pending. That is, checks that the subordinate cannot request that the address phase is extended.

ERROR

AHB_COMMON

During Reset

hready_out_from_slave_not_X_or_Z_during_reset

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 7.1.2 Reset

During reset, HREADY output from subordinate must be either HIGH or LOW

Checks that HREADY output signal from subordinate is either HIGH or LOW when reset is active

ERROR

AHB_COMMON

Response Type

illegal_default_slave_resp_to_nseq_seq

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.1 Default Subordinate

Default subordinate should provide ERROR response for NON_SEQ or SEQ transfer.

Checks that for non existent memory location default subordinate should provide ERROR response for NSEQ/SEQ transfers

ERROR

AHB_COMMON

Subordinate Selection

invalid_hsel_assert_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 4.2.2 Multiple Subordinate select

Invalid HSEL signal asserted for selected subordinate

Checks that if invalid HSEL is asserted for selected subordinate. This is applicable only in mutli_hsel_enable mode

ERROR

AHB_COMMON

Signal Validity

signal_valid_hready_in_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HREADY_IN must not be X/Z

Checks that HREADY_IN is not X or Z

ERROR

AHB_COMMON

Signal Validity

signal_valid_hmastlock_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HMASTLOCK must not be X/Z

Checks that HMASTLOCK is not X or Z on subordinate interface

ERROR

AHB_COMMON

Signal Validity

signal_valid_hmaster_range_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 2.2 Manager signals

HMASTER should not be beyond SVT_AHB_MAX_NUM_MASTERS

Checks that HMASTER value is in valid range based on SVT_AHB_MAX_NUM_MASTERS

ERROR

AHB_COMMON

Signal Validity

signal_valid_hsel_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HSEL must not be X/Z

Checks that HSEL is not X or Z

ERROR

AHB_FULL

Two Cycle Response

two_cycle_retry_resp

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

RETRY response was not completed in two cycles.

Checks that RETRY response completes in two cycles

ERROR

AHB_FULL

Two Cycle Response

two_cycle_split_resp

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

SPLIT response was not completed in two cycles.

Checks that SPLIT response completes in two cycles

ERROR

AHB_FULL

Transfer Type

htrans_not_idle_or_nseq_during_no_grant

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access

Manager should drive HTRANS to IDLE or NSEQ when it does not have access to the bus.

Checks that manager drives HTRANS to IDLE or NSEQ when it does not have access to the bus

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_retry

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during RETRY response.

Checks that HTRANS changes to IDLE during second cycle of RETRY response

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_split

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during SPLIT response.

Checks that HTRANS changes to IDLE during second cycle of SPLIT response

ERROR

AHB_FULL

Signal Validity

signal_valid_hbusreq_check

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.11.2 Requesting bus access

HBUSREQ must not be X/Z

Checks that HBUSREQ is not X or Z

ERROR

AHB_FULL

Rebuild Transaction

rebuild_xact_with_valid_combination_of_bursts

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry

Manager should restart an interrupted burst with a valid combination of bursts.

Checks that the manager restarted an interrupted burst with a valid combination of bursts

ERROR

AHB_FULL

Rebuild Transaction

rebuild_xact_with_expected_addr

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.6.1 Early burst termination, Section 3.9.5 Split and retry

Manager should restart an interrupted burst from the address of the aborted beat.

Checks that the manager restarted an interrupted burst from the address of the aborted beat

ERROR

AHB_FULL

Response Type

hsplit_asserted_for_non_split_master

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers

Subordinate should not assert HSPLIT corresponding to a manager it has not split earlier.

Checks that HSPLIT is not asserted for a manager that has not SPLIT earlier.

ERROR

AHB_FULL

Response Type

hsplit_asserted_for_one_cycle

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers

Subordinate should assert a bit of HSPLIT only for one clock cycle

Checks that HSPLIT is asserted for only one clock cycle

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_retry

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during RETRY response.

Checks that HTRANS changes to IDLE during second cycle of RETRY response

ERROR

AHB_FULL

Transfer Type

htrans_not_changed_to_idle_during_split

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.9.3 Two-cycle response

HTRANS did not change to IDLE during SPLIT response.

Checks that HTRANS changes to IDLE during second cycle of SPLIT response

ERROR

AHB_FULL

Bus Grant

illegal_hgrant_on_split_resp

AMBA AHB Protocol Specification ARM IHI 0011A: Section 3.12 Split transfers

Manager should lose the bus once it gets the split response from the subordinate.

Checks that manager loses the bus once it gets the split response from the subordinate.

ERROR

AHB_FULL

Signal Validity

signal_valid_hgrant_check

AMBA AHB Protocol Specification ARM IHI 0011A: Section 2.2 AMBA AHB signal list

HGRANT must not be X/Z

Checks that HGRANT is not X or Z

ERROR

AHB_FULL

Signal Validity

signal_valid_hmaster_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HMASTER must not be X/Z

Checks that HMASTER is not X or Z

ERROR

AHB_Lite

Response Type

ahb_lite_split_response

AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses

SPLIT response was received when configured as AHB Lite system.

Checks that SPLIT responses are not received when configured for AHB Lite

ERROR

AHB_Lite

Response Type

ahb_lite_retry_response

AMBA AHB Protocol Specification ARM IHI 0033A: Section 5.1 Slave transfer responses

RETRY response was received when configured as AHB Lite system.

Checks that RETRY responses are not received when configured for AHB Lite

ERROR

ARM11/AHB_V6 Exclusive Accesses

Two Cycle Response

two_cycle_xfail_resp

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.3.1 Exclusive Access Protocol

XFAIL response was not completed in two cycles.

Checks that XFAIL response completes in two cycles

ERROR

ARM11/AHB_V6 Unaligned Transfers

Valid Unaligned Transfer

valid_unaligned_transfer

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1.2 Burst, Unaligned accesses and Byte Lane Strobes

HUNALIGN should be asserted for an unaligned transfer

Checks that HUNALIGN signal is correctly set for unaligned transfers. Based on ARMv6 AMBA Extension Spec (Document No: PR022-GENC-001011) section 3.1.2, example 3.1.2.2 in the document and ARM discussions following items are mandatory.

It would be mandatory for any initiator using the ARM11 extensions generating an unaligned AHB transfer to drive HUNALIGN=1
If HUNALIGN=0 it tells the target that HADDR will be fully AHB v2.0 compliant and HADDR will be aligned to HSIZE

ERROR

ARM11/AHB_V6 Unaligned Transfers

Signal Stability

hunalign_changed_during_transfer

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HUNALIGN should not change in middle of a transfer

Checks that HUNALIGN output signal from manager dosenot changes its value in middle of a transfer

ERROR

ARM11/AHB_V6 Unaligned Transfers

Valid Byte Lane Strobes

valid_byte_lane_for_hbstrb

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HRDATA/HWDATA byte lanes corresponding to HBSTRB should be selected

Checks that HRDATA/HWDATA byte lanes are selected corresponding to bits HBSTRB signal which have value 1

ERROR

ARM11/AHB_V6 Unaligned Transfers

Signal Validity

signal_valid_hunalign_check

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HUNALIGN must not be X/Z

Checks that HUNALIGN is not X or Z

ERROR

ARM11/AHB_V6 Unaligned Transfers

Signal Validity

signal_valid_hbstrb_check

ARMv6 AMBA Extensions PR022-GENC-001011 0.7: Section 3.1 Byte Strobes

HBSTRB must not be X/Z

Checks that HBSTRB is not X or Z

ERROR

AHB5 Extended Memory Types

Signal Validity

signal_valid_hprot_ex_range_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.9 Memory types

HPROT signal is not having the valid value

Checks that Extended_Memory_Type supporting HPROT[6:2] is having valid values

ERROR

AHB5 Secure Transfers

Signal Validity

signal_valid_hnonsec_check

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 8.2 Signal validity rules

HNONSEC must not be X/Z

Checks that HNONSEC is not X or Z

ERROR

AHB_Lite_Multilayer

Rebuild Transaction

rebuild_xact_with_valid_combination_of_bursts

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination

Manager should restart an interrupted burst with a valid combination of bursts.

Checks that the manager restarted an interrupted burst with a valid combination of bursts

ERROR

AHB_Lite_Multilayer

Rebuild Transaction

rebuild_xact_with_expected_addr

AMBA AHB Protocol Specification ARM IHI 0033C ID090921: Section 3.6.2 Early burst termination - Multi-layer interconnect termination

Manager should restart an interrupted burst from the address of the aborted beat.

Checks that the manager restarted an interrupted burst from the address of the aborted beat

ERROR

CHI Link Layer

signal validity

valid_rxdatflit_signal_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit. Description : RXDATFLIT must not be X/Z when RXDATFLITV is asserted

RXDATFLIT must not be X/Z when RXDATFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

valid_txdatflit_signal_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit. Description : TXDATFLIT must not be X/Z when TXDATFLITV is asserted

TXDATFLIT must not be X/Z when TXDATFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

valid_reqflit_signal_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit. Description : REQFLIT must not be X/Z when REQFLITV is asserted

REQFLIT must not be X/Z when REQFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txdatlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATLCRDV must be 0 during reset

TXDATLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxdatflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATFLITV must be 0 during reset

RXDATFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txrsplcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPLCRDV must be 0 during reset

TXRSPLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxreqlcrdv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request L-Credit Valid Description : RXREQLCRDV must not be X/Z

RXREQLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxreqlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQLCRDV must be 0 during reset

RXREQLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_compstashdone_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : CompStashDone Description : Check fields for response VC flit of a CompStashDone

Response VC message fields must be set to valid values for a CompStashDone transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_stashdone_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : StashDone Description : Check fields for response VC flit of a StashDone

Response VC message fields must be set to valid values for a StashDone transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_dbidrespord_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : DBIDRespOrd Description : Check fields for response VC flit of a DBIDRespOrd

Response VC message fields must be set to valid values for a DBIDRespOrd transaction.

ERROR

CHI Link Layer

signal validity

signal_valid_rxsnpflitv_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop Flit Valid Description : RXSNPFLITV must not be X/Z

RXSNPFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxsnpflitpend_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop Flit Pending Description : RXSNPFLITPEND must not be X/Z

RXSNPFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxrspflitv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Valid Description : RXRSPFLITV must not be X/Z

RXRSPFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxrspflitpend_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Pending Description : RXRSPFLITPEND must not be X/Z

RXRSPFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txreqlcrdv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request L-Credit Valid Description : TXREQLCRDV must not be X/Z

TXREQLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

valid_rxrspflit_signal_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit. Description : RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted

RXRSPFLIT must not be X/Z when RXRSPFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxrspflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPFLITV must be 0 during reset

RXRSPFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txreqlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQLCRDV must be 0 during reset

TXREQLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxreqflitv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Valid Description : RXREQFLITV must not be X/Z

RXREQFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxreqflitpend_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Pending Description : RXREQFLITPEND must not be X/Z

RXREQFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxreqflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXREQFLITV must be 0 during reset

RXREQFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxrsplcrdv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response L-Credit Valid Description : RXRSPLCRDV must not be X/Z

RXRSPLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txreqflitv_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Valid Description : TXREQFLITV must not be X/Z

TXREQFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxsnplcrdv_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop L-Credit Valid Description : RXSNPLCRDV must not be X/Z

RXSNPLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txreqflitpend_check

ARM-IHI0050E.b:13.8.1 Request,REQ ,channel

Spec Text : Request Flit Pending Description : TXREQFLITPEND must not be X/Z

TXREQFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxrsplcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXRSPLCRDV must be 0 during reset

RXRSPLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txreqflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXREQFLITV must be 0 during reset

TXREQFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxlinkactivereq_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEREQ must be 0 during reset

RXLINKACTIVEREQ must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txlinkactiveack_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEACK must be 0 during reset

TXLINKACTIVEACK must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxlinkactivereq_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEREQ must not be X/Z

RXLINKACTIVEREQ must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxdatflitv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Valid Description : RXDATFLITV must not be X/Z

RXDATFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxdatflitpend_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Pending Description : RXDATFLITPEND must not be X/Z

RXDATFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txrsplcrdv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response L-Credit Valid Description : TXRSPLCRDV must not be X/Z

TXRSPLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txdatlcrdv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data L-Credit Valid Description : TXDATLCRDV must not be X/Z

TXDATLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxsactive_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : RXSACTIVE signal Description : RXSACTIVE must not be X/Z

RXSACTIVE must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txlinkactiveack_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEACK must not be X/Z

TXLINKACTIVEACK must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

valid_txrspflit_signal_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit. Description : TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted

TXRSPFLIT must not be X/Z when TXRSPFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxdatlcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXDATLCRDV must be 0 during reset

RXDATLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txdatflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXDATFLITV must be 0 during reset

TXDATFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txrspflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXRSPFLITV must be 0 during reset

TXRSPFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxlinkactiveack_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXLINKACTIVEACK must be 0 during reset

RXLINKACTIVEACK must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_txlinkactivereq_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : TXLINKACTIVEREQ must be 0 during reset

TXLINKACTIVEREQ must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxdatlcrdv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data L-Credit Valid Description : RXDATLCRDV must not be X/Z

RXDATLCRDV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txrspflitv_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Valid Description : TXRSPFLITV must not be X/Z

TXRSPFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txrspflitpend_check

ARM-IHI0050E.b:13.8.2 Response,RSP ,channel

Spec Text : Response Flit Pending Description : TXRSPFLITPEND must not be X/Z

TXRSPFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txdatflitv_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Valid Description : TXDATFLITV must not be X/Z

TXDATFLITV must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txdatflitpend_check

ARM-IHI0050E.b:13.8.4 Data,DAT ,channel

Spec Text : Data Flit Pending Description : TXDATFLITPEND must not be X/Z

TXDATFLITPEND must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_rxlinkactiveack_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : RXLINKACTIVEACK must not be X/Z

RXLINKACTIVEACK must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txsactive_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : TXSACTIVE signal Description : TXSACTIVE must not be X/Z

TXSACTIVE must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

signal validity

signal_valid_txlinkactivereq_check

ARM-IHI0050E.b:14: Link Handshake

Spec Text : Request and Acknowledge handshake Description : TXLINKACTIVEREQ must not be X/Z

TXLINKACTIVEREQ must not be X/Z.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

l-credit

valid_lcredit_range_check

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : The minimum number of L-Credits that a Receiver can provide is one.The maximum number of L-Credits that a Receiver can provide is 15 Description : The l-credit must be within the valid range

The minimum number of L-Credits that a receiver can provide is one. The maximum number of L-Credits that a receiver can provide is defined as follows based on vc_id
- RXREQ: svt_chi_node_configuration :: rx_req_vc_flit_buffer_size
- RXDAT: svt_chi_node_configuration :: rx_dat_vc_flit_buffer_size
- RXRSP: svt_chi_node_configuration :: rx_rsp_vc_flit_buffer_size
- RXSNP: svt_chi_node_configuration :: rx_snp_vc_flit_buffer_size

ERROR

CHI Link Layer

link deactivation

tx_link_deactive_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner Description : If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner

Link deactivation must complete in a timely manner in response to a received request.

ERROR

CHI Link Layer

link activation

tx_link_active_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner Description : If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the interface, then it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner

Link activation must complete in a timely manner in response to a received request.

ERROR

CHI Link Layer

link activation

tx_link_not_active_during_flit_transfer

ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake

Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be sent on its virtual channel only if the link is active.

Flits must not be transmitted while the link is not active

ERROR

CHI Link Layer

link deactivation

rx_link_deactive_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If a component moves the TXLINK to the DEACTIVATE state, which it controls, it can expect the RXLINK to also move to the DEACTIVATE state, in a timely manner Description : If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner

Link deactivation must complete in a timely manner in response to a received request. If the TXLINK moves to the DEACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the DEACTIVATE state, in a timely manner.

ERROR

CHI Link Layer

link activation

rx_link_active_request_timeout_check

ARM-IHI0050E.b:14.6.1 Introduction

Spec Text : If a component moves the TXLINK to the ACTIVATE state, which it controls, it can expect the RXLINK to also move to the ACTIVATE state, in a timely manner Description : If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner

Link activation must complete in a timely manner in response to a received request. If the TXLINK moves to the ACTIVATE state, which is controlled by the current component, then it is required that the RXLINK also moves to the ACTIVATE state, in a timely manner.

ERROR

CHI Link Layer

link activation

rx_link_not_active_during_flit_reception

ARM-IHI0050E.b:14.5.1 Request and Acknowledge handshake

Spec Text : Behavior for each Request and Acknowledge state Description : A flit can be observed on its RX virtual channel only if the corresponding link is active.

Flits must be observed only when the link is active

ERROR

CHI Link Layer

dat flit valid

invalid_data_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : DAT channel opcodes encoding Description : Check for Reserved opcode bits for Data VC commands

Reserved (opcodes) Data VC commands cannot be used.

ERROR

CHI Link Layer

dat flit valid

data_flit_lcrdreturn_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : DatLCrdReturn Description : Check fields for a DataLCrdReturn flit

Data VC message fields must be set to valid values for a DataLCrdReturn transaction

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_lcrdreturn_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : RspLCrdReturn Description : Check fields for a RspLCrdReturn flit

Response VC message fields must be set to valid values for a RspLCrdReturn transaction

ERROR

CHI Link Layer

req flit valid

req_flit_lcrdreturn_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReqLCrdReturn Description : Check fields for a ReqLCrdReturn flit

Request VC message fields must be set to valid values for a ReqLCrdReturn transaction

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_tagmatch_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : TagMatch Description : Check fields for response VC flit of a TagMatch transaction

Response VC message fields must be set to valid values for a TagMatch transaction.

ERROR

CHI Link Layer

rsp flit valid

invalid_rsp_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : RSP channel opcodes encoding Description : Check for Reserved opcode bits for Response VC commands

Reserved (opcodes) Response VC commands cannot be used.

ERROR

CHI Link Layer

dat flit valid

data_flit_datasepresp_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : DataSepResp Description : Check fields for data VC flit of a DataSepResp

Data VC message fields must be set to valid values for a DataSepResp transaction.

ERROR

CHI Link Layer

dat flit valid

data_flit_compdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : CompData Description : Check fields for data VC flit of a CompData transaction

Data VC message fields must be set to valid values for a CompData transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_pcrdgrant_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : PCrdGrant Description : Check fields for response VC flit of a PCrdGrant transaction

Response VC message fields must be set to valid values for a PCrdGrant transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_dbidresp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : DBIDResp Description : Check fields for response VC flit of a DBIDResp transaction

Response VC message fields must be set to valid values for a DBIDResp transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_compdbidresp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : CompDBIDResp Description : Check fields for response VC flit of a CompDBIDResp transaction

Response VC message fields must be set to valid values for a CompDBIDResp transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_compcmo_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : CompCMO Description : Check fields for response VC flit of a CompCMO response

Response VC message fields must be set to valid values for a CompCMO response.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_persist_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : Persist Description : Check fields for response VC flit of a Persist response

Response VC message fields must be set to valid values for a Persist response to a CompPersistSep transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_comppersist_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : CompPersist Description : Check fields for response VC flit of a CompPersist response

Response VC message fields must be set to valid values for a CompPersist response to CleanSharedPersistSep transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_comp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : Comp Description : Check fields for response VC flit of a Comp transaction

Response VC message fields must be set to valid values for a Comp transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_retryack_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : RetryAck Description : Check fields for response VC flit of a RetryAck transaction

Response VC message fields must be set to valid values for a RetryAck transaction.

ERROR

CHI Link Layer

dat flit valid

data_flit_ncbwrdatacompack_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : NCBWrDataCompAck Description : Check fields for data VC flit of a NcbWrDataCompack flit

Data VC message fields must be set to valid values for a NCBWrDataCompAck transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readnosnpsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadNoSnpSep Description : Check fields for request VC flit of a ReadNoSnpSep transaction

Request VC message fields must be set to valid values for a ReadNoSnpSep transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_respsepdata_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : RespSepData Description : Check fields for response VC flit of a RespSepData

Response VC message fields must be set to valid values for a RespSepData transaction.

ERROR

CHI Link Layer

req flit valid

valid_xact_attributes_combination_check

ARM-IHI0050E.b:2.9.4 Transaction attribute combinations

Spec Text : Legal combinations of MemAttr, SnpAttr, and Order field values Description : check combinations of MemAttr, SnpAttr, LikelyShared and Order for a transaction

Transaction attributes in the Request VC message must take valid combinations.

ERROR

CHI Link Layer

req flit valid

invalid_req_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : REQ channel opcodes Description : Check for Reserved opcode bits for Request VC commands

Reserved (opcodes) Request VC commands cannot be used.

ERROR

CHI Link Layer

dat flit valid

data_flit_writedatacancel_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : WriteDataCancel Description : Check fields for data VC flit of a WriteDataCancel transaction

Data VC message fields must be set to valid values for a writedatacancel transaction.

ERROR

CHI Link Layer

dat flit valid

data_flit_noncopybackwrdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : NonCopyBackWrData Description : Check fields for data VC flit of a NonCopyBackWrData transaction

Data VC message fields must be set to valid values for a NonCopyBackWrData transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readnosnp_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadNoSnp Description : Check fields for request VC flit of a ReadNoSnp transaction

Request VC message fields must be set to valid values for a ReadNoSnp transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpptl_cleansharedpersistsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpPtlCleanShPerSep Description : Check fields for request VC flit of a WriteNoSnpPtl_CleanSharedpersistsep transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpPtl_CleanSharedpersistsep transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpfull_cleansharedpersistsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpFullCleanShPerSep Description : Check fields for request VC flit of a WriteNoSnpFull_CleanSharedpersistsep transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpFull_CleanSharedpersistsep transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpptl_cleaninvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpPtlCleanInv Description : Check fields for request VC flit of a WriteNoSnpPtl_CleanInvalid transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpPtl_CleanInvalid transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpptl_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpPtlCleanSh Description : Check fields for request VC flit of a WriteNoSnpPtl_CleanShared transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpPtl_CleanShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpfull_cleaninvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpFullCleanInv Description : Check fields for request VC flit of a WriteNoSnpFull_CleanInvalid transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpFull_CleanInvalid transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpfull_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpFullCleanSh Description : Check fields for request VC flit of a WriteNoSnpFull_CleanShared transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteNoSnpFull_CleanShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpzero_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpZero Description : Check fields for request VC flit of a WriteNoSnpZero transaction

Request VC message fields must be set to valid values for a WriteNoSnpZero transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_cleansharedpersistsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanSharedPersistSep Description : check fields for request VC flit of a CleanSharedPersistSep transaction

Request VC message fields must be set to valid values for a CleanSharedPersistSep transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpFull Description : Check fields for request VC flit of a WriteNoSnpFull transaction

Request VC message fields must be set to valid values for a WriteNoSnpFull transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writenosnpptl_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteNoSnpPtl Description : Check fields for request VC flit of a WriteNoSnpPtl transaction

Request VC message fields must be set to valid values for a WriteNoSnpPtl transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_pcrdreturn_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : PCrdReturn Description : Check fields for request VC flit of a PCrdReturn transaction

Request VC message fields must be set to valid values for a PCrdReturn transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_stashoncesepshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : StashOnceSepShared Description : check fields for request VC flit of an StashOnceSepShared transaction

Request VC message fields must be set to valid values for an StashOnceSepShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_stashoncesepunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : StashOnceSepUnique Description : check fields for request VC flit of an StashOnceSepUnique transaction

Request VC message fields must be set to valid values for an StashOnceSepUnique transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_stashonceshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : StashOnceShared Description : check fields for request VC flit of an StashOnceShared transaction

Request VC message fields must be set to valid values for an StashOnceShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_stashonceunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : StashOnceUnique Description : check fields for request VC flit of an StashOnceUnique transaction

Request VC message fields must be set to valid values for an StashOnceUnique transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniquefullstash_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniqueFullStash Description : check fields for request VC flit of an WriteUniquefullstash transaction

Request VC message fields must be set to valid values for an WriteUniquefullstash transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniqueptlstash_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniquePtlStash Description : check fields for request VC flit of an WriteUniquePtlstash transaction

Request VC message fields must be set to valid values for an WriteUniquePtlstash transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_prefetchtgt_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : PrefetchTgt Description : Check fields for request VC flit of a Prefetch transaction

Request VC message fields must be set to valid values for a Prefetch transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readoncemakeinvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadOnceMakeInvalid Description : check fields for request VC flit of a ReadOnceMakeInvalid transaction

Request VC message fields must be set to valid values for a ReadOnceMakeInvalid transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readoncecleaninvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadOnceCleanInvalid Description : check fields for request VC flit of a ReadOnceCleanInvalid transaction

Request VC message fields must be set to valid values for a ReadOnceCleanInvalid transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_compack_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : CompAck Description : Check fields for response VC flit of a CompAck transaction

Response VC message fields must be set to valid values for a CompAck transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readonce_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadOnce Description : Check fields for request VC flit of a ReadOnce transaction

Request VC message fields must be set to valid values for a ReadOnce transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniquefull_cleansharedpersistsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniqueFullCleanShPerSep Description : Check fields for request VC flit of a WriteUniqueFull_CleanSharedpersistsep transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniqueFull_CleanSharedpersistsep transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniqueptl_cleansharedpersistsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniquePtlCleanShPerSep Description : Check fields for request VC flit of a WriteUniquePtl_CleanSharedpersistsep transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniquePtl_CleanSharedpersistsep transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniqueptl_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniquePtlCleanSh Description : Check fields for request VC flit of a WriteUniquePtl_CleanShared transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniquePtl_CleanShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniquefull_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniqueFullCleanSh Description : Check fields for request VC flit of a WriteUniqueFull_CleanShared transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteUniqueFull_CleanShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readpreferunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadPreferUnique Description : Check fields for request VC flit of a ReadPreferUnique transaction

Request VC message fields must be set to valid values for a ReadPreferUnique transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_makereadunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : MakeReadUnique Description : Check fields for request VC flit of a MakeReadUnique transaction

Request VC message fields must be set to valid values for a MakeReadUnique transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniquezero_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniqueZero Description : Check fields for request VC flit of a WriteUniqueZero transaction

Request VC message fields must be set to valid values for a WriteUniqueZero transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniquefull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniqueFull Description : Check fields for request VC flit of a WriteUniqueFull transaction

Request VC message fields must be set to valid values for a WriteUniqueFull transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeuniqueptl_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteUniquePtl Description : Check fields for request VC flit of a WriteUniquePtl transaction

Request VC message fields must be set to valid values for a WriteUniquePtl transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_makeinvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : MakeInvalid Description : Check fields for request VC flit of a MakeInvalid transaction

Request VC message fields must be set to valid values for a MakeInvalid value for transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_cleaninvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanInvalid Description : Check fields for request VC flit of a CleanInvalid transaction

Request VC message fields must be set to valid values for a CleanInvalid value for transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanShared Description : Check fields for request VC flit of a CleanShared transaction

Request VC message fields must be set to valid values for a CleanShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_atomiccompare_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : AtomicCompare Description : check fields for request VC flit of an AtomicCompare transaction

Request VC message fields must be set to valid values for an AtomicCompare transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_atomicswap_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : AtomicSwap Description : check fields for request VC flit of an AtomicSwap transaction

Request VC message fields must be set to valid values for an AtomicSwap transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_atomicload_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : AtomicLoad Description : check fields for request VC flit of an AtomicLoad transaction

Request VC message fields must be set to valid values for an AtomicLoad transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_atomicstore_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : AtomicStore Description : check fields for request VC flit of an AtomicStore transaction

Request VC message fields must be set to valid values for an AtomicStore transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_cleansharedpersist_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanSharedPersist Description : check fields for request VC flit of a CleanSharedPersist transaction

Request VC message fields must be set to valid values for a CleanSharedPersist transaction.

ERROR

CHI Link Layer

snp flit valid

invalid_snp_flit_check

ARM-IHI0050E.b:13.10.17 Channel opcodes,Opcode

Spec Text : SNP channel opcodes encoding Description : Check for Reserved opcode bits for Snoop VC commands

Reserved (opcodes) Snoop VC commands cannot be used.

ERROR

CHI Link Layer

snp flit valid

snoop_flit_lcrdreturn_check

ARM-IHI0050E.b:A.4 Snoop Request message field mappings

Spec Text : SnpLCrdReturn Description : Check fields for a SnpLCrdReturn flit

Data VC message fields must be set to valid values for a SnoopLCrdReturn transaction

ERROR

CHI Link Layer

signal validity

valid_snpflit_signal_check

ARM-IHI0050E.b:13.8.3 Snoop,SNP ,channel

Spec Text : Snoop Flit. Description : SNPFLIT must not be X/Z when SNPFLITV is asserted

SNPFLIT must not be X/Z when SNPFLITV is asserted.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

During reset

signal_valid_rxsnpflitv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPFLITV must be 0 during reset

RXSNPFLITV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

snp flit valid

snoop_flit_snpdvmop_check

ARM-IHI0050E.b:A.4 Snoop Request message field mappings

Spec Text : SnpDVMOp Description : Check fields for snoop VC flit of a SnpDVMOp transaction

Snoop VC message fields must be set to valid values for a SnpDVMOp transaction.

ERROR

CHI Link Layer

During reset

signal_valid_rxsnplcrdv_during_reset

ARM-IHI0050E.b:14.1.3 Initialization

Spec Text : During reset the following interface signals must be deasserted by the component Description : RXSNPLCRDV must be 0 during reset

RXSNPLCRDV must be 0 during reset i.e. when reset is active.
Performed from second clock edge onwards once the reset is asserted

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_snprespfwded_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : SnpRespFwded Description : Check fields for response VC flit of a SnpRspFwded transaction

Response VC message fields must be set to valid values for a SnpRspFwded transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_snpresp_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : SnpResp Description : Check fields for response VC flit of a SnpRsp transaction

Response VC message fields must be set to valid values for a SnpRsp transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_dvmop_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : DVMOp Description : Check fields for request VC flit of a DVMOp transaction

Request VC message fields must be set to valid values for a DVMOp transaction.

ERROR

CHI Link Layer

rsp flit valid

rsp_flit_readreceipt_check

ARM-IHI0050E.b:A.2 Response message field mappings

Spec Text : ReadReceipt Description : Check fields for response VC flit of a ReadReceipt transaction

Response VC message fields must be set to valid values for a ReadReceipt transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_ecbarrier_check

ARM-IHI0050A:A.1 Request message field mappings

Check fields for request VC flit of a ECBarrier transaction

Request VC message fields must be set to valid values for a ECBarrier transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_eobarrier_check

ARM-IHI0050A:A.1 Request message field mappings

Check fields for request VC flit of a EOBarrier transaction

Request VC message fields must be set to valid values for a EOBarrier transaction.

ERROR

CHI Link Layer

snp flit valid

snoop_flit_snpreq_check

ARM-IHI0050E.b:A.4 Snoop Request message field mappings

Spec Text : Snoop Request message Description : Check fields for snoop VC flit of a Snoop transaction

Snoop VC message fields must be set to valid values for a Snoop transaction (non-DVMOp).

ERROR

CHI Link Layer

req flit valid

req_flit_writebackfull_cleansharedpersistsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteBackFullCleanShPerSep Description : check fields for request VC flit of a WriteBackFull_CleanSharedpersistsep transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteBackFull_CleanSharedpersistsep transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writecleanfull_cleansharedpersistsep_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteCleanFullCleanShPerSep Description : check fields for request VC flit of a WriteCleanFull_CleanSharedpersistsep transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteCleanFull_CleanSharedpersistsep transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writecleanfull_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteCleanFullCleanSh Description : check fields for request VC flit of a WriteCleanFull_CleanShared transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteCleanFull_CleanShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writebackfull_cleaninvalid_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteBackFullCleanInv Description : check fields for request VC flit of a WriteBackFull_CleanInvalid transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteBackFull_CleanInvalid transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writebackfull_cleanshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteBackFullCleanSh Description : check fields for request VC flit of a WriteBackFull_CleanShared transaction

Request VC message fields must be set to valid values for a combined Write and CMO transaction WriteBackFull_CleanShared transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeevictorevict_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteEvictOrEvict Description : check fields for request VC flit of a WriteEvictorEvict transaction

Request VC message fields must be set to valid values for a WriteEvictorEvict transaction.

ERROR

CHI Link Layer

dat flit valid

data_flit_snprespdataptl_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : SnpRespDataPtl Description : Check fields for data VC flit of a SnpRespDataPtl transaction

Data VC message fields must be set to valid values for a SnpRespDataPtl transaction.

ERROR

CHI Link Layer

dat flit valid

data_flit_copybackwrdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : CopyBackWrData Description : Check fields for data VC flit of a CopyBackWrData transaction

Data VC message fields must be set to valid values for a CopyBackWrData transaction.

ERROR

CHI Link Layer

dat flit valid

data_flit_snprespdatafwded_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : SnpRespDataFwded Description : Check fields for data VC flit of a SnpRespDatafwded transaction

Data VC message fields must be set to valid values for a SnpRespDataFwded transaction.

ERROR

CHI Link Layer

dat flit valid

data_flit_snprespdata_check

ARM-IHI0050E.b:A.3 Data message field mappings

Spec Text : SnpRespData Description : Check fields for data VC flit of a SnpRespData transaction

Data VC message fields must be set to valid values for a SnpRespData transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_evict_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : Evict Description : Check fields for request VC flit of a Evict transaction

Request VC message fields must be set to valid values for a Evict transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writecleanptl_check

ARM-IHI0050A:A.1 Request message field mappings

Check fields for request VC flit of a WriteCleanPtl transaction

Request VC message fields must be set to valid values for a WriteCleanPtl transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writebackptl_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteBackPtl Description : Check fields for request VC flit of a WriteBackPtl transaction

Request VC message fields must be set to valid values for a WriteBackPtl transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writeevictfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteEvictFull Description : Check fields for request VC flit of a WriteEvictFull transaction

Request VC message fields must be set to valid values for a WriteEvictFull transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writecleanfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteCleanFull Description : Check fields for request VC flit of a WriteCleanFull transaction

Request VC message fields must be set to valid values for a WriteCleanFull transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_writebackfull_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : WriteBackFull Description : Check fields for request VC flit of a WriteBackFull transaction

Request VC message fields must be set to valid values for a WriteBackFull transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_makeunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : MakeUnique Description : Check fields for request VC flit of a MakeUnique transaction

Request VC message fields must be set to valid values for a MakeUnique transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_cleanunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : CleanUnique Description : Check fields for request VC flit of a CleanUnique transaction

Request VC message fields must be set to valid values for a CleanUnique transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readunique_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadUnique Description : Check fields for request VC flit of a ReadUnique transaction

Request VC message fields must be set to valid values for a ReadUnique transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readclean_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadClean Description : Check fields for request VC flit of a ReadClean transaction

Request VC message fields must be set to valid values for a ReadClean transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readnotshareddirty_check

ARM-IHI0050E.b:A.1 Request message field mappings

check fields for request VC flit of a ReadNotSharedDirty transaction, ARM-IHI0050E.b:A.1 Request message field mappings

Request VC message fields must be set to valid values for a ReadNotSharedDirty transaction.

ERROR

CHI Link Layer

req flit valid

req_flit_readshared_check

ARM-IHI0050E.b:A.1 Request message field mappings

Spec Text : ReadShared Description : check fields for request VC flit of a ReadShared transaction

Request VC message fields must be set to valid values for a ReadShared transaction.

ERROR

CHI Link Layer

l-credit

valid_num_prot_flits_in_txlasm_deactivate_state_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : The Transmitter must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit Description : The Transmitter in Deactivate state is allowed to transmit protocol flits For each additional credit received it must send an L-Credit return flit to return the credit.

The maximum number of protocol flits that a transmitter (per channel) can send in Deactivate state is the number of l-credits available at the time of entry into Deactivate state.
In other words, The Transmitter in Deactivate state must be prepared to continue receiving credits. For each additional credit received it must send an L-Credit return flit to return the credit.

ERROR

CHI Link Layer

l-credit

valid_lcredit_count_in_rx_stop_state_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : Before entering a low power state, the sending of payload flits must be stopped and all credits must be returned to the Receiver Description : The reciever must ensure that it has received all the lcredits before moving to the stop state

The reciever must ensure that it has received all the lcredits before moving to the stop state i.e before deasserting the RXLINKACTIVEACK signal. Applicable channels:

RN_I: RXRSP VC and RXDAT VC
RN_F/RN_D: RXSNP VC, RXRSP VC and RXDAT VC
SN: RXREQ VC and RXDAT VC

ERROR

CHI Link Layer

l-credit

rx_no_lcredit_issued_for_flit_type

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : When the link is active, the Receiver must provide L-Credits in a timely manner without requiring any action on the part of the Transmitter Description : When the link is active, the receiver at each virtual channel must distribute L-credits for all its flit buffers in a timely manner without requiring any action on the part of the transmitter.

Checks if credits are sent, in a timely manner, by the corresponding active node.
While the number of available L-Credits is less than the configured number of L-Credits (rx_\*_vc_flit_buffer_size in svt_chi_node_configuration), an L-Credit should be returned within the clock cycles specified in svt_chi_node_configuration :: rx_vc_credit_transmission_timeout.

ERROR

CHI Link Layer

port interleaving

port_interleaving_check

SYNOPSYS DEFINED:SYNOPSYS DEFINED

Monitor checks that if interleaved port is expected port for the given flit

Checks if address does fall to correct interleaved port.
Valid when node cfg svt_chi_node_configuration :: port_interleaving_enable = 1.
Applicable for snoop transactions in case of active and passive RN.
Applicable for RN transactions in case of passive RN.

ERROR

CHI Link Layer

dat flit valid

unexpected_poison_value_in_dat_flit_check

SYNOPSYS DEFINED:SYNOPSYS DEFINED

The Poison field in the data flits must be set to all zeroes

Check that the poison field in set to zero in the data flits observed at the node.

ERROR

CHI Link Layer

reserved fields

illegal_reserved_fields_check

ARM-IHI0050E.b:13.9 Flit packet definitions

Spec Text : The following key is used: SBZ Should Be Zero Description : The reserved fields in a flit must be set to zero as defined in CHI Specification.

Check that reserved fields in a flit must be set to zero as per the CHI specification (Section 13.9 Flit packet definitions).

ERROR

CHI Link Layer

SYSCO Interface FSM

sysco_interface_illegal_state_transition

ARM-IHI0050E.b:15.2 Handshake

Spec Text : SYSCOREQ can only change when SYSCOACK is at the same logic state Description : Transition of SYSCO Interface state must be valid

Illegal transition of the SYSCO Interface State.
This check monitors the SYSCOREQ and SYSCOACK signals and records illegal state transitions.

ERROR

CHI Link Layer

signal validity

valid_flitpend_and_flitv_signal_check

ARM-IHI0050E.b:14.4 Flit level clock gating

Spec Text : It is required that the signal is asserted exactly one cycle before a flit is sent from the Transmitter Description : FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter

FLITPEND signal must be asserted exactly one cycle before a flit is sent from the transmitter

ERROR

CHI Link Layer

link active sm

lasm_entry_into_banned_output_race_state_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : The red states can only be reached by observing a race between two output signals. A race between two outputs is not permitted at the edge of a component and therefore the transition into these states is labeled with Banned Output Race Description : The component's Link Active State Machine entry into Banned Output Race state condition is not expected.

lasm is acronym for "Link Active State Machine".
A given component's Link Active State Machine entry into Banned Output Race states can happen when there is a race condition at the output signals of the local component.
A given component's Link Active State Machine entry into Banned Output Race states results in the connected link partner component being entering Async Input Race States.
When a component’s Link Active State Machine entry into Banned Output Race state is observed this check will fail, if not the check will pass.
This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_banned_output_race_state_expected is set to 0.

ERROR

CHI Link Layer

link active sm

illegal_tx_rx_state_transition_combinations_from_async_input_race_state

ARM-IHI0050E.b:14.6.3 Expected transitions

Combination of Tx and Rx link active state machine together from async input race combination must be valid

Check to monitor the illegal Tx and Rx link active state combinations from the async input race states for a given node
Legal Tx and Rx link active state combinations from the async input race states are:
- TXRUN+/RXSTOP to TXRUN/RXACT
- TXACT/RXDEACT+ to TXRUN/RXDEACT
- TXSTOP+/RXRUN to TXSTOP/RXDEACT
- TXDEACT/RXACT+ to TXSTOP/RXDEACT

ERROR

CHI Link Layer

link active sm

lasm_entry_into_async_input_race_state_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : The yellow states can only be reached by observing a race between two input signals. The transition into these states is labeled with Async Input Race Description : The component's Link Active State Machine entry into Async Input Race state condition is not expected.

lasm is acronym for "Link Active State Machine".
A given component Link Active State Machine entry into Async Input Race States can only be reached by observing a race between the two input signals.
In other words, entry into Async Input Race states for a given component can happen only when the connected link partner component observes a Banned Output Signal race condition.
A given component Link Active State Machine entry into Async Input Race state implies that the connected link partner copmonent has entered Banned Output Race state.
When a component’s Link Active State Machine entry into Async Input Race state is observed this check will fail, if not the check will pass.
This check is constructed and executed only when svt_chi_node_configuration :: is_link_active_state_machine_in_async_input_race_state_expected is set to 0.

ERROR

CHI Link Layer

link active sm

lasm_in_banned_output_race_state_timeout_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Banned Output Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by local component.

lasm is acronym for "Link Active State Machine".
A given components Link Active State Machine entry into Banned Output Race states can happen when there is Async Input Signal race condition at the connected link partner component.
The component observing Link Active States corresponding to Banned Output race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component.
When a component’s state machine stays in Banned Output Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued.
This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.

ERROR

CHI Link Layer

link active sm

lasm_in_async_input_race_state_timeout_check

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : All other states are considered transient states that are exited in a timely manner Description : The component's Link Active State Machine entering into Async Input Race state condition is expected to move to next valid link active state within 1 or few clock cycles, initiated by link partner component.

lasm is acronym for "Link Active State Machine".
A given components Link Active State Machine entry into Async Input Race states can happen when there is a Banned Output Signal race condition at the connected link partner component.
The component observing Link Active States corresponding to Async Input race condition, it is expected that the Link Active State machine immediately moved to next valid states within 1 or few clock cycles, initiated by link partner component.
When a component’s state machine stays in Async Input Race state for more than the programmed clock cycles through the configuration parameter svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout, a timeout error is issued.
This check is constructed and executed only when svt_chi_node_configuration :: allow_link_active_signal_banned_output_race_transitions is set to 1 and svt_chi_node_configuration :: async_input_banned_output_race_link_active_states_timeout set to a value greater than or equal to 1.

ERROR

CHI Link Layer

link active sm

illegal_tx_rx_state_transition_combinations_from_banned_output_race_state

ARM-IHI0050E.b:14.6.3 Expected transitions

Combination of Tx and Rx link active state machine together from banned output race combination must be valid

Check to monitor the illegal Tx and Rx link active state combinations from the banned output race states for a given node
Legal Tx and Rx link active state combinations from the banned output race states are:
- TXSTOP/RXRUN to TXACT/RXRUN
- TXRUN/RXSTOP to TXDEACT/RXSTOP
- TXDEACT/RXACT to TXDEACT/RXRUN
- TXACT/RXDEACT to TXACT/RXSTOP

ERROR

CHI Link Layer

link active sm

illegal_tx_rx_state_transition_combinations

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : Stop/Stop to Run/Run state paths Description : Combination of Tx and Rx link active state machine together must be valid

Check to monitor the following illegal Tx and Rx link active state combinations for a given node:
- TXSTOP/RXRUN
- TXRUN/RXSTOP
- TXDEACT/RXACT
- TXACT/RXDEACT

ERROR

CHI Link Layer

link active sm

rx_illegal_state_transition

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Rx link active state machine must be valid

Illegal transition of the Receiver Interface State.
This check monitors the RXLINKACTIVEREQ and RXLINKACTIVEACK signals and records illegal state transitions.

ERROR

CHI Link Layer

link active sm

tx_illegal_state_transition

ARM-IHI0050E.b:14.6.3 Expected transitions

Spec Text : Mapping of states to the LINKACTIVE signals Description : Transition of Tx link active state machine must be valid

Illegal transition of the Transmitter Interface State.
This check monitors the TXLINKACTIVEREQ and TXLINKACTIVEACK signals and records illegal state transitions.

ERROR

CHI Link Layer

l-credit

valid_lcredit_count_in_tx_stop_state_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : The Transmitter has no credits and must not send any flits Description : All the applicable lcredit counter should be zero in tx stop state

When Tx is in stop state all the applicable lcredit counters should be 0. The Interconnect should not deassert the TXLINKACTIVEACK signal before it has recieved back all the lcredits.

RN:
- TXREQ VC: txreq_lcrd_count should be 0.
- TXRSP VC: txrsp_lcrd_count should be 0.
- TXDAT VC: txdat_lcrd_count should be 0.

SN:
- TXRSP VC: txrsp_lcrd_count should be 0.
- TXDAT VC: txdat_lcrd_count should be 0.

ERROR

CHI Link Layer

l-credit

invalid_lcredit_check

ARM-IHI0050E.b:14.5 Interface activation and deactivation

Spec Text : The Receiver must not send any credits Description : The receiver must not send lcredit in stop and activate state.

The receiver must not send lcredit in stop and activate state.

ERROR

CHI Link Layer

l-credit

tx_lcredit_used_same_cycle_which_recieved

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : An L-Credit cannot be used in the cycle it is received Description : An L-credit cannot be used in the cycle it is received.

Flits must not be transmitted on the same cycle that a credit is received

ERROR

CHI Link Layer

l-credit

rx_no_lcredit_sent_for_flit_transfer

ARM-IHI0050E.b:14.2 Link layer Credit

Spec Text : On exit from reset, credits are held by the Receiver and must be passed to the Transmitter before flit transfer can begin Description : A flit can be sent on its virtual channel only if a corresponding L-credit is available at the transmitter and the link is active.

Credits must be available for every transmitted Flit

ERROR

CHI Link Layer

l-credit

tx_no_lcredit_for_flit_transfer

ARM-IHI0050E.b:14.2 Link layer Credit

Credits must be available for every transmitted Flit

ERROR

CHI Protocol Layer

Node performance metrics

perf_min_write_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of write transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of write transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_write_throughput

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_write_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of write transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of write transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_write_throughput

ERROR

CHI Protocol Layer

Node performance metrics

perf_min_read_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of read transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of read transactions in a given interval is not less that the configured min value svt_chi_node_configuration :: perf_min_read_throughput

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_read_throughput_check

SYNOPSYS DEFINED

Monitor Check that the throughput of read transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of read transactions in a given interval is not more that the configured max value svt_chi_node_configuration :: perf_max_read_throughput

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_min_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of read transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of read transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_read_xact_latency

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_max_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of read transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of read transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_read_xact_latency

ERROR

CHI Protocol Layer

Node performance metrics

perf_min_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a read transaction is more than or equal to the configured min value

Checks that the latency of a read transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_read_xact_latency

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_read_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a read transaction is less than or equal to the configured max value

Checks that the latency of a read transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_read_xact_latency

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_min_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of write transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of write transactions in a given interval is not less than the configured min value svt_chi_node_configuration :: perf_avg_min_write_xact_latency

ERROR

CHI Protocol Layer

Node performance metrics

perf_avg_max_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the average latency of write transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of write transactions in a given interval is not more than the configured max value svt_chi_node_configuration :: perf_avg_max_write_xact_latency

ERROR

CHI Protocol Layer

Node performance metrics

perf_min_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a write transaction is more than or equal to the configured min value

Checks that the latency of a write transaction is not lesser than the configured min value svt_chi_node_configuration :: perf_min_write_xact_latency

ERROR

CHI Protocol Layer

Node performance metrics

perf_max_write_xact_latency_check

SYNOPSYS DEFINED

Monitor Check that the latency of a write transaction is less than or equal to the configured max value

Checks that the latency of a write transaction is not greater than the configured max value svt_chi_node_configuration :: perf_max_write_xact_latency

ERROR

CHI Protocol Layer

Snoop Transaction timeout check

snp_transaction_inactivity_timeout_check

SYNOPSYS DEFINED

Check that a Snoop transaction ends within the programmed number of clock cycles.

Checks that a given Snoop transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: snp_xact_inactivity_timeout.
Vip will continue to process the snoop transaction even the snoop transaction has timedout. The timeout of the snoop transaction doesn't have any impact on the procesing or completion of the snoop transaction.
The timer started for snoop transaction will continue to increment even there is a link deactivation when snoop transaction is outstanidng.
This check is currently not designed to handle the cases when there is a dynamic reset.

ERROR

CHI Protocol Layer

Transaction timeout check

transaction_inactivity_timeout_check

SYNOPSYS DEFINED

Check that a transaction ends within the programmed number of clock cycles.

Checks that a given transaction completes within the number of clock cycles specified by svt_chi_node_configuration :: xact_inactivity_timeout.
Vip will continue to process the transaction even the transaction has timedout. The timeout of the transaction doesn't have any impact on the procesing or completion of the transaction.
The timer started for a transaction will continue to increment even there is a link deactivation when transaction is outstanidng.
This check is currently not designed to handle the cases when there is a dynamic reset.

ERROR

CHI Protocol Layer

exclusive access legal data_size transfer check

non_coherent_excl_access_legal_data_size_transfer_check

ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations

Check that the number of bytes to be transferred in an exclusive access must be a legal data transfer size, that is, 1, 2,4, 8, 16, 32, or 64 bytes.

ERROR

CHI Protocol Layer

exclusive access address aligned to total bytes check

non_coherent_excl_access_aligned_total_bytes_transaction_check

ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations

Check that the address of an exclusive access must be aligned to the total number of bytes in the transaction.

ERROR

CHI Protocol Layer

non-coherent exclusive access same lpid check

non_coherent_excl_read_multiple_entry_for_same_lpid_check

ARM-IHI0050E.b: 6.3.3 Exclusive accesses to Snoopable locations

Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time.

Check that an exclusive monitor should not have more than one exclusive transaction of the same lpid at any given time.
Multiple exclusive transactions to Non-snoopable memory locations, either read or write, to the same or different addresses, from the same LP must not be outstanding at the same time.

ERROR

CHI Protocol Layer

SACTIVE signal validity

valid_rxsactive_signal_check

ARM-IHI0050E.b: 14.7 Protocol layer activity indication

RXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received at the link partner node.

RXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received at the link partner node.
A transaction that is given a RetryAck response is considered to be in progress, so RXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned.
The check is performed under following conditions: while the link is active and there is no active reset --
- Whenever there is a flit activity observed(TX*FLITV/RX*FLITV asserted), RXSACTIVE must be sampled as HIGH. Otherwise the check fails.
  - Following are the specific conditions under which this check is performed:
    - In case of SN: if REQ flit is received, then rxsactive must be HIGH at the same clock
    - In case of RN: The same clock where the CompAck RSP is observed, this must be high
    - In case of RN: The same clock where SNPRSP is sampled by all receiving/observing components, this must be high
    - In case of RN: The same clock where SNP flit is observed, this must be HIGH
    - In the same cycle the RSP flit is received/observed, this must be high
    - In the same cycle the Read Data flit is received/observed, this must be high
    - In the same cycle the Snp Data flit is received/observed, this must be high
    - In the same cycle the Write Data flit is received/observed, this must be high
- Whenever the signal RXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity at the link partner node. Otherwise the check fails.
  - Following is the definition of 'pending protocol layer activity':
    - Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits)
    - Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions)
    - Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)

ERROR

CHI Protocol Layer

SACTIVE signal validity

valid_txsactive_signal_check

ARM-IHI0050E.b: 14.7 Protocol layer activity indication

TXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received.

TXSACTIVE must remain asserted until after the last flit relating to all pending transactions is sent or received.
A transaction that is given a RetryAck response is considered to be in progress, so TXSACTIVE must remain asserted until the associated credit has been supplied, and it's used or returned.
Applicable when : the agent is in PASSIVE mode (svt_chi_node_configuration :: is_active = 0), and svt_chi_system_configuration :: top_layer is set to svt_chi_system_configuration :: PROTOCOL, svt_chi_system_configuration :: bottom_layer is set to svt_chi_system_configuration :: LINK
The check is performed under following conditions: while the link is active and there is no active reset --
- Whenever there is a flit activity observed(TX*FLITV/RX*FLITV asserted), TXSACTIVE must be sampled as HIGH. Otherwise the check fails.
  - Following are the specific conditions under which this check is performed:
    - REQ flit is received by PASSIVE agent, then txsactive must be HIGH at:
      - at the same clock, in case of RN
    - In case of RN: the same clock where CompAack RSP flit is observed, this must be high
    - In case of RN: The same clock where SNPRSP is observed, this must be high
    - In the same cycle the RSP flit is received/observed, this must be high
    - In the same cycle the Read Data flit is received/observed, this must be high
    - In the same cycle the Snp Data flit is received/observed, this must be high
    - In the same cycle the Write Data flit is received/observed, this must be high
- Whenever the signal TXSACTIVE is sampled as LOW, the check passes when there is no pending protocol layer activity. Otherwise the check fails.
  - Following is the definition of 'pending protocol layer activity':
    - Any in progress transactions (Transactions that are started, but not yet ended. eg: Waiting for response/data flits)
    - Any transactions with pending retries (Transactions that received retry response along with Credit grants; but neither the credits are returned nor used to retry the transactions)
    - Any in progress snoop transactions (Snoop transactions that are started, but not yet ended. eg: Waiting for response/data flits)

ERROR

CHI Protocol Layer

associate flit to xact

associate_readreceipt_to_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

If the request Order field indicates that ordering is required then a ReadReceipt response must be returned on the CRSP channel when order has been established

Check that the Ordering field of the transaction corresponding to the readreceipt is set.

ERROR

CHI Protocol Layer

snp req validity

valid_rn_d_snoop_flit_check

ARM-IHI0050E.b: Table B-2 Snoop communicating nodes

Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.

Check that only DVMOp related snoop transactions are seen on the Snoop Channel in case of RN-D.
Use of the SNP channel is limited to DVM data transfers in case of RN-D nodes.

ERROR

CHI Protocol Layer

dat flit valid

readunique_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadUnique transaction.
The cache state in the associated CompData flits of a ReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readnotshareddirty_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadNotSharedDirty transaction.
The cache state in the associated CompData flits of a ReadNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readshared_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadShared transaction.
The cache state in the associated CompData flits of a ReadShared transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readclean_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadClean transaction.
The cache state in the associated CompData flits of a ReadClean transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

cleanunique_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a CleanUnique transaction.
The cache state in the associated comp response of a CleanUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

makeunique_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a MakeUnique transaction.
The cache state in the associated comp response of a MakeUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

evict_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a Evict transaction.
The cache state in the associated comp response of an Evict transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readunique_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.

Check that the associated Compdata packet has valid resp_err value for ReadUnique transaction.
The associated compdata packet's resp_err field should not take EXOK value for ReadUnique transaction.

ERROR

CHI Protocol Layer

dat flit valid

expected_response_for_makereadunique_xact_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The Home Node must send a data response for a MakeReadUnique transaction if the line is not cached at the requester at the time of response.

Check that the home node sends a data response for a MakeReadUnique transaction if the line is not cached at the requester at the time of response.

ERROR

CHI Protocol Layer

dat flit valid

readpreferunique_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData or DataSepResp flits of a ReadPreferUnique transaction should take a valid value when the Resperr field does not indicate any error.

Check that the associated CompData or DataSepResp packet has valid cache state value for a ReadPreferUnique transaction.
The cache state in the associated CompData or DataSepResp flits of a ReadPreferUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

makereadunique_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData or DataSepResp flits of a MakeReadUnique transaction should take a valid value when the Resperr field does not indicate any error.

Check that the associated CompData or DataSepResp packet has valid cache state value for a MakeReadUnique transaction.
The cache state in the associated CompData or DataSepResp flits of a MakeReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

makereadunique_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated Comp or RespSepData flit of a MakeReadUnique transaction should take a valid value when the Resperr field does not indicate any error.

Check that the associated Comp or RespSepData packet has valid cache state value for a MakeReadUnique transaction.
The cache state in the associated Comp or RespSepData flits of a MakeReadUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readpreferunique_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated CompData or DataSepResp packet's resp_err field should not take EXOK value for ReadPreferUnique transaction.

Check that the associated CompData or DataSepResp flits have valid resp_err value for ReadPreferUnique transaction.
The associated CompData or DataSepResp flit's resp_err field should not take EXOK for ReadPreferUnique transaction.

ERROR

CHI Protocol Layer

dat flit valid

makereadunique_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated CompData or DataSepResp packet's resp_err field should not take EXOK value for MakeReadUnique transaction.

Check that the associated CompData or DataSepResp flits have valid resp_err value for MakeReadUnique transaction.
The associated CompData or DataSepResp flit's resp_err field should not take EXOK for MakeReadUnique transaction.

ERROR

CHI Protocol Layer

resp flit valid

makereadunique_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated Comp or RespSepData response packet's resp_err field should not take EXOK value for MakeReadUnique transaction.

Check that the associated Comp or RespSepData response flit has valid resp_err value for MakeReadUnique transaction.
The associated Comp or RespSepData response flit's resp_err field should not take EXOK for MakeReadUnique transaction.

ERROR

CHI Protocol Layer

snp req validity

expected_snoop_xact_type_check

SYNOPSYS DEFINED

Stash and Forward type snoops are expected to be received only by a CHI-B or later compliant RN-F, when Stashing and DCT features are enabled in the corresponding HN, respectively.

Check that only supported snoop transactions are seen on the Snoop Channel in case of RN-F.
SYNOPSYS DEFINED :

Stash and Forward type snoops are expected to be received only by a CHI-B or later compliant RN-F, when Stashing and DCT features are enabled in the corresponding HN, respectively.
SnpNotSharedDirty, Stash and Forward type snoops are expected to be received only by a CHI-B or later compliant RN-F.

ERROR

CHI Protocol Layer

dat flit valid

readnotshareddirty_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Compdata packet has valid resp_err value for ReadNotSharedDirty transaction.

ERROR

CHI Protocol Layer

dat flit valid

readshared_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Compdata packet has valid resp_err value for ReadShared transaction.

ERROR

CHI Protocol Layer

dat flit valid

readclean_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Compdata packet has valid resp_err value for ReadClean transaction.

ERROR

CHI Protocol Layer

resp flit valid

cleanunique_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Comp response packet has valid resp_err value for CleanUnique transaction.

ERROR

CHI Protocol Layer

resp flit valid

makeunique_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.

Check that the associated Comp response packet has valid resp_err value for MakeUnique transaction.
The associated comp response packet's resp_err field should not take EXOK value for MakeUnique transaction.

ERROR

CHI Protocol Layer

resp flit valid

evict_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.

Check that the associated Comp response packet has valid resp_err value for Evict transaction.
The associated comp response packet's resp_err field should not take EXOK or DERR value for Evict transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpstashshared_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.2 Stash snoop transactions

The cache state in the associated response of a SnpStashUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated RespSepData, DataSepResp or CompData has valid cache state for SnpStashShared transaction.
The cache state in the associated response of a SnpStashShared transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpstashshared_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp or RespSepData should not take EXOK or DERR resp_err value for SnpStashShared transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.

Check that the associated SnpResp packet has valid resp_err value for SnpStashShared transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpstashunique_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp or RespSepData should not take EXOK or DERR resp_err value for SnpStashUnique transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.

Check that the associated SnpResp packet has valid resp_err value for SnpStashUnique transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpstashunique_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.2 Stash snoop transactions

The cache state in the associated response of a SnpStashUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated RespSepData, DataSepResp or CompData has valid cache state for SnpStashUnique transaction.
The cache state in the associated response of a SnpStashUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpmakeinvalidstash_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.2 Stash snoop transactions

The cache state in the associated response of a SnpMakeInvalidStash transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp,RespSepData,DataSepResp or CompData has valid cache state for SnpMakeInvalidStash transaction.
The cache state in the associated response of a SnpMakeInvalidStash transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpmakeinvalidstash_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp or RespSepData should not take EXOK or DERR resp_err value for SnpMakeInvalidStash transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.

Check that the associated SnpResp, RespSepData, DataSepResp or CompData packet has valid resp_err value for SnpMakeInvalidStash transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpuniquestash_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.2 Stash snoop transactions

The cache state in the associated response of a SnpUniqueStash transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp, SnpRespData, RespSepData, DataSepResp or CompData has a valid cache state for SnpUniqueStash transaction.
The cache state in the associated response of a SnpUniqueStash transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpuniquestash_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp or RespSepData should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUniqueStash transaction while the associated CompData or DataSepResp should not take EXOK resp_err value.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpUniqueStash transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeevict_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction.

Check that the associated response and data packets has valid resp_err value for WriteEvict transaction.

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteEvict transaction.
The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteEvict transaction. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeclean_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction.

Check that the associated response and data packets has valid resp_err value for WriteClean transaction.

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteClean transaction.
The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteClean transaction. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeback_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction.

Check that the associated response and data packets has valid resp_err value for WriteBack transaction.

The associated CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteBack transaction.
The associated Comp should not take EXOK or DERR value whereas compack should not take EXOK or NDERR or DERR resp_err value for WriteBack transaction. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

dat flit valid

writecleanfull_cleanshared_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteCleanFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteCleanFull_CleanShared transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteCleanFull_CleanShared transaction.

ERROR

CHI Protocol Layer

dat flit valid

writebackfull_cleaninvalid_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteBackFull_CleanInvalid should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteBackFull_CleanInvalid transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteBackFull_CleanInvalid transaction.

ERROR

CHI Protocol Layer

dat flit valid

writecleanfull_cleansharedpersistsep_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteCleanFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteCleanFull_CleanSharedPersistSep transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteCleanFull_CleanSharedPersistSep transaction.

ERROR

CHI Protocol Layer

dat flit valid

writebackfull_cleansharedpersistsep_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteBackFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteBackFull_CleanSharedPersistSep transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteBackFull_CleanSharedPersistSep transaction.

ERROR

CHI Protocol Layer

dat flit valid

writebackfull_cleanshared_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteBackFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteBackFull_CleanShared transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteBackFull_CleanShared transaction.

ERROR

CHI Protocol Layer

ordering check

new_req_before_comp_or_compdbid_resp_for_copyback_writes_with_optional_data_to_same_cacheline_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

An RN-F must wait for the Comp/CompDBIDResp response to be received for an outstanding CopyBack Writes with Optional Data transactions WriteEvictorEvict before issuing another request to the same cache line.

Check that a request to a cache line is issued when there are no outstanding Copyback Writes with Optional Data transactions (WriteEvictorEvict) that are expecting Comp/CompDBIDResp.

An RN-F must wait for the Comp/CompDBIDResp response to be received for an outstanding WriteEvictorEvict transaction before issuing another request to the same cache line.

ERROR

CHI Protocol Layer

snp req validity

data_pull_set_for_stash_snoop_when_outstanding_xacts_with_dbidrespord

ARM-IHI0050E.b: 7.2 Write with Stash hint

The data pull in snoop response to stash snoop should be 0 .

The data_pull in the Snoop response to a stash snoop should be set to 0 when there exists outstanding transactions to the cache line which have received DBIDRespOrd response.

ERROR

CHI Protocol Layer

resp flit valid

writecleanfull_cleanshared_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteCleanFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteCleanFull_CleanShared transaction.
The cache state and resp_pass_dirty fields in the associated CompCMO/Comp response flit of a WriteCleanFull_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

resp flit valid

writebackfull_cleaninvalid_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteBackFull_CleanInvalid transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteBackFull_CleanInvalid transaction.
The cache state and resp_pass_dirty fields in the associated CompCMO/Comp response flit of a WriteBackFull_CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

resp flit valid

writecleanfull_cleansharedpersistsep_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteCleanFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteCleanFull_CleanSharedPersistSep transaction.
The cache state and resp_pass_dirty fields in the associated CompCMO/CompPersist/Comp response flit of a WriteCleanFull_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

resp flit valid

writecleanfull_cleansharedpersistsep_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteCleanFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteCleanFull_CleanSharedPersistSep transaction.

The associated responses (CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value.
The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

resp flit valid

writebackfull_cleansharedpersistsep_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteBackFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteBackFull_CleanSharedPersistSep transaction.
The cache state and resp_pass_dirty fields in the associated CompCMO/CompPersist/comp response flit of a WriteBackFull_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

resp flit valid

writebackfull_cleansharedpersistsep_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteBackFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteBackFull_CleanSharedPersistSep transaction.

The associated responses (CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value.
The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

resp flit valid

writebackfull_cleanshared_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteBackFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteBackFull_CleanShared transaction.
The cache state and resp_pass_dirty fields in the associated CompCMO/Comp response flit of a WriteBackFull_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

resp flit valid

writecleanfull_cleanshared_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteCleanFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteCleanFull_CleanShared transaction.

The associated responses (CompDBIDResp, CompCMO) should not take EXOK resp_err value.
The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

resp flit valid

writebackfull_cleaninvalid_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteBackFull_CleanInvalid should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteBackFull_CleanInvalid transaction.

The associated responses (CompDBIDResp, CompCMO) should not take EXOK resp_err value.
The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

resp flit valid

writebackfull_cleanshared_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteBackFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteBackFull_CleanShared transaction.

The associated responses (CompDBIDResp, CompCMO) should not take EXOK resp_err value.
The associated Comp should not take EXOK or DERR resp_err value. Note that this is applicable only for CHI Issue F or later specification.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeevictorevict_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response and data packets of WriteEvictorEvict should take legal values as per CHI ISSUE E Specifications.

Check that the associated response and data packets has valid resp field {cahe state and resp_pass_dirty} value for a WriteEvictorEvict transaction.
The cache state in the associated Write data flits or Comp reponse flits of a WriteEvictorEvict transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeevictorevict_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response and data packets of WriteEvictorEvict should take legal values as per CHI ISSUE E Specifications.

Check that the associated response and data packets has valid resp_err value for WriteEvictorEvict transaction.

The associated CompDBIDResp should not take EXOK resp_err value for WriteEvictorEvict transaction.
The associated Comp should not take EXOK or DATA_ERROR resp_err value for WriteEvictorEvict transaction.
The associated write data packets should not take EXOK or NON_DATA_ERROR resp_err value for WriteEvictorEvict transaction.

ERROR

CHI Protocol Layer

request validity

cache_transitioned_to_dirty_from_uce_for_read

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache transitioned to dirty stateUD/UDP from UCE.

Check if the RN has transitioned from UCE to UD/UDP state while there is an ongoing READSHARED, READNOTSHAREDDIRTY,READCLEAN, READONCE, READONCECLEANINVALID,READONCEMAKEINVALID transactions. This check will flag an error in case the cache is updated via frontdoor or backdoor accesses to move from UCE to dirty state while there is an outstanding Read. .

ERROR

CHI Protocol Layer

dat flit valid

makereadunique_data_response_cache_data_match_check

ARM-IHI0050E.b: 4.7 Cache state transitions at a Requester

The data returned in the data response for a MakeReadUnique should be the same as the data cached in the Requester if the cachestate at the requester before receiving the response is SC and the final state in the associated data response is UD.

Check that the data returned in the data response for a MakeReadUnique is the same as the data cached in the Requester when the cachestate at the requester before receiving the response is SC and the final state in the associated data response is UD.
This check is applicable only when there are no error responses seen in the data response for the MakeReadUnique and the data cached in the RN is not poisoned.

ERROR

CHI Protocol Layer

resp flit valid

valid_final_state_for_non_invalidating_snp_when_outstanding_makereadunique_to_same_cacheline_check

ARM-IHI0050E.b: 4.7 Cache state transitions at a Requester

A requester must not invalidate the line in response to receiving a non-invalidating snoop while MakeReadUnique is outstanding.

Check that the final state in the Snoop response for a non-invaldating type snoop is not I if there is already an outstanding MakeReadUnique transaction to the same cacheline given that the snoop response does not indicate a NON_DATA_ERROR. The MakeReadUnique transaction will be considered only if there were no prior invalidating type Snoops seen while the MakeReadUnique was outstanding. In other words, this check will not be performed if the RN had already received a an invalidating type Snoop overlapping with the MakeReadUnique.

ERROR

CHI Protocol Layer

resp flit valid

invalid_data_pull_in_snoop_response_check

ARM-IHI0050E.b: 7.2 Write with Stash hint

Stash target must not request Data Pull if: DoNotDataPull bit is set or Snoop has an address hazard with an outstanding request

Check that the DataPull value in the Snoop response for a Stash type Snoop is set to a valid value.
DataPull must not be set to 1 when

DoNotDataPull in the Snoop requests was set to 1
sysco interface state is in a state other than Coherency Enabled(when svt_chi_node_configuration :: sysco_interface_enable is set to 1)
There are ongoing transactions to the same cacheline

ERROR

CHI Protocol Layer

resp flit valid

dbid_in_snoop_response_with_data_pull_check

ARM-IHI0050E.b: 2.5 Details of transaction identifier fields

The DBID value used by a Snoop Completer in response to a Stash type snoop that includes a Data Pull must be unique with respect to: the DBID values in other Snoop responses to Stash type snoops that use Data Pull and the TxnID of any outstanding Request from that Snoop Completer

Check that the DBID value in the Snoop response for a Stash type Snoop is set to a unique value when DataPull is asserted.
The DBID must not coincide with the TxnID of any of the outstanding transactions at the RN or the DBID of any of the outstanding Stash type Snoops involving DataPull.

ERROR

CHI Protocol Layer

dat flit valid

snprspdatafwded_compdata_data_integrity_check

ARM-IHI0050E.b: 4.5.3 Snoop response

The data in the SnpRespDataFwded response matches with the data in the CompData response sent for a Forward type Snoop transaction

Check that the data sent in the SnpRespDataFwded response matches with the data sent in the forwarded CompData for a given Forward type Snoop request.

ERROR

CHI Protocol Layer

resp and dat flit valid

valid_fwd_state_in_fwded_snoop_response_check

ARM-IHI0050E.b: 13.10.45 Forward State, FwdState

The FwdState indicated in the SnpRespFwded or SnpRespDataFwded response must indicate the state in the CompData sent from the Snoopee to the Requester

Check that the FwdState indicated in the SnpRespFwded or SnpRespDataFwded response matches with the Resp field in the forwarded CompData.

ERROR

CHI Protocol Layer

resp and dat flit valid

valid_fwded_response_type_for_ret_to_src_check

ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions

For a Forwarding type Snoop request, snooped RN must return a copy to Home using SnpRspDataFwded if the cache line is Dirty or Clean.

Check that SnpRespFwded is issued from the snooped RN to the Interconnect in case DCT is observed for a Forward type snoop with RetToSrc asserted.

ERROR

CHI Protocol Layer

resp flit validity

valid_snprspfwded_flit_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID, TgtID, TxnID fields of the SnpRspFwded flit must match the TgtID, FwdNID, FwdTxnID and TxnID of the Forward type Snoop request

Check that the Transaction ID, SourceID and TargetID fields are set correctly in Snoop response flits.

The TgtID must be set to the the Src of the Forward type Snoop request. The TxnID must be set to the same value as the TxnID of the Forward type Snoop request. The SrcID must be set to the same value as the TgtID of the Forward type Snoop request.

ERROR

CHI Protocol Layer

associate flit to xact

associate_compdata_flit_with_fwd_type_snp_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID, TgtID, TxnID and DBID fields of the forwarded CompData flit must match the TgtID, FwdNID, FwdTxnID and TxnID of the Forward type Snoop request

Check that the SourceID, TargetID, Transaction ID and DBID fields are set correctly in the CompData flits used for DCT.

The TgtID must be set to the the FwdNID of the Snoop request. The SrcID must be set to the the TgtID of the Snoop request. The TxnID must be set to the FwdTxnID of the Snoop request. The DBID must be set to the TxnID of the Snoop request.

ERROR

CHI Protocol Layer

resp and dat flit valid

snppreferuniquefwd_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions

The cache state in the associated response of a SnpPreferUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpPreferUniqueFwd transaction.
The cache state in the associated response of a SnpPreferUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error. A Snoopee that is not executing an exclusive sequence treats SnpPreferUniqueFwd as SnpUniqueFwd. Snoopee that is in the process of executing an exclusive sequence treats SnpPreferUniqueFwd as SnpNotSharedDirtyFwd, with the exception that it must not invalidate its cached copy.

ERROR

CHI Protocol Layer

resp and dat flit valid

snppreferuniquefwd_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR, The associated SnpRespFwd should not take EXOK, whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpPreferUniqueFwd transaction.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid resp_err value for SnpPreferUniqueFwd transaction.
The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpPreferUniqueFwd transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpnotshareddirtyfwd_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions

The cache state in the associated response of a SnpNotSharedDirtyFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpNotSharedDirtyFwd transaction.
The cache state in the associated response of a SnpNotSharedDirtyFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpnotshareddirtyfwd_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirtyFwd transaction.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid resp_err value for SnpNotSharedDirtyFwd transaction.
The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirtyFwd transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpuniquefwd_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions

The cache state in the associated response of a SnpUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpUniqueFwd transaction.
The cache state in the associated response of a SnpUniqueFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpuniquefwd_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpUniqueFwd transaction.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid resp_err value for SnpUniqueFwd transaction.
The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpUniqueFwd transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpsharedfwd_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions

The cache state in the associated response of a SnpSharedFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpSharedFwd transaction.
The cache state in the associated response of a SnpSharedFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpsharedfwd_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpSharedFwd transaction.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData valid resp_err value for SnpSharedFwd transaction.
The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpSharedFwd transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleanfwd_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions

The cache state in the associated response of a SnpCleanFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpCleanFwd transaction.
The cache state in the associated response of a SnpCleanFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleanfwd_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpCleanFwd transaction.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has valid resp_err value for SnpCleanFwd transaction.
The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packet should not take EXOK or NDERR resp_err value for SnpCleanFwd transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snponcefwd_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.3 Forwarding Snoop transactions

The cache state in the associated response of a SnpOnceFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData has a valid cache state for SnpOnceFwd transaction.
The cache state in the associated response of a SnpOnceFwd transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snponcefwd_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp* should not take EXOK or DERR whereas SnpRespData* or CompData packet should not take EXOK or NDERR resp_err value for SnpOnceFwd transaction.

Check that the associated SnpResp, SnpRespFwded, SnpRespData, SnpRespDataFwded or CompData packet has valid resp_err value for SnpOnceFwd transaction.
The associated SnpResp or SnpRespFwded should not take EXOK or DERR whereas SnpRespData, SnpRespDataFwded or CompData packets should not take EXOK or NDERR resp_err value for SnpOnceFwd transaction.

ERROR

CHI Protocol Layer

dat flit valid

copyback_cancellation_write_data_check

ARM-IHI0050E.b: 4.11.1 At the RN-F node

The cache state in the WriteData response after CopyBack cancellation must be I and all byte enables must be deasserted.If all the byte enables are deasserted then the data must be zeroed

Check that when Byte Enables in the CopyBackWriteData are all de-asserted during CopyBack cancellation the Write Data bytes are all zeroed.

ERROR

CHI Protocol Layer

resp and dat flit valid

snppreferunique_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpPreferUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpPreferUnique transaction.
The cache state in the associated response of a SnpPreferUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snppreferunique_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpPreferUnique transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpPreferUnique transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpPreferUnique transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpnotshareddirty_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpNotSharedDirty transaction.
The cache state in the associated response of a SnpNotSharedDirty transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpnotshareddirty_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirty transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpNotSharedDirty transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpNotSharedDirty transaction.

ERROR

CHI Protocol Layer

dat flit valid

valid_snprespdata_when_be_is_zero_check

ARM-IHI0050E.b: 2.10.3 Byte Enables

In Snoop Data, a byte enable value of zero must set the associated data byte value to zero.

Check that in Snoop Data, a byte enable value of zero must set the associated data byte value to zero.

ERROR

CHI Protocol Layer

dat flit valid

expected_tagop_value_in_fwded_compdata_check

ARM-IHI0050E.b: 12.9.2 Forwarding snoops

The TagOp field in the Forwarded CompData must be set to either Invalid or Transfer

Check that the TagOp field in the Comp response is set to a value that is permitted by the specification for the corresponding transaction type.

ERROR

CHI Protocol Layer

dat flit valid

same_tagop_value_in_all_fwded_compdata_flits_check

ARM-IHI0050E.b: 12.9 Snoop requests

In case there are multiple Forwarded CompData response flits corresponding to a Forward type Snoop, the TagOp field must be set to the same value across all the Forwarded CompData flits

Check that, in case there are multipe Forwarded CompData flits corresponding to a Forward type Snoop, the TagOp field is set to the same value in all the Forwarded Compdata flits.

ERROR

CHI Protocol Layer

dat flit valid

expected_tagop_value_in_data_pull_compdata_check

ARM-IHI0050E.b: 12.8 Stash transactions

The TagOp field in the DataPull CompData must be set to either Invalid or Transfer

Check that the TagOp field in the DataPull Compdata response corresponding to a Stash type Snoop involving DataPull is set to a value that is permitted by the specification.

ERROR

CHI Protocol Layer

dat flit valid

same_tagop_value_in_all_data_pull_compdata_flits_check

ARM-IHI0050E.b: 12.8 Stash transactions

In case there are multiple DataPull CompData flits corresponding to a Stash type Snoop involving DataPull, the TagOp field must be set to the same value across all the DataPull CompData flits

Check that, in case there are multipe DataPull CompData flits corresponding to a Stash type Snoop involving DataPull, the TagOp field is set to the same value in all the DataPull Compdata flits.

ERROR

CHI Protocol Layer

dat flit valid

same_tagop_value_in_all_snoop_data_response_flits_check

ARM-IHI0050E.b: 12.9 Snoop requests

In case there are multiple Snoop data response flits corresponding to a Snoop, the TagOp field must be set to the same value across all the SnpRespData flits

Check that, in case there are multiple Snoop data response flits corresponding to a Snoop transaction, the TagOp field is set to the same value across all the Snoop data response flits.

ERROR

CHI Protocol Layer

resp flit valid

snpquery_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The resp_pass_dirty attribute in the associated response of a SnpQuery transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp has valid cache state for SnpQuery transaction.
The resp_pass_dirty attribute in the associated response of a SnpQuery transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp flit valid

snpquery_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR resp_err value for SnpQuery transaction.

Check that the associated SnpResp packet has valid resp_err value for SnpQuery transaction.
The associated SnpResp should not take EXOK or DERR resp_err value for SnpQuery transaction.

ERROR

CHI Protocol Layer

ordering check

new_req_before_compdbid_resp_for_copyback_to_same_cacheline_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.

Check that a request to a cache line is issued when there are no outstanding Copyback transactions that are expecting CompDBIDResp.

An RN-F must wait for the CompDBIDResp response to be received for an outstanding CopyBack transaction before issuing another request to the same cache line.

ERROR

CHI Protocol Layer

resp flit valid

snpmakeinvalid_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp has valid cache state for SnpMakeInvalid transaction.
The cache state in the associated response of a SnpMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleaninvalid_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanInvalid transaction.
The cache state in the associated response of a SnpCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleanshared_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpCleanShared transaction.
The cache state in the associated response of a SnpCleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpunique_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpUnique transaction.
The cache state in the associated response of a SnpUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpshared_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpShared transaction.
The cache state in the associated response of a SnpShared transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpclean_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpClean transaction.
The cache state in the associated response of a SnpClean transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp and dat flit valid

snponce_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.8.1 Non-Forwarding and Non-stash Snoop transactions

The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated SnpResp or SnpRespData has a valid cache state for SnpOnce transaction.
The cache state in the associated response of a SnpOnce transaction should indicate a valid value when the RespErr field does not indicate any error.

ERROR

CHI Protocol Layer

resp flit valid

snpmakeinvalid_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.

Check that the associated SnpResp packet has valid resp_err value for SnpMakeInvalid transaction.
The associated SnpResp should not take EXOK or DERR resp_err value for SnpMakeInvalid transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleaninvalid_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanInvalid transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanInvalid transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpcleanshared_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpCleanShared transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpCleanShared transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpunique_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpUnique transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpUnique transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpshared_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpShared transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpShared transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snpclean_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.5 Other transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpClean transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpClean transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

snponce_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.7 Snoop transactions

The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.

Check that the associated SnpResp and SnpRespData packets has valid resp_err value for SnpOnce transaction.
The associated SnpResp should not take EXOK or DERR whereas SnpRespData packet should not take EXOK or NDERR resp_err value for SnpOnce transaction.

ERROR

CHI Protocol Layer

associate flit to xact

associate_snprspdata_flit_with_snp_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.

Check that the Transaction ID, SourceID and TargetID fields are set correctly in SnpResp Data flits.

The TgtID must be set to the the SrcID of the Snoop request. The TxnID must be set to the same value as the TxnID of the Snoop request.

ERROR

CHI Protocol Layer

resp flit validity

valid_snprsp_flit_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The TgtID and SrcID must be set to the the SrcID and TgtID of the Snoop request respectively. The TxnID is set to the same value as the TxnID of the Snoop request.

Check that the Transaction ID, SourceID and TargetID fields are set correctly in Snoop response flits.

The TgtID must be set to the the SrcID of the Snoop request. The TxnID is set to the same value as the TxnID of the Snoop request.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeevict_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteEvict transaction.
The cache state in the associated Write data flits of a WriteEvict transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeclean_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteClean transaction.
The cache state in the associated Write data flits of a WriteClean transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeback_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteBack transaction.
The cache state in the associated Write data flits of a WriteBack transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

valid_dat_flit_type_for_snp_xact_check

ARM-IHI0050E.b: 4.5 Response types

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

Data flit type must be set to one of the permitted values for the Snoop Request

ERROR

CHI Protocol Layer

dat flit valid

valid_cbwrdata_flit_for_xact_check

ARM-IHI0050E.b: 4.5.2 WriteData response

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

COPYBACKWRDATA is valid only in case of WriteBack, WriteClean and WriteEvict type transactions

ERROR

CHI Protocol Layer

snp req validity

new_snp_req_before_compack_of_coherent_xact_which_received_comp_to_same_cacheline_check

ARM-IHI0050E.b: 4.11 Hazard conditions

The completer can send out the Snoop requests to an RN-F only when there are no outstanding coherent transactions from that particular RN-F targetting the same cache line that received completion response and has not yet received the CompAck/WrData

Check that for an RN-F node, Snoop request is observed when there are no outstanding coherent transactions targetting the same cache line that received completion response and has not yet sent out the CompAck or Write Data.
Once a completion is received for a transaction, the completer must not send a snoop request to the same cache line until it receives:

A CompAck for any Read and Dataless requests except for ReadOnce* and ReadNoSnp.
A WriteData response for CopyBack and Atomic requests.
For WriteUnique, a WriteData response and, if applicable, CompAck.

ERROR

CHI Protocol Layer

snp req validity

new_snp_req_before_completion_of_previous_snp_xact_to_same_cacheline_check

ARM-IHI0050E.b: 4.11 Hazard conditions

The completer can send out the Snoop requests to an RN-F only when there are no outstanding Snoop transactions targetting the same cache line to that particular RN-F

Check that for an RN-F node, Snoop request is observed when there are no outstanding Snoop transactions targetting the same cache line.

ERROR

CHI Protocol Layer

dvm xact

valid_tlbi_fields_in_snpdvmop_check

ARM-IHI0050E.b: 8.2 DVM Operation types

The Range, Num, Scale, TG and TTL fields in a SnpDVMOp transaction are set to legal values

Check that the Range, Num, Scale, TG and TTL fields are set to valid values in a TLB Invalidate Type SnpDVMOp transaction.

Range bit can be set to 1 only in case of SnpDVMOp TLBI requests that are invalidate by VA or PA.
Num and Scale fields can be set to non-zero values only in case of Range based SnpDVMOp TLBI requests.
TG and TTL can be set to non-zero values only in case of TLBI requests that are invalidate by VA or PA.

ERROR

CHI Protocol Layer

dvm xact

valid_order_of_dvmop_rspflits_check

ARM-IHI0050E.b: 2.3.7 DVM transactions

Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete

Check that the order of the responses sent by the Completer is correct in case of DVMOp transactions.
Completer first returns a DBIDResp indicating that it can receive data and sends a Comp Response after the data transfer is complete. When the spec_revision is ISSUE_D or later and the DVMOp is a Non-sync DVMOp, then the interconnect is permitted but not required to wait for WriteData before sending the Comp. Currently VIP does not support early COMP support for DVM transaction.

ERROR

CHI Protocol Layer

dvm xact

valid_snpdvmop_part_check

ARM-IHI0050E.b: 8.1.3 Flow control

SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID

Check that both parts of a SnpDVMOp request are received at the RN.

SnpDVMOp requests consist of two parts. Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID

ERROR

CHI Protocol Layer

dvm xact

single_outstanding_snpdvmop_per_txn_id_check

ARM-IHI0050E.b: 2.4 Transaction identifier fields

The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID

Check that the TxnID of a SnpDVMOp must be unique for a given Requester.

The TxnID must be unique for a given Requester.
The Requester can reuse the ID only after it has received all responses associated with
a previous transaction that has used the same TxnID

ERROR

CHI Protocol Layer

dvm xact

single_outstanding_snpdvmop_sync_check

ARM-IHI0050E.b: 8.1.3 Flow control

Only one SnpDVMOpSync transaction can be outstanding from an MN to an RN.

Check that there is only one outstanding DVMOp sync transaction at a given point in time.
Only one SnpDVMOp(Sync) transaction can be outstanding from an MN to an RN.

ERROR

CHI Protocol Layer

resp flit valid

valid_resp_err_status_for_dvmop_xact_check

ARM-IHI0050E.b: 9.4.5 Other transactions

For DVMOP transaction, resp_err_status field of the associated Comp RSP flit must have one of the following values: 1NORMAL_OKAY 2NON_DATA_ERROR 3in case of chi_spec_revision >= ISSUE_B,DATA_ERROR.

Check that the comp response has valid resp_err value for DVMop transaction.
The associated Comp response should take one of the following resp_err values: 1)NORMAL_OKAY 2)NON_DATA_ERROR 3)in case of svt_chi_node_configuration :: chi_spec_revision >= ISSUE_B,DATA_ERROR for DVMop transaction.

ERROR

CHI Protocol Layer

resp flit validity

valid_rspflit_for_dvmop_check

ARM-IHI0050E.b: 4.5.1 Completion response

A Comp response, with the Resp field set to zero, is always used for DVM transaction completion

Check that only Comp Response is used for DVMOp transactions, and not CompDBIDResp
When the spec_revision is ISSUE_D or later the Completer is permitted to opportunistically combine Comp and DBIDResp into CompDBIDResp response. This is applicable only in case of early comp support. Currently VIP does not support early COMP support for DVM transaction. A Comp response, with the Resp field set to zero, is always used for Barrier and DVM transaction completion.

ERROR

CHI Protocol Layer

resp flit valid

snpdvmop_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.5 Other transactions

The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.

Check that the associated SnpResp packet has valid resp_err value for SnpDVMop transaction.
The associated SnpResp should not take EXOK or DERR resp_err value for SnpDVMop transaction.

ERROR

CHI Protocol Layer

resp flit valid

snpresp_for_snpdvmop_sync_only_after_completion_of_prior_snpdvmop_check

ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no prior SnpDVMOp transactions that are yet to receive a SnpResp from the RN.

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

ERROR

CHI Protocol Layer

resp flit valid

snpresp_for_snpdvmop_sync_only_after_completion_of_all_non_dvm_sync_check

ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

Check that the SnpResp is observerd for a SnpDVMOp(sync) only when there are no outstanding DVMOp transactions at the RN.

Sending of a SnpResp implies that all DVM related operations have completed at the RN structures.

ERROR

CHI Protocol Layer

dvm xact

valid_tlbi_fields_in_dvmop_check

ARM-IHI0050E.b: 8.2 DVM Operation types

The Range, Num, Scale, TG and TTL fields in a DVMOp transaction are set to legal values

Check that the Range, Num, Scale, TG and TTL fields are set to valid values in a TLB Invalidate Type DVMOp transaction.

Range bit can be set to 1 only in case of DVMOp TLBI requests that are invalidate by VA or PA.
Num and Scale fields can be set to non-zero values only in case of Range based DVMOp TLBI requests.
TG and TTL can be set to non-zero values only in case of TLBI requests that are invalidate by VA or PA.

ERROR

CHI Protocol Layer

resp flit validity

valid_snprsp_for_snpdvmop_check

ARM-IHI0050E.b: 8.1.3 Flow control

An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction.

Check that the SnpDVMOpResp is observed only after both SnpDVMOp request packets.

An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp request packets corresponding to that transaction. The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively.

ERROR

CHI Protocol Layer

dvm xact

valid_snpdvmop_req_part_num_check

ARM-IHI0050E.b: 8.2 DVM Operation types

Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.

Check that the part numbers of the SnpDVMOp request packets are set correctly.
Part number must be 0b0 for SnpDVMOp Part 1 and 0b1 for SnpDVMOp Part 2.

ERROR

CHI Protocol Layer

dvm xact

single_outstanding_dvmop_sync_request_check

SYNOPSYS DEFINED

There can only be one outstanding DVMOpSync transaction from an RN at any point in time.

Check that there are no outstanding DVMOp(Sync) transactions when a DVMOp(Sync) request is received.
SYNOPSYS DEFINED
Not more than one DVMOp(Sync) transaction is expected to be outstanding from an RN at any given point in time, when svt_chi_node_configuration :: allow_multiple_dvm_sync_oustanding_xacts is set to 0.

ERROR

CHI Protocol Layer

dvm xact

unused_bits_in_dvm_write_data_check

ARM-IHI0050E.b: 8.1.4 DVMOp field value restrictions

All the unused bits in the write data of a DVMOp transaction must be set to zero.

Check that the unused bits in the Write data of a DVMOp transaction are set to zero.

ERROR

CHI Protocol Layer

dvm xact

expected_dvmop_sync_request_check

ARM-IHI0050E.b: 8.1.2 Sync type DVM transaction flow

All previous DVMOp requests whose completion needs to be guaranteed by the DVMOpSync must have received a Comp response before the RN can send a DVMOpSync.

Check that there are no outstanding DVMOp(Non-sync) transactions when a DVMOp(Sync) request is received.

All previous DVMOp requests whose completion needs to be guaranteed by the DVMOp(Sync) must have received a Comp response before the RN can send a DVMOp(Sync).

ERROR

CHI Protocol Layer

resp flit valid

cleansharedpersistsep_associated_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp/comp_persist response packets of a CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp/CompPersist response packet has valid cache state value for a CleanSharedPersistSep transaction.
The cache state in the associated comp/comppersist response packets of a CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

cleansharedpersistsep_associated_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp/persist/comppersist response packet's resp_err field should not take EXOK value for CleanSharedPersistSep transaction

Check that the associated Comp/Persist/CompPersist response packet has valid resp_err value for CleanSharedPersistSep transaction.
The associated comp/persist/comppersist response packet's resp_err field should not take EXOK value for CleanSharedPersistSep transaction.

ERROR

CHI Protocol Layer

resp flit validity

valid_response_combinations_for_cleansharedpersistsep_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

The Response type must correspond to one of the permitted combinations for the CleanSharedPersistSep transaction

ERROR

CHI Protocol Layer

resp flit validity

valid_comppersist_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

ERROR

CHI Protocol Layer

resp flit validity

valid_persist_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

ERROR

CHI Protocol Layer

associate flit to xact

valid_parity_datacheck_for_snoop_data_check

ARM-IHI0050E.b: 9.6 Data Check

For Snoop transactions involving data transfer, datacheck is set appropriatly such that ODD Byte parity is generated.

Checks that the Datacheck is set correctly such that ODD Byte parity is generated for Snoop Data

For all snoop transactions that involve data transfers, datacheck bit is set appropriatly such that ODD Byte parity is generated across the data that is being transmited.

ERROR

CHI Protocol Layer

barrier xact

normal_non_cacheable_or_device_writes_between_barriers_check

ARM-IHI0050A: 7.5.1

It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.

Check that Normal Non-cacheable or Device type writes were received, prior to the current Barrier and after the previous Barrier transaction

It is recommended that an RN only issues an EOBarrier or ECBarrier if it has issued a Normal Non-cacheable, or Device type memory write request since previously completing an EOBarrier or ECBarrier.

WARNING

CHI Protocol Layer

barrier xact

comp_received_for_normal_non_cacheable_or_device_writes_before_barrier_check

ARM-IHI0050A: 7.5 Barriers

An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request

Check that there are no outstanding Normal Non-cacheable or Device type writes, that are targeting an HN-I, which haven't received a Comp Repsonse, before a Barrier is issued by an RN.

An RN must wait until all Normal Non-cacheable writes, and all Device type writes, that are targeting an HN-I, have received a completion response before issuing an EOBarrier or an ECBarrier request.

ERROR

CHI Protocol Layer

request validity

expected_tgt_id_in_rn_xact_check

ARM-IHI0050E.b: 3.3.1 Target ID determination for Request messages

The Target ID in the request sent by the RN must be set as per the SAM, when target ID remapping is not expected at the Interconnect

Check that the Target ID field in the transaction request is set to the node ID of the HN as per the RN SAM.

When Target ID is not expected to be remapped at the Interconnect, RN must program the tgt_id of the request flit to the correct value as per the SAM.

ERROR

CHI Protocol Layer

dat flit valid

atomic_compare_valid_tag_check

ARM-IHI0050E.b: 12.7 Atomic transactions

The memory tag value should be same in the Tag fields corresponding to the compare and swap data

Checks that the memory tag is same in the Tag fields corresponding to the compare and swap data. Applicable only for ATOMICCOMARE transaction when tag_op is set to TAG_FETCH_MATCH.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeuniquefullstash_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteUniqueptlstash transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteUniquefullstash transaction.
The cache state in the associated Write data flits of a WriteUniquefullstash transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeuniqueptlstash_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteUniqueptlstash transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteUniqueptlstash transaction.
The cache state in the associated Write data flits of a WriteUniqueptlstash transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

Compack timing

owo_combined_writeunique_cmo_compack_timing_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

CompAck for an OWO Combined WriteUnique and CMO type transaction must be sent only after all the previous OWO Combined WriteUnique and CMO type transactions have received Comp response and the current OWO Combined WriteUnique and CMO type transaction transaction has received either Comp or DBIDResp or COMPDBIDRESP response.

Check that the CompAck response for an ordered Combined WriteUnique_(P)CMO type transaction is sent only afer following conditions are met:

Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current Combined WriteUnique_(P)CMO type transaction are received.
DBIDResp or CompDBIDResp or Comp response for the current Combined WriteUnique_(P)CMO type transaction is received.

ERROR

CHI Protocol Layer

Compack timing

owo_combined_writenosnp_cmo_compack_timing_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

CompAck for an OWO Combined WriteNoSnp and CMO type transaction must be sent only after all the previous OWO Combined WriteNoSnp and CMO type transactions have received Comp response and the current OWO Combined WriteNoSnp and CMO type transaction transaction has received either Comp or DBIDResp or COMPDBIDRESP response.

Check that the CompAck response for an ordered Combined WriteNoSnp_(P)CMO type transaction is sent only afer following conditions are met:

Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current Combined WriteNoSnp_CMO type transaction are received.
DBIDResp or CompDBIDResp or Comp response for the current Combined WriteNoSnp_(P)CMO type transaction is received.

ERROR

CHI Protocol Layer

Compack timing

owo_writenosnp_compack_timing_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

CompAck for an OWO WriteNoSnp must be sent only after the Comp response for all previous OWO WriteNoSnp transactions are received and Comp or DBIDResp or COMPDBIDRESP for current WriteNoSnp transaction is received.

Check that the CompAck response for an ordered WriteNoSnp transaction is sent only afer following conditions are met:

Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteNoSnp transaction are received.
DBIDResp or CompDBIDResp or Comp response for the current OWO WriteNoSnp transaction is received.

ERROR

CHI Protocol Layer

Compack timing

owo_writeunique_compack_timing_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

CompAck for an OWO WriteUnique must be sent once the Comp for all previous OWO WriteUnique transactions are received and comp When chi_spec_revision is less than or equal to ISSUE_C/Comp or DBIDResp or CompDBIDReespWhen chi_spec_revision is ISSUE_D or later for current WriteUnique transaction is received.

Check that the CompAck response for an ordered WriteUnique transaction is sent only afer following conditions are met:

Comp response for all earlier ordered Write transactions which are required to be ordered with respect to the current WriteUnique transaction are received.
When svt_chi_node_configuration :: chi_spec_revision >= ISSUE_D, DBIDResp or CompDBIDResp or Comp response for the current OWO WriteUnique is received whereas for svt_chi_node_configuration :: chi_spec_revision <= ISSUE_C, Comp response for the current OWO WriteUnique is received.

ERROR

CHI Protocol Layer

request validity

new_req_before_completion_of_previous_cmo_xacts_to_same_cacheline_check

ARM-IHI0050E.b: 4.2.2 Dataless transactions

Transaction intended for a particular address that can allocate data in Requester caches must not be sent to the interconnect before a previous CMO sent to the same address has completed.

Check that an allocating read request is issued when there are no outstanding CMO transactions to the same cache line.

ERROR

CHI Protocol Layer

request validity

cmo_xact_before_completion_of_previous_xacts_to_same_cacheline_check

ARM-IHI0050E.b: 4.2.2 Dataless transactions

A CMO intended for a particular address must not be sent before all previous requests, targeting the same cacheline, that can allocate data in the requester cache ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique are complete.

Check that a CMO request is issued when there are no outstanding transactions of type mentioned below to the same cache line that can allocate the received data in the Requester caches:

ReadShared, ReadClean, ReadUnique, ReadNotSharedDirty, CleanUnique, MakeUnique

ERROR

CHI Protocol Layer

resp and dat flit valid

writeunique_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteUnique transaction.
The cache state in the associated Write data flits of a WriteUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

expected_compack_check

ARM-IHI0050E.b: 2.3 Transaction structure

CompAck must be observed only after Comp or all CompData responses are received.

Check that the CompAck response is sent only afer Comp* or CompData response.

CompAck, if part of the transaction, must be observed only after Comp* or CompData responses are received.

ERROR

CHI Protocol Layer

resp flit validity

valid_compack_rsp_flit_check

ARM-IHI0050E.b: 2.6.1 Read transactions

The TgtID and SrcID must be set to the the SrcID and TgtID of the read data respectively. The TxnID is set to the same value as the DBID value provided in the read data response.

Check that the TransactionID, TargetID and SourceID fields are set correctly in the CompAck response.

The TgtID and SrcID must be set to the the SrcID and TgtID of the read data/comp/dbidresp/compdbidresp respectively. The TxnID is set to the same value as the DBID value provided in the read data/comp/dbidresp/compdbidresp response.

ERROR

CHI Protocol Layer

single req order stream

single_req_order_stream_check

ARM-IHI0050E.b: 2.8 Ordering

The ordering requirements must be met for preceding active transactions with ReqOrder asserted before initiating next ordered transaction

Check that single ordered stream of requests from RN are ordered as per Request Ordering rules.
Request Ordering Rules update from CHI Issue D onwards:

In CHI Issue C or earlier, the Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range and includes the guarantee of Request Order.
In CHI Issue D or later, there will be no ordering guarantees between two ordered transactions from the same source that have different ordering requirements. In other words, Endpoint ordering guarantees the order of multiple transactions, from the same agent, to the same endpoint address range, but doesn’t include the guarantee of Request Order.

ERROR

CHI Protocol Layer

DWT

dwt_used_by_hn_with_dwt_enabled_check

SYNOPSYS DEFINED

DWT can be used by a HN only when: DWT is enabled for that HN through svt_chi_system_configuration::set_hn_dwt_enable

DWT can be used by an HN only when DWT is enabled for that HN through svt_chi_system_configuration :: set_hn_dwt_enable

ERROR

CHI Protocol Layer

CMO Propagation

cmos_forwarded_to_slave_by_hn_with_forward_cmos_to_slave_enable_check

SYNOPSYS DEFINED

CMO Propagation transactios can only be received by an SN from HN when the required configuration is set to 1 through svt_chi_system_configuration::set_hn_forward_cmos_to_slaves_enable method

SN can receive CleanShared, CLeanInvalid, MakeInvalid, CleanInvalidPOPA transaction from HN only when the required configuration is set through svt_chi_system_configuration :: set_hn_forward_cmos_to_slaves_enable method.

ERROR

CHI Protocol Layer

CMO Propagation

persist_cmos_forwarded_to_slave_by_hn_with_forward_persist_cmos_to_slave_enable_check

SYNOPSYS DEFINED

Persist CMO Propagation transations can only be received by an SN from HN when the required configuration is set to 1 through svt_chi_system_configuration::set_hn_forward_persist_cmos_to_slaves_enable method

SN can receive CleanSharedPersist/CleanSharedPersistSep transaction from HN only when the required configuration is set through svt_chi_system_configuration :: set_hn_forward_persist_cmos_to_slaves_enable method.

ERROR

CHI Protocol Layer

DMT

dmt_used_by_hn_with_dmt_enabled_check

SYNOPSYS DEFINED

DMT can be used by a HN only when: DMT is enabled for that HN through svt_chi_system_configuration::set_hn_dmt_enable

DMT can be used by an HN only when DMT is enabled for that HN through svt_chi_system_configuration :: set_hn_dmt_enable

ERROR

CHI Protocol Layer

resp flit validity

valid_snp_response_check

ARM-IHI0050E.b: 4.11.1 At the RN-F node

If a pending request to the same cache line is present at the RN-F and the pending request has received at least one Data response packet or RespSepData, the RN-F must wait to receive all Data response packets before responding to the Snoop request.

An RN-F must wait for any outstanding Read or DataPull transaction that has received at least one Read data or RespSepData flit to complete before issuing a Snoop response for a Snoop targeting the same cacheline.

ERROR

CHI Protocol Layer

dat flit valid

ncbwrdatacompack_flit_timing_check

ARM-IHI0050E.b: 2.3.2 Write Transactions

NCBWrDataCompAck which implies the combined flit of NCBWrData and compack responses must satisfy the compack response timing rule that all the previous OWO Write*order_type set to REQ_ORDERING_REQUIRED and exp_comp_ack set to 1 transactions should have received the comp response.

Check that the NCBWRDATACOMPACK response for an Ordered Write Observation Write* transaction is seen after all earlier OWO Write* transactions which are required to be ordered with respect to the current OWO Write* transaction received Comp responses.

ERROR

CHI Protocol Layer

dat flit valid

ncbwrdatacompack_after_comp_and_dbid_check

ARM-IHI0050E.b: 2.3.2 Write Transactions

An RN can send combined NCBWrDataCompAck response once it receives both DBIDResp and Comp or CompDBIDResp response from Home. Once RN receives DBIDResp it must send WrData and must not wait for Comp to combine WrData with CompAck

Check that NCBWRDATACOMPACK flits are seen for WriteUnique transactions only after the reception of both Comp and DBIDResp, or, CompDBIDResp response.
Additionally checks that, in case separate Comp and DBID responses were observed, NCBWRDATACOMPACK flits are seen only if the Comp response was received first followed by the DBIDResp Response.

ERROR

CHI Protocol Layer

dat flit valid

valid_ncbwrdatacompack_flit_for_xact_check

ARM-IHI0050E.b: 4.5.2 WriteData response

NCBWrDataCompAck can be sent only for a Writeunique transaction with ExpCompAck asserted. When svt_chi_node_configuration::chi_spec_revision is ISSUE_D or later, NCBWrDataCompAck can also be sent for a Writenosnp transaction with ExpCompAck asserted

When svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_C, check that NCBWRDATACOMPACK flits are seen only for WriteUnique* transactions with ExpCompAck asserted.
When svt_chi_node_configuration :: chi_spec_revision is set to ISSUE_D or later, check that NCBWRDATACOMPACK flits are seen only for WriteUnique* or WriteNoSnp* transactions with ExpCompAck asserted.

ERROR

CHI Protocol Layer

dat flit valid

matching_resp_err_nderr_in_respsepdata_datasepresp_check

ARM-IHI0050E.b: 9.4.1 Read transactions

For a given RN transaction, when resp_err_status field of RespSepData RSP flit is set to NON_DATA_ERROR, resp_err_status field of DataSepResp DAT flits must be set to NON_DATA_ERROR as well as RespSepData and associated DataSepResp flits must be generated from the same HN

For a given RN Read transaction, if resp_err_status is set to NON_DATA_ERROR in RespSepData then the subsequent DataSepResp should also have the resp_err_status set to NON_DATA_ERROR. Moreover, in such cases, the DataSepResp should be issued by the Home node that issued RespSepData

ERROR

CHI Protocol Layer

dat flit valid

valid_data_source_in_datasepresp_check

ARM-IHI0050E.b: 11.1 Data Source indication

The DataSource field in the DataSepResp flits corresponding to a transaction must take legal values.

Check that the DataSource field in the associated Compdata packets have a valid value.

ERROR

CHI Protocol Layer

resp and dat flit valid

matching_dbid_home_nid_in_respsepdata_datasepresp_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The DBID and HomeNID values in the DataSepResp flits must match the DBID and SrcID values in the RespSepData flit

Check that the DBID and HomeNID values in the DataSepResp flits match the DBID and SrcID values in the corresponding RespSepData.

ERROR

CHI Protocol Layer

resp flit valid

associated_respsepdata_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated RespSepData response packet's resp_err field should not take EXOK or DERR value

Check that the associated RespSepData response packet has valid resp_err value..
The associated RespSepData response packet's resp_err field should not take EXOK or DERR value.

ERROR

CHI Protocol Layer

resp flit validity

valid_respsepdata_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

ERROR

CHI Protocol Layer

resp flit valid

associate_respsepdata_to_xact_check

ARM-IHI0050E.b: 2.8.4 Ordering semantics of RespSepData and DataSepResp

RespSepData response is not permitted for Read transactions with Exclusives or ordered Read transactions without CompAck or ordered Read transactions which have received a READRECEIPT.

Check that RespSepData response is seen only for Read transactions with:

exclusive bit de-asserted.
order field de-asserted or order field asserted along with ExpCompAck.

Also, if order field is asserted in the request, there should be no READRECEIPT response in case RespSepData flow is seen.

ERROR

CHI Protocol Layer

DMT

valid_return_txn_id_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

If DMT is used the RetrunNID should be the NodeID of the Requester, whereas if DMT is not used the RetrunNID should be the NodeID of the Home

A transaction request from Home to Slave also includes a ReturnTxnID field to convey the value of TxnID in the data response from the Slave. Its value, when applicable, must be either:

The TxnID generated by Home, when the ReturnNID is the Node ID of the Home when DMT is not used
The TxnID of the original Requester, when the ReturnNID is the Node ID of the original Requester when DMT is used

ERROR

CHI Protocol Layer

DMT

valid_order_type_for_non_dmt_check

ARM-IHI0050E.b: 5.1.8 ReadNoSnp transaction with DMT and separate Non-data and Data-only response

Order field can be set to REQ_ACCEPTED for readnosnp from HN to SN only when DMT is used

ERROR

CHI Protocol Layer

resp flit valid

associate_compstashdone_to_xact_check

ARM-IHI0050E.b: 2.5 Details of transaction identifier fields

TargetID and DBID[7:0] in a CompStashDone response must match the SrcID and StashGroupID fields of the corresponding StashOnceSep* transaction

Check that the TargetID and DBID[7:0] fields are set correctly in CompStashDone responses.
A CompStashDone response can be received only for StashOnceSep* transaction.

ERROR

CHI Protocol Layer

resp flit valid

associate_stashdone_to_xact_check

ARM-IHI0050E.b: 2.5 Details of transaction identifier fields

TargetID and DBID[7:0] in a StashDone response must match the SrcID and StashGroupID fields of the corresponding StashOnceSep* transaction

Check that the TargetID and DBID[7:0] fields are set correctly in StashDone responses.
A StashDone response can be received only for StashOnceSep* transaction.

ERROR

CHI Protocol Layer

resp flit validity

valid_compstashdone_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that COMPSTASHDONE Response flit is seen only in case of StashOnceSepUnique and StashOnceSepShared transaction.

ERROR

CHI Protocol Layer

resp flit validity

valid_stashdone_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that STASHDONE Response flit is seen only in case of StashOnceSepUnique and StashOnceSepShared transaction.

ERROR

CHI Protocol Layer

resp flit valid

stashoncesepshared_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a StashOnceSepShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated response has valid cache state value for a StashOnceSepShared transaction.
The cache state in the associated response of a StashOnceSepShared transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

stashoncesepunique_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a StashOnceSepUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated response has valid cache state value for a StashOnceSepUnique transaction.
The cache state in the associated response of a StashOnceSepUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

stashoncesepshared_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for StashOnceSepShared transaction.

Check that the associated response packet has valid resp_err value for StashOnceSepShared transaction.
The associated response packet's resp_err field should not take EXOK value for StashOnceSepShared transaction.

ERROR

CHI Protocol Layer

resp flit valid

stashoncesepunique_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for StashOnceSepUnique transaction.

Check that the associated response packet has valid resp_err value for StashOnceSepUnique transaction.
The associated response packet's resp_err field should not take EXOK value for StashOnceSepUnique transaction.

ERROR

CHI Protocol Layer

DMT

valid_exclusive_access_for_dmt_check

ARM-IHI0050E.b: 6.3.1 Responses to exclusive requests

Exclusive transaction other than ReadPreferUnique and MakeReadunique that do not fail must not use DMT flow

Exclusive transaction other than ReadPreferUnique and MakeReadunique that do not fail must not use DMT flow.

ERROR

CHI Protocol Layer

DMT

valid_ordering_and_compack_combination_for_dmt_check

ARM-IHI0050E.b: 2.3.1 Read transactions

DMT for Readnosnp, Readonce, ROCI and ROMI is applicable for the combinations of order and compack defined in Table 2-6

DMT for Readnosnp, Readonce, ROCI and ROMI can be used only for the following combinations of order and compack

No ordering and No compack
No ordering and compack
Ordering and compack

DMT for Readnosnp, Readonce, ROCI and ROMI cannot be used with ordering and No compack

ERROR

CHI Protocol Layer

DMT

valid_transaction_supporting_dmt_check

ARM-IHI0050E.b: 4.2.1 Read transactions

DMT is applicable only for the following transactions: Readclean, Readshared, Readunique, RNSD, Readnosnp, Readonce, ROCI and ROMI.

DMT is applicable only for the following transactions: Readclean, Readshared, Readunique, RNSD, Readnosnp, Readonce, ROCI, ROMI, ReadPreferUnique and MakeReadUnique

ERROR

CHI Protocol Layer

resp flit valid

stashonceshared_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a StashOnceShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a StashOnceShared transaction.
The cache state in the associated comp response of a StashOnceShared transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

stashonceunique_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a StashOnceUnique transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a StashOnceUnique transaction.
The cache state in the associated comp response of a StashOnceUnique transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

stashonceshared_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for StashOnceShared transaction.

Check that the associated Comp response packet has valid resp_err value for StashOnceShared transaction.
The associated comp response packet's resp_err field should not take EXOK value for StashOnceShared transaction.

ERROR

CHI Protocol Layer

resp flit valid

stashonceunique_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for StashOnceUnique transaction.

Check that the associated Comp response packet has valid resp_err value for StashOnceUnique transaction.
The associated comp response packet's resp_err field should not take EXOK value for StashOnceUnique transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeuniquefullstash_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUniquefullstash transaction.

Check that the associated response and data packets has valid resp_err value for WriteUniquefullstash transaction.
The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUniquefullstash transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeuniqueptlstash_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUniqueptlstash transaction.

Check that the associated response and data packets has valid resp_err value for WriteUniqueptlstash transaction.
The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUniqueptlstash transaction.

ERROR

CHI Protocol Layer

dat flit valid

readoncemakeinvalid_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadOnceMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadOnceMakeInvalid transaction.
The cache state in the associated CompData flits of a ReadOnceMakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readoncecleaninvalid_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadOnceCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadOnceCleanInvalid transaction.
The cache state in the associated CompData flits of a ReadOnceCleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readoncemakeinvalid_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated compdata packet's resp_err field should not take EXOK value for ReadOncemakeinvalid transaction.

Check that the associated Compdata packet has valid resp_err value for ReadOnceMakeInvalid transaction.
The associated compdata packet's resp_err field should not take EXOK value for ReadOnceMakeInvalid transaction.

ERROR

CHI Protocol Layer

dat flit valid

readoncecleaninvalid_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated compdata packet's resp_err field should not take EXOK value for ReadOncecleaninvalid transaction.

Check that the associated Compdata packet has valid resp_err value for ReadOnceCleanInvalid transaction.
The associated compdata packet's resp_err field should not take EXOK value for ReadOnceCleanInvalid transaction.

ERROR

CHI Protocol Layer

dat flit valid

valid_data_source_in_compdata_check

ARM-IHI0050E.b: 11.1 Data Source indication

The DataSource field in the CompData flits corresponding to a transaction must take legal values.

Check that the DataSource field in the associated Compdata packets have a valid value.

ERROR

CHI Protocol Layer

resp and dat flit valid

expected_remapped_tgt_id_in_response_check

ARM-IHI0050E.b: 3.3.1 Target ID determination for Request messages

The Target ID in the request must be remapped correctly as per the SAM and the Source ID of the subsequent response flits must be set to the remapped Target ID value

Check that the Target ID is remapped correctly at the Interconnect.

When Target ID remapping is expected at the Interconnect, the Target ID field in the received request must be remapped correctly as per the SAM.
This check is performed when target ID is remapped by the Interconnect and the SAM is specified correctly in the system configuration.

ERROR

CHI Protocol Layer

resp flit valid

associated_tagmatch_response_legal_resp_check

ARM-IHI0050E.b: 12.11.2 Non-Tag Match errors

The resp field in the TAGMATCH resposne flit must be valid

Check that the resp field is as per the expectation.The Resp value in the TagMatch response must be:

A Fail when MTE is not supported.
A Pass when MTE is supported but the Tag Match is not performed.
A Pass if BE is all zeroes.
A Pass if Write transaction is cancelled.
A Fail when tag_match response is received and we see that data status is not ACCEPT

ERROR

CHI Protocol Layer

dat flit valid

read_data_tagop_not_invalid_for_transfer_fetch_req_tagop

ARM-IHI0050E.b: 12.4 Read transaction rules

The TagOp field in the Read data corresponding to a Read request, with TagOp Transfer or Fetch, can only be set to Invalid when the address does not support memory tagging

Check that the TagOp field in a Read data flit is not set to Invalid when the Read Request TagOp is Transfer or Fetch and the target HN supports memory tagging.

ERROR

CHI Protocol Layer

Custom

expected_snpquery_custom_check

SYNOPSYS DEFINED

SNPQUERY should be generated only for exclusive MakereadUnique when Snoop filter is disabled at the Interconnect.

Checks that the SNPQUERY is generated for valid transaction types

ERROR

CHI Protocol Layer

dat flit valid

writeuniqueptl_cleansharedpersistsep_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteUniquePtl_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteUniquePtl_CleanSharedPersistSep transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteUniquePtl_CleanSharedPersistSep transaction.

ERROR

CHI Protocol Layer

dat flit valid

writeuniquefull_cleansharedpersistsep_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteUniqueFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteUniqueFull_CleanSharedPersistSep transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteUniqueFull_CleanSharedPersistSep transaction.

ERROR

CHI Protocol Layer

dat flit valid

writeuniqueptl_cleansharedpersistsep_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteUniquePtl_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniquePtl_CleanSharedPersistSep transaction.
The cache state in the associated Write data flits of a WriteUniquePtl_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writeuniquefull_cleansharedpersistsep_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteUniqueFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniqueFull_CleanSharedPersistSep transaction.
The cache state in the associated Write data flits of a WriteUniqueFull_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writeuniqueptl_cleanshared_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteUniquePtl_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteUniquePtl_CleanShared transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteUniquePtl_CleanShared transaction.

ERROR

CHI Protocol Layer

dat flit valid

writeuniquefull_cleanshared_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteUniqueFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteUniqueFull_CleanShared transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteUniqueFull_CleanShared transaction.

ERROR

CHI Protocol Layer

dat flit valid

writeuniqueptl_cleanshared_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteUniquePtl_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniquePtl_CleanShared transaction.
The cache state in the associated Write data flits of a WriteUniquePtl_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writeuniquefull_cleanshared_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteUniqueFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniqueFull_CleanShared transaction.
The cache state in the associated Write data flits of a WriteUniqueFull_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

DWT

valid_ordering_and_compack_combination_for_dwt_check

ARM-IHI0050E.b: 4.2.3 Write transactions

DWT is not permitted in Non-CopyBack writes that are OWO writes.

DWT is not permitted in Non-CopyBack writes that are OWO writes. DWT for Non-CopyBack writes cannot be used with ordering set to REQ_ORDERING_REQUIRED and exp_comp_ack set to 1.

ERROR

CHI Protocol Layer

DWT

valid_transaction_supporting_dwt_check

ARM-IHI0050E.b: 13.10.24 Do Direct Write Transfer, DoDWT

DWT is applicable only for non-copyback write transactions.

ERROR

CHI Protocol Layer

resp flit valid

writeuniqueptl_cleansharedpersistsep_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteUniquePtl_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteUniquePtl_CleanSharedPersistSep transaction.

The associated responses (Comp, CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writeuniquefull_cleansharedpersistsep_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteUniqueFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteUniqueFull_CleanSharedPersistSep transaction.

The associated responses (Comp, CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writeuniqueptl_cleansharedpersistsep_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteUniquePtl_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniquePtl_CleanSharedPersistSep transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteUniquePtl_CleanSharedPersistSep transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writeuniquefull_cleansharedpersistsep_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteUniqueFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniqueFull_CleanSharedPersistSep transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteUniqueFull_CleanSharedPersistSep transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writeuniqueptl_cleanshared_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteUniquePtl_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteUniquePtl_CleanShared transaction.

The associated responses (Comp, CompDBIDResp, CompCMO) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writeuniquefull_cleanshared_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteUniqueFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteUniqueFull_CleanShared transaction.

The associated responses (Comp, CompDBIDResp, CompCMO) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writeuniqueptl_cleanshared_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteUniquePtl_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniquePtl_CleanShared transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteUniquePtl_CleanShared transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writeuniquefull_cleanshared_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteUniqueFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteUniqueFull_CleanShared transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteUniqueFull_CleanShared transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writeuniquezero_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated comp response flit of a WriteUniqueZero transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated comp response packet has valid resp field for a WriteUniqueZero transaction.
The cache state indicated by resp field in the associated Comp response packet of a WriteUniqueZero transaction should take a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

writeuniquezero_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err field in the associated responses of WriteUniqueZero transaction should take the legal values. Valid resp_err field values in DBIDResp is NORMAL_OKAY and in Comp/CompDBIDResp are NORMAL_OKAY, NON_DATA_ERROR and DATA_ERROR.

Check that the associated response packets has valid resp_err value for WriteUniqeZero transaction.

ERROR

CHI Protocol Layer

resp flit validity

valid_dbidrespord_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The DBIDRespOrd flit should correspond to one of the permitted transaction types.

Check that DBIDRespOrd Response flit is seen only in case of non-Copyback Write or atomic transactions.
The Response flit type must correspond to one of the permitted values depending on the type of the transaction

ERROR

CHI Protocol Layer

resp flit valid

dbidresp_or_dbidresoprd_response_received_check

ARM-IHI0050E.b: 4.5 Response types

The transaction should receive either DBIDResp or DBIDRespOrd response.

Checks that a transaction receives either (COMP)DBIDResp or DBIDRespOrd, but not both.

ERROR

CHI Protocol Layer

resp flit validity

valid_pcrdgrant_check

ARM-IHI0050E.b: 2.11 Request Retry

PcrdGrant is not seen without any outstanding transaction

Checks PcrdGrant is not seen without any outstanding transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

writeunique_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUnique transaction.

Check that the associated response and data packets has valid resp_err value for WriteUnique transaction.
The associated Comp and CompDBIDResp should not take EXOK value whereas data packet should not take EXOK or NDERR resp_err value for WriteUnique transaction.

ERROR

CHI Protocol Layer

dat flit valid

readonce_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadOnce transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadOnce transaction.
The cache state in the associated CompData flits of a ReadOnce transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readonce_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The associated compdata packet's resp_err field should not take EXOK value for ReadOnce transaction.

Check that the associated Compdata packet has valid resp_err value for ReadOnce transaction.
The associated compdata packet's resp_err field should not take EXOK value for ReadOnce transaction.

ERROR

CHI Protocol Layer

resp flit valid

cleansharedpersist_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packets of a CleanSharedPersist transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response packet has valid cache state value for a CleanSharedPersist transaction.
The cache state in the associated comp response packets of a CleanSharedPersist transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

cleansharedpersist_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for CleanSharedPersist transaction.

Check that the associated Comp response packet has valid resp_err value for CleanSharedPersist transaction.
The associated comp response packet's resp_err field should not take EXOK value for CleanSharedPersist transaction.

ERROR

CHI Protocol Layer

resp and dat flit valid

atomic_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.4 Atomic transactions

The cache state in the associated Comp or CompDBIDResp as well as the data packets corresponding to an Atomic transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated response and data packets have valid cache state value for an Atomic transaction.
The cache state in the associated response and data packets of an Atomic transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp and dat flit valid

atomic_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.4 Atomic transactions

The associated Comp or CompDBIDResp should not take EXOK value whereas the data packets should not take EXOK or NDERR resp_err value for Atomic transaction.

Check that the associated response and data packets have valid resp_err value for Atomic transaction.

ERROR

CHI Protocol Layer

resp flit valid

makeinvalid_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a MakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a MakeInvalid transaction.
The cache state in the associated comp response of a MakeInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

cleaninvalid_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a CleanInvalid transaction.
The cache state in the associated comp response of a CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

cleanshared_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.2 Dataless request transactions

The cache state in the associated comp response packet of a CleanShared transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Comp response has valid cache state value for a CleanShared transaction.
The cache state in the associated comp response of a CleanShared transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

resp flit valid

makeinvalid_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for MakeInvalid transaction.

Check that the associated Comp response packet has valid resp_err value for MakeInvalid transaction.
The associated comp response packet's resp_err field should not take EXOK value for MakeInvalid transaction.

ERROR

CHI Protocol Layer

resp flit valid

cleaninvalid_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for CleanInvalid transaction.

Check that the associated Comp response packet has valid resp_err value for CleanInvalid transaction.
The associated comp response packet's resp_err field should not take EXOK value for CleanInvalid transaction.

ERROR

CHI Protocol Layer

resp flit valid

cleanshared_associated_comp_response_legal_resperr_check

ARM-IHI0050E.b: 9.4.2 Dataless transactions

The associated comp response packet's resp_err field should not take EXOK value for CleanShared transaction.

Check that the associated Comp response packet has valid resp_err value for CleanShared transaction.
The associated comp response packet's resp_err field should not take EXOK value for CleanShared transaction.

ERROR

CHI Protocol Layer

dat flit valid

valid_resp_for_data_packet_check

ARM-IHI0050E.b: 4.5 Response types

The Resp field in a response must have the same value for every packet of a data message regardless of whether or not there is an error condition.

Check that the resp field has the same value for all data flits of a multi-flit data transfer .
The resp field in a response must have the same value for every packet of a data message regardless of whether or not there is an error condition.

ERROR

CHI Protocol Layer

dat flit valid

single_xact_mix_ok_exok_response_check

ARM-IHI0050E.b: 9.2 Error response fields

A single transaction is not permitted to mix OK and EXOK responses.

Check that a single transaction does not mix OK and EXOK responses within its data packets .
A single transaction is not permitted to mix OK and EXOK responses.

ERROR

CHI Protocol Layer

dat flit field

valid_ccid_in_dat_flit_check

ARM-IHI0050E.b: 2.10.6 Critical Chunk Identifier

CCID of all the data packets belonging to a transaction must be the same and equal to addr[5:4] of the corresponding Request

Check that the CCID field value in the data flit is set correctly.

CCID of all the data packets belonging to a transaction must be the same and equal to addr[5:4] of the corresponding Request.

ERROR

CHI Protocol Layer

dat flit valid

dbid_value_must_be_same_across_read_data_flits_check

ARM-IHI0050E.b: 2.5.9 Data Buffer ID

DBID must take the same value in all read data flits corresponding to a Read transaction with ExpCompAck set to 1

For a Read transaction, if the DBID is valid then the DBID field must take same value in all the corresponding read data flits. DBID is valid if ExpCompAck is set to 1 for the corresponding Read transaction.

ERROR

CHI Protocol Layer

resp flit valid

separate_dbidresp_and_comp_must_include_same_dbid_value_check

ARM-IHI0050E.b: 2.5 Details of transaction identifier fields

A Comp response message sent separate from a DBIDResp or DBIDRespOrd message for a Write transaction must include the same DBID field value in the Comp and DBIDResp or DBIDRespOrd message

A Comp response sent separate from a DBIDResp or DBIDRespOrd response for a write transaction (except Atomic transactions) must include the same DBID field value in the Comp and DBIDResp or DBIDRespOrd message.
Applicable only in case of non-copyback Write transactions and non-copyback Combined Write plus CMO transactions as the copyback transactions always include a combined CompDBIDResp response. Applicable only if the Direct Write Data transfer is not exercised for the Write transaction.

ERROR

CHI Protocol Layer

resp flit valid

expected_tagop_value_in_comp_response_check

ARM-IHI0050E.b: 12.4 Read transaction rules

For a Comp response, the TagOp field is only used in response to a MakeReadUnique transaction and is used to indicate if responsibility for Dirty Tags is being passed to the Requester. In all other cases, it must be set to zero

Check that the TagOp field in the Comp response is set to a value that is permitted by the specification for the corresponding transaction type.
This check is not performed in case the Comp response has RespErr set to NON_DATA_ERROR as the TagOp in the response can take any value in case of a Non-Data Error.

ERROR

CHI Protocol Layer

dat flit valid

expected_tagop_value_in_read_data_check

ARM-IHI0050E.b: 12.4 Read transaction rules

The TagOp field in a Read data flit must be set to a valid value for the corresponding Atomic or Read transaction type

Check that the TagOp field in a Read data flit is set to a valid value for the corresponding Atomic or Read transaction type.
This check is not performed in case the Read transaction has received a NON_DATA_ERROR response as the TagOp in the Read data can take any value in such a case.

ERROR

CHI Protocol Layer

dat flit valid

same_tagop_value_in_all_read_data_flits_check

ARM-IHI0050E.b: 12.4 Read transaction rules

In case there are multiple Read data flits corresponding to a Read type transaction, the TagOp field must be set to the same value across all the Read data flits

Check that, in case there are multiple Read data flits corresponding to a Read type transaction, the TagOp field is set to the same value across all the Read data flits.

ERROR

CHI Protocol Layer

resp flit valid

associate_tagmatch_to_xact_check

ARM-IHI0050E.b: 12.11.1 Tag Match

The TgtID and TagGroupID fields in a TagMatch response must match the SrcID or ReturnNID and TagGroupID fields of the corresponding Write transaction with TagOp set to Match

Check that the TargetID and TagGroupID fields are set correctly in TagMatch responses.

A TagMatch response can be received only for Write or Atomic transactions whose TagOp is set to Match.
The TgtID and TagGroupID fields in a TagMatch response must match the SrcID and TagGroupID fields of the corresponding Write transaction with TagOp set to Match.

ERROR

CHI Protocol Layer

associate flit to xact

valid_parity_datacheck_for_read_data_check

ARM-IHI0050E.b: 9.6 Data Check

For transactions involving read data, datacheck is set appropriatly such that ODD Byte parity is generated.

Check that the Datacheck is set correctly such that ODD Byte parity is generated for Read Data

For all transactions, datacheck bit is set appropriatly such that ODD Byte parity is generated across the data that is being received.

ERROR

CHI Protocol Layer

resp flit valid

rsp_flit_dbid_check

ARM-IHI0050E.b: Table A-8 Response message field mappings

DBID field of the observed RSP flit must be valid

Check that the DBID field value of the following RSP flits is as follows.
RSP flits:

Comp/DBID/CompDBIDResp: DBID field must be unique for a given transaction and can be reused only after the transaction completes

In case of WriteNoSnpZero and WriteUniqueZero transactions dbid field in Comp/DBID/COMPSBISREesp is inapplicable and can take any value.

ERROR

CHI Protocol Layer

dat flit valid

readnosnp_associated_compdata_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

The cache state in the associated CompData flits of a ReadNoSnp transaction should indicate a valid value when the RespErr field does not indicate any error.

Check that the associated Compdata packet has valid cache state value for a ReadNoSnp transaction.
The cache state in the associated CompData flits of a ReadNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

readnosnp_associated_compdata_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.1 Read transactions

The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

Check that the associated Compdata packet has valid resp_err value for ReadNoSnp transaction.
The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.

ERROR

CHI Protocol Layer

resp flit validity

valid_compdbid_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that CompDBID Response flit is seen only in case of Write/CopyBack or AtomicStore transactions.
The Response flit type must correspond to one of the permitted values depending on the type of the transaction

ERROR

CHI Protocol Layer

resp flit validity

valid_dbid_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that DBID Response flit is seen only in case of non-Copyback Write transactions.
The Response flit type must correspond to one of the permitted values depending on the type of the transaction

ERROR

CHI Protocol Layer

resp flit validity

valid_compcmo_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5 Response types

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that CompCMO Response flit is seen only in case of Combined Write and (P)CMO transactions.

ERROR

CHI Protocol Layer

resp flit validity

valid_comp_flit_type_for_xact_check

ARM-IHI0050E.b: 4.5.1 Completion response

The Response flit type must correspond to one of the permitted values depending on the type of the transaction

Check that Comp Response flit is seen only in case of non-Snoop transactions.
The Response flit type must correspond to one of the permitted values depending on the type of the transaction

ERROR

CHI Protocol Layer

associate flit to xact

expected_rsp_flit_for_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The number of Response flits received for a transaction must match the number of responses, specified in the spec, for that transaction type.

Check that the transaction for which the coherent response is received has not already received a coherent response

The number of Response flits received for a transaction must match the number of responses, specified in the spec, for that transaction type.

ERROR

CHI Protocol Layer

associate flit to xact

associate_rsp_flit_to_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID of the response flit must be match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

Check that the Transaction ID, SourceID and TargetID fields are set correctly in the Response flits.

The SrcID and TgtID of the response flit must match the TgtID and SrcID of the request while the Txn ID of the response flit must be the same as that of the Request

ERROR

CHI Protocol Layer

associate flit to xact

expected_num_read_data_flits_check

ARM-IHI0050E.b: 2.10.4 Data packetization

The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

Check that the number of Read Data flits is equal to the expected value
The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

ERROR

CHI Protocol Layer

associate flit to xact

associate_read_dat_flit_with_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID of the Read data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

Check that the Transaction ID, SourceID and TargetID fields are set correctly in Read Data flits.

When SVT_CHI_ISSUE_B_ENABLE or SVT_CHI_ISSUE_C_ENABLE macro is not defined:
The TgtID of the Read data flit must match the SrcID of the Request
The SrcID of the Read data flit must match the TgtID of the Request
The TxnID of the Read data flit must be the same as that of the Request

When SVT_CHI_ISSUE_B_ENABLE or SVT_CHI_ISSUE_C_ENABLE macro is defined:
For RN: The TgtID of the Read data flit must match the SrcID of the Request irrespective of spec revision
For SN/HN: The TgtID of the Read data flit must match the SrcID of the Request for spec revision ISSUE_A
For SN/HN: The TgtID of the Read data flit must match the ReturnNID of the Request for spec revision ISSUE_B or later
For RN: The SrcID of the Read data flit must match the TgtID of the Request for ISSUE_A
For RN: The HomeNID of the Read data flit must match the TgtID of the Request for ISSUE_B or later
For SN/HN: The SrcID of the Read data flit must match the TgtID of the Request irrespective of spec revision
For RN: The TxnID of the Read data flit must be the same as that of the Request irrespective of spec revision
For SN/HN: The TxnID of the Read data flit must be the same as that of the Request for spec revision ISSUE_A
For SN/HN: The TxnID of the Read data flit must be the same as that of the ReturnTxnID Request for spec revision ISSUE_B or later

ERROR

CHI Protocol Layer

dat flit valid

valid_compdata_flit_for_xact_check

ARM-IHI0050E.b: 4.5.1 Completion response

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

COMPDATA is valid only in case of Read type transactions

ERROR

CHI Protocol Layer

dat flit valid

valid_combination_of_data_resp_err_field_in_read_xact_check

ARM-IHI0050E.b: 9.4.3 Write transactions

In a Data response to a Read request, Non-data Error response is permitted only in none or all data response packets.

Checks that either all or none of the data flits sent by a completer in response to a READ transaction have the RespErr field set to NDERR.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpptl_cleaninvalid_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteNoSnpPtl_CleanInvalid should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteNoSnpPtl_CleanInvalid transaction.

The associated responses (Comp, CompDBIDResp, CompCMO) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpfull_cleansharedpersistsep_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteNoSnpFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteNoSnpFull_CleanSharedPersitsSep transaction.

The associated responses (Comp, CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpptl_cleansharedpersistsep_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteNoSnpPtl_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteNoSnpPtl_CleanSharedPersistSep transaction.

The associated responses (Comp, CompDBIDResp, CompCMO, Persist, CompPersist) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpptl_cleanshared_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteNoSnpPtl_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteNoSnpPtl_CleanShared transaction.

The associated responses (Comp, CompDBIDResp, CompCMO) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpfull_cleaninvalid_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteNoSnpFull_CleanInvalid should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteNoSnpFull_CleanInvalid transaction.

The associated responses (Comp, CompDBIDResp, CompCMO) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpfull_cleanshared_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated response flits of WriteNoSnpFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp_err value for WriteNoSnpFull_CleanShared transaction.

The associated responses (Comp, CompDBIDResp, CompCMO) should not take EXOK resp_err value.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpzero_associated_response_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err field in the associated responses of WriteNoSnpZero transaction should take the legal values. Valid resp_err field values in DBIDResp is NORMAL_OKAY and in Comp/CompDBIDResp are NORMAL_OKAY, NON_DATA_ERROR and DATA_ERROR.

Check that the associated response packets has valid resp_err value for WriteNoSnpZero transaction.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpptl_cleaninvalid_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteNoSnpPtl_CleanInvalid transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpPtl_CleanInvalid transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteNoSnpPtl_CleanInvalid transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpptl_cleansharedpersistsep_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteNoSnpPtl_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpPtl_CleanSharedPersistSep transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteNoSnpPtl_CleanSharedPersistSep transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpfull_cleansharedpersistsep_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteNoSnpFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpFull_CleanSharedPersistSep transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteNoSnpFull_CleanSharedPersistSep transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpptl_cleanshared_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteNoSnpPtl_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpPtl_CleanShared transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteNoSnpPtl_CleanShared transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpfull_cleaninvalid_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteNoSnpFull_CleanInvalid transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpFull_CleanInvalid transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteNoSnpFull_CleanInvalid transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpfull_cleanshared_associated_response_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated response flits of WriteNoSnpFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated response flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpFull_CleanShared transaction.
The cache state and resp_pass_dirty fields in the associated reponse flits (Comp and CompCMO) of a WriteNoSnpFull_CleanShared transaction must be set to zero.

ERROR

CHI Protocol Layer

resp flit valid

writenosnpzero_associated_comp_response_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated comp response flit of a WriteNoSnpZero transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated comp response packet has valid resp field for a WriteNoSnpZero transaction.
The cache state indicated by resp field in the associated Comp response packet of a WriteNoSnpZero transaction should take a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpptl_cleaninvalid_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteNoSnpPtl_CleanInvalid should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteNoSnpPtl_CleanInvalid transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteNoSnpPtl_CleanInvalid transaction.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpfull_cleansharedpersistsep_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteNoSnpFull_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteNoSnpFull_CleanSharedPersitSep transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteNoSnpFull_CleanSharedPersitSep transaction.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpptl_cleansharedpersistsep_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteNoSnpPtl_CleanSharedPersistSep should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteNoSnpPtl_CleanSharedPersistSep transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteNoSnpPtl_CleanSharedPersistSep transaction.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpptl_cleanshared_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteNoSnpPtl_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteNoSnpPtl_CleanShared transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteNoSnpPtl_CleanShared transaction.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpfull_cleaninvalid_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteNoSnpFull_CleanInvalid should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteNoSnpFull_CleanInvalid transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteNoSnpFull_CleanInvalid transaction.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpfull_cleanshared_associated_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The resp_err value in associated write data flits of WriteNoSnpFull_CleanShared should take legal values as per CHI ISSUE E Specifications.

Check that the associated write data flits has valid resp_err value for WriteNoSnpFull_CleanShared transaction.

The associated write data flits should not take EXOK or NON_DATA_ERROR resp_err value for WriteNoSnpFull_CleanShared transaction.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpptl_cleaninvalid_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteNoSnpPtl_CleanInvalid transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpPtl_CleanInvalid transaction.
The cache state in the associated Write data flits of a WriteNoSnpPtl_CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpptl_cleansharedpersistsep_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteNoSnpPtl_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpPtl_CleanSharedPersistSep transaction.
The cache state in the associated Write data flits of a WriteNoSnpPtl_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpfull_cleansharedpersistsep_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteNoSnpFull_CleanSharedPersistSep transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpFull_CleanSharedPersistSep transaction.
The cache state in the associated Write data flits of a WriteNoSnpFull_CleanSharedPersistSep transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpptl_cleanshared_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteNoSnpPtl_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpPtl_CleanShared transaction.
The cache state in the associated Write data flits of a WriteNoSnpPtl_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpfull_cleaninvalid_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteNoSnpFull_CleanInvalid transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpFull_CleanInvalid transaction.
The cache state in the associated Write data flits of a WriteNoSnpFull_CleanInvalid transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

dat flit valid

writenosnpfull_cleanshared_associated_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The resp field cache state, Pass Dirty value in associated data flits of WriteNoSnpFull_CleanShared transaction should take legal values as per CHI ISSUE E Specifications.

Check that the associated data flits has valid resp field {cahe state and resp_pass_dirty} value for a WriteNoSnpFull_CleanShared transaction.
The cache state in the associated Write data flits of a WriteNoSnpFull_CleanShared transaction should indicate a valid value when the RespErr field does not indicate NON_DATA_ERROR.

ERROR

CHI Protocol Layer

request validity

new_req_before_completion_of_previous_read_write_xact_to_same_cacheline_check

ARM-IHI0050E.b: 2.9.4 Transaction attribute combinations

Read and Write transactions from the same source to addresses that overlap must remain ordered.

Check that a Read, Write, Dataless or Atomic request is issued when there are no outstanding Read or Write transactions to the same cache line.

"Outstanding Read" refers to all Read as well as dataless transactions other than CMOs.
"Outstanding Write" refers to all Write and Atomic transactions.

ERROR

CHI Protocol Layer

request validity

expected_xact_type_check

SYNOPSYS DEFINED

Only supported transaction types must be issued to a given node.

Check that only supported transaction types are received for a given node.
SYNOPSYS DEFINED:

DVMOp transactions are epected to be seen only for RNs with svt_chi_node_configuration :: dvm_enable set to 1
CHI-B or later specific transactions (RNSD, ROMI, ROCI, CSP, PrefetchTgt, AtomicOps) are expected to be seen only for a CHI-B or later compliant RN.
CHI-E or later specific transactions (Write*Zero, WriteEvictorEivct,...) are expected to be seen only for a CHI-E or later compliant RN.
CHI-F or later specific transactions (CleanInvalidPopa, WriteNoSnpDef, WriteBackFull_CleanInvalidPopa, WriteNoSnpFull_CleanInvalidPopa, WriteNoSnpPtl_CleanInvalidPopa) are expected to be seen only for a CHI-F or later compliant RN.
CHI-F transaction WriteNoSnpDef is currently unsupported by all CHI VIP components.
VIP currently does not support PrefetchTgt transactions.

ERROR

CHI Protocol Layer

retry xact

valid_pcrdreturn_check

ARM-IHI0050E.b: 2.3.8 Retry

PcrdReturn transaction can only be sent after the reception of a PcrdGrant flit

Check that PCrdReturn is sent only after RetryAck and PCrdGrant flits are received from the Target node.
PcrdReturn transaction can only be sent after the reception of a PcrdGrant flit

ERROR

CHI Protocol Layer

retry xact

valid_retry_xact_check

ARM-IHI0050E.b: 2.3.8 Retry

The transaction with credit must only be sent by the Requester after both the RetryAck response and an appropriate PCrdGrant response are received

Check that the transaction is retried only after RetryAck and PCrdGrant responses are received from the Target node.
The transaction with credit must only be sent by the Requester after both the RetryAck response and an appropriate PCrdGrant response are received, and the transaction attributes other than PCrdType, AllowRetry and QoS must be the same as the original request.

ERROR

CHI Protocol Layer

retry xact

valid_retry_xact_after_pcrdcgrant_check

ARM-IHI0050E.b: 2.11 Request Retry

The transaction must only be retried by the Requester when a PCrdGrant is received with the correct PCrdType.

The transaction must only be retried by the Requester when a PCrdGrant is received with the correct PCrdType

ERROR

CHI Protocol Layer

retry xact

valid_p_crd_type_in_pcrdreturn_flit_check

ARM-IHI0050E.b: 2.11.2 Transaction Retry mechanism

A PCrdReturn transaction must have the credit type set to the value of the credit type that is being returned

Check that the credit type field in a PCrdReturn transaction is set correctly.
Before the PCrdReturn flit, a PCrdGrant must have been received with the same PCrdType

ERROR

CHI Protocol Layer

associate flit to xact

associate_write_dat_flit_with_xact_check

ARM-IHI0050E.b: 2.6 Transaction identifier field flows

The SrcID of the Write data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

Check that the Transaction ID, SourceID and TargetID fields are set correctly in Write Data flits.

The SrcID of the Write data flit must match the Tgt ID of the request while the Txn ID of the response flit must be the same as that of the Request

ERROR

CHI Protocol Layer

associate flit to xact

valid_byte_enable_for_write_data_check

ARM-IHI0050E.b: 2.10.3 Byte Enables

For all Write transactions, byte enables that are not within the data window, specified by Addr and Size, must be deasserted.

Check that the Byte Enables are set correctly for Write Data

For all Write transactions, byte enables that are not within the data window, specified by Addr and Size, must be deasserted.
For DVMOp transactions, only the least significant 8 bits must be asserted.
For all Atomic transactions, byte enables that are not within the data window,specified by Addr and Size ,muts be deasserted.

ERROR

CHI Protocol Layer

associate flit to xact

expected_num_write_data_flits_check

ARM-IHI0050E.b: 2.10.4 Data packetization

The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

Check that the number of Write Data flits is equal to the expected value
The number of data flits for a transaction is determined by number of bytes to be transferred and data bus width

ERROR

CHI Protocol Layer

associate flit to xact

write_dat_xfer_after_dbid_check

ARM-IHI0050E.b: 2.3 Transaction structure

WriteData must only be sent by the Requester after either DBIDResp or CompDBIDResp is received.

Check that the Write Data flits are transmitted only after CompDBIDResp/DBIDResp.

ERROR

CHI Protocol Layer

dat flit valid

writenosnp_associated_response_data_packets_legal_cache_state_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

The cache state in the associated Write data flits of a WriteNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.

Check that the associated data packets has valid cache state value for a WriteNoSnp transaction.
The cache state in the associated Write data flits of a WriteNoSnp transaction should indicate a valid value when the RespErr field does not indicate any errors.

ERROR

CHI Protocol Layer

dat flit valid

valid_tag_when_tu_is_zero_in_tag_update_write_check

ARM-IHI0050E.b: 12.5 Write transactions

In Write Data with TagOp Update, a TU value of zero must set the associated TU value to zero.

Check that in Write Data with TagOp Update, a TU value of zero must set the associated Tag value to zero.

ERROR

CHI Protocol Layer

dat flit valid

valid_tag_update_value_in_write_data_check

ARM-IHI0050E.b: 12.5 Write transactions

The TU bits must be set appropriately in the Write data responses seen for Write transactions based on the TagOp field in the data as well as the corresponding request type

Check that the TU bits are set correctly in the Write data responses seen for Write transactions.

For all Write transactions with TagOp set to Update, TU bits that are not within the data window, specified by Addr and Size, must be deasserted.
In case of full cacheline Write transactions (Write*Full) with TagOp set to Update, all TU bits must be asserted.
In case of Writes with TagOp set to a value other than TAG_UPDATE, the TU bits are inappicable and must be set to zero.

ERROR

CHI Protocol Layer

dat flit valid

expected_tagop_value_in_write_data_check

ARM-IHI0050E.b: 12.5 Write transactions

The TagOp field in a Write data flit must be set appropriately based on the corresponding Atomic or Write request type and the TagOp in the request

Check that the TagOp field in a Write data flit is set to a valid value for the corresponding Atomic or Write transaction type.

ERROR

CHI Protocol Layer

dat flit valid

same_tagop_value_in_all_write_data_flits_check

ARM-IHI0050E.b: 12.5 Write transactions

In case there are multiple Write data flits corresponding to a Write type transaction, the TagOp field must be set to the same value across all the Write data flits

Check that, in case there are multiple Write data flits corresponding to a Write or Atomic type transaction, the TagOp field is set to the same value across all the Write data flits.

ERROR

CHI Protocol Layer

associate flit to xact

valid_parity_datacheck_for_write_data_check

ARM-IHI0050E.b: 9.6 Data Check

For transactions involving write data, datacheck is set appropriatly such that ODD Byte parity is generated.

Checks that the Datacheck is set correctly such that ODD Byte parity is generated for Write Data

For all transactions, datacheck bit is set appropriatly such that ODD Byte parity is generated across the data that is being transmited.

ERROR

CHI Protocol Layer

dat flit valid

valid_write_data_when_be_is_zero_check

ARM-IHI0050E.b: 2.10.3 Byte Enables

In Write Data, a byte enable value of zero must set the associated data byte value to zero.

Check that in Write Data, a byte enable value of zero must set the associated data byte value to zero.

ERROR

CHI Protocol Layer

dat flit valid

valid_writedatacancel_flit_for_xact_check

ARM-IHI0050E.b: 4.5.2 WriteData response

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

WRITEDATACANCEL is valid only in case of WriteNoSnoop transactions with mem_attr other than DEVICE memory type and WriteUniquePtl type transactions

ERROR

CHI Protocol Layer

dat flit valid

valid_noncbwrdata_flit_for_xact_check

ARM-IHI0050E.b: 4.5.2 WriteData response

Data flit type must be set to one of the permitted values for the Request

Check that the data type of the flit matches the expected value.

NONCOPYBACKWRDATA is valid only in case of WriteNoSnoop, WriteUnique and DVMOp type transactions

ERROR

CHI Protocol Layer

request validity

single_outstanding_req_per_txn_id_check

ARM-IHI0050E.b: 2.5.2 Transaction ID

The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID

Check that there are no multiple outstanding transactions from the same source with the same transaction IDs.

The TxnID must be unique for a given Requester. The Requester can reuse the ID only after it has received all responses associated with a previous transaction that has used the same TxnID

ERROR

CHI Protocol Layer

dat flit field

dat_flit_dbid_check

ARM-IHI0050E.b: Table A-9 Data message field mappings

DBID field of the observed DAT flit must be valid

Check that the DBID field value of the following DAT flits is as follows.
DAT flits:

SnpRespData, SnpRespDataPtl, NonCopyBackWrData, CopyBackWrData: In case of CHI-A nodes, DBID field must be zeroes or must be set to TxnID of originating request. For SnpRespData*, originating request is the Snoop request.
CompData: DBID field must be unique for a given non-DMT and non-DCT Read transaction with ExpCompAck asserted and can be reused only after the transaction completes.

ERROR

CHI Protocol Layer

dat flit field

tx_dat_flit_data_id_check

ARM-IHI0050E.b: 13.10.50 Data Identifier, DataID

data_id of the observed Tx DAT flit must be valid

Check the DataId field value of transmitted DAT flits from the monitored DUT.
This is determined based on data width of DAT VC along with data size of the corresponding transaction.
Note that this check, in case CCF Wrap Order is set to True at the sender, checks that the first data flit transmitted corresponds to the critical chunk indicated by CCID (,ie, the data_id of the first data flit matches the CCID value). For the subsequent flits, the check ensures that the data_id values are set correctly.
In case CCF Wrap Order is set to False at the sender, this check only verifies that the data_id takes one of the legal values prescribed in Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b)
Following are the Tx DAT flit types considered by this check.
. If the monitored DUT is RN:

CopyBackWrData
NonCopyBackWrData
SnpRespData
SnpRespDataPtl

If the monitored DUT is SN:

CompData

ERROR

CHI Protocol Layer

dat flit valid

valid_data_source_in_snprespdata_check

ARM-IHI0050E.b: 11.1 Data Source indication

The DataSource field in the snprespdata flits corresponding to a snoop transaction must take legal values.

Check that the DataSource field in the associated snprespdataptl,snprespdata packets have a valid value.

ERROR

CHI Protocol Layer

dat flit field

rx_dat_flit_data_id_check

ARM-IHI0050E.b: 13.10.50 Data Identifier, DataID

data_id of the observed Rx DAT flit must be valid

Check the DataId field value of received DAT flits by the monitored DUT.
This is determined based on data width of DAT VC along with data size of the corresponding transaction.
Note that this check, in case of in-order Interconnect, checks that the first data flit transmitted corresponds to the critical chunk indicated by CCID (,ie, the data_id of the first data flit matches the CCID value). For the subsequent flits, the check ensures that the data_id values are set correctly.
Incase of out-of-order interconnect, this check only verifies that the Data_ID takes one of the legal values prescribed in Table 11-29 (ARM-IHI0050A), Table 12-41(ARM-IHI0050B) and Table 13-40 (ARM-IHI0050E.b).
Following are the Rx DAT flit types considered by this check.
. If the monitored DUT is RN:

CompData

If the monitored DUT is SN:

NonCopyBackWrData

ERROR

CHI Protocol Layer

SYSCO Interface Validity

sysco_interface_snoop_traffic_validity_check

ARM-IHI0050E.b: 15.2 Handshake

An RN is not expected to receive any snoops when it is in COHERENCY_DISABLED state.

ERROR

CHI Protocol Layer

SYSCO Interface Validity

sysco_interface_coherency_enabled_state_traffic_validity_check

ARM-IHI0050E.b: 15.2 Handshake

A transaction that permits it to cache a coherent location should be issued only in the coherency_enabled state.

A transaction that permits it to cache a coherent location should be issued only in the coherency_enabled state.
If svt_chi_node_configuration :: block_all_transactions_until_coherency_enabled is set to 1 then any transaction should be issued only in the coherency_enabled state.

ERROR

CHI Protocol Layer

SYSCO Interface Validity

sysco_interface_coherency_disconnect_state_traffic_validity_check

ARM-IHI0050E.b: 15.2 Handshake

All coherent transactions that can be cached must be completed before entering COHERENCY_DISCONNECT_STATE.

All coherent transactions that can be cached must be completed before entering COHERENCY_DISCONNECT_STATE.
If svt_chi_node_configuration :: block_all_transactions_until_coherency_enabled is set to 1 then there should not be any outstanding transactions in COHERENCY_DISCONNECT_STATE.

ERROR

CHI Protocol Layer

SYSCO Interface Validity

sysco_interface_coherency_disabled_state_traffic_validity_check

ARM-IHI0050E.b: 15.2 Handshake

During COHERENCY_DISABLED_STATE there should not be any outstanding snoop transactions.

ERROR

CHI Protocol Layer

trace tag valid

trace_tag_validity_check

ARM-IHI0050E.b: 11.5 Trace Tag

Monitor Check that the spawned response or data packet has valid trace_tag value

The response or data packet should have the valid trace_tag value in response to the request packet.

ERROR

CHI Protocol Layer

dvm outstanding transactions

num_non_dvm_snoop_exceeded_configured_value_check

SYNOPSYS DEFINED

The number of outstanding non-dvm snoop should not exceed the configured value.

Check that the number of outstanding non-dvm snoop transactions have not reached the value configured in svt_chi_node_configuration :: num_outstanding_non_dvm_snoop_xact.

ERROR

CHI Protocol Layer

dvm outstanding transactions

num_dvm_snoop_exceeded_configured_value_check

SYNOPSYS DEFINED

The number of outstanding dvm snoop should not exceed the configured value.

Check that the number of outstanding dvm snoop transactions have not reached the value configured in svt_chi_node_configuration :: num_outstanding_dvm_snoop_xact.

ERROR

CHI Protocol Layer

retry xact

end_of_simulation_outstanding_protocol_credit_check

SYNOPSYS DEFINED

There shouldn't be any outstanding protocol credits at the end of simulation. Protocol credits must be utilized by retrying the original transaction or by PCRDRETURN

Check that there shouldn't be any outstanding protocol credits at the end of simulation. Protocol credits must be utilized by retrying the original transaction or returned via PCRDRETURN.

ERROR

CHI Protocol Layer

resp and dat flit valid

writenosnp_associated_response_data_packets_legal_resperr_check

ARM-IHI0050E.b: 9.4.3 Write transactions

The associated data packet's resp_err field should not take EXOK or NDERR value for WriteNoSnp transaction. The resp_err field in the associated response should not take EXOKAY for a non-Exclusive WriteNoSnp transaction

Check that the associated response and data packets has valid resp_err value for WriteNoSnp transaction.
The associated data packet's resp_err field should not take EXOK or NDERR value for WriteNoSnp transaction.

ERROR

SYSTEM: ACE

CMO

forward_cmos_to_slave_check

Synopsys Defined

Monitor check that cache maintenance transactions are forwarded to slaves if forward_cmos_to_slaves_check_enable is set in the slave configuration

Checks that cache maintenance transactions are forwarded to slaves If two or more slaves are in the same address space of the memory map, this check is performed on each of the slave ports with overlapping address.

ERROR

SYSTEM: ACE

Exclusive Access

exclusive_snoop_propagation_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.3.1 Minimum PoS Exclusive Monitor

Monitor Checks that if interconnect stopped snoop propagation for exclusive transaction that was not successful

Checks if interconnect stopped snoop propagation for exclusive transaction that was not successful

ERROR

SYSTEM: ACE

Exclusive Access

exclusive_store_from_valid_state_sys_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Checks that if cacheline is in invalid state then exclusive store transaction is not issued

Checks that if cacheline is in invalid state then exclusive store transaction is not issued

ERROR

SYSTEM: ACE

Exclusive Access

exclusive_load_from_valid_state_sys_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load

Monitor Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

ERROR

SYSTEM: ACE

Exclusive Access

restart_exclusive_seq_post_cache_line_invalidation_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Check that an exclusive sequence is reset after a cacheline is invalidated by a snoop. After a snoop invalidates a cacheline, an exclusive load must always be sent prior to sending the exclusive store

Checks that an exclusive sequence is reset after a cacheline is invalidated by a snoop. This checks that after a snoop invalidates a cacheline, an exclusive load is always sent prior to sending the exclusive store.

ERROR

SYSTEM: ACE

Barrier

outstanding_master_barrier_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check that an ACE master interface must not issue more than 256 outstanding barrier transactions

System monitor should ensure that an ACE master interface must not issue more than 256 outstanding barrier transactions

ERROR

SYSTEM: ACE

Routing

no_slave_respond_with_decerr_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A3.4.5 Read and write response structure

Monitor Check that each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it

System monitor should ensure that each slave responds with DECERR if any transaction is routed to it with an address range that is not visible to it

ERROR

SYSTEM: ACE

DVM

master_dvm_no_data_transfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.1.1 Transaction groups

Monitor Check that no data is transferred for a DVM transaction

Checks that no data is transferred for a DVM transaction

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_response_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Check that the interconnect sets RRESP value of a DVM transaction correctly

Checks that the interconnect sets RRESP value of a DVM transaction correctly based on the following: The interconnect component gathers all response values and responds to the originator as follows: if CRRESP is 0b00000 for all responses, the interconnect component sets RRESP to 0b0000. If CRRESP is 0b00010 for any responses, the interconnect component sets RRESP to 0b0010.

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_complete_issue_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that the interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master

Checks that the interconnect issues a DVM complete to the master that issued the DVM Sync only after it receives a DVM Complete from each participating master.

ERROR

SYSTEM: ACE

DVM

master_dvm_complete_issue_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that a DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master.

Checks that a DVM Complete on the read address channel is issued after the handshake of the associated DVM Sync on the snoop address channel of the same master

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_response_timing_check

Synopsys Defined

Monitor Check that the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync after all snoop responses are received.

Checks that the interconnect collects the acknowledgements to DVM sent on snoop channel and responds to original DVM Sync. This check ensures that this acknowledgement is sent only after all snoop responses are received.

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_sync_snoop_transaction_association_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component.

Checks that interconnect sends a dvm sync on the snoop address channel of all participating components when it receives a dvm sync transaction from a component

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_operation_snoop_transaction_association_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.1 DVM message transactions

Monitor Check that interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component.

Checks that interconnect sends a dvm operation on the snoop address channel of all participating components when it receives a dvm operation transaction from a component.

ERROR

SYSTEM: ACE

DVM

interconnect_dvm_complete_dvm_sync_association_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that a DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel

Checks that a DVM Complete is received on the snoop channel only if the port has sent a DVM Sync on the read channel

ERROR

SYSTEM: ACE

DVM

master_outstanding_snoop_dvm_sync_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.4 DVM Complete

Monitor checks that maximum number of outstanding DVM Sync messages that a master must be able to accept is 256. The number of outstanding DVM Sync messages accepted by master exceeds 256.

Checks that maximum number of outstanding DVM Sync messages that a master must be able to accept is 256. This check fires an error if the number of outstanding DVM Sync messages exceeds 256.

ERROR

SYSTEM: ACE

DVM

master_outstanding_dvm_sync_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.2 DVM Synchronization and DVM Complete transactions

Monitor Check that a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction

Checks that a component must have only one outstanding DVM Sync transaction. A component must receive a DVM Complete transaction before it issues another DVM Sync transaction

ERROR

SYSTEM: ACE

Data Integrity

data_integrity_with_outstanding_coherent_write_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.5.1 Interconnect read from main memory or peripheral device

Monitor Check that data returned in a coherent read transaction matches that of a WRITEBACK/WRITECLEAN transaction that was in progress when the read was initiated

Checks that the read data returned for a coherent read is the same as that of a WRITEBACK or WRITECLEAN transaction which was in progress when the read was initiated. This is to check that an interconnect that does speculative reads re-fetches the data in a scenario where the preceding WRITEBACK/WRITECLEAN did not complete and none of the snoops returned data. For example, consider that a WRITEBACK was in progress while a read is initiated by the master. If the interconnect does speculative reads, the speculative read may return stale data since the WRITEBACK is not complete. If none of the snoops return data as well, the interconnect should re-fetch data after the completion of the WRITEBACK.

ERROR

SYSTEM: ACE

Routing

slave_read_xact_timing_relative_to_last_posted_write_xact_check

Synopsys Defined

Monitor Check that a read transaction is routed to the slave only after the last posted write transaction with overlapping address from the same port has completed at the slave

Checks that a READ transaction is routed to a slave only after a previous WRITE transaction from the same port and with an overlapping address completes at the slave. This is required in posted writes to ensure that a READ transaction retreives the same data as the previous WRITE transaction.

ERROR

SYSTEM: ACE

Cache Coherency

cacheline_and_memory_coherency_check_per_xact

Synopsys Defined

Monitor Check that if cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory. This check may not pass if a transaction to the slave is in the interconnect's buffer by the time a coherent transaction completes.

Checks that if all cachelines are clean, the data in cacheline is consistent with data in memory. This check is done on a per transaction basis at the end of each coherent transaction. Note that in some implementations a transaction to the memory could still be in the interconnect's buffer in which case this check would fail. Hence this check is issued as a warning, rather than an error.

WARNING

SYSTEM: ACE

Cache Coherency

interconnect_generated_write_xact_to_update_main_memory_check

Synopsys Defined

Monitor Check that if a snoop response has the PassDirty response asserted, and the interconnect does not assert the PassDirty transaction response for the initiating master, the interconnect must generate a write transaction to update main memory.

ERROR

SYSTEM: ACE

Cache Coherency

cacheline_and_memory_coherency_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model

Monitor Check that if cachelines of all masters of a particular address are clean, the data in cache should be consistent with data in memory

Checks that if all cachelines are clean, the data in cacheline is consistent with data in memory

ERROR

SYSTEM: ACE

Cache Coherency

no_two_cachelines_in_dirty_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model

Monitor Check that no two masters have the same cacheline in the dirty state

Checks that no two masters have the same cacheline in dirty state

ERROR

SYSTEM: ACE

Cache Coherency

no_two_cachelines_in_unique_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.2.3 Cache state model

Monitor Check that no two masters have the same cacheline in the unique state

Checks that no two masters have the same cacheline in unique state

ERROR

SYSTEM: ACE

Cache Coherency

overlapping_addr_sequencing_check

Synopsys Defined

Monitor Check that if two masters access the same cache line, one master is sequenced after the other

Checks that if two masters access the same cache line, one master is sequenced after the other

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_and_snoop_data_match_check

Synopsys Defined

Monitor Check that data returned to initiating master matches the data received from snoop transaction

Checks that data returned to initiating master matches the data received from snoop transaction

ERROR

SYSTEM: ACE

Snoop Response

snoop_data_consistency_check

Synopsys Defined

Monitor Check that data returned from all snoop transactions are consistent

Checks that data returned from all snoop transactions are consistent

ERROR

SYSTEM: ACE

Snoop Response

snoop_resp_passdirty_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that no two responses to a snoop transaction have the PassDirtyCRRESP[2] bit asserted

Checks that no two responses to a snoop transaction have the PassDirty(CRRESP[2]) bit asserted

ERROR

SYSTEM: ACE

Snoop Response

snoop_resp_wasunique_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that no two responses to a snoop transaction have the WasUniqueCRRESP[4] bit asserted

Checks that no two responses to a snoop transaction have the WasUnique(CRRESP[4]) bit asserted

ERROR

SYSTEM: ACE

Coherent Response

coherent_resp_passdirty_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.4 Transaction responses from the interconnect

Monitor Check that the PassDirty response to initiating master is correct

Checks that the PassDirty response to initiating master is correct

ERROR

SYSTEM: ACE

Coherent Response

coherent_resp_isshared_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.4 Transaction responses from the interconnect

Monitor Check that the IsShared response to initiating master is correct

Checks that the IsShared response to initiating master is correct

ERROR

SYSTEM: ACE

Coherent Response

coherent_resp_start_conditions_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that the response to a coherent transaction is not started before sufficient information from snooped masters are obtained

Checks that the response to a coherent transaction is not started before sufficient information from snooped masters are obtained

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_xact_with_no_snoop_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.3 Issuing snoop transactions

Monitor Check that READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters

Checks that READNOSNOOP,WRITENOSNOOP,WRITEBACK,WRITECLEAN and EVICT do not cause a snoop of cached masters

ERROR

SYSTEM: ACE

Coherent And Snoop

snoop_not_sent_to_initiating_master_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.3 Issuing snoop transactions

Monitor Check that a snoop is not sent to the initiating master

Checks that a snoop is not sent to the initiating master

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_snoop_prot_type_match_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor Check that the security level determined by signal ACPROT[1] of the snoop transaction matches the security level of corresponding coherent transaction determined by signal AxPROT[1]

Monitor Check that the security level (determined by signal ACPROT[1]) of the snoop transaction matches the security level of corresponding coherent transaction (determined by signal AxPROT[1])

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_snoop_domain_match_check

Synopsys Defined

Monitor Check that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master

Checks that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master

ERROR

SYSTEM: ACE

Coherent And Snoop

coherent_snoop_type_match_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.1 Mapping coherency operations to snoop operations

Monitor Check that the snoop transaction type corresponds to the coherent transaction type of initiating master

Checks that the snoop transaction type corresponds to the coherent transaction type of initiating master

ERROR

SYSTEM: ACE

Coherent And Snoop

snoop_addr_matches_coherent_addr_check

Synopsys Defined

Monitor Check that the address of a snoop transaction must match one of the outstanding coherent transactions

Checks that the address of a snoop transaction matches address of one of the outstanding coherent transactions.

ERROR

SYSTEM: AXI3 Onwards

Data Integrity

write_byte_count_match_across_interconnect

Synopsys Defined

Monitor check that the effective number of bytes bytes for which strobe is asserted of write transactions sent by masters match the effective number of bytes for write transactions sent by interconnect to slave

Checks that the effective number of bytes for write transactions sent by master components match that which are sent by the interconnect to the slaves. This basically checks for spurious writes from the interconnect. The effective write byte count is the number of bytes for which write strobe is asserted. If there are writes generated by the interconnect because dirty data returned by a snoop could not be passed back to a master, the effective write byte count includes the number of bytes in a snoop also.

ERROR

SYSTEM: AXI3 Onwards

M2S Correlation

eos_unmapped_master_xact

Synopsys Defined

Monitor check that all master transactions are correlated to corresponding slave transactions

At the end of the simulation if there are master transactions that could not be associated to corresponding slave transactions, this error is issued.

ERROR

SYSTEM: AXI3 Onwards

Memory Type

eos_unmapped_non_modifiable_xact

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.4.1 Memory type requirements

Monitor check that all non-modifiable transactions are made visible to the final destination in a timely manner

At the end of simulation there should be no non-modifiable transaction that hasn't been mapped to a slave transaction. If such a transaction exists it shows that a non-modifiable transaction hasn't been made visible at the slave, which is not allowed

ERROR

SYSTEM: AXI3 Onwards

Memory Type

device_non_bufferable_response_match_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.4.1 Memory type requirements

Monitor check that for device non-bufferable transactions, responses are obtained from the final destination

For device non-bufferable transactions, responses must be obtained from the final destination. Checks that the timing of the response of the master transaction is after that of the corresponding slave transaction and that the responses match.

ERROR

SYSTEM: AXI3 Onwards

Ordering

ordering_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, transactions with the same ID to the same slave must be ordered

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, transactions in the same direction to the same slave with the same ID, must be ordered irrespective of the address

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

cache_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, cache_type matches between master transaction and corresponding slave transaction for all bits except the bufferable bit cache_type[0]

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the cache_type should match between master transaction and corresponding slave transaction, except for ARCACHE[0]/AWCACHE[0].

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

burst_size_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, burst_size matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_size should match between master transaction and corresponding slave transaction

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

burst_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, burst_type matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_type should match between master transaction and corresponding slave transaction

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

burst_length_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, burst_length matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the burst_length should match between master transaction and corresponding slave transaction if burst_length <= 16. For larger burst lengths a transaction could get split if getting routed to an AXI interface that doesn't support burst length > 16. This check is not done when burst_length > 16.

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

region_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, region matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the region should match between master transaction and corresponding slave transaction

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

prot_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, prot_type matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the prot_type should match between master transaction and corresponding slave transaction

ERROR

SYSTEM: AXI3 Onwards

Attributes Propagation

atomic_type_match_for_non_modifiable_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A4.3.1 AxCACHE[1], Modifiable

Monitor check that for non-modifiable transactions, atomic_type matches between master transaction and corresponding slave transaction

For non-modifiable transactions with ARCACHE[1] == 1'b0 or AWCACHE[1] == 1'b0, the atomic_type should match between master transaction and corresponding slave transaction

ERROR

SYSTEM: AXI3 Onwards

Data Integrity

master_slave_xact_data_integrity_check

Synopsys Defined

Monitor Check that data in slave transaction matches that in the master transaction

Checks that the data in a slave transaction is the same as that of the corresponding master transaction. In order to perform this check, slave transactions are correlated to corresponding master transactions. When only the former is set, this check is done only on non-modifiable transactions.

ERROR

SYSTEM: AXI3 Onwards

Data Integrity

data_integrity_check

Synopsys Defined

Monitor Check that data is fetched and routed correctly by the interconnect

Checks that data in transaction is consistent with data in memory when the transaction completes. This checks that a WRITE transaction issued by a master is written to memory correctly. Similarly, it checks that a READ transaction fetches the correct data from memory. The check assumes that a transaction issued by a master completes only after response is received from the slave to which that transaction was routed. It also assums that there is no other transaction that accesses an overlapping address during the period that the response is issed by the slave and the transaction completes in the master that issued the transaction. In ACE, this check is issued only when the snoop has not returned any data and data is fetched from memory or when data is written to memory.

ERROR

SYSTEM: AXI3 Onwards

Routing

slave_transaction_routing_check

Synopsys Defined

Monitor Check that transaction is routed to the correct slave based on address

Checks that a transaction is routed correctly to a slave port based on address

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysreq_stable_till_csysack_check

AXI low-power interface

while exiting from low power state, csysreq has gone low before the cactive, csysack have gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysack_timeout_after_cactive_check

AXI low-power interface

after cactive, csysreq have gone high, timedout waiting for csysack to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_cactive_stable_till_csysreq_csysack_check

AXI low-power interface

while exiting from low power state, cactive has gone low before the csysack has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysack_before_cactive_check

AXI low-power interface

while exiting from low power state, csysack has gone high before the cactive has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_cactive_timeout_after_csysreq_check

AXI low-power interface

after csysreq has gone high, timedout waiting for cactive to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_ctrl_csysreq_stable_till_cactive_check

AXI low-power interface

while exiting from low power state, csysreq has gone low before the cactive has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysreq_stable_till_csysack_check

AXI low-power interface

while exiting from low power state, csysreq has gone low before the csysack has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysack_timeout_after_csysreq_check

AXI low-power interface

after cactive, csysreq have gone high, timedout waiting for csysack to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_cactive_stable_till_csysreq_csysack_check

AXI low-power interface

while exiting from low power state, cactive has gone low before the csysreq, csysack have gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysack_before_csysreq_check

AXI low-power interface

while exiting from low power state, csysack has gone high before the csysreq has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_csysreq_timeout_after_cactive_check

AXI low-power interface

after cactive has gone high, timedout waiting for csysreq to go high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_prp_cactive_stable_till_csysreq_check

AXI low-power interface

while exiting from low power state, cactive has gone low before the csysreq has gone high

ERROR

PORT: AXI_LP

Exit From LP

exit_from_lp_csysack_before_cactive_csysreq_check

AXI low-power interface

while exiting from low power state, csysack has gone high before cactive/csysreq going high

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysreq_stable_till_csysack_check

AXI low-power interface

csysreq has gone high without waiting for csysack to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysack_timeout_after_csysreq_check

AXI low-power interface

after csysreq has gone low, timedout waiting for csysack to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_cactive_stable_till_csysreq_csysack_check

AXI low-power interface

while entering into low power state, cactive has gone high without waiting for csysreq and csysack to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysack_before_csysreq_check

AXI low-power interface

after cactive has gone low, csysack has gone low before csysreq going low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysreq_timeout_after_cactive_check

AXI low-power interface

after cactive has gone low, timedout waiting for csysreq to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_cactive_stable_till_csysreq_check

AXI low-power interface

while entering into low power state, cactive has gone high without waiting for csysreq to go low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysack_before_cactive_check

AXI low-power interface

while entering into low power state, csysack has gone low before cactive going low

ERROR

PORT: AXI_LP

Entry To LP

entry_to_lp_csysreq_before_cactive_check

AXI low-power interface

while entering into low power state, csysreq has gone low before cactive going low

ERROR

PORT: AXI_LP

Signal Validity

signal_valid_csysack_check

AXI low-power interface

X/Z on the csysack signal

ERROR

PORT: AXI_LP

Signal Validity

signal_valid_csysreq_check

AXI low-power interface

X/Z on the csysreq signal

ERROR

PORT: AXI_LP

Signal Validity

signal_valid_cactive_check

AXI low-power interface

X/Z on the cactive signal

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

armmussidv_valid_with_atst_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.2 ATST flow

Monitor checks that the value of ARMMUSSIDV is Low when ARMMUATST signal is asserted

Checks that the value of ARMMUSSIDV is compatibles ARMMUATST signal or ARMMUFLOW.
When ARMMUATST is asserted, ARMMUSSIDV must be Low.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

awmmussidv_valid_with_atst_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.2 ATST flow

Monitor checks that the value of AWMMUSSIDV is Low when AWMMUATST signal is asserted

Checks that the value of AWMMUSSIDV is compatibles AWMMUATST signal or AWMMUFLOW.
When AWMMUATST is asserted, AWMMUSSIDV must be Low.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

armmusecsid_valid_with_atst_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.2 ATST flow

Monitor checks that the value of ARMMUSECSID is compatibles ARMMUATST signal or ARMMUFLOW

Checks that the value of ARMMUSECSID is compatibles ARMMUATST signal or ARMMUFLOW.
When ARMMUATST is asserted or ARMMUFLOW is ATST, ARMMUSECSID must be Non-secure or Realm.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

awmmusecsid_valid_with_atst_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.1 Secure Stream Identifier SECSID

Monitor checks that the value of AWMMUSECSID is compatibles AWMMUATST signal or AWMMUFLOW

Checks that the value of AWMMUSECSID is compatibles AWMMUATST signal or AWMMUFLOW.
When AWMMUATST is asserted or AWMMUFLOW is ATST, AWMMUSECSID must be Non-secure or Realm.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

armmusecsid_arprot_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.1 Secure Stream Identifier SECSID

Monitor Check for untranslated transaction that ARPROT[1] is HIGH, when ARMMUSECSID is deasserted!

For transactions that are in a Non-secure stream, as indicated by ARMMUSECSID deasserted, ARPROT[1] must be HIGH, which indicates a Non-secure transaction.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

awmmusecsid_awprot_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.1 Secure Stream Identifier SECSID

Monitor Check for untranslated transaction that AWPROT[1] is HIGH, when AWMMUSECSID is deasserted!

For transactions that are in a Non-secure stream, as indicated by AWMMUSECSID deasserted, AWPROT[1] must be HIGH, which indicates a Non-secure transaction.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v2_valid_rresp_when_transfault_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.4 PRI flow

Monitor Check for untranslated transaction that, If TRANSFAULT is used for one response beat, it must be used for all response beats of a transaction!

If TRANSFAULT is used for one response beat, it must be used for all response beats of a transaction.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v2_valid_armmuflow_rresp_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.4 PRI flow

Monitor Check for untranslated transaction that RRESP must not be TRANSFAULT, When ARMMUFLOW is not PRI !

If ARMMUFLOW is not PRI, RRESP must not be TRANSFAULT.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v2_atst_armmuflow_valid_armmussidv_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.2 ATST flow

Monitor Check for untranslated transaction that ARMMUSSIDV must be LOW, When ARMMUFLOW is ATST!

When ARMMUFLOW is ATST,ARMMUSSIDV must be LOW. Secure translated transactions are not supported.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v2_atst_armmuflow_valid_armmusecsid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.2 ATST flow

Monitor Check for untranslated transaction that ARMMUSECSID must be LOW, When ARMMUFLOW is ATST!

When ARMMUFLOW is ATST,ARMMUSECSID must be LOW. Secure translated transactions are not supported.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v3_valid_artagop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.6 Untranslated transaction qualifier

Monitor Check for untranslated transaction that ARTAGOP must be 0b00 Invalid when ARMMUVALID is asserted!

When ARMMUVALID is asserted, ARTAGOP must be 0b00 (Invalid).

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_armmuvalid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for signal stability when corresponding valid signal is high

ARMMUVALID should be stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_armmuvalid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUVALID is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_armmuflow_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for signal stability when corresponding valid signal is high

ARMMUFLOW should be stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_armmuflow_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUFLOW is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v2_valid_awmmuflow_bresp_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.4 PRI flow

Monitor Check for untranslated transaction that BRESP must not be TRANSFAULT, When AWMMUFLOW is not PRI !

If AWMMUFLOW is not PRI, BRESP must not be TRANSFAULT.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v2_atst_awmmuflow_valid_awmmussidv_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.2 ATST flow

Monitor Check for untranslated transaction that AWMMUSSIDV must be LOW, When AWMMUFLOW is ATST!

When AWMMUFLOW is ATST,AWMMUSSIDV must be LOW. Secure translated transactions are not supported.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v2_atst_awmmuflow_valid_awmmusecsid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.5.2 ATST flow

Monitor Check for untranslated transaction that AWMMUSECSID must be LOW, When AWMMUFLOW is ATST!

When AWMMUFLOW is ATST,AWMMUSECSID must be LOW. Secure translated transactions are not supported.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

untranslated_v3_valid_awtagop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.6 Untranslated transaction qualifier

Monitor Check for untranslated transaction that AWTAGOP must be 0b00 Invalid when AWMMUVALID is asserted!

When AWMMUVALID is asserted, AWTAGOP must be 0b00 (Invalid).

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_awmmuvalid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for signal stability when corresponding valid signal is high

AWMMUVALID should be stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_awmmuvalid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUVALID is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_awmmuflow_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for signal stability when corresponding valid signal is high

AWMMUFLOW should be stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_awmmuflow_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.3 Untranslated transaction signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUFLOW is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_bresp_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.3 Response to a WriteDeferrable request

Monitor Check for a writedeferrable transaction that BRESP is not EXOKAY'b001 and RESERVED'b110!

Checks that BRESP has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_wstrb_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that all bits of WSTRB must be set within the 64-byte container!

Checks that WSTRB has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

no_outstanding_writedeferrable_transaction_with_same_id

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Checks that there are no outstanding Writedeferrable transactions with ID values that are used by Writedeferrable transactions or Non-Writedeferrable transactions on either of write channels!

Check that there is no outstanding Writedeferrable transactions with ID values that are used by Writedeferrable or Non-Writedeferrable transactions on either of the write channels.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awidunq_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWIDUNQ must be asserted!

Checks that AWIDUNQ has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awtagop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWTAGOP is set to 'Invalid' type!

Checks that AWTAGOP has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awatop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWATOP is Non-atomic transaction!

Checks that AWATOP has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awlock_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWLOCK is Normal!

Checks that AWLOCK has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awburst_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWBURST is INCR!

Checks that AWBURST has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awaddr_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWADDR is aligned to 64-bytes!

Checks that AWADDR has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awlen_awsize_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWLEN and AWSIZE has following combinations:1 x 64B,2 x 32B, 4 x 16B,8 x 8B,16 x 4B

Checks that AWLEN and AWSIZE has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awcache_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWCACHE is set to 'Device or Normal Non-cacheable'!

Checks that AWCACHE has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awdomain_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWDOMAIN is set to 'System Shareable' i.e. 'b11 !

Checks that AWDOMAIN has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

WriteDeferrable Transaction

writedef_valid_awsnoop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.2.2 WriteDeferrable signaling

Monitor Check for a writedeferrable transaction that AWSNOOP is 'b10000!

Checks that AWSNOOP has a valid value when WriteDeferrable feature in AXI5/ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

axmmussid_valid_with_value_with_axmmussidv_signals_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.3 SubstreamID SSID

Monitor Check that when AxVALID is asserted and AxMMUSSIDV is deasserted, the AxMMUSSID must be all zeros

Checks the value of AxMMUSSID when AxMMUSSIDV deasserted.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

armmusecsid_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.1 Secure Stream Identifier SECSID

Monitor checks that the value of ARMMUSECSID is a valid value

Checks that the value of ARMMUSECSID is a valid value

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

awmmusecsid_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.1 Secure Stream Identifier SECSID

Monitor checks that the value of AWMMUSECSID is a valid value

Checks that the value of AWMMUSECSID is a valid value

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

armmusecsid_valid_with_arnse_arport_signals_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.1 Secure Stream Identifier SECSID

Monitor checks that the value of ARMMUSECSID is compatibles with ARNSE/ARPROT signals

Checks that the value of ARMMUSECSID is compatibles with ARNSE/ARPROT signals.
When ARMMUSECSID indicates Non-secure, AWNSE/AWPROT must indicate Non-secure.
When ARMMUSECSID indicates Secure, ARNSE/ARPROT must indicate Non-secure or Secure.
When ARMMUSECSID indicates Realm, ARNSE/ARPROT must indicate Non-secure or Realm.

ERROR

AXI5,ACE5_Lite

Untranslated Transactions

awmmusecsid_valid_with_awnse_awport_signals_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.4.1 Secure Stream Identifier SECSID

Monitor checks that the value of AWMMUSECSID is compatibles with AWNSE/AWPROT signals

Checks that the value of AWMMUSECSID is compatibles with AWNSE/AWPROT signals.
When AWMMUSECSID indicates Non-secure, AWNSE/AxPROT must indicate Non-secure.
When AWMMUSECSID indicates Secure, AWNSE/AxPROT must indicate Non-secure or Secure.
When AWMMUSECSID indicates Realm, AWNSE/AxPROT must indicate Non-secure or Realm.

ERROR

AXI5,ACE5_Lite

Parity: Signal Stability

signal_stable_armmussidchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUSSIDCHK is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Stability

signal_stable_armmusidchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUSIDCHK is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Stability

signal_stable_armmuchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUCHK is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Validity

signal_valid_armmussidchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUSSIDCHK is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Validity

signal_valid_armmusidchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUSIDCHK is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Validity

signal_valid_armmuchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUCHK is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Stability

signal_stable_awmmussidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUSSIDCHK is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Stability

signal_stable_awmmusidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUSIDCHK is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Stability

signal_stable_awmmuchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUCHK is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Validity

signal_valid_awmmussidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUSSIDCHK is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Validity

signal_valid_awmmusidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUSIDCHK is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite

Parity: Signal Validity

signal_valid_awmmuchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUCHK is not X or Z when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Stash Translation

stashtranslation_valid_awbar_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.9.7 StashTranslation

Monitor Check for a stashtranslation transaction that AWBAR[0] is Zero!

Checks that AWBAR has a valid value for Stashtranslation transaction.

ERROR

ACE5_Lite,ACE5_LiteDVM

Stash Translation

stashtranslation_valid_awlock_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.9.7 StashTranslation

Monitor Check for a stashtranslation transaction that AWLOCK is Normal!

Checks that AWLOCK has a valid value for Stashtranslation transaction.

ERROR

ACE5_Lite,ACE5_LiteDVM

Stash Translation

no_oustanding_non_stashtrnslation_transaction_with_same_id

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.9.7 StashTranslation

Monitor Checks that there are no outstanding Nonstashtranslation transaction with ID values that are used by Stashtranslation transaction!

Check that there is no outstanding Non transaction with ID values that are used by Stashtranslation transaction

ERROR

ACE5_Lite,ACE5_LiteDVM

Write Zero

writezero_valid_bresp_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.1 WriteZero Transaction

Monitor Check for a Writezero transaction that BRESP is not EXOKAY

Checks that BRESP(response on B channel) has a valid value when WriteZero feature is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Write Zero

no_outstanding_writezero_transaction_with_same_id

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.1 WriteZero Transaction

Monitor Check that there are no outstanding Writezero and write transactions with same ID values at a time

Checks that there are no outstanding write transactions with same AWID values when the WriteZero feature is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Write Zero

writezero_valid_awidunq_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.1 WriteZero Transaction

Monitor Check for a Writezero transaction that AWIDUNQ must be asserted if present

Checks that AWIDUNQ has a valid value when WriteZero feature is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Write Zero

writezero_valid_awtagop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.1 WriteZero Transaction

Monitor Check for a Writezero transaction that AWTAGOP is Invalid!

Checks that AWTAGOP has a valid value when WriteZero feature is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Write Zero

writezero_valid_awlock_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.1 WriteZero Transaction

Monitor Check for a Writezero transaction that AWLOCK is Normal!

Checks that AWLOCK has a valid value when WriteZero feature is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Write Zero

writezero_valid_awdomain_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.1 WriteZero Transaction

Monitor Check for a Writezero transaction that AWDOMAIN is not INNERSHAREABLE'

Checks that AWDOMAIN has a valid value when WriteZero feature is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Write Zero

writezero_valid_awsnoop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A12.1 WriteZero Transaction

Monitor Check for a Writezero transaction that AWSNOOP is 'b0111!

Checks that AWSNOOP has a valid value when WriteZero feature is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

prefetch_valid_rresp_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Checks that a PREFETCHED response is not sent for an exclusive read

Checks that a PREFETCHED response is not sent for an exclusive read.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

prefetch_valid_bresp_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Check for a Prefetch transaction that BRESP is not EXOKAY

Checks that BRESP has a valid value when Prefetch feature in ACE5_LITE is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

no_outstanding_prefetch_and_write_transaction_with_same_id

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Check that there are no outstanding Prefetch and write transactions with same ID values at a time

Check that there are no outstanding Prefetch and write transactions with same ID values at a time.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

prefetch_valid_awidunq_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Check for a Prefetch transaction that AWIDUNQ must be asserted if present

Checks that AWIDUNQ has a valid value when Prefetch feature in ACE5_LITE is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

prefetch_valid_awlock_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Check for a Prefetch transaction that AWLOCK is Normal!

Checks that AWLOCK has a valid value when WriteDeferrable feature in ACE5_LITE is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

prefetch_valid_awcache_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Check for a Prefetch transaction that AWCACHE is set to 'Normal

Checks that AWCACHE has a valid value when Prefetch feature in ACE5_LITE is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

prefetch_valid_awdomain_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Check for a Prefetch transaction that AWDOMAIN is set to 'NONSHAREABLE, INNERSHAREABLE or OUTERSHAREABLE'

Checks that AWDOMAIN has a valid value when Prefetch feature in ACE5_LITE is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Prefetch

prefetch_valid_awsnoop_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.6 Prefetch transaction

Monitor Check for a Prefetch transaction that AWSNOOP is 'b1111!

Checks that AWSNOOP has a valid value when Prefetch feature in ACE5_LITE is enabled.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awburst_wrap_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that for a WRAP burst for WriteUniqueptlstash transaction, AWSIZE x AWLEN must not exceed the cache line size!

Check that for a WRAP burst for WriteUniqueptlstash transaction, AWSIZE x AWLEN must not exceed the cache line size!

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awburst_incr_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that for an INCR burst for WriteUniqueptlstash transaction, the last byte in the burst added to the AWSIZE aligned start address, must be within the same cache line as the first byte in the burst!

Check that for an INCR burst for WriteUniqueptlstash transaction, the last byte in the burst added to the AWSIZE aligned start address, must be within the same cache line as the first byte in the burst!

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

valid_awsnoop_arsnoop_and_awcmo_values_based_on_cfg_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.5 CMOs on the write channels

Check that awsnoop and awcmo signal has value values based on configuration

Check that awsnoop and awcmo takes valid values based on configuration.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

pcmo_transactions_valid_bresp_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.8.4 PCMOs on write channels

Check that bresp can be OKAY, SLVERR or DECERR for persist CMO transactions on write channel

Check that bresp can be OKAY, SLVERR or DECERR for persist CMO transactions on write channel.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

bcomp_response_recieved_if_signal_present_on_interface_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.8.4 PCMOs on write channels

Check that bcomp response is recieved for write transactions if bcomp signal is present on the interface

Check that bcomp response has been recieved by the write transaction if the bcomp signal is present on the interface

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

all_responses_recieved_for_write_with_cmo_or_cmo_on_write_transaction_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.8.4 PCMOs on write channels

Check that all valid responses have been recieved for cmo_on_write transactions and write_with_cmo transactions

Check that all valid responses have been recieved for cmo transaction on write channel or for write with cmo transaction

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

writeptlcmo_awburst_wrap_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.6.1 Attributes for write with CMO

Monitor Check that for a WRAP burst for WritePTLCMO transaction, AWSIZE x AWLEN must not exceed the cache line size!

Check that for a WRAP burst for WritePTLCMO transaction, AWSIZE x AWLEN must not exceed the cache line size!

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

writeptlcmo_awburst_incr_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.6.1 Attributes for write with CMO

Monitor Check that for an INCR burst for WritePtlCMO transaction, the last byte in the burst added to the AWSIZE aligned start address, must be within the same cache line as the first byte in the burst!

Check that for an INCR burst for WritePtlCMO transaction, the last byte in the burst added to the AWSIZE aligned start address, must be within the same cache line as the first byte in the burst!

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

stash_signals_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signalling

Monitor Check that cache stashing signals such as awstashnid should be zero if awstashnid_en is zero, awstashlpid should be zero if awstashlpid_en must be zero

Checks that cache stashing signals such as awstashnid should be zero if awstashnid_en is 0 and
awstashlpid should be zero if awstashlpid_en is 0.

ERROR

ACE5_Lite,ACE5_LiteDVM

Stash Translation

stash_signals_valid_value_for_non_stash_xacts_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A14.7 StashTranslation Opcode

Monitor Check that for Non cache stashing transactions cache stashing signals such as awstashnid, awstashnid_en , awstashlpid and awstashlpid_en must be zero

Checks that cache stashing signals such as awstashnid,awstashnid_en,awstashlpid,awstashlpid_en
must be zero for all transactions except WriteUniqueFullStash,WriteUniquePtlStash,StashOnceShared and
StashOnceUnique.

ERROR

ACE5_Lite,ACE5_LiteDVM

Atomic Transactions

atomic_transaction_awsnoop_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section: A7.4.5 Request attribute restrictions for Atomic transactions

Monitor Check that for a atomic transaction AWSNOOP is all zeros!

Checks for ATOMIC transactions, AWSNOOP must be set to all zeros

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

writeuniquefullstash_wstrb_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that writeuniquefullstash transactions are required to have every write data strobe asserted, that is, sparse write data strobes are not permitted

Monitor check that all byte strobes are asserted for a writeuniquefullstash transaction

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awlock_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section E9.7.2 Stash transaction signaling

Monitor Check that AWLOCK is valid for writeuniqueptlstash Transactions!

Checks if the AWLOCK is valid for writeuniqueptlstash Transactions

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awcache_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that AWCACHE is valid for writeuniqueptlstash Transactions!

Checks if the AWCACHE is valid for writeuniqueptlstash Transactions

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that AWBURST is valid for writeuniqueptlstash Transactions!

Checks if the AWBURST is valid for writeuniqueptlstash Transactions

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

writeuniqueptlstash_awdomain_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.2 Stash transaction signaling

Monitor Check that AWDOMAIN is valid for WriteUniqueptlstash Transactions!

Checks if the AWDOMAIN is valid for WriteUniquePtlstash Transactions

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance: Signal Stability

signal_valid_awcmo_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.5 CMOs on the write channels

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCMO is not X or Z when AWVALID is high

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing

no_oustanding_non_stashonce_transaction_with_same_id

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.5 Transaction ID for stash transactions

Monitor Checks that there are no outstanding Nonstashonce transaction with ID values that are used by Stashonce transaction!

Check that there is no outstanding Non Stashonce transaction with ID values that are used by StashOnce transactions.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Stability

signal_stable_awstashlpiden_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSTASHLPIDEN is stable when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Stability

signal_stable_awstashlpid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSTASHLPID is stable when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Stability

signal_stable_awstashniden_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSTASHNIDEN is stable when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Stability

signal_stable_awstashnid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSTASHNID is stable when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Validity

signal_valid_stash_lpid_valid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that stash_lpid_valid is not X or Z when AWVALID is high

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Validity

signal_valid_stash_nid_valid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that stash_nid_valid is not X or Z when AWVALID is high

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Validity

signal_valid_stash_lpid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that stash_lpid is not X or Z when AWVALID is high

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Stashing: Signal Validity

signal_valid_stash_nid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A9.7.4 Stash target identifiers

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that stash_nid is not X or Z when AWVALID is high

ERROR

ACE5_Lite,ACE5_LiteDVM

Cache Maintenance: Signal Stability

signal_stable_awcmo_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.5 CMOs on the write channels

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCMO is stable when AWVALID is high

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_arctlchk2_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARCTLCHK2 is stable when ARVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arctlchk2_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARCTLCHK2 is not X or Z when ARVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awstashlpidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSTASHLPIDCHK is stable when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awstashnidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSTASHNIDCHK is stable when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awctlchk2_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCTLCHK2 is stable when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awstashlpidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWSTASHLPIDCHK is not X or Z when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awstashnidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWSTASHNIDCHK is not X or Z when AWVALID is high.

ERROR

ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awctlchk2_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWCTLCHK2 is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

mte_transaction_size_validity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.4 Transporting tags

Monitor Check that the transaction size is valid for MTE transactions

This check checks the validity of the transaction size for MTE.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

mte_tag_op_fetch_transaction_validity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.5 Reads with tags

Monitor Checks that transactions using Fetch must be cache line sized and Regular

Checks that Transactions using Fetch must be cache line sized and Regular.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

mte_valid_tag_op_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.6 Writes with tags, A13.2.5 Reads with tags

Monitor Check that the TAG_OP is valid for MTE enabled transactions

This check performs the validity of the tag_op for transactions based on the mte_support_type

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

valid_wtagupdate_in_write_data_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.6 Writes with tags

Monitor Check that the WTAGUPDATE is valid for MTE enabled transactions

WTAGUPDTAE is valid. WTAGUPDTAE bits outside the transaction container must be deasserted. For INVALID/TRANSFER/MATCH tag operation WTAGUPDTAE must be deasserted

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

valid_wtag_in_write_data_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.6 Writes with tags

Monitor Check that the WTAG is valid for MTE enabled transactions

WTAG is valid. WTAG bits outside the transaction container must be deasserted. For INVALID tag operation WTAG must be deasserted

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

valid_rtag_in_read_data_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.5 Reads with tags

Monitor Check that the RTAG is valid for MTE enabled transactions

RTAG is valid. RTAG bits outside the transaction container must be deasserted. For INVALID tag operation RTAG must be deasserted

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

tag_match_response_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.6 Writes with tags

Monitor Checks that for Tag MATCH request when completion and tagmatch response are sent separately, BTAGMATCH must be 0b01Match result in separate response for Completion response. BTAGMATCH must be 0b11Pass or 0b10Fail for Match response or Combined response

Checks that Tag MATCH response should be 0b01(Match result in separate response) for Completion Response, and 0b11(Pass) or 0b10(Fail) for Match or Combined Response

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

atomic_compare_swap_tag_match_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.8 MTE and Atomic transactions

Monitor Check that for AtomicCompare Transaction of 32 bytes ,same tag value must be associated with the compare and swap bytes.

Checks that AtomicCompare Transaction of 32 byte must have same tag value associated with the compare and swap bytes.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

mte_valid_unique_id_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.4 Transporting tags

Monitor Check that the AxIDUNQ is valid for MTE enabled transactions

Checks that AxIDUNQ has a valid value when MTE feature in ACE5_LITE is enabled.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

mte_valid_cache_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.4 Transporting tags

Monitor Check that the cache_type is valid for MTE enabled transactions

The transaction must be to Normal Write-Back memory for MTE enabled transactions. AxCACHE[3:2] is not 0b00 and AxCACHE[1:0] is 0b11.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

mte_valid_burst_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.4 Transporting tags

Monitor Check that the burst type is valid for MTE enabled transactions

BURST type must be INCR or WRAP, not FIXED for MTE enabled transactions.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE

no_outstanding_mte_enabled_transaction_with_same_id

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.4 Transporting tags: Section E1.15 Memory tagging

Monitor Check that there are no outstanding MTE and read/write transactions with same ID values at a time

A read with tag Transfer or Fetch can only be issued if there are no outstanding read transactions using the same ARID value.
A master must not issue a request on the read channel with the same ARID as an outstanding read with tag Transfer or Fetch.
A write with tag Transfer, Update or Match can only be issued if there are no outstanding write transactions using the same AWID value.
A master must not issue a request on the write channel with the same AWID as an outstanding write with tag Transfer, Update, or Match.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Stability

signal_stable_btagmatch_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that BTAGMATCH is stable when BVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Validity

signal_valid_btagmatch_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BTAGMATCH is not X or Z when BVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Stability

signal_stable_rtag_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that RTAG is stable when RVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Validity

signal_valid_rtag_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RTAG is not X or Z when RVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Stability

signal_stable_artagop_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARTAGOP is stable when ARVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Validity

signal_valid_artagop_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARTAGOP is not X or Z when ARVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Stability

signal_stable_wtagupdate_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that WTAGUPDATE is stable when WVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Validity

signal_valid_wtagupdate_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WTAGUPDATE is not X or Z when WVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Stability

signal_stable_wtag_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that WTAG is stable when WVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Validity

signal_valid_wtag_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WTAG is not X or Z when WVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Stability

signal_stable_awtagop_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWTAGOP is stable when AWVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

MTE: Signal Validity

signal_valid_awtagop_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A13.2.2 MTE signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWTAGOP is not X or Z when AWVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Atomic Transactions

atomic_transaction_valid_wstrb_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A7.4.3 Atomic transactions attributes

Monitor Check for an Atomic transaction that all bits of WSTRB must be set within the data window!

Checks that WSTRB has a valid value when Atomic transactions are enabled in AXI5/ACE5_LITE.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Atomic Transactions

no_outstanding_atomic_transaction_with_same_id

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A7.4.4 ID use for Atomic transactions

Monitor Checks that there are no outstanding Atomic transactions with ID values that are used by Atomic transactions or Non-atomic transactions on either the AR or AW channels.

Check that there is no outstanding Atomic transactions with ID values that are used by Atomic transactions or Non-atomic transactions on either the AR or AW channels.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

no_outstanding_read_chunk_with_same_arid

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that ARCHUNKEN is asserted only if there are no outstanding read transactions using the same ARID value and Manager doesn't issue a request on the read channel with the same ARID as an outstanding request that had ARCHUNKEN asserted

Check that there is no outstanding transaction with same arid when read data chunking feature is enabled and archunken. Manager should not initiate another outstanding transaction with same ID when ARCHUNKEN is set to 1. ARCHUNKEN only be asserted if there is no outstanding txn with same ARID.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_arsize_lt_data_width_rchunkstrb_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when RVALID and RCHUNKV are asserted, higher bits of rchunstrb must be 0s for burst_size < data_width

Checks that when ARSIZE is smaller than DATA_WIDTH, the response would only have partial RCHUNKSTRB asserted

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_unalign_addr_rchunkstrb_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when RVALID and RCHUNKV are asserted, lower bits of rchunstrb must be 0s for data_width unalign address

Checks that for unaligned burst where ARADDR is not aligned to DATA_WIDTH, the lower order bits of RCHUNKSTRB (depends on ARADDR) must not be asserted

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_data_unique_entry_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when RVALID and RCHUNKV are asserted, each read data chunk entry must be unique

Checks that the same chunk data should not be sent twice

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_num_bytes_transfer_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that number of bytes that are transferred through read data chunking must be consistant with ARSIZE and ARLEN

Checks that the number of bytes that are transferred through read data chunking must be consistant with ARSIZE and ARLEN

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_rchunkstrb_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when RVALID and RCHUNKV are asserted, RCHUNKSTRB must not be zero

Checks that RCHUNKSTRB must not be zero when RVALID and RCHUNKV are high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_rchunknum_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when RVALID and RCHUNKV are asserted, RCHUNKNUM must be between zero and ARLEN

Checks that RCHUNKNUM must be between zero and ARLEN when RVALID and RCHUNKV are high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_rchunkv_same_for_all_response_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that RCHUNKV must be same for every response beat of transaction

Checks that RCHUNKV must be the same for every response beat of a transaction

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_rchunkv_zero_when_archunken_deasserted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is deasserted, RCHUNKV must be deasserted for all response beats of the transaction

Checks that RCHUNKV is deasserted for all the transfers when ARCHUNKEN is deasserted

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_valid_xact_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is asserted, if present on the interface, xact type can only be READ or COHERENT

checks that when archunken is asserted xact_type is either READ or COHERENT.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_aridunq_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is asserted, if present on the interface, ARIDUNQ must be asserted

Checks that ARIDUNQ must be asserted for rdata chunking

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_arsnoop_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is asserted, ARSNOOP must be ReadNoSnoop, ReadOnce, ReadOnceCleanInvalid or ReadOnceMakeInvalid

Checks that ARSNOOP is ReadNoSnoop, ReadOnce, ReadOnceCleanInvalid or ReadOnceMakeInvalid for rdata chunking

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_arsize_same_as_bus_width_or_arlen_one_beat_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is asserted, ARSIZE must be same as BUS_WIDTH or ARLEN must be 1

Checks that ARSIZE is same as BUS_WIDTH or ARLEN is 1 for rdata chunking

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_arburst_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is asserted, ARBURST must be INCR or WRAP

Checks that ARBURST is INCR or WRAP for rdata chunking

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_araddr_aligned_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is asserted, ARADDR must be aligned to 16 bytes

Checks that ARADDR is aligned to 16 bytes for rdata chunking

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking

rdata_chunking_arsize_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.2 Read data chunking protocol rules

Monitor Check that when ARCHUNKEN is asserted, ARSIZE must be equal to the data bus width or ARLEN is one beat and ARSIZE must be 128 bits or larger

Checks that ARSIZE is equal to the data bus width or ARLEN is one beat and ARSIZE is 128 bits or larger for rdata chunking

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Stability

signal_stable_rchunkstrb_when_rvalid_rchunkv_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that RCHUNKSTRB is stable when RVALID and RCHUNKV are high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Stability

signal_stable_rchunknum_when_rvalid_rchunkv_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that RCHUNKNUM is stable when RVALID and RCHUNKV are high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Stability

signal_stable_rchunkv_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that RCHUNKV is stable when RVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Stability

signal_stable_archunken_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARCHUNKEN is stable when ARVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Validity

signal_valid_rchunkstrb_when_rvalid_rchunkv_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RCHUNKSTRB is not X or Z when RVALID and RCHUNKV are high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Validity

signal_valid_rchunknum_when_rvalid_rchunkv_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RCHUNKNUM is not X or Z when RVALID and RCHUNKV are high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Validity

signal_valid_rchunkv_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RCHUNKV is not X or Z when RVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Read Data Chunking: Signal Validity

signal_valid_archunken_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.2.1 Read data chunking signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARCHUNKEN is not X or Z when ARVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Atomic Transactions

atomic_transaction_awlock_type_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A7.4.5 Request attribute restrictions for Atomic transactions

Monitor Check that for a atomic transaction AWLOCK is Normal Access 'b0!

Checks for ATOMIC transactions, AWLOCK must be 0b0, Normal access

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

RME: Signal Stability

signal_stable_arnse_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.5 Memory protection and the Realm Management Extension

Monitor check for signal stability when corresponding valid signal is high

Checks that ARNSE is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

RME: Signal Validity

signal_valid_arnse_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.5 Memory protection and the Realm Management Extension

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARNSE is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

RME: Signal Stability

signal_stable_awnse_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.5 Memory protection and the Realm Management Extension

Monitor check for signal stability when corresponding valid signal is high

Checks that AWNSE is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

RME: Signal Validity

signal_valid_awnse_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.5 Memory protection and the Realm Management Extension

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWNSE is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Atomic Transactions: Signal Validity

signal_valid_awatop_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A7.4.6 Atomic transaction signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that awatop is not X or Z when AWVALID is high

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance: Signal Stability

signal_stable_bpersist_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.8.4 PCMOs on write channels

Monitor check for signal stability when corresponding valid signal is high

BPERSIST should be stable when BVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance: Signal Stability

signal_stable_bcomp_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.8.4 PCMOs on write channels

Monitor check for signal stability when corresponding valid signal is high

BCOMP should be stable when BVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance: Signal Validity

signal_valid_bpersist_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.8.4 PCMOs on write channels

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BPERSIST is not X or Z when BVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance: Signal Validity, MTE

signal_valid_bcomp_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A10.8.4 PCMOs on write channels, A13.2 MTE signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BCOMP is not X or Z when BVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_bloopchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that BLOOPCHK is stable when BVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_bloopchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BLOOPCHK is not X or Z when BVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rtagchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RATGCHK is stable when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rchunkchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RCHUNKCHK is stable when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rloopchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RLOOPCHK is stable when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rlastchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RLASTCHK is stable when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rtagchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RTAGCHK is not X or Z when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rchunkchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RCHUNKCHK is not X or Z when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rloopchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RLOOPCHK is not X or Z when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rlastchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RLASTCHK is not X or Z when RVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_stable_wtagchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WTAGCHK is stable when WVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_wlastchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WLASTCHK is stable when WVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wtagchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WTAGCHK is not X or Z when WVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wlastchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WLASTCHK is not X or Z when WVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_armpamchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMPAMCHK is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_arloopchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARLOOPCHK is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_arnsaidchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARNSAIDCHK is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_arctlchk3_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARCTLCHK3 is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_arctlchk1_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARCTLCHK1 is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_arlenchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARLENCHK is stable when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_armpamchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMPAMCHK is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arloopchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARLOOPCHK is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arnsaidchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARNSAIDCHK is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arctlchk3_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARCTLCHK3 is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arctlchk1_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARCTLCHK1 is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arlenchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARLENCHK is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awmpamchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMPAMCHK is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awloopchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWLOOPCHK is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awnsaidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWNSAIDCHK is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awctlchk3_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCTLCHK3 is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awctlchk1_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCTLCHK1 is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awlenchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWLENCHK is stable when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awmpamchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMPAMCHK is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awloopchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWLOOPCHK is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awnsaidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWNSAIDCHK is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awctlchk3_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWCTLCHK3 is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awctlchk1_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWCTLCHK1 is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awlenchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWLENCHK is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator

bidunq_validity_with_awidunq_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor checks if AWIDUNQ is asserted or deasserted for a request the corresponding BIDUNQ should be asserted or deasserted for all response beat for that transaction

Check that if AWIDUNQ is asserted for a request, the corresponding BIDUNQ signals is asserted for all response beats for that transaction and if AWIDUNQ is deasserted for a request, the corresponding BIDUNQ signals is deasserted for all response beats for that transaction.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator

ridunq_validity_with_aridunq_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor checks if ARIDUNQ is asserted or deasserted for a request the corresponding RIDUNQ should be asserted or deasserted for all response beat for that transaction

Check that if ARIDUNQ is asserted for a request, the corresponding RIDUNQ signals is asserted for all response beats for that transaction and if ARIDUNQ is deasserted for a request, the corresponding RIDUNQ signals is deasserted for all response beats for that transaction.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator

no_outstanding_write_unique_transaction_with_same_awid

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor checks that master must not assert unique_id when there is a write request or ongoing write outstanding transaction with same AWID

Check that there is no outstanding transaction with same arid when unique id feature is enabled and AWIDUNQ is asserted. Manager should not initiate another outstanding transaction with same ID when AWIDUNQ is set to 1. AWIDUNQ only be asserted if there is no outstanding txn with same ARID.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator

no_outstanding_read_unique_transaction_with_same_arid

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor checks that master must not assert unique_id when there is a read request or ongoing read outstanding transaction with same ARID

Check that there is no outstanding transaction with same arid when unique id feature is enabled and ARIDUNQ is asserted. Manager should not initiate another outstanding transaction with same ID when ARIDUNQ is set to 1. ARIDUNQ only be asserted if there is no outstanding txn with same ARID.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Wake-up Signaling

awakeup_valid_with_awvalid_arvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A16.2 AWAKEUP rules and recommendations
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.7 Wake-up Signaling

Monitor Check that if AWAKEUP is asserted in a cycle when AWVALID/ARVALID is asserted and AWREADY/ARREADY is deasserted, then AWAKEUP must remain asserted until AWREADY/ARREADY is asserted.

Checks that deassertion of the AWAKEUP signal guarantee progress of the AWVALID/ARVALID signaling

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Wake-up Signaling

awakeup_valid_with_sysco_signals_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A16.2.1 AWAKEUP and Coherency Connection signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.7 Wake-up Signaling

Monitor Check that when AWAKEUP signal is asserted to guarantee progress of a transition on the Coherency Connection signaling

Checks that assertion and deassertion of the AWAKEUP signal guarantee progress of a transition on the Coherency Connection signaling

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals

trace_tag_validity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor Check that if valid loopback trace_tag is generated for data and response channel when

Trace tag value on data channel or resposne channel should be valid as per the trace tag value on the address channel.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals

loopback_trace_tag_validity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor Check that if trace_tag value on data channel or resposne channel directly mapped to the associated request when svt_axi_port_configuration::loopback_trace_tag_enable is enabled

Trace_tag value on data channel or resposne channel should be directly mapped to the associated request.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Stability

signal_stable_bidunq_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for signal stability when corresponding valid signal is high

Checks that BIDUNQ is stable when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_btrace_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that BTRACE is stable when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Validity

signal_valid_bidunq_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BIDUNQ is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_btrace_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BTRACE is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Stability

signal_stable_wpoison_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for signal stability when corresponding valid signal is high

Checks that WPOISON is stable when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_wtrace_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WTRACE is stable when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_wtrace_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WTRACE is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Validity

signal_valid_wpoison_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WPOISON is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Stability

signal_stable_awidunq_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for signal stability when corresponding valid signal is high

Checks that AWIDUNQ is stable when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_awtrace_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWTRACE is stable when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Validity

signal_valid_awidunq_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWIDUNQ is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_awtrace_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWTRACE is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Stability

signal_stable_ridunq_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for signal stability when corresponding valid signal is high

Checks that RIDUNQ is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Stability

signal_stable_rpoison_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for signal stability when corresponding valid signal is high

Checks that RPOISON is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_rtrace_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RTRACE is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Validity

signal_valid_ridunq_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RIDUNQ is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_rtrace_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RTRACE is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Poison: Signal Validity

signal_valid_rpoison_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A17.1 Data protection using Poison
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E2.1 Poison

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RPOISON is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Stability

signal_stable_aridunq_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for signal stability when corresponding valid signal is high

Checks that ARIDUNQ is stable when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Stability

signal_stable_artrace_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARTRACE is stable when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Unique ID Indicator: Signal Validity

signal_valid_aridunq_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A6.2 Unique ID indicator
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.13 Unique ID indicator

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARIDUNQ is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Trace Signals: Signal Validity

signal_valid_artrace_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.3 Trace signals
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARTRACE is not X or Z when ARVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Wake-up Signaling

acwakeup_valid_with_acvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A16.3 ACWAKEUP rules and recommendations
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.7 Wake-up Signaling

Monitor Check that ACWAKEUP must remain asserted until the associated ACVALID / ACREADY handshake to ensure progress of the snoop transaction.

Checks that deassertion of the ACWAKEUP signal guarantee progress of the ACVALID signaling

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

sysco_interface_read_chan_dvm_traffic_validity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.6.1 Coherency Connection Handshake
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.8.3 Coherency Connection signaling and DVM messages

Monitor Check that a DVM messge except DVM complete must not be observed when syscoreq is de-asserted

A master must not issue any DVM messages, except DVM Complete, on its AR channel after it has deasserted syscoreq.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

sysco_interface_coherency_disconnect_state_traffic_validity_check

Monitor Check that All coherent transactions that can be cached must be completed before entering COHERENCY_DISCONNECT_STATE.

All coherent transactions that can be cached must be completed before entering COHERENCY_DISCONNECT_STATE.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

sysco_interface_coherency_enabled_state_traffic_validity_check

Monitor Check that a transaction that permits Master to cache a coherent location should be issued only in the coherency_enabled state.

A transaction that permits it to cache a coherent location should be issued only in the coherency_enabled state.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

signal_valid_syscoreq_check_during_reset

Monitor Check that syscoreq must be de-asserted During Reset!

Checks that syscoreq must be de-asserted during Reset.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

sysco_interface_snoop_chan_dvm_traffic_validity_check

Check that a DVM messge must not be issued by Interconnect after syscoack is de-asserted

An Interconnect must not issue any DVM messages on its AC channel after it has deasserted syscoack.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

sysco_interface_snoop_traffic_validity_check

Check that Interconnect can send snoops only in COHERENCY_CONNECT and COHERENCY_ENABLED state.

Interconnect must not issue Snoop transactions in COHERENCY_DISABLED state.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

sysco_interface_coherency_disabled_state_traffic_validity_check

Check that during COHERENCY_DISABLED_STATE there should not be any outstanding snoop transactions.

During COHERENCY_DISABLED_STATE there should not be any outstanding snoop transactions.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

sysco_interface_illegal_state_transition

Check that Transition of SYSCO Interface state must be valid

Illegal transition of the Coherency Connection Signaling SYSCO Interface State.
This check monitors the syscoreq and syscoack signals and detects illegal state transitions.

ERROR

ACE5,ACE5_LiteDVM

Coherency Connection

signal_valid_syscoack_check_during_reset

Check that syscoack must be de-asserted During Reset!

Checks that syscoack must be de-asserted during Reset.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_crrespchk_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CRRESPCHK is stable when CRVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_crtracechk_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CRTRACECHK is stable when CRVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_crrespchk_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRRESPCHK is not X or Z when CRVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_crtracechk_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRTRACECHK is not X or Z when CRVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_actracechk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ACTRACECHK is stable when ACVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_acvmidextchk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ACVMIDEXTCHK is stable when ACVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_acctlchk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ACCTLCHK is stable when ACVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_acaddrchk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ACADDRCHK is stable when ACVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_actracechk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACTRACECHK is not X or Z when ACVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_acvmidextchk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACVMIDEXTCHK is not X or Z when ACVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_acctlchk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACCTLCHK is not X or Z when ACVALID is high.

ERROR

ACE5,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_acaddrchk_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACADDRCHK is not X or Z when ACVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling

rloop_valid_value_for_atomic_xacts_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor Check that when RVALID is asserted, RLOOP must be equal to the AWLOOP for atomic transactions

Checks the value of rloop matches with the value of awloop seen in the corresponding atomic transaction

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling

rloop_valid_value_for_read_xacts_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor Check that when RVALID is asserted, RLOOP must be equal to the ARLOOP for read transactions

Checks the value of rloop matches with the value of arloop seen in the corresponding read transaction

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling

bloop_valid_value_for_write_xacts_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor Check that when BVALID is asserted, BLOOP must be equal to the AWLOOP for write transactions

Checks the value of bloop matches with the value of awloop seen in the corresponding write transaction

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Non-secure Access: Signal Stability

signal_stable_awnsaid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A11.1.1 NSAID signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.10.1 NSAID signaling

Monitor check for signal stability when corresponding valid signal is high

AWNSAID should be stable when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Non-secure Access: Signal Stability

signal_stable_arnsaid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A11.1.1 NSAID signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.10.1 NSAID signaling

Monitor check for signal stability when corresponding valid signal is high

ARNSAID should be stable when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Non-secure Access: Signal Validity

signal_valid_awnsaid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A11.1.1 NSAID signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.10.1 NSAID signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWNSAID is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Non-secure Access: Signal Validity

signal_valid_arnsaid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A11.1.1 NSAID signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.10.1 NSAID signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARNSAID is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Stability

signal_stable_awloop_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWLOOP is stable when AWVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Stability

signal_stable_arloop_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARLOOP is stable when ARVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Validity

signal_valid_awloop_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWLOOP is not X or Z when AWVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Validity

signal_valid_arloop_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARLOOP is not X or Z when ARVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

MPAM: Signal Stability

signal_stable_awmpam_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.1.1 MPAM signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.14.2 MPAM component interactions

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMPAM is stable when AWVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

MPAM: Signal Stability

signal_stable_armpam_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.1.1 MPAM signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.14.2 MPAM component interactions

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMPAM is stable when ARVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

MPAM: Signal Validity

signal_valid_awmpam_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.1.1 MPAM signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.14.2 MPAM component interactions

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that awmpam is not X or Z when AWVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

MPAM: Signal Validity

signal_valid_armpam_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.1.1 MPAM signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.14.2 MPAM component interactions

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that armpam is not X or Z when ARVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Stability

signal_stable_bloop_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that BLOOP is stable when BVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Validity

signal_valid_bloop_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BLOOP is not X or Z when BVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Stability

signal_stable_rloop_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that RLOOP is stable when RVALID is high

ERROR

AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Loopback Signaling: Signal Validity

signal_valid_rloop_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.4 User Loopback signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.5 User Loopback signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RLOOP is not X or Z when RVALID is high

ERROR

ACE

Outstanding

no_outstanding_write_transaction_with_same_awid

Synopsys Defined

Monitor checks that master must not drive same AWID transaction when there is a write request or ongoing write outstanding transaction with same AWID

Checks that there is no outstanding transaction with same awid

ERROR

ACE

Outstanding

no_outstanding_read_transaction_with_same_arid

Synopsys Defined

Monitor checks that master must not drive same ARID transaction when there is a read request or ongoing read outstanding transaction with same ARID

Checks that there is no outstanding transaction with same arid

ERROR

ACE

Performance Metrics

perf_min_write_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of write transactions in a given interval is more than or equal to the configured min value

Checks that the bandwidth of write transactions in a given interval is not less that the configured min value

ERROR

ACE

Performance Metrics

perf_max_write_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of write transactions in a given interval is less than or equal to the configured max value

Checks that the bandwidth of write transactions in a given interval is not more that the configured max value

ERROR

ACE

Performance Metrics

perf_min_read_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of read transactions in a given interval is more than or equal to the configured min value

Checks that the bandwidth of read transactions in a given interval is not less that the configured min value

ERROR

ACE

Performance Metrics

perf_max_read_bandwidth_check

Synopsys Defined

Monitor Check that the bandwidth of read transactions in a given interval is less than or equal to the configured max value

Checks that the bandwidth of read transactions in a given interval is not more that the configured max value

ERROR

ACE

Performance Metrics

perf_min_write_throughput_check

Synopsys Defined

Monitor Check that the throughput of write transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of write transactions in a given interval is not less that the configured min value

ERROR

ACE

Performance Metrics

perf_max_write_throughput_check

Synopsys Defined

Monitor Check that the throughput of write transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of write transactions in a given interval is not more that the configured max value

ERROR

ACE

Performance Metrics

perf_min_read_throughput_check

Synopsys Defined

Monitor Check that the throughput of read transactions in a given interval is more than or equal to the configured min value

Checks that the throughput of read transactions in a given interval is not less that the configured min value

ERROR

ACE

Performance Metrics

perf_max_read_throughput_check

Synopsys Defined

Monitor Check that the throughput of read transactions in a given interval is less than or equal to the configured max value

Checks that the throughput of read transactions in a given interval is not more that the configured max value

ERROR

ACE

Performance Metrics

perf_avg_min_read_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of read transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of read transactions in a given interval is not less than the configured min value

ERROR

ACE

Performance Metrics

perf_avg_max_read_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of read transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of read transactions in a given interval is not more than the configured max value

ERROR

ACE

Performance Metrics

perf_min_read_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a read transaction is more than or equal to the configured min value

Checks that the latency of a read transaction is not lesser than the configured min value

ERROR

ACE

Performance Metrics

perf_max_read_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a read transaction is less than or equal to the configured max value

Checks that the latency of a read transaction is not greater than the configured max value

ERROR

ACE

Performance Metrics

perf_avg_min_write_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of write transactions in a given interval is more than or equal to the configured min value

Checks that the average latency of write transactions in a given interval is not less than the configured min value

ERROR

ACE

Performance Metrics

perf_avg_max_write_xact_latency_check

Synopsys Defined

Monitor Check that the average latency of write transactions in a given interval is less than or equal to the configured max value

Checks that the average latency of write transactions in a given interval is not more than the configured max value

ERROR

ACE

Performance Metrics

perf_min_write_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a write transaction is more than or equal to the configured min value

Checks that the latency of a write transaction is not lesser than the configured min value

ERROR

ACE

Performance Metrics

perf_max_write_xact_latency_check

Synopsys Defined

Monitor Check that the latency of a write transaction is less than or equal to the configured max value

Checks that the latency of a write transaction is not greater than the configured max value

ERROR

ACE

Non DVM Non Device

write_non_dvm_non_device_xact_id_overlap_check

Synopsys Defined

Monitor Check for the AWID overlap of Non-DVM or Non-device transactions with another active transaction

Checks the overlapping AWID of Non-DVM or Non-Device transactions with any active transactions

ERROR

ACE

Non DVM Non Device

read_non_dvm_non_device_xact_id_overlap_check

Synopsys Defined

Monitor Check for the ARID overlap of Non-DVM or Non-device transactions with another active transaction

Checks the overlapping ARID of Non-DVM or Non-Device transactions with any active transactions

ERROR

AXI3

Port Interleaving

port_interleaving_check

Synopsys Defined

Monitor checks that if interleaved port is expected port for the given transaction

Checks if address does fall to correct interleaved port.
Valid when port cfg port_interleaving_enable = 1.

ERROR

AXI3

Locked Accesses

locked_sequence_to_same_slave_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that only locked slave is used for all the transactions in the locked sequence

Checks that when a master does a lock transaction, it does not target subsequent transactions in the lock sequence to any slave other than the locked slave

WARNING

AXI3

Locked Accesses

locked_sequence_length_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that a locked sequence does not have more than two consecutive locked transactions at the same time

Check that the master follows as per the recommendation from spec to limit 2 transaction for the lock access

WARNING

AXI3

Locked Accesses

no_pending_locked_xacts_before_normal_xacts_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that there are no pending transactions of a locked sequence when a normal transaction is received

Checks that there are no pending transactions of a locked sequeunce when a normal transaction is received

ERROR

AXI3

Locked Accesses

locked_sequeunce_id_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that all transactions of a locked sequence have the same id

Checks that all transactions of locked sequence have the same id

ERROR

AXI3

Locked Accesses

no_pending_xacts_during_locked_xact_sequeunce_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A7.3 Locked accesses

Monitor Check that there are no pending transactions before a locked sequence starts

Checks that there are no pending transactions before a locked sequence starts

ERROR

AXI3

Write Data Ordering

write_data_interleave_order_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A5.2.2 Write data ordering

Monitor check that the order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions for Write Data Interleaving

Checks that the order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions for Write Data Interleaving transactions

ERROR

AXI3

Write Data Ordering

write_data_interleave_depth_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section A5.2.2 Write data ordering

Monitor check that received write data is not interleaved beyond write_data_interleave_depth value. An error is issued if write data is interleaved beyond this value for Write data interleaving

Checks that received write data is not interleaved beyond write_data_interleave_depth value

ERROR

AXI3

Signal Stability

signal_stable_wid_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that WID is stable when WVALID is high

ERROR

AXI3

Signal Validity

signal_valid_wid_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WID is not X or Z when WVALID is high

ERROR

ACE,ACE_Lite

Barrier Transactions

writebarrier_norm_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the AWID overlap of Write transactions with other active WriteBarrier transactions

Checks the overlapping AWID of Non-Barrier Non-DVM transactions with any active Barrier/DVM transactions

ERROR

ACE,ACE_Lite

Barrier Transactions

readbarrier_dvm_norm_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the ARID overlap of Read transactions with other active ReadBarrier/DVM transactions

Checks the overlapping ARID of Non-Barrier Non-DVM transactions with any active Barrier/DVM transactions

ERROR

ACE,ACE_Lite

Barrier Transactions

readbarrier_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the ARID overlap of ReadBarrier transactions with other active Non-Barrier transactions

Checks the overlapping ARID of Read Barrier transactions with any active Read transactions

ERROR

ACE,ACE_Lite

Barrier Transactions

writebarrier_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check for the AWID overlap of WriteBarrier transactions with other active Non-Barrier transactions

Checks the overlapping AWID of Write Barrier transactions with any active Write transactions

ERROR

ACE,ACE_Lite

DVM

dvm_message_arbar_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARBAR[0] is 'b0 Normal Access!

Checks for DVM ARBAR[0] is 1'b0

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_pair_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.1 About barrier transactions

Monitor Check that Barrier pairs must be issued in the same sequence on the read address and write address channels

Checks that barrier pairs must be issued in the same sequence on the read address and write address channels

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_pair_cntrl_signals_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.4.1 Manager requirements

Monitor Check that Both transactions in a barrier pair must have the same AxID, AxBAR, AxDOMAIN, and AxPROT values.

Checks that both transactions in a barrier pair must have the same AxID, AxBAR, AxDOMAIN, and AxPROT values

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_write_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Check that for barrier write transaction only BRESP = '00 response is permitted!

Checks the Write Barrier valid response

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_read_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Check that for barrier read transaction only RRESP ='00 response is permitted!

Checks the Read Barrier valid response

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_id_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Check that the range of ID for barrier transactions should be inside svt_axi_transaction::barrier_id_min and svt_axi_transaction::barrier_id_max!

Checks the Barrier Id valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions

read_barrier_arlock_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARLOCK is Normal Access 'b0!

Checks the combinations of ARLOCK and ARBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARSNOOP is all zeros !

Checks the combinations of ARSNOOP and ARBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arcache_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARCACHE is Normal non-cacheable'b0010 !

Checks the combinations of ARCACHE and ARBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arsize_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction ARSIZE matches the data bus width!

Checks the combinations of ARSIZE and ARBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that a barrier read transaction should be of length 1!

Checks the combinations of ARLEN and ARBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

read_barrier_arburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction the burst_type is INCR !

Checks the combinations ARBURST and ARBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions

read_barrier_araddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier read transaction the ARADDR should be all zeros!

Checks the ARADDR is valid for ARBAR

ERROR

ACE,ACE_Lite

Barrier Transactions

barrier_transaction_user_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D8.2.3 Response signaling

Monitor Checks that for a barrier transaction AxUSER has valid value 0x00

Checks the valid value of AxUSER for write barrier transactions

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awlock_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction AWLOCK is Normal Access 'b0!

Checks the combinations of AWLOCK and AWBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions

write_barrier_awsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction AWSNOOP is all zeros!

Checks the combinations of AWSNOOP and AWBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awcache_type_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction AWCACHE is Normal non-cacheable 'b0010!

Checks the combinations of AWCACHE and AWBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awsize_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction the AWSIZE matches the data bus width!

Checks the combinations of AWSIZE and AWBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions Constraints

write_barrier_awlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that a barrier write transaction should be of length 1!

Checks the combinations of AWLEN and AWBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions

write_barrier_awburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction the burst_type is INCR!

Checks the combinations AWBURST and AWBAR are valid and unreserved

ERROR

ACE,ACE_Lite

Barrier Transactions

write_barrier_awaddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a barrier write transaction the AWADDR should be all zeros!

Checks the AWADDR is valid for AWBAR

ERROR

ACE,ACE_Lite

Cache Line Size Transactions Constraints

cache_line_axbar_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AxBAR is valid for Cache Line Size Transactions!

Checks if the AxBAR is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite

Signal Stability

signal_stable_awbar_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for signal stability when corresponding valid signal is high

Checks that AWBAR is stable when AWVALID is high

ERROR

ACE,ACE_Lite

Barrier Transactions: Signal Validity

signal_valid_awbar_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWBAR is not X or Z when AWVALID is high

ERROR

ACE,ACE_Lite

Signal Stability

signal_stable_arbar_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for signal stability when corresponding valid signal is high

Checks that ARBAR is stable when ARVALID is high

ERROR

ACE,ACE_Lite

Barrier Transactions: Signal Validity

signal_valid_arbar_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.2 Read and write barrier transactions

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARBAR is not X or Z when ARVALID is high

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_snoop_successive_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.1 DVM message transactions

Monitor Checks that there are no unrelated snoop channel transfer in between two multi-part DVM operations which relate to the same DVM transaction

Checks that all snoop transactions of multi-part DVM operation are sent in successive manner and no unrelated snoop transaction sent during multi-part DVM opearion over AC channel

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_coherent_successive_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.1 DVM message transactions

Monitor Checks that there are no unrelated read-address channel transfer in between two multi-part DVM operations which relate to the same DVM transaction

Checks that all coherent transactions of multi-part DVM operation are sent in successive manner and no unrelated coherent transaction sent during multi-part DVM opearion over AR channel

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_snoop_same_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Checks that each snoop transaction related to a multi-part DVM Operation must send same snoop response

Checks that all transactions of multi-part DVM operation have same snoop response

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_coherent_same_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Checks that each transaction of a multi-part DVM Message must send same coherent response

Checks that all transactions of multi-part DVM operation have same coherent response

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

multipart_dvm_coherent_same_id_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.4 DVM ID values

Monitor Checks that each transaction of a multi-part DVM Message must use the same AXI ID

Checks that all transactions of multi-part DVM operation have same ID

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_xact_id_overlap_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.4 DVM ID values

Monitor Check for the ARID overlap of DVM transactions with other active Non-DVM transactions

Checks the overlapping ARID of DVM transactions with any active Read transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvmmessage_snoop_araddr_reserve_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.3 DVM messages

Monitor Check that for DVM Message the value of reserve address bits must be zero!

Checks FOR DVM Message the value of reserve address bit should be zero

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[0] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[0] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[5] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[5] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[6] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[6] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[9:8] for DVM Message type Virtual Instruction Cache Invalidate!

Checks the valid values of ARADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_invalidate_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[11:10] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ARADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_addr_specified_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[0] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ARADDR[0] of DVM message type Physical Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_vid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[6:5] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ARADDR[6:5] of DVM message type Physical Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_secure_nonsecure_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ARADDR[9:8] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ARADDR[9:8] of DVM message type Physical Instruction Cache Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Branch Predictor

dvmmessage_branch_predictor_invalidate_supported_message_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate

Monitor Check for the supported values of ARADDR[0] for DVM Message type Branch Predictor Invalidate!

Checks the valid values of ARADDR[0] of DVM message type Branch Predictor Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[0] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[0] of DVM message type TLB Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[5] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[5] of DVM message type TLB Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[6] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[6] of DVM message type TLB Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check the for supported values of ARADDR[9:8] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[9:8] of DVM message type TLB Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_hypervisor_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ARADDR[11:10] for DVM Message type TLB Invalidate !

Checks the valid values of ARADDR[11:10] of DVM message type TLB Invalidate

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvmmessage_araddr_reserve_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.3.5 DVM message encoding, first part

Monitor Check that for DVM Message the value of reserve address bits must be zero!

Checks FOR DVM Message the value of reserve address bit should be zero

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvmcomplete_araddr_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for a DVM Complete message, ARADDR is defined to be all zeros!

Checks For a DVM Complete message, ARADDR is defined to be all zeros

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Hint

dvm_operation_dvm_hint_araddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.12 Hint

Monitor Checks that for DVM HINT Message ARADDR bit[15] == 1

Checks for DVMHINT, DVM Operation the valid value of ARADDR[15]

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM Operation

dvm_operation_dvm_sync_araddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.11 Synchronization

Monitor Checks that for DVM SYNC Message ARADDR bits [n-1:32] and [11:0] are all set to 0 and bit[15] == 1

Checks for DVMSYNC, DVM Operation the valid value of ARADDR[(n-1):32],[15],[11:0] bits

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM Operation

dvm_operation_dvm_sync_arsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ARSNOOP is 'b1111 for DVM Operation and DVM Sync!

Checks for DVMSYNC, DVM Operation the valid value of ARSNOOP

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_ardomain_type_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARDOMAIN is Inner shareable or Outer shareable!

Checks for DVM ARDOMAIN is Inner shareable or Outer shareable

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arlock_type_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARLOCK is 'b0 Normal Access!

Checks for DVM ARLOCK 'b0 Normal Access

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arcache_type_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions ARCACHE is 'b0010 Normal non-cacheable!

Checks for DVM ARCACHE 'b0010 Normal non-cacheable

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arsize_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions the ARSIZE Matches the data bus width !

Checks for DVM ARSIZE Matches the data bus width

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that DVM transactions are of length 1!

Checks For DVM ARLEN All zero

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM

dvm_message_arburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A15.5 DVM Sync and Complete
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D13.2.3 DVM request attributes

Monitor Check that for DVM transactions burst_type is INCR !

Checks For DVM ARBURST 'b01 Burst Type INCR

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

awsnoop_awdomain_awbar_reserve_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.3 Read and write Shareable transaction types

Monitor Check that the combinations of AWDOMAIN,AWSNOOP and AWBAR are Valid and are un-reserved!

Checks the combinations of AWDOMAIN,AWSNOOP and AWBAR are valid and unreserved

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

arsnoop_ardomain_arbar_reserve_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.3 Read and write Shareable transaction types

Monitor Check that the combinations of ARDOMAIN,ARSNOOP and ARBAR are Valid and are un-reserved!

Checks the combinations of ARDOMAIN,ARSNOOP and ARBAR are valid and unreserved

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Burst Type

fixed_burst_type_valid

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that the FIXED burst type is only permitted for ReadNoSnoop and WriteNoSnoop transactions!

Checks that the FIXED burst type is not supported for shareable transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

valid_snoop_response_during_cache_maintenance_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D1.4.4 Cache maintenance transactions

Monitor checks that when master initiates a CleanShared cache maintenance transaction, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty snoop response. It also checks that when master initiates CleanInvalid or MakeInvalid cache maintenance transactions, and receives any snoop transaction to the same cacheline, the initiating master must not assert PassDirty, IsShared and DataTransfer snoop responses

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

no_memory_update_or_shareable_txn_during_cache_maintenance_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.9 ACE Managers and CMOs

Monitor checks that WriteBack, WriteClean or any shareable transactions which permits the line to be allocated are not issued while cache maintenance transaction is in progress

Checks that WriteBack, WriteClean or any shareable transactions that permits the line to be allocated are not issued while cache maintenance transaction is in progress.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

cache_maintenance_outstanding_transaction_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D12.1 About the interface control signals

Monitor checks that CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding. Checks that CleanShared cache maintenance transactions are not initiated while any memory update or any shareable transactions that can make the cacheline dirty, are outstanding

Checks that CleanInvalid and MakeInvalid cache maintenance transactions are not initiated while any memory update or shareable transactions are outstanding. It also checks that CleanShared cache maintenance transactions are not initiated while any memory update or any shareable transactions that can make the cacheline dirty, are outstanding

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_dvmcomplete_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for DVMComplete Transaction are IsShared=0;PassDirty=0 !

Checks the valid response of DVM Complete Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_dvmmessage_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for DVMMessage Transaction are IsShared=0;PassDirty=0 !

Checks the valid response of DVM Message Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_readbarrier_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadBarrier Transaction are IsShared=0;PassDirty=0 !

Checks the valid response of readbarrier Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Data Transfer Check

coherent_single_read_data_transfer_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED,CLEANSHAREDPERSIST, CLEANINVALID, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer

Checks the CLEANUNIQUE, MAKEUNIQUE, CLEANSHARED, CLEANINVALID,CLEANSHAREDPERSIST, MAKEINVALID, READBARRIER, DVMCOMPLETE, DVMMESSAGE transactions have only single read data channel transfer

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_readnosnoop_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadNoSnoop Transaction are IsShared=0;PassDirty=0!

Checks the valid response of readnosnoop Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_readonce_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadOnce Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of readonce Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_cleaninvalid_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for CleanInvalid Transaction are IsShared=0;PassDirty=0!

Checks the valid response of cleaninvalid Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_makeinvalid_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for MakeInvalid Transaction are IsShared=0;PassDirty=0!

Checks the valid response of makeinvalid Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Maintenance

read_data_chan_cleansharedpersist_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.7.4 PCMOs on read channels

Monitor Check that the valid response for CleanSharedPersist Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of cleansharedPersist Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Read response signaling

read_data_chan_cleanshared_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for CleanShared Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of cleanshared Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Data Transfer Check

perform_no_datatransfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that no data transfer occurs for a CleanShared,CleansharedPersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions !

Checks for no data transfer occurs for a CleanShared,Cleansharedpersist, CleanInvalid, CleanUnique, MakeUnique, MakeInvalid and Evict Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

writelineunique_wstrb_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that WriteLineUnique transactions are required to have every write data strobe bits asserted, that is, sparse write data strobes are not permitted

Monitor check that all write strobes bits are asserted for a WRITELINEUNIQUE transaction

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_arlock_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Checks that ARLOCK is valid for ReadOnce Transactions!

Checks if the ARLOCK is valid for ReadOnce Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awlock_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWLOCK is valid for WriteUnique Transactions!

Checks if the AWLOCK is valid for WriteUnique Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_arcache_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that ARCACHE is valid for ReadOnce Transactions!

Checks if the ARCACHE is valid for ReadOnce Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awcache_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWCACHE is valid for WriteUnique Transactions!

Checks if the AWCACHE is valid for WriteUnique Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_arburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that ARBURST is valid for ReadOnce Transactions!

Checks if the ARBURST is valid for ReadOnce Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWBURST is valid for WriteUnique Transactions!

Checks if the AWBURST is valid for WriteUnique Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

readonce_ardomain_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that ARDOMAIN is valid for ReadOnce Transactions!

Checks if the ARDOMAIN is valid for ReadOnce Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

ReadOnce and WriteUnique Transactions Constraints

writeunique_awdomain_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWDOMAIN is valid for WriteUnique Transactions!

Checks if the AWDOMAIN is valid for ReadOnce & WriteUnique Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_sz_eq_alen_asize_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AxLEN is correctly indicated according to Cache Line Size configured!

Checks if the AxLEN is correctly indicated as per the Cache Line Size configured

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arlock_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that ARLOCK is valid for Cache Line Size Transactions!

Checks if the ARLOCK is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awlock_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AWLOCK is valid for Cache Line Size Transactions!

Checks if the AWLOCK is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arcache_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that ARCACHE is valid for Cache Line Size Transactions!

Checks if the ARCACHE is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awcache_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AWCACHE is valid for Cache Line Size Transactions!

Checks if the AWCACHE is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_ardomain_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that ARDOMAIN is valid for Cache Line Size Transactions!

Checks if the ARDOMAIN is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awdomain_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that AWDOMAIN is valid for Cache Line Size Transactions!

Checks if the AWDOMAIN is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arburst_incr_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to cache line size for INCR burst in a Cache Line Size Transaction!

Checks if the address is aligned for ARBURST in Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awburst_incr_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to cache line size for INCR burst in a Cache Line Size Transaction!

Checks if the address is aligned for AWBURST in Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arburst_wrap_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction!

Checks if the address is aligned for ARBURST in Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awburst_wrap_addr_aligned_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the address is aligned to burst_size for WRAP burst in a Cache Line Size Transaction!

Checks if the address is aligned for AWBURST in Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arsize_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the total number of bytes transferred in the transaction is equal to the cache_line_size!

Checks if the ARSIZE is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that If DataTransfer de-asserted then no data transfer will occur on the snoop data channel for this transaction DataTransfer, CRRESP[0]!

Checks if the ARBURST is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awsize_valid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the total number of bytes transferred in the transaction is equal to the cache_line_size!

Checks if the AWSIZE is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awburst_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that awburst is valid for Cache Line Size Transactions!

Checks if the AWBURST is valid for Cache Line Size Transactions

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

axcache_axdomain_invalid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.6 Domains and memory types
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor Check that the combination of AxDOMAIN and AxCACHE are valid !

Checks if the AXCACHE and AXDOMAIN value are valid

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types

axcache_axdomain_restriction_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.6 Domains and memory types
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor Check that Device transactions, as indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 System Shareable !

Checks if the Device transactions, as indicated by AxCACHE[1] = 0, must only use AxDOMAIN = 11 Checks if the Cacheable transactions, as indicated by AxCACHE[3:2] != 00, must not use AxDOMAIN = 11

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses: ACE Master

exclusive_ace_transaction_type_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.1 About Exclusive accesses from ACE Managers

Monitor check that exclusive transaction sent on AXI_ACE interface are only of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type

Checks that exclusive transaction sent on AXI_ACE interface are only of WRITENOSNOOP, READNOSNOOP, READCLEAN, READSHARED and CLEANUNIQUE type

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_id_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.1 Exclusive access process

Monitor check that the bits of the AXI ID signal that are used to identify the Exclusive-capable thread must be the same for all Exclusive transactions from the same Exclusive-capable thread. In other words, monitor checks that same ID is used for exclusive access READ and WRITE transactions

Checks that id is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses: ACE Master

exclusive_store_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor check that response generated for exclusive store accesss is correct

Checks that response generated for exclusive store accesss is correct

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses: ACE Master

exclusive_load_response_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load

Monitor check that response generated for exclusive load accesss is correct

Checks that response generated for exclusive load accesss is correct

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Data: Signal Stability

signal_stable_awsnoop_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A8.1 Opcode signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.3 Read and write Shareable transaction types

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSNOOP is stable when AWVALID is high

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Stability

signal_stable_awdomain_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for signal stability when corresponding valid signal is high

Checks that AWDOMAIN is stable when AWVALID is high

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Data: Signal Stability

signal_stable_arsnoop_when_arvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that ARSNOOP is stable when ARVALID is high

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Stability

signal_stable_ardomain_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for signal stability when corresponding valid signal is high

Checks that ARDOMAIN is stable when ARVALID is high

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

DVM: Mulipart

signal_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.2 Addresses in DVM messages

Monitor check for dvm multipart xact ADDR[2:0] should be SBZ

Checks that ARADDR[2:0] for multipart dvm xact is not other than SBZ

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_arsnoop_when_arvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARSNOOP is not X or Z when ARVALID is high

ERROR

ACE,ACE_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Validity

signal_valid_ardomain_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARDOMAIN is not X or Z when ARVALID is high

ERROR

ACE,ACE5

Interconnect Requirements

snoop_to_same_cache_line_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.2 Sequencing transactions

The interconnect must ensure that, if the interconnect sends a snoop transaction to a master, it must not provide the same master with a response to a transaction to the same cache line, until it has received a snoop response on CRRESP to the snoop transaction

Checks that if received a snoop transaction, response to a transaction to the same cache line is not received , until snoop response is sent

ERROR

ACE,ACE5

Interconnect Requirements

resp_to_same_cache_line_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.2 Sequencing transactions

The interconnect must ensure that, if the interconnect provides a master with a response to a transaction, it must not send the same master a snoop transaction to the same cache line until it has received an acknowledgment of the transaction response on either RACK or WACK

Checks that Master does not receive a snoop transaction until any preceding transaction to the same cache line has completed

ERROR

ACE,ACE5

WACK Signaling

wack_status_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling

Monitor Check that WACK is asserted in response to BVALID/BREADY handshakes!

Checks the WACK for valid response

ERROR

ACE,ACE5

RACK Signaling

rack_status_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling

Monitor Check that RACK is asserted in response to all RLAST/RVALID/RREADY handshakes!

Checks the RACK for valid response

ERROR

ACE,ACE5

Snoop Transactions

snoop_addr_snoop_data_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor Check that the master must wait for both ACVALID and ACREADY to be asserted before asserting CDVALID!

Checks that ACVALID and ACREADY to be asserted before asserting CDVALID

ERROR

ACE,ACE5

Snoop Data

cdlast_asserted_for_last_snoopread_data_beat

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check that the CDLAST signal is asserted during the final data transfer associated with a snoop transaction!

Checks that CDLAST signal is asserted during the final data transfer

ERROR

ACE,ACE5

Snoop Response

snoop_response_channel_isshared_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that for ReadUnique, CleanInvalid and MakeInvalid transaction, snoop_resp_isshared cannot be asserted!

Checks for readunique cleaninvalid makeinvalid illegal response

ERROR

ACE,ACE5

Snoop Data

full_cache_line_datatransfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check that if DataTransfer is asserted, a full cache line of data must be provided on the snoop data channel!

If DataTransfer is asserted, a full cache line of data must be provided on the snoop data channel

ERROR

ACE,ACE5

Snoop Response

snoop_resp_passdirty_datatransfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that snoop_resp_datatransfer is asserted if snoop_resp_passdirty is asserted!

Checks that for MakeInvalid transactions a data transfer is never required

ERROR

ACE,ACE5

Coherency Transactions

complete_outstanding_writeunique_writelineunique_before_memory_write_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.7 Restrictions on WriteUnique and WriteLineUnique usage

Monitor checks that no additional WriteBack, WriteClean, or WriteEvict transactions are issued until all outstanding WriteUnique or WriteLineUnique transactions are completed

Checks that a cached master does not issue WriteBack, WriteClean or WriteEvict transaction while any WriteUnique or WriteLineUnique coherent write transaction is in progress. It automatically checks second rule which says, Complete any incoming snoop transactions without the use of WriteBack, WriteClean, or WriteEvict transactions while a WriteUnique or WriteLineUnique transaction is in progress

ERROR

ACE,ACE5

Coherency Transactions

complete_outstanding_memory_write_before_writeunique_writelineunique_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.7 Restrictions on WriteUnique and WriteLineUnique usage

Monitor checks that a cached master completes any outstanding WriteBack, WriteClean, or WriteEvict transactions before issuing a WriteUnique or WriteLineUnique transaction

Checks that a cached master does not initiate WriteUnique or WriteLineUnique coherent write transaction while any WriteBack, WriteClean or WriteEvict transaction is outstanding

ERROR

ACE,ACE5

Snoop Address

acaddr_aligned_to_cddata_width_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor Check that ACADDR must be aligned to the data transfer size, which is determined by the width of the snoop data bus in bytes

Checks if snoop address is aligned with snoop data width

ERROR

ACE,ACE5

Snoop Transactions

snoop_transaction_burst_length_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check that snoop transaction burst length must be 1, 2, 4, 8, or 16

Checks if number of databeat transferred over snoop data channel is valid

ERROR

ACE,ACE5

Read response signaling

read_data_chan_readclean_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadClean Transaction are IsShared=0;PassDirty=0 & IsShared=1;PassDirty=0!

Checks the valid response of readclean Transactions

ERROR

ACE,ACE5

Read response signaling

read_data_chan_readnotshareddirty_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadNotSharedDirty Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1 & IsShared=1;PassDirty=0!

Checks the valid response of readnotshareddirty Transactions

ERROR

ACE,ACE5

Read response signaling

read_data_chan_readunique_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for ReadUnique Transaction are IsShared=0;PassDirty=0 & IsShared=0;PassDirty=1!

Checks the valid response of readunique Transactions

ERROR

ACE,ACE5

Read response signaling

read_data_chan_cleanunique_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for CleanUnique Transaction are IsShared=0;PassDirty=0!

Checks the valid response of cleanunique Transactions

ERROR

ACE,ACE5

Read response signaling

read_data_chan_makeunique_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.2.1 Read response signaling

Monitor Check that the valid response for MakeUnique Transaction are IsShared=0;PassDirty=0!

Checks the valid response of makeunique Transactions

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_transaction_from_shared_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Checks that if cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED

Checks that if cacheline is in shared state then exclusive transaction is issued only as CLEANUNIQUE, READCLEAN or READSHARED

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_store_from_valid_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor Checks that if cacheline is in invalid state then exclusive store transaction is not issued

Checks that if cacheline is in invalid state then exclusive store transaction is not issued

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_load_from_valid_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.1 Exclusive Load

Monitor Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

Checks that if cacheline is in invalid state then exclusive load transaction is issued only as READCLEAN or READSHARED

ERROR

ACE,ACE5

Coherency Transactions

writeevict_wstrb_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict

Monitor Check that all write strobes bits are asserted for a WRITEEVICT transaction

Monitor check that all write strobes bits are asserted for a WRITEEVICT transaction

ERROR

ACE,ACE5

Cache Line Size Transactions Constraints

writeevict_awunique_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWUNIQUE is asserted for a WRITEEVICT transaction

AWUNIQUE must be asserted for WRITEEVICT transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeclean_awunique_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWUNIQUE is deasserted for a WRITECLEAN transaction

AWUNIQUE must be deasserted for WRITECLEAN transactions

ERROR

ACE,ACE5

Awnique Signal

snoop_response_to_same_cacheline_during_xact_with_awunique_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal

Monitor check that while a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line

While a transaction is in progress which has the AWUNIQUE signal asserted, the master must not give a snoop response that would allow another copy of the line to be created, or an agent to consider that it has another Unique copy of the line

ERROR

ACE,ACE5

Coherency Transactions

snoop_response_to_same_cacheline_during_writeevict_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict

Monitor check that if a snooped master receives a snoop transaction when it has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time

If a snooped master receives a snoop transaction when it is has an outstanding WriteEvict transaction, then it is the responsibility of the snooped master to ensure that no other master can update the same area of main memory at the same time. The snooped master achieves this by delaying the snoop response until the snooped master has completed the WriteEvict transaction

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awlock_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a WRAP burst for WriteBack and WriteClean transactions, AWSIZE x AWLEN must not exceed the cache line size!

Checks if the AWLOCK is 0 for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_wrap_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for a WRAP burst for WriteBack and WriteClean transactions, AWSIZE x AWLEN must not exceed the cache line size!

Checks if the AWSIZE x AWLEN not exceed the cache line size WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_incr_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that for an INCR burst for WriteBack and WriteClean transactions, the last byte in the burst added to the AWSIZE aligned start address, must be within the same cache line as the first byte in the burst!

Checks if the Address aligned for INCR is valid for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awcache_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWCACHE is valid for WriteBack and WriteClean Transactions!

Checks if the AWCACHE is valid for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awdomain_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWDOMAIN is valid for WriteBack and WriteClean Transactions!

Checks if the AWDOMAIN is valid for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWBURST is valid for WriteBack and WriteClean Transactions!

Checks if the AWBURST is valid for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awburst_awlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWLEN and AWBURST are valid for WriteBack and WriteClean Transactions!

Checks if the AWLEN for INCR is valid for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awlen_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWLEN is valid for WriteBack and WriteClean Transactions!

Checks if the AWLEN is valid for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

WriteBack and WriteClean Transactions Constraints

writeback_writeclean_awsize_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.6 Transaction constraints

Monitor Check that AWSIZE is valid for WriteBack and WriteClean Transactions!

Checks if the AWSIZE is valid for WriteBack and WriteClean Transactions

ERROR

ACE,ACE5

Snoop Transactions

dirty_state_data_transfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.2.2 Snoop data transfers

Monitor checks that, if cacheline is in Dirty state UD or SD then dataTransfer bit must be set when master sends snoop response

Checks if snoop response has data transfer bit set for cacheline in dirty state

ERROR

ACE,ACE5

Coherency Transactions

evict_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.9.1 Evict

Monitor checks that, EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state

Checks if EVICT transaction starts only from UNIQUECLEAN or SHAREDCLEAN state

ERROR

ACE,ACE5

Coherency Transactions

writeevict_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.6 WriteEvict

Monitor checks that, WRITEEVICT transaction starts only from UNIQUECLEAN state

Checks if WRITEEVICT transaction starts only from UNIQUECLEAN state

ERROR

ACE,ACE5

Coherency Transactions

writeclean_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.5 WriteClean

Monitor checks that, WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

Checks if WRITECLEAN transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

ERROR

ACE,ACE5

Coherency Transactions

writeback_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.4 WriteBack

Monitor checks that, WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

Checks if WRITEBACK transaction starts only from UNIQUEDIRTY or SHAREDDIRTY state

ERROR

ACE,ACE5

Coherency Transactions

writelineunique_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.3 WriteLineUnique

Monitor checks that, WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if WRITELINEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

ERROR

ACE,ACE5

Coherency Transactions

writeunique_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.8.2 WriteUnique

Monitor checks that, WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if WRITEUNIQUE transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

ERROR

ACE,ACE5

Coherency Transactions

makeinvalid_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.7.2 MakeInvalid

Monitor checks that, MAKEINVALID transaction starts only from INVALID state

Checks if MAKEINVALID transaction starts only from INVALID state

ERROR

ACE,ACE5

Coherency Transactions

cleaninvalid_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.6.3 CleanInvalid

Monitor checks that, CLEANINVALID transaction starts only from INVALID state

Checks if CLEANINVALID transaction starts only from INVALID state

ERROR

ACE,ACE5

Cache Maintenance

cleansharedpersist_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D7.7 Cache maintenance for Persistence

Monitor checks that, CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if CLEANSHAREDPERSIST transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

ERROR

ACE,ACE5

Coherency Transactions

cleanshared_correct_start_state_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D4.6.2 CleanShared

Monitor checks that, CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

Checks if CLEANSHARED transaction starts only from INVALID, UNIQUECLEAN or SHAREDCLEAN state

ERROR

ACE,ACE5

Snoop Transactions

cdvalid_high_no_data_transfer_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D5.2.1 Channel activity

Monitor Check that arburst is valid for Cache Line Size Transactions!

Checks that the if DataTransfer de-asserted then no data transfer will occur on the snoop data channel for this transaction DataTransfer, CRRESP[0]

ERROR

ACE,ACE5

Reset

cdvalid_low_when_reset_is_active_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D2.3.3 Reset requirements

Monitor Check for CDVALID low when reset is active!

Checks if cdvalid is low when reset is active

ERROR

ACE,ACE5

Signal Stability

cdvalid_interrupted_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check for CDVALID held steady until CDREADY is asserted!

Checks if cdvalid was interrupted before cdrready got asserted

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cdvalid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor Check for X or Z on CDVALID!

Checks that CDVALID is not X or Z

ERROR

ACE,ACE5

WACK Signaling

signal_wack_after_handshake_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling

Monitor Checks that WACK signal must be asserted the cycle after the associated handshake or later!

Checks that WACK signal must be asserted the cycle after the associated handshake or later

ERROR

ACE,ACE5

WACK Signaling

signal_wack_single_cycle_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.5 Write Acknowledge signaling

Monitor Checks that WACK is asserted for a single cycle!

Checks that WACK is asserted for a single cycle

ERROR

ACE,ACE5

RACK Signaling

signal_rack_after_handshake_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling

Monitor Checks that RACK signal must be asserted the cycle after the associated handshake or later!

Checks that RACK signal must be asserted the cycle after the associated handshake or later

ERROR

ACE,ACE5

RACK Signaling

signal_rack_single_cycle_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.3 Read acknowledge signaling

Monitor Checks that RACK is asserted for a single cycle!

Checks that RACK is asserted for a single cycle

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exokay_not_sent_until_successful_exclusive_store_rack_observed_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.3.1 Minimum PoS Exclusive Monitor

Monitor checks that, once a master receives successful exclusive store response EXOKAY from interconnect, then no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK

Checks that, once a master receives successful exclusive store response EXOKAY from interconnect, then no other master should be provided with EXOKAY response, until current master acknowledges completing successful exclusive store by asserting RACK

ERROR

ACE,ACE5

Exclusive Accesses: ACE Master

exclusive_store_overlap_with_another_exclusive_sequence_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D9.2.3 Exclusive Store

Monitor check that a master must not permit an Exclusive Store transaction to be in progress at the same time as any transaction that registers that it is performing an Exclusive sequence

Checks that master does not permit an Exclusive Store transaction to be in progress at the same time as any transaction that registers that it is performing an Exclusive sequence

ERROR

ACE,ACE5

Trace Signals: Signal Stability

signal_stable_cdtrace_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.4 Trace signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CDTRACE is stable when CDVALID is high.

ERROR

ACE,ACE5

Signal Stability

signal_stable_cdlast_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that cdlast is stable when cdvalid is high

ERROR

ACE,ACE5

Signal Stability

signal_stable_cddata_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that CDDATA is stable when CDVALID is high

ERROR

ACE,ACE5

Trace Signals: Signal Validity

signal_valid_cdtrace_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E1.4 Trace signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDTRACE is not X or Z when CDVALID is high.

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cdlast_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that cdlast is not X or Z when cdvalid is high

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cddata_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDDATA is not X or Z when CDVALID is high

ERROR

ACE,ACE5

Snoop Data: Signal Validity

signal_valid_cdready_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.8 Snoop data channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDREADY is not X or Z when CDVALID is high

ERROR

ACE,ACE5

Signal Stability

signal_stable_awunique_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal

Monitor check for signal stability when corresponding valid signal is high

Checks that AWUNIQUE is stable when AWVALID is high

ERROR

ACE,ACE5

Awnique Signal

signal_valid_awunique_when_awvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.1.4 AWUNIQUE signal

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWUNIQUE is not X or Z when AWVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_virtual_inst_cache_snoop_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[0] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[0] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[5] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[5] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[6] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[6] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[9:8] for DVM Message type Virtual Instruction Cache Invalidate!

Checks the valid values of ACADDR[9:8] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_virtual_inst_cache_invalidate_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.4 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[11:10] for DVM Message type Virtual Instruction Cache Invalidate !

Checks the valid values of ACADDR[11:10] of DVM message type Virtual Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

dvmmessage_physical_inst_cache_snoop_addr_specified_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[0] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ACADDR[0] of DVM message type Physical Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_physical_inst_cache_vid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.10 Instruction cache invalidations

Monitor Check for the supported values of ACADDR[6:5] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ACADDR[6:5] of DVM message type Physical Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Instruction Cache invalidations

snoop_dvmmessage_physical_inst_cache_secure_nonsecure_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate

Monitor Check for the supported values of ACADDR[9:8] for DVM Message type Physical Instruction Cache Invalidate !

Checks the valid values of ACADDR[9:8] of DVM message type Physical Instruction Cache Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: Branch Predictor

snoop_dvmmessage_branch_predictor_invalidate_supported_message_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.9 Branch Predictor Invalidate

Monitor Check for the supported values of ACADDR[0] for DVM Message type Branch Predictor Invalidate!

Checks the valid values of ACADDR[0] of DVM message type Branch Predictor Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

dvmmessage_tlb_snoop_addr_specified_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[0] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[0] of DVM message type TLB Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_asid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[5] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[5] of DVM message type TLB Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_vmid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[6] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[6] of DVM message type TLB Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_secure_nonsecure_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[9:8] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[9:8] of DVM message type TLB Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: TLBI

snoop_dvmmessage_tlb_hypervisor_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A15.3.2 TLB Invalidate messages

Monitor Check for the supported values of ACADDR[11:10] for DVM Message type TLB Invalidate !

Checks the valid values of ACADDR[11:10] of DVM message type TLB Invalidate

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

dvmcomplete_acaddr_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that for a DVM Complete, ACADDR is defined to be all zeros!

Checks For a DVM Complete, ACADDR is defined to be all zeros

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM Operation

dvm_operation_dvm_sync_acsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ACSNOOP is 'b1111 for DVM Operation and DVM Sync!

Checks the value of ACSNOOP for the DVM SYNC

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

dvm_complete_acsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ACSNOOP is 'b1110 for DVM Complete !

Checks the value of ACSNOOP for the DVM complete

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

dvm_complete_arsnoop_valid_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.3 DVM request attributes

Monitor Check that ARSNOOP is 'b1110 for DVM Complete!

Checks for DVMCOMPLETE the valid value of ARSNOOP

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Transactions

snoop_transaction_order_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor Check that all snoop transactions are ordered. The response, as given on the snoop response channel, must be in the same order that the transactions are presented on the snoop address channel!

Checks all snoop transactions are ordered

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Transactions

snoop_addr_snoop_resp_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor Check that the master must wait for both ACVALID and ACREADY to be asserted before asserting CRVALID!

Checks that ACVALID and ACREADY to be asserted before asserting CRVALID

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address

acsnoop_reserved_value_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor Check that ACSNOOP does not have a reserved value!

Checks that ACSNOOP does not have reserved values

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

snoop_chan_dvmcomplete_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Check that a snoop responseCRRESP of 5'b00010 is not given for DVMComplete Transaction !

Checks the valid snoop response of DVM Complete Transactions

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM

snoop_chan_dvmsync_resp_valid_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.2.5 DVM responses

Monitor Check that a snoop responseCRRESP of 5'b00010 is not given for DVMSync Transaction !

Checks the valid snoop response of DVM Message Transactions

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the arlen is valid for Cache Line Size Transactions!

Checks if the ARLEN is valid for Cache Line Size Transactions

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the awlen is valid for Cache Line Size Transactions!

Checks if the AWLEN is valid for Cache Line Size Transactions

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_arsize_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the arsize is valid for Cache Line Size Transactions!

Checks if the ARSIZE is valid for Cache Line Size Transactions

ERROR

ACE,ACE5,ACE5_LiteDVM

Cache Line Size Transactions Constraints

cache_line_awsize_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.2 Cache line size
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.6 Transaction constraints

Monitor Check that the awsize is valid for Cache Line Size Transactions!

Checks if the AWSIZE is valid for Cache Line Size Transactions

ERROR

ACE,ACE5,ACE5_LiteDVM

Reset

acvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.1 Snoop request channel AC
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D2.3.3 Reset requirements

Monitor Check for ACVALID low when reset is active!

Checks if acvalid is low when reset is active

ERROR

ACE,ACE5,ACE5_LiteDVM

Reset

crvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D2.3.3 Reset requirements

Monitor Check for CRVALID low when reset is active!

Checks if crvalid is low when reset is active

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

crvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.9 Snoop channel dependencies

Monitor Check for CRVALID held steady until CRREADY is asserted!

Checks if crvalid was interrupted before crready got asserted

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

acvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.1 Snoop request channel AC
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.6.2 Snoop address channel signaling

Monitor Check for ACVALID held steady until ACREADY is asserted!

Checks if acvalid was interrupted before acready got asserted

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A3.6.2 Snoop response channel CR
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.7 Snoop response channel signaling

Monitor Check for X or Z on CRVALID!

Checks that CRVALID is not X or Z

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acvalid_check

Monitor Check for X or Z on ACVALID!

Checks that ACVALID is not X or Z

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_crtrace_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that CRTRACE is stable when CRVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_crresp_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that CRRESP is stable when CRVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_acprot_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that ACPROT is stable when ARVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_acsnoop_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that ACSNOOP is stable when ARVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Signal Stability

signal_stable_acaddr_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.9 Snoop channel dependencies

Monitor check for signal stability when corresponding valid signal is high

Checks that ACADDR is stable when ARVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crtrace_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRTRACE is not X or Z when CRVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crresp_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRRESP is not X or Z when CRVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Response: Signal Validity

signal_valid_crready_when_crvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.7 Snoop response channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CRREADY is not X or Z when CRVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acprot_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACPROT is not X or Z when ARVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acsnoop_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACSNOOP is not X or Z when ARVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acaddr_when_acvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACADDR is not X or Z when ARVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_acready_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D3.6.2 Snoop address channel signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ACREADY is not X or Z when ARVALID is high

ERROR

ACE,ACE5,ACE5_LiteDVM

DVM: VMID

signal_valid_arvmidext_when_arvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.4 Support for 16-bit VMID

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARVMIDEXT is not X or Z when ARVALID is high

ERROR

ACE5_LiteDVM

DVM v8.4

signal_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that observed_araddr[2:0] must be zero for multipart DVM transactions for dvm version less than DVMv8_4

Checks that observed_acaddr[2:0] must be zero for dvm_version less than DVM_v8.4 for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_num_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[5:4] and observed_araddr[2:0] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[5:4] and observed_acaddr[2:0] (NUM bits) must be zero for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_scale_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[7:6] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[7:6] (SCALE) must be zero for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_ttl_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[9:8] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[9:8] (TTL) must be zero for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_tg_acaddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_acaddr[11:10] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_acaddr[11:10] (TG) must be zero for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_num_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[5:4] and observed_araddr[2:0] (NUM bits) must be zero for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_scale_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[7:6] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[7:6] (SCALE) must be zero for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_ttl_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[9:8] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[9:8] (TTL) must be zero for multipart DVM transactions.

ERROR

ACE5_LiteDVM

DVM v8.4

valid_tg_araddr_multipart_dvm_xact_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D13.3.7 TLB Invalidate operations in DVM v8.4

Monitor Check that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, the observed_araddr[11:10] must be zero for multipart DVM transactions

Checks that if the dvm_version is greater than or equal to DVM_v8.4 and the message type is not TLB Invalidate by IPA or VA, The observed_araddr[11:10] (TG) must be zero for multipart DVM transactions.

ERROR

AXI4,AXI5

Atomic Accesses

align_addr_atomicity_size_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A7.1 Single-copy atomicity size

Monitor Check that a transaction never has an atomicity guarantee greater than the alignment of its start address on ARADDR/AWADDR.

Checks that ARADDR/AWADDR should always be aligned to Atomicity Size

ERROR

AXI4,AXI5

Interface Requirements

excl_access_on_write_only_interface_check

Synopsys Defined

Monitor Check that write only interface does not support exclusive access!

Checks that WRITE_ONLY_INTERFACE does not support exclusive access

ERROR

AXI4,AXI5

Interface Requirements

excl_access_on_read_only_interface_check

Synopsys Defined

Monitor Check that read only interface does not support exclusive access!

Checks that READ_ONLY_INTERFACE does not support exclusive access

ERROR

AXI4,AXI5

Interface Requirements

write_xact_on_write_only_interface_check

Synopsys Defined

Monitor Check that write only interface supports only write Transactions!

Checks that WRITE_ONLY_INTERFACE supports only write transactions

ERROR

AXI4,AXI5

Interface Requirements

read_xact_on_read_only_interface_check

Synopsys Defined

Monitor Check that read only interface supports only read Transactions!

Checks that READ_ONLY_INTERFACE supports only read transactions

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exokay_resp_observed_only_for_exclusive_transactions_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2 Exclusive accesses

Monitor checks that the EXOKAY response is observed only for permitted exclusive access transactions.For AXI3/AXI4 interfaces these are transactions with atomic_type is equal to EXCLUSIVE,For ACE_LITE interface these are READNOSNOOP, WRITENOSNOOP transaction or READONCE, WRITEUNIQUE if shareable_exclusive_access_from_acelite_ports_enable is set to '1'. For ACE interface these are READSHARED, READCLEAN and CLEANUNIQUE transaction !

checks that the EXOKAY response is observed only for permitted exclusive access transactions

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Interface Requirements

awburst_awlen_valid_value_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that AWLEN and AWBURST are valid for AXI Transactions!

Checks if the AWLEN for INCR is valid for AXI Transactions

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Interface Requirements

rlast_asserted_for_last_read_data_beat

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that RLAST is HIGH only for the last beat of READ burst !

Monitor Check that RLAST is HIGH only for the last beat of READ burst

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Interface Requirements

wlast_asserted_for_last_write_data_beat

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.3.2 Write data channel W

Monitor Check that WLAST is asserted for last beat of write data!

Checks that WLAST is asserted for the last beat of write data
Can be done reliably only if data_before_addr is not set, since if data_before_addr, observed_wlast could come at any point before the address comes

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_prot_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that protection type is generated same for exclusive accesss READ and WRITE transactions

Checks that protection type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_cache_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that cache type is generated same for exclusive accesss READ and WRITE transactions

Checks that cache type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_burst_type_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst type is generated same for exclusive accesss READ and WRITE transactions

Checks that burst type is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_burst_size_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst size is generated same for exclusive accesss READ and WRITE transactions

Checks that burst size is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_burst_length_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst length is generated same for exclusive accesss READ and WRITE transactions

Checks that burst length is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

exclusive_read_write_addr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that address is generated same for exclusive accesss READ and WRITE transactions

Checks that address is generated same for exclusive read and write transactions This is pass only check as VIP will consider a load and store to be exclusive pairs only when these properties are matching. Not having the matched properties b/w load store pair is not a protocol violation.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_write_addr_aligned_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access start address is aligned to the total number of bytes of the transaction

Checks that address is aligned for exclusive write transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_awcache_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access being monitored by a slave must not have an ARCACHE[3:0] or AWCACHE[3:0] value that indicates that the transaction is cacheable

Checks that AWCACHE is valid for exclusive read transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_awlen_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

The burst length for an exclusive access must not exceed 16 transfers.

Checks that AWLEN is valid for exclusive store transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_awlen_awsize_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst size and burst_length combination is valid for Exclusive access. The number of bytes that can be transferred in an exclusive access burst must be power of 2

Checks that AWLEN and AWSIZE are valid for exclusive store transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_read_addr_aligned_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access start address is aligned to the total number of bytes of the transaction

Checks that address is aligned for exclusive read transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_arcache_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that exclusive access being monitored by a slave must not have an ARCACHE[3:0] or AWCACHE[3:0] value that indicates that the transaction is cacheable

Checks that ARCACHE is valid for exclusive read transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_arlen_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

The burst length for an exclusive access must not exceed 16 transfers.

Checks that ARLEN is valid for exclusive read transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Exclusive Accesses

signal_valid_exclusive_arlen_arsize_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A7.3 Exclusive accesses
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A7.2.4 Exclusive access restrictions

Monitor check that burst size and burst_length combination is valid for Exclusive access. The number of bytes that can be transferred in an exclusive access burst must be power of 2

Checks that ARLEN and ARSIZE are valid for exclusive read transaction

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_wlast_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that WLAST is stable when WVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_wlast_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WLAST is not X or Z when WVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awcache_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCACHE is stable when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awlock_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWLOCK is stable when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awburst_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWBURST is stable when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awlen_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWLEN is stable when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awcache_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWCACHE is not X or Z when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awlock_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWLOCK is not X or Z when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awburst_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWBURST is not X or Z when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awlen_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWLEN is not X or Z when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_rlast_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RLAST is stable when RVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_rlast_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RLAST is not X or Z when RVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arcache_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARCACHE is stable when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arlock_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARLOCK is stable when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arburst_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARBURST is stable when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arlen_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARLEN is stable when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arcache_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARCACHE is not X or Z when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arlock_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARLOCK is not X or Z when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arburst_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARBURST is not X or Z when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arlen_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARLEN is not X or Z when ARVALID is high

ERROR

ACE5,ACE5_Lite,ACE5_LiteDVM

Cache Line Size Transactions Constraints

full_cache_line_size_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section D6.7.2 Additional Cache Line conversion considerations

Monitor Check that all transactions other than ReadNoSnoop, ReadOnce,ReadonceCleaninvalid,ReadonceMakeinvalid, WriteNoSnoop, WriteUnique, Writeuniqueptlstash,WriteptlCMO,Stashtranslation,DVM Message,Barrier WriteBack and WriteClean are required to be a full cache line size!

Checks if all transactions (other than ReadNoSnoop, ReadOnce,ReadonceCleaninvalid,ReadonceMakeinvalid, WriteNoSnoop, WriteUnique, Writeuniqueptlstash,WriteptlCMO,Stashtranslation,DVM Message,Barrier WriteBack and WriteClean) are required to be a full cache line size

ERROR

ACE5

Poison: Signal Stability

signal_stable_cdpoison_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.1 Poison

Monitor check for signal stability when corresponding valid signal is high

Checks that CDPOISON is stable when CDVALID is high.

ERROR

ACE5

Poison: Signal Validity

signal_valid_cdpoison_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.1 Poison

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDPOISON is not X or Z when CDVALID is high.

ERROR

ACE5

Parity

cddatachk_parity_calculated_cddata_parity_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Checks that a sampled snoop transaction CDDATACHK is same as calculated parity value from CDDATA,if error is deducted then it will be converted in to poison

Checks the received CDDATACHK is same as the parity calculated from CDDATA in a snoop transaction

ERROR

ACE5

Parity: Signal Validity

signal_valid_cdpoisonchk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDPOISONCHK is not X or Z when CDVALID is high

ERROR

ACE5

Parity: Signal Validity

signal_valid_cdtracechk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDTRACECHK is not X or Z when CDVALID is high

ERROR

ACE5

Parity: Signal Validity

signal_valid_cdlastchk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDLASTCHK is not X or Z when CDVALID is high

ERROR

ACE5

Parity: Signal Validity

signal_valid_cddatachk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that CDDATACHK is not X or Z when CDVALID is high

ERROR

ACE5

Parity: Signal Stability

signal_stable_cdpoisonchk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CDPOISONCHK is stable when CDVALID is high.

ERROR

ACE5

Parity: Signal Stability

signal_stable_cdtracechk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CDTRACECHK is stable when CDVALID is high.

ERROR

ACE5

Parity: Signal Stability

signal_stable_cdlastchk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CDLASTCHK is stable when CDVALID is high.

ERROR

ACE5

Parity: Signal Stability

signal_stable_cddatachk_when_cdvalid_high_check

AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621: Section E2.6 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that CDDATACHK is stable when CDVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_armmuatst_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A14.3 Untranslated transaction signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section E1.9.1 Untranslated Transaction signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUATST is stable when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_armmussidv_when_arvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUSSIDV is stable when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_armmusecsid_when_arvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUSECSID is stable when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_armmussid_when_arvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUSSID is stable when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_armmusid_when_arvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that ARMMUSID is stable when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_awmmuatst_when_awvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUATST is stable when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_awmmussidv_when_awvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUSSIDV is stable when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_awmmusecsid_when_awvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUSECSID is stable when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_awmmussid_when_awvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUSSID is stable when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Stability

signal_stable_awmmusid_when_awvalid_high_check

Monitor check for signal stability when corresponding valid signal is high

Checks that AWMMUSID is stable when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_armmuatst_when_arvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUATST is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_armmussidv_when_arvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUSSIDV is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_armmusecsid_when_arvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUSECSID is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_armmussid_when_arvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUSSID is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_armmusid_when_arvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARMMUSID is not X or Z when ARVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_awmmuatst_when_awvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUATST is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_awmmussidv_when_awvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUSSIDV is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_awmmusecsid_when_awvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUSECSID is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_awmmussid_when_awvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUSSID is not X or Z when AWVALID is high.

ERROR

AXI5,ACE5,ACE5_Lite

Untranslated Transactions: Signal Validity

signal_valid_awmmusid_when_awvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWMMUSID is not X or Z when AWVALID is high.

ERROR

ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Snoop Address: Signal Validity

signal_valid_awsnoop_when_awvalid_high_check

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWSNOOP is not X or Z when AWVALID is high

ERROR

ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Domain Types: Signal Validity

signal_valid_awdomain_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A9.3.4 Domain signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section D3.1.1 Shareability domain types

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWDOMAIN is not X or Z when AWVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_wuser_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that WUSER is stable when WVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_wuser_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WUSER is not X or Z when WVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_awuser_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWUSER is stable when AWVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_buser_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that BUSER is stable when BVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_buser_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BUSER is not X or Z when BVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_awuser_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWUSER is not X or Z when AWVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_ruser_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that RUSER is stable when RVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_ruser_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RUSER is not X or Z when RVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Stability

signal_stable_aruser_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARUSER is stable when ARVALID is high

ERROR

AXI4,AXI4_Lite,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

User Signaling: Signal Validity

signal_valid_aruser_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A13.5 User defined signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.3 User-defined signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARUSER is not X or Z when ARVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Stability

signal_stable_awregion_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWREGION is stable when AWVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Stability

signal_stable_awqos_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that AWQOS is stable when AWVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Validity

signal_valid_awregion_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWREGION is not X or Z when AWVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Validity

signal_valid_awqos_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWQOS is not X or Z when AWVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Stability

signal_stable_arregion_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARREGION is stable when ARVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Stability

signal_stable_arqos_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for signal stability when corresponding valid signal is high

Checks that ARQOS is stable when ARVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

Region Signaling: Signal Validity

signal_valid_arregion_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.7 Multiple region interfaces
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.2 Multiple region signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARREGION is not X or Z when ARVALID is high

ERROR

AXI4,ACE,ACE_Lite,AXI5,ACE5,ACE5_Lite,ACE5_LiteDVM

QoS Signaling: Signal Validity

signal_valid_arqos_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K:Section A5.8 QoS signaling
AMBA AXI and ACE Protocol Specification ARM IHI 0022H.c ID012621:Section A8.1 QoS signaling

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARQOS is not X or Z when ARVALID is high

ERROR

AXI3 Onwards

Interface Requirements

write_resp_follows_last_write_xfer_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that write response must always follow last write data transfer!

When a write response is sampled, checks that there is a transaction with corresponding ID whose data phase is complete

ERROR

AXI3 Onwards

Interface Requirements

read_data_follows_addr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that read data must always follow address to which the data relates!

Checks that sample read data has associated address

ERROR

AXI3 Onwards

Interface Requirements

write_resp_after_write_addr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that a slave must not transmit the write response before the corresponding address is accepted!

Checks if A slave must not give a write response before the write address

ERROR

AXI3 Onwards

Interface Requirements

write_resp_after_last_wdata_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that a slave must only give a write response after the last write data item is transferred !

Checks if the slave must only give a write response after the last write data item is transferred

ERROR

AXI3 Onwards

Interface Requirements

wdata_awlen_match_for_corresponding_awaddr_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.4 Relationships between the channels

Monitor Check that the number of write data items matches AWLEN for the corresponding address!

Checks if the number of write data items matches AWLEN for the corresponding address

ERROR

AXI3 Onwards

Transaction Attributes

arvalid_arcache_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.2 Memory Attributes

Monitor Check that ARCACHE[3:2] is 2'b00 when ARVALID is HIGH and ARCACHE[1] is LOW !

Checks if the value of arcache[3:2]=2'b00 when arvalid is high and arcache[1] is also low

ERROR

AXI3 Onwards

Interface Requirements

arburst_reserved_val_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that a value of 2'b11 on ARBURST is not permitted when ARVALID is HIGH !

Checks if the value of arburst=2'b11 when arvalid is high

ERROR

AXI3 Onwards

Interface Requirements

arsize_data_width_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that a Read transfer does not exceed the width of the data interface!

Checks if size of read transfer exceeds the width of the data bus

ERROR

AXI3 Onwards

Interface Requirements

arlen_wrap_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Read Transaction with burst type WRAP has a valid burst length!

Checks if read burst of WRAP type has a valid length

ERROR

AXI3 Onwards

Interface Requirements

araddr_wrap_aligned_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Read Transaction with burst type WRAP has an aligned address!

Checks if read burst of WRAP type has an aligned address

ERROR

AXI3 Onwards

Interface Requirements

araddr_4k_boundary_cross_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.2 Length attribute

Monitor Check that a Read burst cannot cross a 4K boundary!

Checks if read burst cross a 4KB boundary

ERROR

AXI3 Onwards

Transaction Attributes

awvalid_awcache_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A5.2 Memory Attributes

Monitor Check that AWCACHE[3:2] is 2'b00 when AWVALID is HIGH and AWCACHE[1] is LOW !

Checks if the value of awcache[3:2]=2'b00 when awvalid is high and awcache[1] is also low

ERROR

AXI3 Onwards

Interface Requirements

awburst_reserved_val_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that a value of 2'b11 on AWBURST is not permitted when AWVALID is HIGH !

Checks if the value of awburst=2'b11 when awvalid is high

ERROR

AXI3 Onwards

Interface Requirements

awsize_data_width_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.1 Size attribute

Monitor Check that size of a transfer does not exceed the width of the data interface!

Checks if size of write transfer exceeds the width of the data bus

ERROR

AXI3 Onwards

Interface Requirements

valid_write_strobe_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.2.1 Write strobes

Monitor Check that valid Write Strobes are driven for each data beat!

WSTRB must not be asserted for invalid byte lanes

ERROR

AXI3 Onwards

Interface Requirements

awlen_wrap_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Write Transaction with burst type WRAP has a valid burst length!

Checks if write burst of WRAP type has a valid length

ERROR

AXI3 Onwards

Interface Requirements

awaddr_wrap_aligned_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.4 Burst attribute

Monitor Check that a Write Transaction with burst type WRAP has an aligned address!

Checks if write burst of WRAP type has an aligned address

ERROR

AXI3 Onwards

Interface Requirements

awaddr_4k_boundary_cross_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A4.1.2 Length attribute

Monitor Check that a write burst cannot cross a 4K boundary!

Checks if write burst cross a 4KB boundary

ERROR

AXI3 Onwards

Reset

bvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for BVALID low when reset is active!

Checks if bvalid is low when reset is active

ERROR

AXI3 Onwards

Reset

wvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for WVALID low when reset is active!

Checks if wvalid is low when reset is active

ERROR

AXI3 Onwards

Reset

awvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for AWVALID low when reset is active!

Checks if awvalid is low when reset is active

ERROR

AXI3 Onwards

Reset

rvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for RVALID low when reset is active!

Checks if rvalid is low when reset is active

ERROR

AXI3 Onwards

Reset

arvalid_low_when_reset_is_active_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for ARVALID low when reset is active!

Checks if arvalid is low when reset is active

ERROR

AXI3 Onwards

Outstanding

max_num_outstanding_xacts_check

Synopsys Defined

Checks that AXI master and AXI slave are not exceeding the user configured maximum number of outstanding transactions

Checks that AXI master and AXI slave are not exceeding the user configured maximum number of outstanding transactions (num_outstanding_xact) If num_outstanding_xact = -1 then num_outstanding_xact will not be considered, instead num_read_outstanding_xact and num_write_outstanding_xact will be considered for read and write transactions respectively. .

ERROR

AXI3 Onwards

Signal Stability

bvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for BVALID held steady until BREADY is asserted!

Checks if bvalid was interrupted before bready got asserted

ERROR

AXI3 Onwards

Signal Stability

wvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for WVALID held steady until WREADY is asserted!

Checks if wvalid was interrupted before wready got asserted

ERROR

AXI3 Onwards

Signal Stability

awvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for AWVALID held steady until AWREADY is asserted!

Checks if awvalid was interrupted before awready got asserted

ERROR

AXI3 Onwards

Signal Stability

rvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for RVALID held steady until RREADY is asserted!

Checks if rvalid was interrupted before rready got asserted

ERROR

AXI3 Onwards

Signal Stability

arvalid_interrupted_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.5 Dependencies between channel handshake signals

Monitor Check for ARVALID held steady until ARREADY is asserted!

Checks if arvalid was interrupted before arready got asserted

ERROR

AXI3 Onwards

Reset

signal_valid_bready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on BREADY During Reset!

Checks that BREADY is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_wready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on WREADY During Reset!

Checks that WREADY is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_awready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on AWREADY During Reset!

Checks that AWREADY is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_rready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on RREADY During Reset!

Checks that RREADY is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_arready_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on ARREADY During Reset!

Checks that ARREADY is not X or Z During Reset

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor Check for X or Z on BREADY!

BREADY should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor Check for X or Z on WREADY!

WREADY should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor Check for X or Z on AWREADY!

AWREADY should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor Check for X or Z on RREADY!

RREADY should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arready_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor Check for X or Z on ARREADY!

ARREADY should not be X/Z.

ERROR

AXI3 Onwards

Reset

signal_valid_aresetn_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on ARESETn!

ARESETn should not be X/Z.

ERROR

AXI3 Onwards

Reset

signal_valid_bvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on BVALID During Reset!

Checks that BVALID is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_wvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on WVALID During Reset!

Checks that WVALID is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_awvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on AWVALID During Reset!

Checks that AWVALID is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_rvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on RVALID During Reset!

Checks that RVALID is not X or Z During Reset

ERROR

AXI3 Onwards

Reset

signal_valid_arvalid_check_during_reset

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A3.1.2 Reset

Monitor Check for X or Z on ARVALID During Reset!

Checks that ARVALID is not X or Z During Reset

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor Check for X or Z on BVALID!

BVALID should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor Check for X or Z on WVALID!

WVALID should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor Check for X or Z on AWVALID!

AWVALID should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor Check for X or Z on RVALID!

RVALID should not be X/Z.

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arvalid_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor Check for X or Z on ARVALID!

ARVALID should not be X/Z.

ERROR

AXI3 Onwards

Signal Stability

signal_stable_bresp_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for signal stability when corresponding valid signal is high

Checks that BRESP is stable when BVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_bid_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for signal stability when corresponding valid signal is high

Checks that BID is stable when BVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bready_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BREADY is not X or Z when BVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bresp_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BRESP is not X or Z when BVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_bid_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.3 Write response channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BID is not X or Z when BVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_stable_wstrb_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WSTRB is stable when WVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_wdata_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that WDATA is stable when WVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wready_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WREADY is not X or Z when WVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wstrb_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WSTRB is not X or Z when WVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_wdata_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.2 Write data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WDATA is not X or Z when WVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_awprot_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWPROT is stable when AWVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_awaddr_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWADDR is stable when AWVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_awid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWID is stable when AWVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awready_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWREADY is not X or Z when AWVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awprot_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWPROT is not X or Z when AWVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awaddr_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWADDR is not X or Z when AWVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_awid_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWID is not X or Z when AWVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_rresp_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RRESP is stable when RVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_rdata_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RDATA is stable when RVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_rid_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for signal stability when corresponding valid signal is high

Checks that RID is stable when RVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rready_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RREADY is not X or Z when RVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rresp_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RRESP is not X or Z when RVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rdata_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RDATA is not X or Z when RVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_rid_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.2 Read data channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RID is not X or Z when RVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_arprot_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARPROT is stable when ARVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_araddr_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARADDR is stable when ARVALID is high

ERROR

AXI3 Onwards

Signal Stability

signal_stable_arid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARID is stable when ARVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arready_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARREADY is not X or Z when ARVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arprot_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARPROT is not X or Z when ARVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_araddr_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARADDR is not X or Z when ARVALID is high

ERROR

AXI3 Onwards

Signal Validity

signal_valid_arid_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARID is not X or Z when ARVALID is high

ERROR

AXI3,AXI4,AXI5,ACE5_Lite

Read interleaving property

read_data_interleave_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A6.6.1 Read data interleaving

Monitor check that Master VIP has recieved interleaved read data though the svt_axi_port_configuration::read_interleaving_disabled is set to 1

Checks that Master reports an error when it recieves interleaved read data.

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_awsize_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that AWSIZE is stable when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_awsize_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.1.1 Write request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWSIZE is not X or Z when AWVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Stability

signal_stable_arsize_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for signal stability when corresponding valid signal is high

Checks that ARSIZE is stable when ARVALID is high

ERROR

AXI3,AXI4,ACE,ACE_Lite,AXI5,AXI5_Lite,ACE5,ACE5_Lite,ACE5_LiteDVM

Signal Validity

signal_valid_arsize_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A2.2.1 Read request channel

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARSIZE is not X or Z when ARVALID is high

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity

wdatachk_parity_calculated_wdata_parity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Checks that the observed parity value as seen on the WDATACHK signal has matched with that of the calculated parity value on WDATA, if a parity mismatch is detected, then it will be converted in to poison

Checks the received WDATACHK is same as the parity calculated from WDATA in a write transaction.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity

received_parity_calculated_parity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Checks that the observed parity value as seen on the *chk signals has matched with that of the calculated parity value

Checks that observed parity value as seen in *chk signals match that of calculated parity value from respective signal.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity

rdatachk_parity_calculated_rdata_parity_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Checks that the observed parity value as seen on the RDATACHK signal has matched with that of the calculated parity value on RDATA

Checks the received RDATACHK is same as the parity calculated from RDATA in a read transaction.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_btracechk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that BTRACECHK is stable when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_buserchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that BUSERCHK is stable when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_brespchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that BRESPCHK is stable when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_bidchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that BIDCHK is stable when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_btracechk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BTRACECHK is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_buserchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BUSERCHK is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_brespchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BRESPHK is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_bidchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BIDCHK is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_breadychk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BREADYCHK is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_bvalidchk_when_bvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that BVALIDCHK is not X or Z when BVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rtracechk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RTRACECHK is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rpoisonchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RPOISONCHK is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_ruserchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RUSERCHK is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rrespchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RRESPCHK is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_rdatachk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RDATACHK is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_ridchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that RIDCHK is stable when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rtracechk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RTRACECHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rpoisonchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RPOISONCHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_ruserchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RUSERCHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rrespchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RRESPCHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rdatachk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RDATACHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_ridchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RIDCHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rreadychk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RREADYCHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_rvalidchk_when_rvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that RVALIDCHK is not X or Z when RVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_wtracechk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WTRACECHK is stable when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_wpoisonchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WPOISONCHK is stable when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_wuserchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WUSERCHK is stable when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_wstrbchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WSTRBCHK is stable when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_wdatachk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that WDATACHK is stable when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wtracechk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WTRACECHK is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wpoisonchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WPOISONCHK is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wuserchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WUSERCHK is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wstrbchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WSTRBCHK is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wdatachk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WDATACHK is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wreadychk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WREADYCHK is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_wvalidchk_when_wvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that WVALIDCHK is not X or Z when WVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_artracechk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARTRACECHK is stable when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_aruserchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARUSERCHK is stable when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_arctlchk0_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARCTLCHK0 is stable when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_araddrchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARADDRCHK is stable when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_aridchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that ARIDCHK is stable when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_artracechk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARTRACECHK is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_aruserchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARUSERCHK is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arctlchk0_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARCTLCHK0 is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_araddrchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARADDRCHK is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_aridchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARIDCHK is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arreadychk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARREADYCHK is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_arvalidchk_when_arvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that ARVALIDCHK is not X or Z when ARVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awtracechk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWTRACECHK is stable when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awuserchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWUSERCHK is stable when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awctlchk0_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWCTLCHK0 is stable when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awaddrchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWADDRCHK is stable when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Stability

signal_stable_awidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for signal stability when corresponding valid signal is high

Checks that AWIDCHK is stable when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awtracechk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWTRACECHK is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awuserchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWUSERCHK is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awctlchk0_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWCTLCHK0 is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awaddrchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWADDRCHK is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWIDCHK is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awreadychk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWVALIDCHK is not X or Z when AWVALID is high.

ERROR

AXI5,AXI5_Lite,ACE5_Lite,ACE5_LiteDVM

Parity: Signal Validity

signal_valid_awvalidchk_when_awvalid_high_check

AMBA AXI Protocol Specification ARM IHI 0022 Issue K: Section A17.2.3 Parity check signals

Monitor check for X or Z on signal when corresponding valid signal is high

Checks that AWVALIDCHK is not X or Z when AWVALID is high.

ERROR

AXI5_STREAM

Wakeup Signaling

stream_twakeup_tvalid_same_cycle_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.3 Wake-up signaling

If TWAKEUP and TVALID are HIGH in the same cycle, TWAKEUP must remain asserted until TREADY is asserted

Checks that if both twakeup and tvalid are asserted at the same cycle then twakeup must remain asserted until tready is asserted.

ERROR

AXI5_STREAM

Interface Parity

stream_observed_calculated_parity_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 5.3 Parity check

The observed parity value as seen on the check signal must match with that of the calculated parity value on the signal covered by a check signal

Checks that observed parity value as seen in *chk signals match that of calculated parity value.

ERROR

AXI5_STREAM

Interface Parity

stream_tdata_parity_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 5.3 Parity check

The observed parity value as seen on the TDATACHK signal must match with that of the calculated parity value on TDATA

Checks the received TDATACHK is same as the parity calculated from TDATA in a transfer.

ERROR

AXI5_STREAM

Interface Parity: Signal Stability

signal_stable_tdestchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TDESTCHK is stable when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Stability

signal_stable_tuserchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TUSERCHK is stable when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Stability

signal_stable_tidchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TIDCHK is stable when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Stability

signal_stable_tlastchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TLASTCHK is stable when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Stability

signal_stable_tkeepchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TKEEPCHK is stable when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Stability

signal_stable_tstrbchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TSTRBCHK is stable when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Stability

signal_stable_tdatachk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TDATACHK is stable when TVALID is high.

ERROR

AXI5_STREAM

Wakeup Signaling: Signal Validity

signal_valid_twakeup_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If twakeup is enabled, checks that twakeup is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_twakeupchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If twakeup is enabled, checks that twakeupchk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tdestchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tdest is enabled, checks that tdestchk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tuserchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tuser is enabled, checks that tuserchk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tidchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tid is enabled, checks that tidchk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tlastchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tlast is enabled, checks that tlastchk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tkeepchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tkeep is enabled, checks that tkeepchk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tstrbchk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tstrb is enabled, checks that tstrbchk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tdatachk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tdata is enabled, checks that tdatachk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_treadychk_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

Monitor check for X or Z on signal when corresponding valid signal is high

If tready is enabled, checks that treadychk is not X or Z when TVALID is high.

ERROR

AXI5_STREAM

Interface Parity: Signal Validity

signal_valid_tvalidchk_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section B.1 AXI-Stream signals

TVALIDCHK must not be X/Z

Checks that tvalidchk is not X or Z.

ERROR

AXI4_STREAM,AXI5_STREAM

Packet Checks

max_stream_burst_length_exceeded_check

Synopsys Defined

The burst length of received data stream should not exceed the maximum value allowed for stream_burst_length

Checks that the burst length of received data stream is not exceeding the maximum value allowed for stream_burst_length defined by 256

ERROR

AXI4_STREAM,AXI5_STREAM

Packet Checks

tid_or_tdest_change_before_tlast_assertion

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.6 Packet boundaries

The TID or TDEST must not change before the packet end, that is before TLAST assertion as all bytes within a packet are from the same source and for the same destination and have the same TID and TDEST values

Checks if TID or TDEST changed before the packet end (TLAST assertion).

ERROR

AXI4_STREAM,AXI5_STREAM

Interleaving Checks

stream_interleave_depth_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 4.1 Transfer interleaving

If a Receiver has a limited interleaving capability then the received data stream must not get interleaved beyond stream_interleave_depth value

Checks that received data stream is not interleaved beyond stream_interleave_depth value.
An error is issued if data stream is interleaved beyond this value

ERROR

AXI4_STREAM,AXI5_STREAM

Byte Checks

tstrb_low_when_tkeep_low_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.5.3 TKEEP and TSTRB combinations

TSTRB must be low when corresponding TKEEP is low

Checks that TSTRB is low if TKEEP is low

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

tvalid_interrupted_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2 Handshake signaling

Once TVALID is asserted, it must remain asserted until the handshake occurs

Checks if tvalid was interrupted before tready got asserted

ERROR

AXI4_STREAM,AXI5_STREAM

Reset Checks

tvalid_low_when_reset_is_active_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.8.2 Reset

During reset, TVALID must be driven LOW

Checks that TVALID is low when reset is active

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tdest_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TDEST is stable when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tuser_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TUSER is stable when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tid_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TID is stable when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tlast_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TLAST is stable when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tkeep_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TKEEP is stable when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tstrb_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TSTRB is stable when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Stability

signal_stable_tdata_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.2.1 Handshake with TVALID asserted before TREADY

Monitor check for signal stability when corresponding valid signal is high

Checks that TDATA is stable when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tdest_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tdest is enabled, checks that tdest is not X or Z when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tuser_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tuser is enabled, checks that tuser is not X or Z when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tid_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tid is enabled, checks that tid is not X or Z when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tlast_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tlast is enabled, checks that tlastchk is not X or Z when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tkeep_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tkeep is enabled, checks that tkeep is not X or Z when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tstrb_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tstrb is enabled, checks that tstrb is not X or Z when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tdata_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tdata is enabled, checks that tdata is not X or Z when TVALID is high.If svt_axi_port_configuration :: check_valid_data_bytes_only_enable is set to 1,this check is performed on masked_tdata(bytes of tdata having tstrb bit set to 1).

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tready_when_tvalid_high_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

Monitor check for X or Z on signal when corresponding valid signal is high

If tready is enabled, checks that tready is not X or Z when TVALID is high.

ERROR

AXI4_STREAM,AXI5_STREAM

Signal Validity

signal_valid_tvalid_check

AMBA AXI-Stream Protocol Specification ARM IHI 0051B ID040921: Section 2.1 Signal list

TVALID must not be X/Z

Checks that tvalid is not X or Z.

ERROR

None

master_slave_xact_data_integrity_check

Monitor Check that data in downstream transaction matches that in the upstream transaction

ERROR

None

data_integrity_check

Monitor Check that transaction data contents are consistent with memory

ERROR

None

slave_transaction_routing_check

Monitor Check that transaction is routed to the correct slave based on address

ERROR

AMBA Multi Chip System

Custom Combined Write CMO Check

rn_combined_writecmo_xact_propagated_to_slave_custom_check

ARM AES 0003 v6.0

Monitor Custom Check that RN Combined Write and PCMO type transaction propagation to slave by HN should be valid as per the configuration attribute svt_chi_hn_configuration::combined_write_and_cmo_propagation_to_slave_policy

This check ensure the propagation of RN Combined_Write_and_CMO type transaction to Slave by a HN is as per the value programmed by the attribute combined_write_and_cmo_propagation_to_slave_policy. For a HN, if combined_write_and_cmo_propagation_to_slave_policy is set to ALWAYS_FWD_COMBINED_WRITE_AND_CMO_TO_SLAVE:

Every RN Combined_Write_and_CMO type transaction to that HN there should be a corresponding Combined_Write_and_CMO type Slave transaction.

For a HN, if combined_write_and_cmo_propagation_to_slave_policy is set to ALWAYS_FWD_STANDALONE_WRITE_TO_SLAVE:

Every RN Combined_Write_and_CMO type transaction to that HN there should be a corresponding Standalone Write Slave transaction.

For a HN, if combined_write_and_cmo_propagation_to_slave_policy is set to Default value EITHER_FWD_STANDALONE_WRITE_OR_COMBINED_WRITE_AND_CMO_TO_SLAVE:

This Check is not executed.

ERROR

AMBA Multi Chip System

coherent rsp

coherent_resp_start_conditions_check

ARM-IHI0050A, ARM-IHI0050B

Monitor Check that the response to a coherent transaction is not started before appropriate RN-Fs are snooped

Checks that the response to a coherent transaction is not started before the appropriate RN-Fs are snooped.
This check is applicable only when svt_chi_system_configuration :: perform_expected_snoops_checks is set to 1.

ERROR

AMBA Multi Chip System

Exclusive Access

exclusive_chi_transaction_type_check

ARM-IHI0050A: 6.3, ARM-IHI0050B: 6.3

Monitor check that observed exclusive transaction is one of the allowed coherent/non-coherent exclusive load/store transaction types.

Checks that before processing any exclusive transactions from RN if that transaction is part of an allowed transaction type for an exclusive access.
Following are the permitted transaction types to have svt_chi_base_transaction :: is_exclusive set to 1: CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER) Prefetchtgt(is_exclusive is a don't care field for prefetchtgt so it is permitted to take any value)
This check is performed when an RN transaction is started.

ERROR

AMBA Multi Chip System

Exclusive Access

exclusive_store_resp_check

ARM-IHI0050A: 6.2, ARM-IHI0050B: 6.2

Monitor check that the resposne for exclusive store transaction matches the expected response for the given lpid and address.

Checks that the resposne for exclusive store transaction(CleanUnique, WriteNoSnp*) matches the expected response(svt_chi_transaction :: response_resp_err_status) for the given lpid and address.
The expected response is determined by the exclusive monitor.
This check is executed when the store transaction is complete.

ERROR

AMBA Multi Chip System

Exclusive Access

exclusive_load_resp_check

ARM-IHI0050A: 6.2, ARM-IHI0050B: 6.2

Monitor check that the resposne for exclusive load transaction matches the expected response for the given lpid and address.

Checks that the resposne for exclusive load transaction(ReadNoSnp, ReadShared, ReadClean, ReadNotSharedDirty) matches the expected response(svt_chi_transaction :: data_resp_err_status) for the given lpid and address.
The expected response is determined by the exclusive monitor.
This check is executed when the load transaction is complete.

ERROR

AMBA Multi Chip System

cmos

forward_cmos_to_slave_check

ARM-IHI0050B: 4.2.2

Monitor Check that the HN propagates the CMOs beyond the HN

When HN is configured to send the CMOs to downsteam caches, then all the slaves whose address belogs to them, should receive the CMO transactions. System monitor checks if all the slaves got the CMOs corresponding to CMOs at RN node.
This check is performed in report phase where all the un-associated system transactions are found.

ERROR

AMBA Multi Chip System

Memory Tagging check

slave_tag_integrity_check

ARM AES 0003 v6.0

Monitor Check that the slave transaction tag matches with the Tags in the slave memory

Checks that the Tags in a transaction routed to the slave matches with the Tags within the memory of that slave when the transaction ends successfully.

ERROR

AMBA Multi Chip System

poison integrity

slave_poison_integrity_check

ARM-IHI0050B, ARM-IHI0050C

Monitor Check that the slave transaction poison matches with content of slave memory

Checks that the poison value of a transaction routed to the slave matches with the poison within the memory of that slave when the transaction ends successfully. This check is supported only when the transaction is routed to a CHI SN.
In the case of the transaction is routed to CHI SN, this check is performed under following conditions:

The transaction doesn't have NDERR response
This check currently does not consider transactions with overlapping addresses that are active simultaneously.

ERROR

AMBA Multi Chip System

data integrity

slave_data_integrity_check

ARM-IHI0050A, ARM-IHI0050B

Monitor Check that the slave transaction data matches with content of slave memory

Checks that the data of a transaction routed to the slave matches with the data within the memory of that slave when the transaction ends successfully. The slave can be a CHI SN or an AXI slave. In the case of the transaction is routed to AXI slave, this check is performed under following conditions:

The CHI system monitor (that is part of a CHI system ENV) and the AXI slave (that is part of an AXI system ENV) are part of an AMBA system ENV
The mapping between CHI SNs and AXI slaves is provided through the APIs of AMBA system configuration
Methodology used is UVM

In the case of the transaction is routed to CHI SN, this check is performed under following conditions:

This check currently does not consider transactions with overlapping addresses that are active simultaneously.

ERROR

AMBA Multi Chip System

dvm

interconnect_dvm_snoop_timing_check

ARM-IHI0050A: 8.1, ARM-IHI0050B: 8.1

Monitor Check that the interconnect sends DVM Snoops only after DBIDResp is issued to the initiating RN and NCBWrData is received for the corresponding DVM request.

Checks that the interconnect issues DBIDResp and waits for the WriteData for a DVM request before issuing SnpDVMOp requests.

ERROR

AMBA Multi Chip System

dvm

valid_dvm_response_from_interconnect_check

ARM-IHI0050A: 8.1, ARM-IHI0050B: 8.1

Monitor Check that the Comp response for a DVMOp requestnon-sync,sync indicates an Error resposne if any of the associated snoops has Error response.

Checks that the interconnect sends correct response to the DVMOp(non-sync,sync) requests from then initiating RNs based on the response received from the SnpDvmop(non-sync,sync) from the snooped Rns. This check ensures that this comp response to the DVMOp request(non-sync,sync) is sent as Error resposne if any of the associated snoops has Error response.

ERROR

AMBA Multi Chip System

dvm

interconnect_dvm_response_timing_check

ARM-IHI0050A: 8.1, ARM-IHI0050B: 8.1

Monitor Check that the interconnect waits for the responses for all corresponding SnpDVMOpnon-sync,sync requests before responding to original DVMOpnon-sync,sync transaction.

Checks that the interconnect waits for the responses to SnpDVMOp(non-sync,sync) requests from then snooped RNs before sending a comp response to original DVMOp request(non-sync,sync). This check ensures that this comp response to the DVMOp request(non-sync,sync) is sent only after all associated snoops are complete.
This check will only be performed when there are no error responses seen in the Data/Response flits corresponding to the DVMOp transaction. This is because the Interconnect behaviour in case of error responses in DVMOp transactions is implementation defined.

ERROR

AMBA Multi Chip System

dvm

interconnect_dvm_sync_snoop_transaction_association_check

ARM-IHI0050A: 8.1, ARM-IHI0050B: 8.1

Monitor Check that interconnect broadcasts SnpDVMOpsync transactions to all other RNs that are DVM snoopable when it receives a DVMOpsync request transaction from an RN.

Checks that interconnect broadcasts SnpDVMOp(sync) transactions to all other RNs that are DVM snoopable when it receives a DVMOp(sync) request transaction from an RN.
This check will only be performed when there are no error responses seen in the Data/Response flits corresponding to the DVMOp transaction. This is because the Interconnect behaviour in case of error responses in DVMOp transactions is implementation defined.

ERROR

AMBA Multi Chip System

dvm

interconnect_dvm_operation_snoop_transaction_association_check

ARM-IHI0050A: 8.1, ARM-IHI0050B: 8.1

Monitor Check that interconnect broadcasts SnpDVMOpnon-sync transactions to all other RNs that are DVM snoopable when it receives a DVMOpnon-sync request transaction from an RN.

Checks that interconnect broadcasts SnpDVMOp(non-sync) transactions to all other RNs that are DVM snoopable when it receives a DVMOp(non-sync) request transaction from an RN.

ERROR

AMBA Multi Chip System

hazard

coherent_copyback_atomic_hazard_check

ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent copyback request and a coherent atomic request to the same cacheline(copyback-atomic hazard) are correctly handled by HN.
While there is a pending coherent copyback request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the atomic transaction is completed and copyback-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_atomic_copyback_hazard_check

ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent copyback request to the same cacheline(atomic-copyback hazard) are correctly handled by HN.
While there is a pending atomic request, if a Copyback request is received to the same cacheline, the coherent copyback request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent copyback transaction is completed and atomic-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_copyback_write_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent write request to the same cacheline(copyback-write hazard) are correctly handled by HN.
While there is a pending copyback request, if a Write request is received to the same cacheline, the coherent write request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and copyback-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_write_copyback_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a Copyback request to the same cacheline(write-copyback hazard) are correctly handled by HN.
While there is a pending coherent write request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the copyback transaction is completed and write-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_copyback_read_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent read request to the same cacheline(copyback-read hazard) are correctly handled by HN.
While there is a pending copyback request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and copyback-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_read_copyback_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a Copyback request to the same cacheline(read-copyback hazard) are correctly handled by HN.
While there is a pending coherent read request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the copyback transaction is completed and read-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

Memory Tagging check

tag_not_dirty_at_any_rn_when_snpmakeinvalid_issued_check

ARM AES 0003 v6.0

Monitor Check that the interconnect issues SnpMakeInvalid for a WriteUnique, MakeUnique or MakeInvalid transaction only when it can be sure that the Snoopee does not hold dirty tags or when the corresponding coherent transaction is a MakeUnique or WriteUniqueFull with TagOp set to UPDATE.

Checks that the HN issues a SnpMakeInvalid corresponding to a coherent Write, MakeUnique or MakeInvalid transaction only when either the HN can be sure that the Snooped RN does not hold dirty tags or when the RN transaction is a WriteUniqueFull or MakeUnique with TagOp set to Update.
This check is only performed when the Snooped RN supports memory tagging and Snoop filter is enabled for the HN.
The HN can be sure that a Snoopee does not contain dirty tags when the cache line state tracked by its Snoop filter is not UC, UD or SD.
The system monitor refers to its own snoop filter model to determine if it's possible for the snooped RN to have cached Tag in dirty state.
If this check must not be performed for certain addresses, it can be bypassed using the system monitor callback "pre_check_execute".

ERROR

AMBA Multi Chip System

coherent and snoop

valid_snp_xact_type_for_makereadunique_check

ARM AES 0003 v7.0

Monitor Check that the Snoop transaction is one of the valid snoop types for MakeReadUnique transaction.

Checks that the Snoop transaction is one of the valid snoop types for MakeReadUnique transaction.

ERROR

AMBA Multi Chip System

Memory Tagging check

coherent_and_snoop_tag_match_check

ARM AES 0003 v6.0

Monitor Check that Tags returned to initiating RN matches with the full cacheline tags received from associated snoop transaction

Checks that Tags returned to initiating RN in the Read data response matches with the Tags received from associated snoop transaction under following scenarios:
- Scenario 1: Full cacheline Tag are returned for one of the associated snoop transaction, with TagOp in the snoop data response set to either TAG_TRANSFER or TAG_UPDATE.
- Scenario 2: Partial cacheline Tags are returned for one of the associated snoop transaction with TagOp in the snoop data response set to TAG_UPDATE.
This check is not performed in case partial cacheline Tags are returned for one of the snoop transaction but HN-F L3 doesn't have the cacheline.
This check is applicable when : coherent Read transaction has TagOp in the data response set to Transfer or Update and there are associated snoop transactions that returned Tags.
This check is performed when the coherent transaction is complete

ERROR

AMBA Multi Chip System

Memory Tagging check

snoop_tag_integrity_check

ARM AES 0003 v6.0

Monitor Check that the Tags transferred in snoop response data matches with system monitor HN-F L3 view when the TagOp in the SnpRspData is set to Transfer and final state resp[1:0] is set to UC/SC/I.

Checks that clean Tags returned for a Snoop transaction are consistent with system monitor HN(HN-F L3/HN-I memory).
This check is applicable only when the TagOp in the Snoop data response is set to Transfer and the final state indicated in the Snoop response is Clean.

ERROR

AMBA Multi Chip System

coherent rsp

cache_state_of_stash_resp_check

ARM-IHI0050E.b: 7

Monitor Check that no peer RN has cached the line when the cache state is UC/UD in the DataPull read response of Stash snoop

Checks that no peer RN has cached the line when the Cache state in the DataPull read response of the Stash snoop is UC/UD.The checker relies on the Snoop filter in the System monitor to check if any peer RNs might have cached the line

ERROR

AMBA Multi Chip System

coherent and snoop

stash_data_pull_integrity_check

ARM-IHI0050B: 7

Monitor Check that the Data Pull Read data returned for Stash type Snoops is as expected

Performs data integrity checks on the Data Pull Read data that is received by a Stash target. In case of WriteUnique*Stash transactions, if the Stash snoop involves Data pull, the Data Pull Read data should match the WriteUnique*Stash data. In case of other Stash transactions, if the Stash snoop involves Data pull and the DataPull Read data is returned in clean state, the Data Pull Read data must match the data in the memory.

ERROR

AMBA Multi Chip System

coherent and snoop

associated_snoop_trace_tag_validity_check

ARM-IHI0050B: 11.2

Monitor Check that the associated snoop transaction has valid trace_tag value

The snoops generated in responce to a request from an RN must have valid trace tag value.

ERROR

AMBA Multi Chip System

coherent and snoop

only_one_snoop_with_rettosrc_check

ARM-IHI0050B: 4.8

Monitor Check that only one snoop transaction, corresponding to a given coherent transaction, has RetToSrc asserted

Checks that for a given coherent transaction, only one of the associated snooped RNs has RetToSrc set to 1 (svt_chi_common_transaction :: ret_to_src = 1).
This check is performed when the coherent transaction is complete.

ERROR

AMBA Multi Chip System

coherent and snoop

only_one_forward_snoop_per_coherent_transaction_check

ARM-IHI0050B: 4.3

Monitor Check that only one snoop transaction, corresponding to a given coherent transaction, is a forwarding type Snoop

Checks that for a given coherent transaction, only one of the associated snoop requests is a forward type Snoop (is_forward_type_snoop = 1).
This check is performed when the coherent transaction is complete.

ERROR

AMBA Multi Chip System

coherent rsp

cache_state_of_xact_resp_check

ARM-IHI0050E.b: 4.7

Monitor Check that no peer RN has cached the line when the Cache state is UC/UD in the Comp/CompData response of coherent transactions

Checks that no peer RN has cached the line when the Cache state is UC/UD in the Comp/CompData of coherent transactions.The checker relies on the Snoop filter in the System monitor to check if any peer RNs might have cached the line

ERROR

AMBA Multi Chip System

coherent and snoop

coherent_snoop_type_match_check

ARM-IHI0050A: 4.4 Table 4-1, ARM-IHI0050B: 4.4 Table 4-3

Monitor Check that the snoop transaction type corresponds to the coherent transaction type of initiating master

Checks that the associated snoop transaction type corresponds to the coherent transaction type from initiating RN as per:
- Table 4-1 of CHI Issue A specification
- Table 4-3 of CHI Issue B specification for the supported coherent and snoop types
This check is performed when coherent transaction is complete, and when a given snoop transaction is associated that is:
- not sent to initiating RN (snoop_not_sent_to_initiating_master_check not failed)
- only one snoop is outstanding at the snooped RN to the given cache line address
- not aborted

ERROR

AMBA Multi Chip System

coherent and snoop

snoop_not_sent_to_initiating_master_check

ARM-IHI0050A, ARM-IHI0050B

Monitor Check that a snoop is not sent to the initiating master

Checks that an associated snoop transaction is not sent to the RN, that initiated corresponding coherent transaction.
This check is performed once coherent transaction is complete, and snoop transaction is assoiated to coherent transaction.
Note that this check doesn't include DVM transactions.

ERROR

AMBA Multi Chip System

coherent and snoop

overlapping_addr_sequencing_check

ARM-IHI0050A: 5.4, ARM-IHI0050B: 4.9.2

Monitor Check that if two masters initiate requests to access the same cache line simultaneously, one master is sequenced after the other

Checks that if more than one RN initiate requests to access the same cache line simultaneously, one RN is sequenced after the other. If more than one RN initiate requests to access the same cache line simultaneously, the interconnect is expected to process these simultaneous requests one after another. In the case that this results in a scenario that is not corresponding to the check svt_amba_multi_chip_system_err_check :: snoop_not_sent_to_initiating_master_check, then the following details are applicable.

ERROR

AMBA Multi Chip System

coherent and snoop

snoop_addr_matches_coherent_addr_check

ARM-IHI0050A: 4.3, ARM-IHI0050B: 4.3

Monitor Check that the address of a snoop transaction must match one of the outstanding coherent transactions

Checks that the address of a snoop transaction must match one of the outstanding coherent transactions
This check is performed when the snoop transaction starts, even before coherent to snoop transaction association is done.
Note that this doesn't check for snoop transaction type that corresponds to coherent transaction type
The coherent transaction types that are checked for matching address are all the types excluding the following: WriteNoSnp*, ReadNoSnp, WriteBack*, WriteClean*, Evict, WriteEvictFull.

ERROR

AMBA Multi Chip System

snoop rsp

only_one_snoop_returns_data_check

ARM-IHI0050A: 4.1.1, ARM-IHI0050B

Monitor Check that only one snoop transaction returns data

Checks that for a given coherent transaction, only one of the associated snooped RNs responded to the snoop requests with data (svt_chi_snoop_transaction :: snp_rsp_datatransfer = 1).
This check is performed when the coherent transaction is complete.

ERROR

AMBA Multi Chip System

snoop rsp

snoop_resp_passdirty_check

ARM-IHI0050A: 4.7.5, ARM-IHI0050B: 4.7.6

Monitor Check that no two associated snooped RNs responded to snoop transactions with PassDirtyresp[2] in the snoop responses asserted.

Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with PassDirty(resp[2] - svt_chi_common_transaction :: resp_pass_dirty) asserted to HN.
This check is performed when the coherent transaction is complete.

ERROR

AMBA Multi Chip System

snoop rsp

snoop_resp_wasunique_check

ARM-IHI0050A: 4.7.5, ARM-IHI0050B: 4.7.6

Monitor Check that no two associated snooped RNs responded to snoop transactions with cache line state as Unique.

Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with 'final cache line state as Unique'(WasUnique response asserted) at the respective snooped RNs.
This check is performed when the coherent transaction is complete.

ERROR

AMBA Multi Chip System

coherent and snoop

coherent_xact_with_no_snoop_check

ARM-IHI0050A: 4.4 Table 4-1, ARM-IHI0050B: 4.4 Table 4-3

Monitor Check that non-coherent requests READNOSNOOP,WRITENOSNOOP -- Except in case of invisibile cache mode at HN-F L3 , copyback requests WRITEBACK,WRITECLEAN,WRITEEVICTFULL and EVICT do not cause a snoop of cached RNs.

Checks that READNOSNOOP,WRITENOSNOOP*,WRITEBACK*,WRITECLEAN*, WRITEEVICTFULL and EVICT transactions do not lead to snooping of peer RN-Fs.
This check is performed when the snoop transaction starts.
The check compares the address of the snoop transaction with outstanding coherent transactions.
The check does not compare the snoop transaction type with coherent transaction type.
Note that, in case of Invisible Cahe Mode at HN, it's possible to have Snoops for non-coherent transactions, please refer to svt_chi_system_configuration :: set_hn_invisible_cache_mode_enable for more details. In this case, the check factors in the set_hn_invisible_cache_mode_enable() settings along with Snoop Filter entries to validate the correctness of observed snoops for the non-coherent requests.

ERROR

AMBA Multi Chip System

coherent and snoop

coherent_and_snoop_data_match_check

ARM-IHI0050A: 4.3, ARM-IHI0050B: 4.3

Monitor Check that data returned to initiating RN matches with the full cacheline data received from associated snoop transaction

Checks that data returned to initiating RN matches with the data received from associated snoop transaction under following scenarios:
- Scenario 1: Full cacheline data is returned for one of the associated snoop transaction
- Scenario 2: Partial cacheline data is returned for one of the associated snoop transaction and HN-F L3 has the cacheline
This check is not performed in case of partial cacheline data is returned for one of the snoop transaction and HN-F L3 doesn't have the cacheline.
This check is applicable when : coherent transaction has data response and there are associated snoop transactions
This check is performed when the coherent transaction is complete

ERROR

AMBA Multi Chip System

data integrity

snoop_data_integrity_check

ARM-IHI0050A: 4.7.5, ARM-IHI0050B: 4.7.6

Monitor Check that snoop response data from snooped RN matches with system monitor HN-F L3 view when the final state resp[1:0] in the SnpRspData flits is set to UC/SC/I.

Checks that data in snoop transaction is consistent with system monitor HN-F L3 view when the snoop transaction completes.
This check is performed when the coherent transaction is complete and system monitor has already associated the snoop transactions.
This check is not applicable in case the snoop transaction returns the dirty data.

ERROR

AMBA Multi Chip System

data integrity

copyback_data_integrity_check

ARM-IHI0050A: 4.7.3, ARM-IHI0050B: 4.7.3

Monitor Check that CopyBack write data from RN matches with system monitor HN-F L3 view when the current state resp[1:0] in the CopyBack write DAT flits is set to UC/SC.

Checks that data in transaction is consistent with data in system monitor HN-F L3 view, when the CopyBack transaction completes.
This check is applicable when the current state in the CopyBack transaction is UC/SC and there are no overlapping transactions to the same cacheline.
In case the current state is dirty, system monitor HN-F L3 view will be updated with the CopyBack write data. There is no need to compare the CopyBack write data with system monitor HN-F L3 view in such a case.
In case the current state is I, interconnect is expected to ignore/drop the CopyBack write data. System monitor HN-F L3 view will not be updated with the CopyBack write data in this case. Also there is no need to compare CopyBack write data with system monitor HN-F L3 view.
Current State indicates the cacheline state at the RN when the data is sent (resp[1:0]).

ERROR

AMBA Multi Chip System

MPAM

matching_mpam_values_for_original_request_and_associated_stash_snoop_check

ARM-IHI-0050D: 11.2

Monitor Check that all the mpam attributes of RN transaction are propagated to stash snoops

The stash-snoops generated in response to a request from an Rn must have valid mpam attributes.

ERROR

AMBA Multi Chip System

MPAM

matching_mpam_values_for_original_request_and_associated_slave_xact_check

ARM-IHI-0050D: 11.2

Monitor Check that all the mpam attributes of RN transaction are propagated to slaves

The MPAM fields mpam_ns, mpam_perfmongroup and mpam_partid must be preserved on a request from HN to SN that is sent in response to a request to HN.
This check is performed after master-slave association is complete.

ERROR

AMBA Multi Chip System

hazard

coherent_atomic_atomic_hazard_check

ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and another coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and another atomic request to the same cacheline(atomic-atomic hazard) are correctly handled by HN.
While there are pending coherent atomic and atomic requests to the same cacheline, only one of those coherent atomic or atomic requests are in progress at any given point in time.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent atomic or atomic transaction is completed and atomic-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_atomic_read_hazard_check

ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent read request to the same cacheline(atomic-read hazard) are correctly handled by HN.
While there is a pending atomic request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and atomic-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_read_atomic_hazard_check

ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent atomic request to the same cacheline(read-atomic hazard) are correctly handled by HN.
While there is a pending coherent read request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the atomic transaction is completed and read-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_atomic_write_hazard_check

ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent write request to the same cacheline(atomic-write hazard) are correctly handled by HN.
While there is a pending atomic request, if a write request is received to the same cacheline, the coherent write request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and atomic-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_write_atomic_hazard_check

ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent atomic request to the same cacheline(write-atomic hazard) are correctly handled by HN.
While there is a pending coherent write request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the atomic transaction is completed and write-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

Memory Tagging check

expected_tag_match_result_check

ARM AES 0003 v6.0

Monitor Check that the result indicated in the Tag Match response for a Write or Atomic transaction matches the result expected by the System monitor

Checks that the Tag matching result indicated in Resp field of the TagMatch response sent by a Home node for a Write or Atomic transaction with TagOp set to Match matches with the result expected by the System monitor.
In case the Home node does not support memory tagging, it is expected that the TagMatch response will indicate that the Match operation failed.
This check is performed only when the TagOp in the Write data response of the Write or Atomic transaction is set to Match(TAG_FETCH_MATCH).

ERROR

AMBA Multi Chip System

hazard

coherent_read_read_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and another coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent read request and another coherent read request to the same cacheline(read-read hazard) are correctly ordered by HN
There should not be more than one coherent read transactions to the same cacheline that are in progress at any given point in time
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and a read-read hazard condition was detected when it was started
This check doesn't include coherent read transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

AMBA Multi Chip System

hazard

coherent_req_compack_hazard_check

ARM-IHI0050A: 5.4.1, ARM-IHI0050B: 5.6.1

Monitor check that - for a given cacheline, hazard condition between a Coherent request and CompAck is handled correctly by the HN

Checks that hazard condition between a pending CompAck and another coherent request to same cacheline are correctly ordered by HN.
When HN receives a new RN request transaction to a cacheline while there's a pending transaction to the same cacheline that is yet to receive a CompAck, HN must not process the new request till the CompAck for the outstanding transaction is received.
This check is not applicable for the coherent requests from ACE-Lite master as CompAck is not present in ACE-Lite protocol.
This check is performed when a coherent request receives a response from HN

ERROR

AMBA Multi Chip System

hazard

coherent_write_write_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and another coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent write request and another coherent write request to the same cacheline(write-write hazard) are correctly ordered by HN
There should not be more than one coherent write transactions to the same cacheline that are in progress at any given point in time
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and a write-write hazard condition was detected when it was started
This check doesn't include coherent write transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_write_read_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent read request to the same cacheline(write-read hazard) are correctly handled by HN.
While there is a pending write request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and write-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

hazard

coherent_read_write_hazard_check

ARM-IHI0050A: 5.4.2, ARM-IHI0050B: 5.6.2

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent write request to the same cacheline(read-write hazard) are correctly handled by HN.
While there is a pending coherent read request, if a write request is received to the same cacheline, the write request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the write transaction is completed and read-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

AMBA Multi Chip System

DWT

no_snoop_resp_dirty_with_dwt_check

ARM AES 0003 v8.0

Monitor Check that - For a partial cacheline coherent transaction from RN, HN doesn't issue DWT request to Slave if any of the associated snoop transactions return dirty data

Checks that DWT is not used by the HN if any of the associated snoop transactions returns dirty data.
This check is performed when the RN transaction is complete.
Applicable only for partial cacheline coherent writes

ERROR

AMBA Multi Chip System

DWT

comp_after_snoop_xacts_completion_with_dwt_check

ARM AES 0003 v8.0

Monitor Check that the HN issued Comp response to the requester after receiving all snoop responses for any snoops that were sent

The Comp response must be sent only after receiving all snoop responses for any snoops that were sent. THe HN must wait for all the associated snoop transactions to complete, before initiating a comp response to the requester.
This check is performed when the RN transaction is complete and there are associated snoop transactions.

ERROR

AMBA Multi Chip System

Custom Combined Write CMO Check

valid_combined_writecmo_slave_xact_custom_check

ARM AES 0003 v6.0

Monitor Custom Check that generation of Combined Write and PCMO type transaction to slave should always be associated with a Combined Write and PCMO type RN transaction

Check that when a Combined Write and (P)CMO type transaction is observed on the slave, there must be a corresponding RN transaction which is of Combined Write and (P)CMO type to the same cacheline.

ERROR

AMBA Multi Chip System

Memory Tagging check

write_tag_integrity_check

ARM AES 0003 v6.0

Monitor Check that Tags transferred in clean state by an RN for a Write transaction matches with system monitor HNHN-F L3/HN-I memory view

Checks that Clean Tags transferred in Write transaction data are consistent with system monitor HN(HN-F L3/HN-I memory) when the Write transaction completes at the RN.
This check is applicable only when the TagOp in the Write data is set to Transfer.

ERROR

AMBA Multi Chip System

Memory Tagging check

atomic_returned_initial_tag_integrity_check

ARM AES 0003 v6.0

Monitor Check that Tags returned in clean state by an HN for an AtomicLoad/Swap/Compare transaction matches with system monitor HNHN-F L3/HN-I memory view

Checks that the Tags in the returned initial data response are consistent with the system monitor memory view when an Atomic LOAD/SWAP/COMPARE completes at an RN.
In case there are associated snoops wherein Tags were transferred in the Snoop data response, the system monitor compares the Tags in the returned initial data response with the corresponding Tags in the snoop data response.
In case there are no associated snoops or none of the Snooped RNs returned Tags, the system monitor compares the Tags in the returned initial data response with the corresponding Tags in the system monitor memory.

ERROR

AMBA Multi Chip System

Memory Tagging check

read_tag_integrity_check

ARM AES 0003 v6.0

Monitor Check that Tags returned in clean state by an HN for a Read transaction matches with system monitor HNHN-F L3/HN-I memory view when: the snooped RNs return tags in clean state OR none of the snooped RNs return any tags OR there are no snoops

Checks that clean Tags returned for a read transaction are consistent with system monitor HN(HN-F L3/HN-I memory) when the read transaction completes at RN.
This check is applicable only when the TagOp in the Read data is set to Transfer and the snooped RNs return the Tags in clean state or none of the snooped RNs return any Tags.

ERROR

AMBA Multi Chip System

DMT

dmt_after_snoop_xacts_completion_check

ARM-IHI0050B 2.3.1

Monitor Check that - For a given RN transaction, HN issues DMT request to Slave only after the completion of all the associated snoop transactions

If HN needs to send snoop requests for a given RN transaction, the HN must wait for all the associated snoop transactions to complete, before initiating a corresponding DMT request to slave.
This check is performed when the RN transaction is complete and there are associated snoop and slave transactions.

ERROR

AMBA Multi Chip System

DMT

valid_xacts_for_optimized_dmt_check

ARM-IHI0050B 2.3.1

Monitor Check that - HN issues optimized DMT request to Slave only for RN transactions of the type ReadNoSnp and ReadOnce with ExpCompAck asserted OR order set to NO_ORDERING_REQUIRED

Checks that HN issues optimized DMT request to Slave only for RN transactions of the type ReadNoSnp and ReadOnce with ExpCompAck asserted OR order set to NO_ORDERING_REQUIRED
This check is performed when the RN transaction is complete and there are associated slave transactions.

ERROR

AMBA Multi Chip System

DMT

no_snoop_resp_dirty_with_dmt_check

ARM-IHI0050B 2.3.1

Monitor Check that - For a given RN transaction, HN doesn't issue DMT request to Slave if any of the associated snoop transactions return full cacheline dirty data

Checks that DMT is not used by the HN to respond back to initiating RN's transaction, if any of the associated snoop transactions returns full cacheline dirty data.
This check is performed when the RN transaction is complete.

ERROR

AMBA Multi Chip System

ATOMICOPS

comp_or_compdata_response_after_snoop_xacts_completion_for_atomic_transaction_check

ARM-IHI0050B 4.2

Monitor Check that - The Completer must wait for all snoop responses before sending the Comp or CompData response.

The Completer must wait for all snoop responses before sending the Comp response in case of atomic store or CompData response in case of atomic load, swap and compare transactions.

ERROR

AMBA Multi Chip System

data integrity

atomic_returned_initial_data_integrity_check

ARM-IHI0050B 2.3

Monitor Check that the returned initial data is consistent with the system monitor when read data completes at RN for Atomic LOAD/SWAP/COMPARE.

Checks that the returned initial data is consistent with the system monitor memory view when an Atomic LOAD/SWAP/COMPARE completes at an RN.
In case there are associated snoops with data transfer the system monitor compares the returned initial data with the corresponding bytes in the snoop data.
In case there are no associated snoops or none of the associated Snoop requests received a data response, the system monitor compares the returned initial data with the corresponding bytes in the memory.

ERROR

AMBA Multi Chip System

Transaction ordering

ordering_of_xacts_when_dbidrespord_received_check

ARM-AES 0003 v8: 8

Monitor Checks that the associated slave transactions of a request ordered or unordered RN transaction should be started only after all the associated slave transactions of a prior unordered or request ordered RN xact that had received a DBIDRESPORD

Checks that the interconnect maintains the order in which slave transactions are issued corresponding to an unordered or request ordered transaction that receives a DBIDRespOrd and a subsequent unordered or Request ordered transaction targeting the same address.

ERROR

AMBA Multi Chip System

Transaction ordering

slave_xacts_ordering_for_ordered_rn_xact_check

ARM-IHI0050B: 2.4.4

Monitor Check that the associated slave xacts of ordered RN transaction should be started after all the associated slave xacts of earlier issued ordered RN xact

The interconnect must maintain the order in which slave transactions are issued corresponding to ordered RN transactions from an RN to same address/address range

ERROR

AMBA Multi Chip System

Propagation of Attr

memory_attributes_propagation_check

ARM-IHI0050B: 2.9.3

Monitor Check that all the memory attributes of RN transaction are propagated to slaves

The MemAttr bits EWA, Device, Cacheable, and Allocate, must be preserved on a request from HN to SN that is sent in response to a request to HN.
This check is performed after master-slave association is complete.

ERROR

AMBA Multi Chip System

coherent rsp

coherent_resp_passdirty_check

ARM-IHI0050A: 11.9.20 Table 11-26 and 11-27, ARM-IHI0050B: 12.9.36 Table 12-35 and 12-36

Monitor Check that the PassDirty response to initiating RN is correct

Checks that the PassDirty response(resp[2]) in the coherent response to initiating RN-F is correct.
In case of ReadShared, ReadUnique, ReadNotSharedDirty(CHI-B OR LATER): If PassDirty was asserted for any snoop response received by the interconnect, and the interconnect has not asserted PassDirty in the coherent response to initiating RN, it's possible that Interconnect has taken the responsibility of updating the L3 cache or main memory. Note that this check does not verify if the interconnect updated L3 or main memory with dirty data. However, in this case, if the HN is not able to properly handle the dirty data, a subsequent read to same cacheline would result into read_data_integrity_check failure.
This check is performed when the coherent transaction is complete.

ERROR

AMBA Multi Chip System

coherent rsp

coherent_resp_isshared_check

ARM-IHI0050A: 11.9.20 Table 11-26 and 11-27, ARM-IHI0050B: 12.9.36 Table 12-35 and 12-36

Monitor Check that the final state in the coherent response to the initiating RN is set to Shared as expected

Checks the correctness of 'the final state in the coherent response to be Shared State or not'(IsShared response), for the following coherent transaction types from HN to initiating RN-F is correct:
- ReadClean, ReadShared
- CleanShared with svt_chi_base_transaction :: snp_attr_is_snoopable set to 1 (Snoopable CleanShared)
- ReadNotSharedDirty, ReadSpec (CHI-B OR LATER)
- CleanSharedPersist with svt_chi_base_transaction :: snp_attr_is_snoopable set to 1 (Snoopable CleanSharedPersist: CHI-B OR LATER)
This check is performed when the coherent transaction is complete

ERROR

AMBA Multi Chip System

data integrity

read_data_integrity_check

ARM-IHI0050A: 4.7.1, ARM-IHI0050B: 4.7.1

Monitor Check that read data from HN matches with system monitor HNHN-F L3/HN-I memory view when: the snooped RNs return the data in clean state OR none of the snooped RNs return any data OR there are no snoops

Checks that data in read transaction is consistent with system monitor HN(HN-F L3/HN-I memory) when the read transaction completes at RN.
This check is applicable when the snooped RNs return the data in clean state or none of the snooped RNs return any data.

ERROR

AMBA Multi Chip System

routing

slave_transaction_routing_check

ARM-IHI0050A, ARM-IHI0050B

Monitor Check that transaction is routed to the correct slave based on the address of the transaction request

Checks that a transaction is routed correctly to a slave port based on address. This check is performed on the transactions routed from CHI interconnect to a CHI SN or an AXI slave, when the transactions are started at the slave. In case the transaction is routed to AXI slave, this check is performed under following conditions:

The CHI system monitor (that is part of a CHI system ENV) and the AXI slave (that is part of an AXI system ENV) are part of an AMBA system ENV
The mapping between CHI SNs and AXI slaves is provided through the APIs of AMBA system configuration
Methodology used is UVM

ERROR

CHI System

Custom Combined Write CMO Check

rn_combined_writecmo_xact_propagated_to_slave_custom_check

SYNOPSYS DEFINED

Every RN Combined_Write_and_CMO type transaction to that HN there should be a corresponding Combined_Write_and_CMO type Slave transaction.

For a HN, if combined_write_and_cmo_propagation_to_slave_policy is set to ALWAYS_FWD_STANDALONE_WRITE_TO_SLAVE:

Every RN Combined_Write_and_CMO type transaction to that HN there should be a corresponding Standalone Write Slave transaction.

For a HN, if combined_write_and_cmo_propagation_to_slave_policy is set to Default value EITHER_FWD_STANDALONE_WRITE_OR_COMBINED_WRITE_AND_CMO_TO_SLAVE:

This Check is not executed.

ERROR

CHI System

coherent rsp

coherent_resp_start_conditions_check

ARM-IHI0050E.b: 4.3 Snoop request types

Monitor Check that the response to a coherent transaction is not started before appropriate RN-Fs are snooped

ERROR

CHI System

Exclusive Access

exclusive_chi_transaction_type_check

ARM-IHI0050E.b: 6.3 Exclusive transactions

Monitor check that observed exclusive transaction is one of the allowed coherent/non-coherent exclusive load/store transaction types.

Checks that before processing any exclusive transactions from RN if that transaction is part of an allowed transaction type for an exclusive access.
Following are the permitted transaction types to have svt_chi_base_transaction :: is_exclusive set to 1: CleanUnique, ReadShared, ReadClean, ReadNoSnp, WriteNoSnp*, ReadNoSharedDirty(CHI-B OR LATER), ReadPreferUnique(CHI-E OR LATER), MakeReadUnique(CHI-E OR LATER) Prefetchtgt(is_exclusive is a don't care field for prefetchtgt so it is permitted to take any value)
This check is performed when an RN transaction is started.

ERROR

CHI System

Exclusive Access

exclusive_store_resp_check

ARM-IHI0050E.b: 6.2 Exclusive monitors

Monitor check that the resposne for exclusive store transaction matches the expected response for the given lpid and address.

Checks that the response for exclusive store transaction(CleanUnique, MakeReadUnique, WriteNoSnp*) matches the expected response(svt_chi_transaction :: response_resp_err_status in case of CleanUnique and WriteNoSnp, svt_chi_common_transaction :: final_state in case of MakeReadUnique) for the given lpid and address.
The expected response is determined by the exclusive monitor.
This check is executed when the store transaction is complete.

ERROR

CHI System

Exclusive Access

exclusive_load_resp_check

ARM-IHI0050E.b: 6.2 Exclusive monitors

Monitor check that the resposne for exclusive load transaction matches the expected response for the given lpid and address.

Checks that the response for exclusive load transaction(ReadNoSnp, ReadShared, ReadClean, ReadNotSharedDirty, ReadPreferUnique) matches the expected response(svt_chi_transaction :: data_resp_err_status) for the given lpid and address.
The expected response is determined by the exclusive monitor.
This check is executed when the load transaction is complete.

ERROR

CHI System

atomics

forward_atomics_to_slave_check

ARM-IHI0050E.b: 2.3.1

Checks that the HN propagates the Atomic transactions to downstream nodes as expected

This check is applicable for ATOMIC transactions. This check checks that if the transactions seen at slave side are correct as per the atomic_xact_propagation_to_slave_policy.

When HN is configured to send the Atomic transactions as it is, then any master atomic transaction should not be associated to non-atomic slave transaction.
When HN is configured to send the ATOMIC transactions as READ and WRITE to slaves, then any master atomic transaction should not be associated with slave atomic transactions.
This check also checks in System monitor report_phase if there are any outstanding atomic transactions from RN to a HN and if the atomic_xact_propagation_to_slave_policy was configured correctly for those HNs.
This check is performed in report phase where all the un-associated system transactions are found.
This check is performed when L3 cache is disabled.

ERROR

CHI System

cmos

forward_cmos_to_slave_check

ARM-IHI0050E.b: 4.2.2 Dataless transactions

Monitor Check that the HN propagates the CMOs beyond the HN

When HN is configured to send the CMOs to downsteam caches, then all the slaves whose address belogs to them, should receive the CMO transactions. System monitor checks if all the slaves got the CMOs corresponding to CMOs at RN node.
This check is performed in report phase where all the un-associated system transactions are found.

ERROR

CHI System

Memory Tagging check

slave_tag_integrity_check

ARM-IHI0050E.b: 12 Memory Tagging

Monitor Check that the slave transaction tag matches with the Tags in the slave memory

Checks that the Tags in a transaction routed to the slave matches with the Tags within the memory of that slave when the transaction ends successfully.

ERROR

CHI System

poison integrity

slave_poison_integrity_check

ARM-IHI0050E.b: 9.5 Poison

Monitor Check that the slave transaction poison matches with content of slave memory

The transaction doesn't have NDERR response
This check currently does not consider transactions with overlapping addresses that are active simultaneously.

ERROR

CHI System

data integrity

slave_data_integrity_check

SYNOPSYS DEFINED

Monitor Check that the data observed in the subordinate VIP agent transaction from Home NodeHN to Subordinate matches with the expected data present in the subordinate VIP agent memory, when the subordinate VIP agent transaction ends successfully.

Checks that the data observed in the subordinate VIP agent transaction from Home Node(HN) to Subordinat, matches with the expected data present in the subordinate VIP agent memory, when the subordinate VIP agent transaction ends successfully. The subordinate can be a CHI SN or an AXI subordindate. In case of the transaction that is routed to AXI subordiniate, this check is performed under the following conditions:

The CHI system monitor (that is part of a CHI system ENV) and the AXI subordinate agent (that is part of an AXI system ENV) are part of an AMBA system ENV
The mapping between CHI SN agents and AXI subordinate agents is provided through the API set_axi_slave_to_chi_sn_map, of AMBA system configuration class.
Methodology used is UVM

This check is performed when there are no overlapping cacheline address transactions to the same subordinate. .

ERROR

CHI System

dvm

interconnect_dvm_snoop_timing_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that the interconnect sends DVM Snoops only after DBIDResp is issued to the initiating RN and NCBWrData is received for the corresponding DVM request.

Checks that the interconnect issues DBIDResp and waits for the WriteData for a DVM request before issuing SnpDVMOp requests.

ERROR

CHI System

dvm

valid_dvm_response_from_interconnect_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that the Comp response for a DVMOp requestnon-sync,sync indicates an Error resposne if any of the associated snoops has Error response.

ERROR

CHI System

dvm

interconnect_dvm_response_timing_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that the interconnect waits for the responses for all corresponding SnpDVMOpnon-sync,sync requests before responding to original DVMOpnon-sync,sync transaction.

ERROR

CHI System

dvm

interconnect_dvm_sync_snoop_transaction_association_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that interconnect broadcasts SnpDVMOpsync transactions to all other RNs that are DVM snoopable when it receives a DVMOpsync request transaction from an RN.

ERROR

CHI System

dvm

interconnect_dvm_operation_snoop_transaction_association_check

ARM-IHI0050E.b: 8.1 DVM transaction flow

Monitor Check that interconnect broadcasts SnpDVMOpnon-sync transactions to all other RNs that are DVM snoopable when it receives a DVMOpnon-sync request transaction from an RN.

Checks that interconnect broadcasts SnpDVMOp(non-sync) transactions to all other RNs that are DVM snoopable when it receives a DVMOp(non-sync) request transaction from an RN.

ERROR

CHI System

Domain and snoop

coherent_snoop_domain_match_check

ARM-IHI0050E.b: 2.9.6 Snoop Attribute

Monitor Check that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master

Checks that the port on which snoop transaction is received corresponds to the domain indicated in coherent transaction of initiating master .
This check is performed when the snoop transaction is received at RN-F node , .
The check compares the domain of the snoop transaction with domain of the initiating RN-F,RN-I(s) coherent transaction.

ERROR

CHI System

hazard

coherent_copyback_atomic_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent copyback request and a coherent atomic request to the same cacheline(copyback-atomic hazard) are correctly handled by HN.
While there is a pending coherent copyback request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN copyback transaction and there was a Hazard condition with a subsequent coherent atomic transaction.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_atomic_copyback_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent copyback request to the same cacheline(atomic-copyback hazard) are correctly handled by HN.
While there is a pending atomic request, if a Copyback request is received to the same cacheline, the coherent copyback request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN atomic transaction and there was a Hazard condition with a subsequent coherent copyback transaction.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_copyback_write_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent write request to the same cacheline(copyback-write hazard) are correctly handled by HN.
While there is a pending copyback request, if a Write request is received to the same cacheline, the coherent write request is processed only after the completion of the copyback transaction.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given copyback transaction and there was a Hazard condition with a subsequent coherent write transaction.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_write_copyback_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a Copyback request to the same cacheline(write-copyback hazard) are correctly handled by HN.
While there is a pending coherent write request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent write transaction.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent copyback transaction.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_copyback_read_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent read request to the same cacheline(copyback-read hazard) are correctly handled by HN across the system.
While there is a pending copyback request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent copyback transaction and there was a Hazard condition with a subsequent coherent read transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_read_copyback_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a Copyback request to the same cacheline(read-copyback hazard) are correctly handled by HN across the system.
While there is a pending coherent read request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN read transaction and there was a Hazard condition with a subsequent copyback transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_copyback_atomic_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent copyback request and a coherent atomic request to the same cacheline(copyback-atomic hazard) are correctly handled by HN.
While there is a pending coherent copyback request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the atomic transaction is completed and copyback-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_atomic_copyback_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent copyback request to the same cacheline(atomic-copyback hazard) are correctly handled by HN.
While there is a pending atomic request, if a Copyback request is received to the same cacheline, the coherent copyback request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent copyback transaction is completed and atomic-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_copyback_write_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent write request to the same cacheline(copyback-write hazard) are correctly handled by HN.
While there is a pending copyback request, if a Write request is received to the same cacheline, the coherent write request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and copyback-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_write_copyback_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a Copyback request to the same cacheline(write-copyback hazard) are correctly handled by HN.
While there is a pending coherent write request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the copyback transaction is completed and write-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_copyback_read_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a copyback request and a coherent read request to the same cacheline(copyback-read hazard) are correctly handled by HN.
While there is a pending copyback request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the copyback transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and copyback-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_read_copyback_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a copyback request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a Copyback request to the same cacheline(read-copyback hazard) are correctly handled by HN.
While there is a pending coherent read request, if a copyback request is received to the same cacheline, the copyback request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the copyback transaction is completed and read-copyback hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

Memory Tagging check

tag_not_dirty_at_any_rn_when_snpmakeinvalid_issued_check

ARM-IHI0050E.b: 12 Memory Tagging

Checks that the HN issues a SnpMakeInvalid corresponding to a coherent Write, MakeUnique or MakeInvalid transaction only when either the HN can be sure that the Snooped RN does not hold dirty tags or when the RN transaction is a WriteUniqueFull or MakeUnique with TagOp set to Update.
This check is only performed when the Snooped RN supports memory tagging and Snoop filter is enabled for the HN.
The HN can be sure that a Snoopee does not contain dirty tags when the cache line state tracked by its Snoop filter is not UC, UD or SD.
The system monitor refers to its own snoop filter model to determine if it's possible for the snooped RN to have cached Tag in dirty state.
If this check must not be performed for certain addresses, it can be bypassed using the system monitor callback "pre_check_execute".

ERROR

CHI System

coherent and snoop

valid_snp_xact_type_for_makereadunique_check

ARM-IHI0050E.b:4.4 Request transactions and corresponding Snoop requests

Monitor Check that the Snoop transaction is one of the valid snoop types for MakeReadUnique transaction.

Checks that the Snoop transaction is one of the valid snoop types for MakeReadUnique transaction.

ERROR

CHI System

Memory Tagging check

coherent_and_snoop_tag_match_check

ARM-IHI0050E.b: 12 Memory Tagging

Monitor Check that Tags returned to initiating RN matches with the full cacheline tags received from associated snoop transaction

Checks that Tags returned to initiating RN in the Read data response matches with the Tags received from associated snoop transaction under following scenarios:
- Scenario 1: Full cacheline Tag are returned for one of the associated snoop transaction, with TagOp in the snoop data response set to either TAG_TRANSFER or TAG_UPDATE.
- Scenario 2: Partial cacheline Tags are returned for one of the associated snoop transaction with TagOp in the snoop data response set to TAG_UPDATE.
This check is not performed in case partial cacheline Tags are returned for one of the snoop transaction but HN-F L3 doesn't have the cacheline.
This check is applicable when : coherent Read transaction has TagOp in the data response set to Transfer or Update and there are associated snoop transactions that returned Tags.
This check is performed when the coherent transaction is complete

ERROR

CHI System

Memory Tagging check

snoop_tag_integrity_check

ARM-IHI0050E.b: 12 Memory Tagging

Checks that clean Tags returned for a Snoop transaction are consistent with system monitor HN(HN-F L3/HN-I memory).
This check is applicable only when the TagOp in the Snoop data response is set to Transfer and the final state indicated in the Snoop response is Clean.

ERROR

CHI System

coherent rsp

cache_state_of_stash_resp_check

ARM-IHI0050E.b: 7 Cache Stashing

Monitor Check that no peer RN has cached the line when the cache state is UC/UD in the DataPull read response of Stash snoop

ERROR

CHI System

coherent and snoop

stash_data_pull_integrity_check

ARM-IHI0050E.b: 7 Cache Stashing

Monitor Check that the Data Pull Read data returned for Stash type Snoops is as expected

ERROR

CHI System

coherent and snoop

associated_snoop_trace_tag_validity_check

ARM-IHI0050E.b: 11.5 Trace Tag

Monitor Check that the associated snoop transaction has valid trace_tag value

The snoops generated in responce to a request from an RN must have valid trace tag value. This is not supported for coherent requests generated by ACE-Lite master.

ERROR

CHI System

coherent and snoop

only_one_snoop_with_rettosrc_check

ARM-IHI0050E.b: 4.9 Returning Data with Snoop response

Monitor Check that only one snoop transaction, corresponding to a given coherent transaction, has RetToSrc asserted

Checks that for a given coherent transaction, only one of the associated snooped RNs has RetToSrc set to 1 (svt_chi_common_transaction :: ret_to_src = 1).
This check is performed when the coherent transaction is complete.

ERROR

CHI System

coherent and snoop

only_one_forward_snoop_per_coherent_transaction_check

ARM-IHI0050E.b: 4.3 Snoop request types

Monitor Check that only one snoop transaction, corresponding to a given coherent transaction, is a forwarding type Snoop

Checks that for a given coherent transaction, only one of the associated snoop requests is a forward type Snoop (is_forward_type_snoop = 1).
This check is performed when the coherent transaction is complete.

ERROR

CHI System

coherent rsp

cache_state_of_xact_resp_check

ARM-IHI0050E.b: 4.7 Cache state transitions at a Requester

Monitor Check that no peer RN has cached the line when the Cache state is UC/UD in the Comp/CompData response of coherent transactions

ERROR

CHI System

coherent and snoop

coherent_snoop_type_match_check

ARM-IHI0050E.b: Table 4-24 Expected snoop requests per Request from an RN

Monitor Check that the snoop transaction type corresponds to the coherent transaction type of initiating master

Checks that the associated snoop transaction type corresponds to the coherent transaction type from initiating RN as per:
- Table 4-1 of CHI Issue A specification
- Table 4-3 of CHI Issue B specification for the supported coherent and snoop types
This check is performed when coherent transaction is complete, and when a given snoop transaction is associated that is:
- not sent to initiating RN (snoop_not_sent_to_initiating_master_check not failed)
- only one snoop is outstanding at the snooped RN to the given cache line address
- not aborted

ERROR

CHI System

coherent and snoop

snoop_not_sent_to_initiating_master_check

ARM-IHI0050E.b: 4.4 Request transactions and corresponding Snoop requests

Monitor Check that a snoop is not sent to the initiating master

Checks that an associated snoop transaction is not sent to the RN, that initiated corresponding coherent transaction.
This check is performed once coherent transaction is complete, and snoop transaction is assoiated to coherent transaction.
Note that this check doesn't include DVM transactions.

ERROR

CHI System

coherent and snoop

overlapping_addr_sequencing_check

ARM-IHI0050E.b: 4.11.2 At the ICNHN-F node

Monitor Check that if two masters initiate requests to access the same cache line simultaneously, one master is sequenced after the other

Checks that if more than one RN initiate requests to access the same cache line simultaneously, one RN is sequenced after the other. If more than one RN initiate requests to access the same cache line simultaneously, the interconnect is expected to process these simultaneous requests one after another. In the case that this results in a scenario that is not corresponding to the check svt_chi_system_err_check :: snoop_not_sent_to_initiating_master_check, then the following details are applicable.

ERROR

CHI System

coherent and snoop

snoop_addr_matches_coherent_addr_check

ARM-IHI0050E.b: 4.3 Snoop request types

Monitor Check that the address of a snoop transaction must match one of the outstanding coherent transactions

Checks that the address of a snoop transaction must match one of the outstanding coherent transactions
This check is performed when the snoop transaction starts, even before coherent to snoop transaction association is done.
Note that this doesn't check for snoop transaction type that corresponds to coherent transaction type
The coherent transaction types that are checked for matching address are all the types excluding the following: WriteNoSnp*, ReadNoSnp, WriteBack*, WriteClean*, Evict, WriteEvictFull.

ERROR

CHI System

snoop rsp

only_one_snoop_returns_data_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that only one snoop transaction returns data

Checks that for a given coherent transaction, only one of the associated snooped RNs responded to the snoop requests with data (svt_chi_snoop_transaction :: snp_rsp_datatransfer = 1).
This check is performed when the coherent transaction is complete.

ERROR

CHI System

snoop rsp

snoop_resp_passdirty_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that no two associated snooped RNs responded to snoop transactions with PassDirtyresp[2] in the snoop responses asserted.

Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with PassDirty(resp[2] - svt_chi_common_transaction :: resp_pass_dirty) asserted to HN.
This check is performed when the coherent transaction is complete.

ERROR

CHI System

snoop rsp

snoop_resp_wasunique_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that no two associated snooped RNs responded to snoop transactions with cache line state as Unique.

Checks that for a given coherent transaction, no two associated snooped RNs responded to the snoop requests with 'final cache line state as Unique'(WasUnique response asserted) at the respective snooped RNs.
This check is performed when the coherent transaction is complete.

ERROR

CHI System

coherent and snoop

coherent_xact_with_no_snoop_check

ARM-IHI0050E.b: 4.4 Request transactions and corresponding Snoop requests

Checks that READNOSNOOP,WRITENOSNOOP*,WRITEBACK*,WRITECLEAN*, WRITEEVICTFULL and EVICT transactions do not lead to snooping of peer RN-Fs.
This check is performed when the snoop transaction starts.
The check compares the address of the snoop transaction with outstanding coherent transactions.
The check does not compare the snoop transaction type with coherent transaction type.
Note that, in case of Invisible Cahe Mode at HN, it's possible to have Snoops for non-coherent transactions, please refer to svt_chi_system_configuration :: set_hn_invisible_cache_mode_enable for more details. In this case, the check factors in the set_hn_invisible_cache_mode_enable() settings along with Snoop Filter entries to validate the correctness of observed snoops for the non-coherent requests.

ERROR

CHI System

coherent and snoop

coherent_and_snoop_data_match_check

ARM-IHI0050E.b: 4.3 Snoop request types

Monitor Check that data returned to initiating RN matches with the full cacheline data received from associated snoop transaction

Checks that data returned to initiating RN matches with the data received from associated snoop transaction under following scenarios:
- Scenario 1: Full cacheline data is returned for one of the associated snoop transaction
- Scenario 2: Partial cacheline data is returned for one of the associated snoop transaction and HN-F L3 has the cacheline
This check is not performed in case of partial cacheline data is returned for one of the snoop transaction and HN-F L3 doesn't have the cacheline.
This check is applicable when : coherent transaction has data response and there are associated snoop transactions
This check is performed when the coherent transaction is complete

ERROR

CHI System

data integrity

snoop_data_integrity_check

ARM-IHI0050E.b: 4.8 Cache state transitions at a Snoopee

Monitor Check that snoop response data from snooped RN matches with system monitor HN-F L3 view when the final state resp[1:0] in the SnpRspData flits is set to UC/SC/I.

Checks that data in snoop transaction is consistent with system monitor HN-F L3 view when the snoop transaction completes.
This check is performed when the coherent transaction is complete and system monitor has already associated the snoop transactions.
This check is not applicable in case the snoop transaction returns the dirty data.

ERROR

CHI System

data integrity

copyback_data_integrity_check

ARM-IHI0050E.b: 4.7.3 Write request transactions

Monitor Check that CopyBack write data from RN matches with system monitor HN-F L3 view when the current state resp[1:0] in the CopyBack write DAT flits is set to UC/SC.

Checks that data in transaction is consistent with data in system monitor HN-F L3 view, when the CopyBack transaction completes.
This check is applicable when the current state in the CopyBack transaction is UC/SC and there are no overlapping transactions to the same cacheline.
In case the current state is dirty, system monitor HN-F L3 view will be updated with the CopyBack write data. There is no need to compare the CopyBack write data with system monitor HN-F L3 view in such a case.
In case the current state is I, interconnect is expected to ignore/drop the CopyBack write data. System monitor HN-F L3 view will not be updated with the CopyBack write data in this case. Also there is no need to compare CopyBack write data with system monitor HN-F L3 view.
Current State indicates the cacheline state at the RN when the data is sent (resp[1:0]).

ERROR

CHI System

Streaming order

single_rn_optimized_streaming_order_check

ARM-IHI0050E.b: 2.8.5

Monitor Check that not more than one RN is configured to use the optimized streaming ordered WriteUnique/writeNoSnp flow, in the system.

Checks that not more than one RN is configured to use the optimized streaming ordered WriteUnique/WriteNoSnp flow.

OrderWriteObservation is enabled for WriteUnique transactions when svt_chi_transaction :: xact_type is WRITEUNIQUEFULL/WRITEUNIQUEPTL, with svt_chi_base_transaction :: order_type == REQ_ORDERING_REQUIRED and svt_chi_base_transaction :: exp_comp_ack set to 1.
Optimized streaming ordered WriteUnique is enabled through setting svt_chi_node_configuration :: optimized_streaming_ordered_writeunique_enable=1.
OrderWriteObservation is enabled for WriteNoSnp transactions when svt_chi_transaction :: xact_type is WRITENOSNPFULL/WRITENOSNPPTL, with svt_chi_base_transaction :: order_type == REQ_ORDERING_REQUIRED and svt_chi_base_transaction :: exp_comp_ack set to 1.
Optimized streaming ordered WriteNoSnp is enabled through setting svt_chi_node_configuration :: optimized_streaming_ordered_writenosnp_enable=1.
This Check is performed when the transaction is started.

WARNING

CHI System

MPAM

matching_mpam_values_for_original_request_and_associated_stash_snoop_check

ARM-IHI0050E.b: 11.3 MPAM

Monitor Check that all the MPAM attributes of RN transaction are propagated to associated Stash snoop transactions

MPAM attributes in the Stash snoop must match with the MPAM attributes in the request that caused the generation of Stash snops.

ERROR

CHI System

MPAM

matching_mpam_values_for_original_request_and_associated_slave_xact_check

ARM-IHI0050E.b: 11.3 MPAM

Monitor Check that all the MPAM attributes of RN transaction are propagated to associated subordinate transactions

The MPAM fields mpam_ns, mpam_perfmongroup and mpam_partid must be preserved on a request from HN to SN that is sent in response to a request to HN.
This check is performed after master-slave association is complete.

ERROR

CHI System

Mismatched Memory attributes

same_memory_snoop_attributes_for_addr_check

ARM-IHI0050E.b: 2.9.7 Mismatched Memory attributes

Monitor Check that All outstanding transactions targetting the same address must have the same MemAttr bits Device, Cacheable and SnpAttr bit. All the agents should maintain a consistent view of the attributes of any region of memory addresses

All the nodes should maintain a consistent view of the attributes of any region of memory addresses.
When software rules checking is enabled, all outstanding transactions targetting the same address are expected to have the same MemAttr bits Device, Cacheable and SnpAttr bit.

ERROR

CHI System

hazard

coherent_atomic_atomic_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and another coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and another atomic request to the same cacheline(atomic-atomic hazard) are correctly handled by HN.
While there are pending coherent atomic and atomic requests to the same cacheline, only one of those coherent atomic or atomic requests are in progress at any given point in time.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent atomic or atomic transaction is completed and atomic-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_atomic_read_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent read request to the same cacheline(atomic-read hazard) are correctly handled by HN.
While there is a pending atomic request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and atomic-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_read_atomic_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent atomic request to the same cacheline(read-atomic hazard) are correctly handled by HN.
While there is a pending coherent read request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the atomic transaction is completed and read-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_atomic_write_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent write request to the same cacheline(atomic-write hazard) are correctly handled by HN.
While there is a pending atomic request, if a write request is received to the same cacheline, the coherent write request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and atomic-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_write_atomic_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent atomic request to the same cacheline(write-atomic hazard) are correctly handled by HN.
While there is a pending coherent write request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the atomic transaction is completed and write-atomic hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_atomic_atomic_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and another coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and another atomic request to the same cacheline(atomic-atomic hazard) are correctly handled by HN.
While there are pending coherent atomic and atomic requests to the same cacheline, only one of those coherent atomic or atomic requests are in progress at any given point in time.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN atomic transaction and there was a Hazard condition with a subsequent coherent atomic transaction.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_atomic_read_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent read request to the same cacheline(atomic-read hazard) are correctly handled by HN.
While there is a pending atomic request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN atomic transaction and there was a Hazard condition with a subsequent coherent read transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_read_atomic_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent atomic request to the same cacheline(read-atomic hazard) are correctly handled by HN.
While there is a pending coherent read request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN read transaction and there was a Hazard condition with a subsequent coherent atomic transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_atomic_write_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent atomic request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent atomic request and a coherent write request to the same cacheline(atomic-write hazard) are correctly handled by HN.
While there is a pending atomic request, if a write request is received to the same cacheline, the coherent write request is processed only after the completion of the Atomic transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN atomic transaction and there was a Hazard condition with a subsequent coherent write transaction.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_write_atomic_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent atomic request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent atomic request to the same cacheline(write-atomic hazard) are correctly handled by HN.
While there is a pending coherent write request, if an Atomic request is received to the same cacheline, the atomic request is processed only after the completion of the coherent write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent coherent atomic transaction.
This check doesn't include coherent transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_copyback_copyback_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a copyback request and another copyback request are correctly ordered by HN

Checks that hazard condition between a copyback and another copyback request to the same cacheline(copyback-copyback hazard) are correctly ordered by HN across the system.
There should not be more than one copyback transactions to the same cacheline that are in progress at any given point in time A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given RN copyback transaction and there was a Hazard condition with a subsequent copyback transaction.
This check doesn't include copyback transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_read_read_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and another coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent read request and another coherent read request to the same cacheline(read-read hazard) are correctly ordered by HN across the system.
There should not be more than one coherent read transactions to the same cacheline that are in progress at any given point in time. A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN Read transaction and there was a Hazard condition with a subsequent coherent Read transaction.
This check doesn't include coherent read transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_write_write_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and another coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent write request and another coherent write request to the same cacheline(write-write hazard) are correctly ordered by HN across the system.
There should not be more than one coherent write transactions to the same cacheline that are in progress at any given point in time A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent coherent write transaction.
This check doesn't include coherent write transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_write_read_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent read request to the same cacheline(write-read hazard) are correctly handled by HN.
While there is a pending write request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the write transaction.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when master-slave association is done for a given coherent RN write transaction and there was a Hazard condition with a subsequent coherent read transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_read_write_hazard_after_slave_xact_association_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent write request to the same cacheline(read-write hazard) are correctly handled by HN across the system.
While there is a pending coherent read request, if a write request is received to the same cacheline, the write request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
A coherent transaction is considered complete when all responses corresponding to the request are seen at the RN and all slave transactions, if any, are also complete.
This check is executed when master-slave association is done for a given coherent RN read transaction and there was a Hazard condition with a subsequent coherent write transaction.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

Memory Tagging check

expected_tag_match_result_check

ARM-IHI0050E.b: 12 Memory Tagging

Monitor Check that the result indicated in the Tag Match response for a Write or Atomic transaction matches the result expected by the System monitor

Checks that the Tag matching result indicated in Resp field of the TagMatch response sent by a Home node for a Write or Atomic transaction with TagOp set to Match matches with the result expected by the System monitor.
In case the Home node does not support memory tagging, it is expected that the TagMatch response will indicate that the Match operation failed.
This check is performed only when the TagOp in the Write data response of the Write or Atomic transaction is set to Match(TAG_FETCH_MATCH).

ERROR

CHI System

hazard

coherent_read_read_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and another coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent read request and another coherent read request to the same cacheline(read-read hazard) are correctly ordered by HN
There should not be more than one coherent read transactions to the same cacheline that are in progress at any given point in time
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and a read-read hazard condition was detected when it was started
This check doesn't include coherent read transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_req_compack_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor check that - for a given cacheline, hazard condition between a Coherent request and CompAck is handled correctly by the HN

Checks that hazard condition between a pending CompAck and another coherent request to same cacheline are correctly ordered by HN.
When HN receives a new RN request transaction to a cacheline while there's a pending transaction to the same cacheline that is yet to receive a CompAck, HN must not process the new request till the CompAck for the outstanding transaction is received.
This check is not applicable for the coherent requests from ACE-Lite master as CompAck is not present in ACE-Lite protocol.
This check is performed when a coherent request receives a response from HN

ERROR

CHI System

hazard

coherent_write_write_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and another coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent write request and another coherent write request to the same cacheline(write-write hazard) are correctly ordered by HN
There should not be more than one coherent write transactions to the same cacheline that are in progress at any given point in time
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent write transaction is completed and a write-write hazard condition was detected when it was started
This check doesn't include coherent write transactions from ACE-Lite master

ERROR

CHI System

hazard

coherent_write_read_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent write request and a coherent read request are correctly ordered by HN

Checks that hazard condition between a coherent write request and a coherent read request to the same cacheline(write-read hazard) are correctly handled by HN.
While there is a pending write request, if a Read request is received to the same cacheline, the coherent read request is processed only after the completion of the write transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the coherent read transaction is completed and write-read hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

hazard

coherent_read_write_hazard_check

ARM-IHI0050E.b: 5.6.2 Request hazard at HN-F

Monitor Check that - for a given cacheline, hazard condition between a coherent read request and a coherent write request are correctly ordered by HN

Checks that hazard condition between a coherent read request and a coherent write request to the same cacheline(read-write hazard) are correctly handled by HN.
While there is a pending coherent read request, if a write request is received to the same cacheline, the write request is processed only after the completion of the coherent read transaction.
In progress transaction refers to a transaction which is outstanding and has received a request response from the HN.
This check is executed when the write transaction is completed and read-write hazard was detected when it was started.
This check doesn't include coherent transactions from ACE-Lite master
Coherent read transactions include dataless transactions

ERROR

CHI System

DWT

no_snoop_resp_dirty_with_dwt_check

ARM-IHI0050E.b: 13.10.26 Do Direct Write Transfer, DoDWT

Monitor Check that - For a partial cacheline coherent transaction from RN, HN doesn't issue DWT request to Slave if any of the associated snoop transactions return dirty data

Checks that DWT is not used by the HN if any of the associated snoop transactions returns dirty data.
This check is performed when the RN transaction is complete.
Applicable only for partial cacheline coherent writes

ERROR

CHI System

DWT

comp_after_snoop_xacts_completion_with_dwt_check

ARM-IHI0050E.b: 13.10.26 Do Direct Write Transfer, DoDWT

Monitor Check that the HN issued Comp response to the requester after receiving all snoop responses for any snoops that were sent

The Comp response must be sent only after receiving all snoop responses for any snoops that were sent. THe HN must wait for all the associated snoop transactions to complete, before initiating a comp response to the requester.
This check is performed when the RN transaction is complete and there are associated snoop transactions.

ERROR

CHI System

Custom Combined Write CMO Check

valid_combined_writecmo_slave_xact_custom_check

SYNOPSYS DEFINED

Monitor Custom Check that generation of Combined Write and PCMO type transaction to slave should always be associated with a Combined Write and PCMO type RN transaction

Check that when a Combined Write and (P)CMO type transaction is observed on the slave, there must be a corresponding RN transaction which is of Combined Write and (P)CMO type to the same cacheline.

ERROR

CHI System

Memory Tagging check

write_tag_integrity_check

ARM-IHI0050E.b: 12 Memory Tagging

Monitor Check that Tags transferred in clean state by an RN for a Write transaction matches with system monitor HNHN-F L3/HN-I memory view

Checks that Clean Tags transferred in Write transaction data are consistent with system monitor HN(HN-F L3/HN-I memory) when the Write transaction completes at the RN.
This check is applicable only when the TagOp in the Write data is set to Transfer.

ERROR

CHI System

Memory Tagging check

atomic_returned_initial_tag_integrity_check

ARM-IHI0050E.b: 12 Memory Tagging

Monitor Check that Tags returned in clean state by an HN for an AtomicLoad/Swap/Compare transaction matches with system monitor HNHN-F L3/HN-I memory view

Checks that the Tags in the returned initial data response are consistent with the system monitor memory view when an Atomic LOAD/SWAP/COMPARE completes at an RN.
In case there are associated snoops wherein Tags were transferred in the Snoop data response, the system monitor compares the Tags in the returned initial data response with the corresponding Tags in the snoop data response.
In case there are no associated snoops or none of the Snooped RNs returned Tags, the system monitor compares the Tags in the returned initial data response with the corresponding Tags in the system monitor memory.

ERROR

CHI System

Memory Tagging check

read_tag_integrity_check

ARM-IHI0050E.b: 12.4 Read transaction rules

Checks that clean Tags returned for a read transaction are consistent with system monitor HN(HN-F L3/HN-I memory) when the read transaction completes at RN.
This check is applicable only when the TagOp in the Read data is set to Transfer and the snooped RNs return the Tags in clean state or none of the snooped RNs return any Tags.

ERROR

CHI System

DMT

dmt_after_snoop_xacts_completion_check

ARM-IHI0050E.b: 2.3.1 Read transactions

Monitor Check that - For a given RN transaction, HN issues DMT request to Slave only after the completion of all the associated snoop transactions

If HN needs to send snoop requests for a given RN transaction, the HN must wait for all the associated snoop transactions to complete, before initiating a corresponding DMT request to slave.
This check is performed when the RN transaction is complete and there are associated snoop and slave transactions.

ERROR

CHI System

DMT

valid_xacts_for_optimized_dmt_check

ARM-IHI0050E.b: 2.3.1 Read transactions

Monitor Check that - HN issues optimized DMT request to Slave only for RN transactions of the type ReadNoSnp and ReadOnce with ExpCompAck asserted OR order set to NO_ORDERING_REQUIRED

Checks that HN issues optimized DMT request to Slave only for RN transactions of the type ReadNoSnp and ReadOnce with ExpCompAck asserted OR order set to NO_ORDERING_REQUIRED
This check is performed when the RN transaction is complete and there are associated slave transactions.

ERROR

CHI System

DMT

no_snoop_resp_dirty_with_dmt_check

ARM-IHI0050E.b: 2.3.1 Read transactions

Monitor Check that - For a given RN transaction, HN doesn't issue DMT request to Slave if any of the associated snoop transactions return full cacheline dirty data

Checks that DMT is not used by the HN to respond back to initiating RN's transaction, if any of the associated snoop transactions returns full cacheline dirty data.
This check is performed when the RN transaction is complete.

ERROR

CHI System

ATOMICOPS

comp_or_compdata_response_after_snoop_xacts_completion_for_atomic_transaction_check

ARM-IHI0050E.b: 4.2 Request types

Monitor Check that - The Completer must wait for all snoop responses before sending the Comp or CompData response.

The Completer must wait for all snoop responses before sending the Comp response in case of atomic store or CompData response in case of atomic load, swap and compare transactions.

ERROR

CHI System

data integrity

atomic_returned_initial_data_integrity_check

ARM-IHI0050E.b: 2.3.3 Atomic transactions

Monitor Check that the returned initial data is consistent with the system monitor when read data completes at RN for Atomic LOAD/SWAP/COMPARE.

Checks that the returned initial data is consistent with the system monitor memory view when an Atomic LOAD/SWAP/COMPARE completes at an RN.
In case there are associated snoops with data transfer the system monitor compares the returned initial data with the corresponding bytes in the snoop data.
In case there are no associated snoops or none of the associated Snoop requests received a data response, the system monitor compares the returned initial data with the corresponding bytes in the memory.

ERROR

CHI System

Transaction ordering

ordering_of_xacts_when_dbidrespord_received_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

ERROR

CHI System

Transaction ordering

slave_xacts_ordering_for_ordered_rn_xact_check

ARM-IHI0050E.b: 2.8.5 Transaction ordering

Monitor Check that the associated slave xacts of ordered RN transaction should be started after all the associated slave xacts of earlier issued ordered RN xact

The interconnect must maintain the order in which slave transactions are issued corresponding to ordered RN transactions from an RN to same address/address range

ERROR

CHI System

Propagation of Attr

memory_attributes_propagation_check

ARM-IHI0050E.b: 2.9.3 Memory Attributes

Monitor Check that all the memory attributes of RN transaction are propagated to slaves

The MemAttr bits EWA, Device, Cacheable, and Allocate, must be preserved on a request from HN to SN that is sent in response to a request to HN.
This check is performed after master-slave association is complete.

ERROR

CHI System

coherent rsp

coherent_resp_passdirty_check

ARM-IHI0050E.b: 13.10.44 Response status, Resp

Monitor Check that the PassDirty response to initiating RN is correct

Checks that the PassDirty response(resp[2]) in the coherent response to initiating RN-F is correct.
In case of ReadShared, ReadUnique, ReadNotSharedDirty(CHI-B OR LATER): If PassDirty was asserted for any snoop response received by the interconnect, and the interconnect has not asserted PassDirty in the coherent response to initiating RN, it's possible that Interconnect has taken the responsibility of updating the L3 cache or main memory. Note that this check does not verify if the interconnect updated L3 or main memory with dirty data. However, in this case, if the HN is not able to properly handle the dirty data, a subsequent read to same cacheline would result into read_data_integrity_check failure.
This check is performed when the coherent transaction is complete.

ERROR

CHI System

coherent rsp

coherent_resp_isshared_check

ARM-IHI0050E.b: 13.10.44 Response status, Resp

Monitor Check that the final state in the coherent response to the initiating RN is set to Shared as expected

Checks the correctness of 'the final state in the coherent response to be Shared State or not'(IsShared response), for the following coherent transaction types from HN to initiating RN-F is correct:
- ReadClean, ReadShared
- ReadNotSharedDirty, ReadSpec (CHI-B OR LATER)
This check is performed when the coherent transaction is complete

ERROR

CHI System

data integrity

read_data_integrity_check

ARM-IHI0050E.b: 4.7.1 Read request transactions

Monitor Check that observed/received read data at RN matches with expected data from system monitor when: the snooped RNs return the data in clean state OR none of the snooped RNs return any data OR there are no snoops. System monitor establishes expected data based on observed RN requests with write data & RN snoop transactions with data, but does not depend on any subordinate transactions.

Checks that data in read transaction is consistent with system monitor HN(HN-F L3/HN-I memory) when the read transaction completes at RN.
This check is applicable when the snooped RNs return the data in clean state or none of the snooped RNs return any data.

ERROR

CHI System

ABF

multiple_abf_requests_targeted_to_same_addr_and_to_same_target

SYNOPSYS DEFINED

Monitor Checks that there are no more than one address based flush requests to same address and to same target.

Checks that only one snoop transaction is issued to a given RN targeting a particular cacheline, as a result of Address based flush operation.
This check will be performed if the address in the snoop transaction lies in range svt_chi_hn_status :: min_abf_addr and svt_chi_hn_status :: max_abf_addr.

ERROR

CHI System

routing

slave_transaction_routing_check

SYNOPSYS DEFINED

Monitor Check that transaction is routed to the correct slave based on the address of the transaction request

The CHI system monitor (that is part of a CHI system ENV) and the AXI slave (that is part of an AXI system ENV) are part of an AMBA system ENV
The mapping between CHI SNs and AXI slaves is provided through the APIs of AMBA system configuration
Methodology used is UVM

ERROR

VIP Smartsearch

AMBA SVT UVM Documentation - Protocol Checks Defined in VIP

Product: amba_svt - Protocol Checks Details:

All Group Sub Group Protocol Check Instance name Reference Description Check Intent Error Category Protocol Check Class

VIP Smartsearch

AMBA SVT UVM Documentation - Protocol Checks Defined in VIP

Product: amba_svt - Protocol Checks Details:

Show/Hide All Group Sub Group Protocol Check Instance name Reference Description Check Intent Error Category Protocol Check Class

All Group Sub Group Protocol Check Instance name Reference Description Check Intent Error Category Protocol Check Class